Semiconductor integrated circuit, receiving device, and receiving method

Abstract

To provide a semiconductor integrated circuit suitably reproducing data on the basis of a received signal, and to provide a receiving device and a receiving method.SOLUTION: A semiconductor integrated circuit of an embodiment comprises: a first converter which samples a first digital value from an analog signal on the basis of a first clock signal; a second converter which samples a second digital value from the analog signal on the basis of a second clock signal phase-shifted from the first clock signal by a first phase; a first processing circuit which calculates a phase difference between the first clock signal and the second clock signal on the basis of the first and second digital values using a first frequency of a third clock signal as an operating frequency; and a second processing circuit which generates a control signal for correcting the phase difference between the first and second clock signals on the basis of the phase difference calculated by the first processing circuit using a second frequency which is 2m times (where m is an integer of 1 or more) the first frequency of the fourth clock signal as an operating frequency.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor integrated circuit, a receiving device, and a receiving method. [Background technology]

[0002] The transmitting device and the receiving device are connected via a transmission path. The receiving device receives a received signal that has passed through the transmission path. The receiving device includes a semiconductor integrated circuit that processes the received signal. The receiving device regenerates a clock signal based on the received signal. The receiving device regenerates data from the received signal based on the regenerated clock signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-136009 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor integrated circuit, a receiving device, and a receiving method are provided that suitably recover data based on a received signal. [Means for solving the problem]

[0005] A semiconductor integrated circuit according to an embodiment includes a first converter, a second converter, a first processing circuit, and a second processing circuit. The first converter samples a first digital value from an analog signal based on a first clock signal. The second converter samples a second digital value from the analog signal based on a second clock signal that is phase-shifted from the first clock signal by a first amount. The first processing circuit uses a first frequency of a third clock signal as an operating frequency and calculates a phase shift between the first and second clock signals based on the first and second digital values. The second processing circuit calculates a phase shift between the first and second clock signals based on a second frequency of a fourth clock signal that is phase-shifted by a first amount. mA control signal is generated to correct the phase shift between the first clock signal and the second clock signal based on the phase shift calculated by the first processing circuit, using a second frequency that is 1 / 2 times (m is an integer greater than or equal to 1) times the frequency of the first clock signal as the operating frequency. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an example of a configuration of an information processing system including a receiving device according to an embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a receiving circuit in the receiving device according to the embodiment. [Figure 3] FIG. 2 is a block diagram showing an example of the configuration of an ADC in the receiving circuit according to the embodiment. [Figure 4] FIG. 2 is a block diagram showing an example of the configuration of a phase detection circuit in the receiving circuit according to the embodiment. [Figure 5] FIG. 2 is a block diagram showing an example of the configuration of a loop filter in the receiving circuit according to the embodiment. [Figure 6] 5 is a flowchart illustrating an example of an operation of a receiving circuit in the receiving device according to the embodiment. [Figure 7] 10 is a timing chart showing the relationship between signals and clock signals in an ADC according to an embodiment. [Figure 8] 10 is a timing chart showing the relationship between signals and clock signals in an ADC of a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be assigned the same reference numerals, and a letter or number may be added to the end of the common reference numerals. Furthermore, the functional blocks can be realized as either hardware or computer software, or a combination of both. It is not necessary for the functional blocks to be distinguished as in the following example. For example, some functions may be performed by functional blocks other than the illustrated functional blocks. Furthermore, the illustrated functional blocks may be further divided into smaller functional sub-blocks.

[0008] 1. Configuration of the embodiment The configuration of the receiving device according to the embodiment will be described.

[0009] 1.1 Information Processing System First, the configuration of an information processing system including a receiving device according to an embodiment will be described. Fig. 1 is a block diagram showing an example of the configuration of an information processing system including a receiving device according to an embodiment.

[0010] The information processing system 1 is a system that transmits information by serial communication. The information processing system 1 includes a host device 2 and a memory system 3. The memory system 3 is connectable to the host device 2 via a host bus BUS.

[0011] The host device 2 is an information processing device external to the memory system 3. The host device 2 is, for example, a personal computer or a server installed in a data center. The host device 2 transmits various requests to the memory system 3. When transmitting requests to the memory system 3, the host device 2 functions as a transmitting device.

[0012] The memory system 3 is a storage device. The memory system 3 may be, for example, a universal flash storage (UFS) device, a solid state drive (SSD), or an SD TMThe memory system 3 performs data write, read, and erase operations in response to requests from the host device 2. When receiving a request from the host device 2, the memory system 3 functions as a receiving device.

[0013] 1.2 Memory system (receiving device) The internal configuration of the receiving device of the embodiment, that is, the memory system 3, will be described below with reference to FIG.

[0014] The memory system 3 includes a memory device 4 and a memory controller 5 .

[0015] The memory device 4 is, for example, a nonvolatile memory. The memory device 4 is, for example, a NAND flash memory. The memory device 4 stores data in a nonvolatile manner.

[0016] The memory controller 5 is configured by an integrated circuit such as a system-on-a-chip (SoC). The memory controller 5 controls the memory device 4 based on a request from the host device 2. Specifically, for example, the memory controller 5 writes write data to the memory device 4 based on a write request from the host device 2. The memory controller 5 also reads read data from the memory device 4 based on a read request from the host device 2. The memory controller 5 then transmits the read data to the host device 2.

[0017] Next, we will explain the internal configuration of the memory controller 5. The memory controller 5 includes a control unit (or control circuit) 6, a buffer memory 7, a host interface circuit (host I / F) 8, and a memory interface circuit (memory I / F) 9. The functions of the memory controller 5 described below can be realized by either a hardware configuration or a configuration that combines hardware resources and firmware.

[0018] The control unit 6 is a circuit that controls the entire memory controller 5. The control unit 6 includes, for example, a processor such as a CPU (central processing unit) and a ROM (read only memory).

[0019] The buffer memory 7 is, for example, an SRAM (static random access memory). The buffer memory 7 buffers data transmitted between the host device 2 and the memory device 4. The buffer memory 7 temporarily stores write data and read data. A configuration (memory) having a function equivalent to that of the buffer memory 7 may be provided outside the memory controller 5.

[0020] The host interface circuit 8 is, for example, a semiconductor integrated circuit. The host interface circuit 8 controls communication between the memory controller 5 and the host device 2. When receiving a request from the host device 2, a part of the circuit of the host interface circuit 8 functions as a receiving circuit. The host interface circuit 8 is connected to the host device 2 via a host bus BUS. The host bus BUS is, for example, a PCIe TM (peripheral component interconnect express), MIPI (Mobile Industry Processor Interface), SAS (serial attached SCSI (small computer system interface)), SATA (serial ATA (advanced technology attachment)), or SD TM Conform to the interface.

[0021] The memory interface circuit 9 is, for example, a semiconductor integrated circuit. The memory interface circuit 9 controls communication between the memory device 4 and the memory controller 5. The memory interface circuit 9 is connected to the memory device 4 via a memory bus. The memory bus conforms to, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0022] 1.3 Host interface circuit (receiving circuit) Next, a description will be given of the configuration of the receiving circuit included in the host interface circuit 8. Fig. 2 is a block diagram showing an example of the configuration of the receiving circuit in the receiving device of the embodiment.

[0023] The receiving circuit provided in the host interface circuit 8 includes pads P1 and P2, an analog processing circuit 10, an ADC 20, an aligner 30, an OGC 40, an FFE 50, a data processing circuit 60, a PD 70, an LF 80, a PIC 90, a PLL 100, and a PI 110, and a clock generation circuit 120.

[0024] Each of the pads P1 and P2 is a terminal connected to the host bus BUS. In the example of Fig. 2, the pads P1 and P2 receive signals S0 and / S0, respectively, from the host device 2 via the host bus BUS.

[0025] The signals S0 and / S0 are differential signals. Before passing through the host bus BUS, the signals S0 and / S0 are, for example, pulse signals. Data from the host device 2 is modulated onto each pulse of the signals S0 and / S0. The voltage level of each pulse of the signals S0 and / S0 corresponds to one or more bits of data. In the following explanation, it is assumed that two bits of data are modulated per pulse. This type of data transmission method is also called PAM4 (Four-level Pulse Amplitude Modulation).

[0026] By passing through the host bus BUS, the signals S0 and / S0 are subject to loss due to the transmission characteristics (for example, frequency characteristics) of the host bus BUS. As a result, inter-symbol interference (ISI) occurs in the signals S0 and / S0 that have passed through the host bus BUS. For this reason, the signals S0 and / S0 that have passed through the host bus BUS are processed as analog signals.

[0027] The analog processing circuit 10 is an AFE (Analog Front End). The analog processing circuit 10 includes, for example, a continuous time linear equalizer (CTLE) and a variable gain amplifier (VGA). The CTLE is an amplifier circuit having frequency characteristics that compensate for the frequency characteristics of the host bus BUS. The VGA is an amplifier circuit whose gain can be changed.

[0028] Signals S0 and / S0 are input to the analog processing circuit 10 from pads P1 and P2, respectively. The analog processing circuit 10 performs analog processing on the signals S0 and / S0 using a CTLE and a VGA. The analog processing circuit 10 generates signals S1 and / S1 based on the signals S0 and / S0. The analog processing circuit 10 outputs the signals S1 and / S1 to the ADC 20.

[0029] The ADC 20 is a time-interleaved analog-to-digital conversion circuit. The ADC 20 receives signals S1 and / S1 from the analog processing circuit 10 and receives a clock signal CLKa from the clock generation circuit 120. The ADC 20 converts the signals S1 and / S1 into a signal X0 based on the signal CLKa. The ADC 20 outputs the signal X0 to the aligner 30.

[0030] Signal CLKa includes n clock signals, where n is an integer equal to or greater than 1 (e.g., 40). The n clock signals of signal CLKa differ in phase by at least 360° / n, for example. Hereinafter, the n clock signals in signal CLKa may be individually referred to as signals CLKa_1, CLKa_2, ..., and CLKa_n. In other words, signal CLKa is an n-phase signal. The frequency of signal CLKa is 1 / n of the frequency of the clock signals embedded in signals S0 and / S0 by host device 2. The frequency of signal CLKa is, for example, 1.6 GHz.

[0031] The signal X0 is a digital signal. The signal X0 includes a plurality of consecutive digital values. The bit value of one digital value included in the signal X0 is sampled from one symbol of the signals S1 and / S1 based on one clock signal of the signal CLKa. One digital value is, for example, 7-bit data. Here, the bit value of each of 2n consecutive digital values ​​included in the signal X0 is sampled from n consecutive symbols of the signals S1 and / S1 based on n clock signals of the signal CLKa. Hereinafter, the period during which the ADC 20 generates the 2n consecutive digital values ​​included in the signal X0 is also simply referred to as a "period." The 2n consecutive digital values ​​included in the signal X0 are also referred to as "one period of the signal X0." The 2n consecutive digital values ​​included in the signal X0 may also be distinguished by values ​​X0_1, ..., and X0_2n.

[0032] The aligner 30 receives the signal X0 from the ADC 20 and outputs it as a signal X1. The aligner 30 receives the signal X0 from the ADC 20 via n transmission paths. The aligner 30 converts the received signal X0 into a signal X1 that can be transmitted via 2n transmission paths. The aligner 30 outputs the signal X1 to the OGC 40.

[0033] The OGC40 is an offset / gain correction circuit. A clock signal CLKb is supplied to the OGC40. The clock signal CLKb provides the OGC40 with an operating frequency (or clock frequency). The frequency of the signal CLKb is, for example, 0.8 GHz. The OGC40 receives a signal X1 as input. The signal X1 has an offset error and a gain error that occurred when the ADC 20 converted the signals S1 and / S1 into a signal X0. The OGC40 corrects the offset error and the gain error of the signal X1. The OGC40 outputs the corrected signal X2 to the FFE50.

[0034] The FFE50 is a feed forward equalizer (FFE). Similarly, a clock signal CLKb is supplied to the FFE50. The clock signal CLKb provides an operating frequency for the FFE50. As described above, the frequency of the signal CLKb is, for example, 0.8 GHz. The FFE50 shapes the waveform of the signal X2 and generates a waveform-shaped signal X2. Specifically, the signal X2 is input to the FFE50 every period. The FFE50 extracts a signal X3 related to the clock signal and data A1 from the generated signal X2. The FFE50 outputs the signal X3 and data A1 to the PD70 and the data processing circuit 60.

[0035] The data processing circuit 60 performs various processes on the signal X3 and data A1. A clock signal CLKb is supplied to the data processing circuit 60. The clock signal CLKb provides the operating frequency for the data processing circuit 60. As mentioned above, the frequency of the signal CLKb is, for example, 0.8 GHz. The signal X3 and data A1 are input to the data processing circuit 60. The data processing circuit 60 includes, for example, an FFE. The data processing circuit 60 processes the signal X3 and data A1, whose waveforms have been shaped by the FFE, to generate a signal X4 and data A2. The data processing circuit 60 outputs the signal X4 and data A2 to a subsequent circuit (not shown).

[0036] The PD70 is, for example, an MM baud rate phase detector (Mueller-Muller Baud-Rate Phase Detector). The PD70 is supplied with a clock signal CLKb. The clock signal CLKb provides the PD70 with an operating frequency. As described above, the frequency of the signal CLKb is, for example, 0.8 GHz. The MM baud rate phase detector uses one sampling result per symbol when detecting a phase shift related to the signal CLKa used in the ADC 20. Furthermore, the MM baud rate phase detector does not use sampling results of pulse edges (boundaries) corresponding to data encoded in the signals S0 and / S0 when detecting a phase shift. Specifically, the PD70 receives the signal X3 and data A1 from the FFE 50. Based on the signal X3 and data A1, the PD70 generates a value PDO. The value PDO corresponds to the phase shift between the current sampling timing of the signal CLKa and the optimal sampling timing in the ADC 20. The PD 70 outputs the value PDO to the LF 80 .

[0037] The LF80 is a loop filter. A clock signal CLKc is supplied to the LF80. The clock signal CLKc provides the LF80 with an operating frequency. The frequency of the signal CLKc is, for example, 1.6 GHz. The value PDO is input to the LF80 from the PD70. The LF80 accumulates the input value PDO and calculates a value LFO corresponding to the accumulated value PDO. The value LFO is a value corresponding to an accumulated value obtained by accumulating the phase shift of the signal CLKa in the ADC20. The LF80 outputs the value LFO to the PIC90.

[0038] The PIC90 is a controller that controls a phase interpolator (PI) 110 (described later). A clock signal CLKc is supplied to the PIC90. The clock signal CLKc provides the PIC90 with an operating frequency. As described above, the frequency of the signal CLKc is, for example, 1.6 GHz. The value LFO is input to the PIC90 from the LF80. The PIC90 generates a control code PICO that controls the PI 110 based on the value LFO. The control code PICO is a code generated based on the value LFO, i.e., based on the integrated value of the phase shift of the clock signal CLKa. The PIC90 outputs the control code PICO to the PI 110.

[0039] The PLL 100 is a phase locked loop circuit. The PLL 100 generates a reference clock signal REF. The PLL 100 outputs the reference clock signal REF to the PI 110. In the following description, the difference between the reference frequency of the reference clock signal REF, or the frequency of the signal CLKa, and the frequency of the clock signal embedded in the signals S0 and / S0 by the host device 2 is also referred to as the "frequency deviation."

[0040] The PI110 is a phase interpolation circuit. A control code PICO and a reference clock signal REF are input to the PI110. The PI110 generates a signal PIO from the reference clock signal REF based on the control code PICO. The signal PIO is an n-phase signal whose phase is adjusted based on the control code PICO. The PI110 outputs the signal PIO to the clock generation circuit 120.

[0041] The clock generation circuit 120 is a circuit that generates signals CLKa, CLKb, and CLKc. Specifically, the signal PIO is input to the clock generation circuit 120. Based on the signal PIO generated in response to the control code PICO, the clock generation circuit 120 generates a signal CLKa in which the phase shift has been corrected, i.e., a signal CLKa in which the phase shift due to frequency deviation has been reduced. The clock generation circuit 120 uses, for example, a frequency divider circuit to generate the signal CLKa. The clock generation circuit 120 supplies the signal CLKa to the ADC 20.

[0042] The frequency of the signal CLKa is twice the frequency of the signal CLKb described above. m where m is an integer equal to or greater than 1. In this embodiment, the frequency of signal CLKa is described as being twice the frequency of signal CLKb. As described above, the frequency of signal CLKa is, for example, 1.6 GHz.

[0043] As described above, the ADC 20, aligner 30, FFE 50, PD 70, LF 80, PIC 90, PI 110, and clock generation circuit 120 regenerate the signal CLKa, which serves as a reference for the sampling timing of the signal X0 for one cycle, based on the signal X3 and data A1 generated from the signal X0 for one cycle. This cyclic process from the ADC 20 to the clock generation circuit 120 for each cycle is also called a "CDR loop."

[0044] The clock generation circuit 120 also generates a signal CLKb. Specifically, the clock generation circuit 120 generates the signal CLKb based on the signal PIO. The clock generation circuit 120 uses, for example, a frequency divider circuit to generate the signal CLKb. The clock generation circuit 120 supplies the signal CLKb to the OGC 40, the FFE 50, the PD 70, and the data processing circuit 60. For example, the frequency of the signal CLKb is 1 / 2 the frequency of the signal CLKa. m This is the divided frequency, which is 0.8 GHz as mentioned above.

[0045] The clock generation circuit 120 also generates a signal CLKc. Specifically, the clock generation circuit 120 generates the signal CLKc based on the signal PIO. The clock generation circuit 120 uses, for example, a frequency divider circuit to generate the signal CLKc. The clock generation circuit 120 supplies the signal CLKc to the LF80 and the PIC90. For example, the frequency of the signal CLKc is 2 times the frequency of the signal CLKb. m It is twice as fast as the 1.6GHz.

[0046] The receiving circuit included in the host interface circuit 8 includes, for example, a DSP (digital signal processor) 130. The DSP 130 includes an OGC 40, an FFE 50, a data processing circuit 60, a PD 70, an LF 80, and a PIC90.

[0047] The DSP 130 also includes a first digital processing circuit 131 and a second digital processing circuit 132. The first digital processing circuit 131 includes an OGC 40, an FFE 50, a data processing circuit 60, and a PD 70. The second digital processing circuit 132 includes an LF 80 and a PIC 90.

[0048] A clock signal CLKb is supplied to the first digital processing circuit 131. The first digital processing circuit 131 uses a first frequency of the clock signal CLKb as an operating frequency. The first digital processing circuit 131 calculates the phase shift of the signals CLKa_1 to CLKa_n based on the signal X0 converted by the ADC 20.

[0049] The second digital processing circuit 132 is supplied with a clock signal CLKc. The second digital processing circuit 132 uses the second frequency of the clock signal CLKc as its operating frequency. The second frequency is twice the first frequency. m The frequency is twice as high as m (m is an integer equal to or greater than 1). Based on the phase shift calculated by the first digital processing circuit 131, the second digital processing circuit 132 generates a control signal (i.e., a control code PICO) that corrects the phase shift of the signals CLKa_1 to CLKa_n.

[0050] 1.3.1 ADC (Analog-to-Digital Converter) Next, the internal configuration of the ADC 20 included in the receiving circuit will be described below. Fig. 3 is a block diagram showing an example of the configuration of the ADC in the receiving circuit of the embodiment.

[0051] The ADC 20 includes a plurality of ADCs 21. The plurality of ADCs 21 includes n ADCs 21_1, 21_2, 21_3, ..., 21_n. Each of the ADCs 21_1 to 21_n is an analog-to-digital conversion circuit that converts an analog signal into a digital signal.

[0052] Signals S1 and / S1 are input to n ADCs 21_1 to 21_n. Furthermore, signals CLKa_1 to CLKa_n are supplied to ADCs 21_1 to 21_n, respectively. The ADCs 21_1 to 21_n sample the signals S1 and / S1 based on the signals CLKa_1 to CLKa_n, respectively, and output digital values ​​X0_1, X0_2, X0_3, X0_4, ..., X0_(2n-1), and X0_2n based on the sampling results. In this way, 2n consecutive digital values ​​X0_1 to X0_2n included in the signal X0 are sampled by different ADCs 21_1 to 21_n, respectively.

[0053] The n ADCs 21_1 to 21_n may have different conversion characteristics. Specifically, for example, a slight deviation may occur in the sample timings of the signals CLKa_1 to CLKa_n in the ADCs 21_1 to 21_n. This slight deviation in the sample timing is a phase deviation. Therefore, the CDR loop including the FFE50, the PD70, the LF80, the PIC90, the PI110, and the clock generation circuit 120 adjusts the phase of the signal CLKa to correct the phase deviation occurring in the ADCs 20.

[0054] 1.3.2 PD (Phase Detector) Next, the internal configuration of the phase detection circuit (PD70) included in the receiving circuit will be described. Fig. 4 is a block diagram showing an example of the configuration of the phase detection circuit in the receiving circuit of the embodiment.

[0055] The PD 70 includes a plurality of multipliers 71, a plurality of adders 72, a plurality of sign function circuits 73, and an adder 74. The plurality of multipliers 71 include 4n multipliers 71_1, 71_2, ..., 71_(4k-1) (not shown), 71_4k (not shown), ..., 71_(4n-1), and 71_4n. The plurality of adders 72 include 2n adders 72_1, ..., 72_2k (not shown), ..., and 72_2n. The plurality of sign function circuits 73 include 2n sign function circuits 73_1, ..., 73_2k (not shown), ..., and 73_2n, where k is an integer greater than or equal to 2 and less than or equal to (2n-1) (2≦k≦2n-1).

[0056] In FIG. 4, the 2n digital values ​​included in one cycle of signal X3 are represented as values ​​X3[1], ..., and X3[2n]. Similarly, the 2n digital values ​​included in one cycle of data A1 are represented as values ​​A1[1], ..., and A1[2n]. The values ​​X3[0] and A1[0] correspond to the symbols immediately preceding the values ​​X3[1] and A1[1], respectively. For example, the values ​​X3[0] and A1[0] are the value X3[2n] included in signal X3 and the value A1[2n] included in data A1 in the CDR loop one cycle before. The values ​​X3[0] and A1[0] are pre-stored in a register (not shown) during the CDR loop one cycle before, for example.

[0057] First, the multiplier 71_1 multiplies the value X3[0] by the value A1[1], and outputs the result of the operation, the value X3[0]A1[1], to the adder 72_1.

[0058] The multiplier 71_2 multiplies the value X3[1] by the value A1[0] and outputs the result of the operation, that is, the value X3[1]A1[0], to the adder 72_1.

[0059] The adder 72_1 subtracts the value X3[1]A1[0] from the value X3[0]A1[1]. The adder 72_1 outputs the operation result (X3[0]A1[1]-X3[1]A1[0]) to the sign function circuit 73_1.

[0060] The sign function circuit 73_1 determines whether the value (X3[0]A1[1]-X3[1]A1[0]) is positive or negative. If the value (X3[0]A1[1]-X3[1]A1[0]) is positive, the sign function circuit 73_1 outputs "1" to the adder 74. If the value (X3[0]A1[1]-X3[1]A1[0]) is negative, the sign function circuit 73_1 outputs "-1" to the adder 74.

[0061] Furthermore, the multiplier 71_(4k-1) multiplies the value X3[2k-1] by the value A1[2k], and outputs the result of the operation, the value X3[2k-1]A1[2k], to the adder 72_2k.

[0062] The multiplier 71_4k multiplies the value X3[2k] by the value A1[2k-1] and outputs the result of the operation, the value X3[2k]A1[2k-1], to the adder 72_2k.

[0063] The adder 72_2k subtracts the value X3[2k]A1[2k-1] from the value X3[2k-1]A1[2k]. The adder 72_2k outputs the operation result (X3[2k-1]A1[2k]-X3[2k]A1[2k-1]) to the sign function circuit 73_2k.

[0064] The sign function circuit 73_2k determines whether the value (X3[2k-1]A1[2k]-X3[2k]A1[2k-1]) is positive or negative. If the value (X3[2k-1]A1[2k]-X3[2k]A1[2k-1]) is positive, the sign function circuit 73_2k outputs "1" to the adder 74. If the value (X3[2k-1]A1[2k]-X3[2k]A1[2k-1]) is negative, the sign function circuit 73_2k outputs "-1" to the adder 74.

[0065] The explanations regarding the multipliers 71_(4k-1) and 71_4k, the adder 72_2k, and the sign function circuit 73_2k are valid for all k values ​​greater than or equal to 2 and less than or equal to (2n-1).

[0066] Similarly, the multiplier 71_(4n-1) multiplies the value X3[2n-1] by the value A1[2n], and outputs the result of the operation, the value X3[2n-1]A1[2n], to the adder 72_2n.

[0067] The multiplier 71_4n multiplies the value X3[2n] by the value A1[2n-1], and outputs the result of the operation, the value X3[2n]A1[2n-1], to the adder 72_2n.

[0068] The adder 72_2n subtracts the value X3[2n]A1[2n-1] from the value X3[2n-1]A1[2n]. The adder 72_2n outputs the operation result (X3[2n-1]A1[2n]-X3[2n]A1[2n-1]) to the sign function circuit 73_2n.

[0069] The sign function circuit 73_2n determines whether the value (X3[2n-1]A1[2n]-X3[2n]A1[2n-1]) is positive or negative. If the value (X3[2n-1]A1[2n]-X3[2n]A1[2n-1]) is positive, the sign function circuit 73_2n outputs "1" to the adder 74. If the value (X3[2n-1]A1[2n]-X3[2n]A1[2n-1]) is negative, the sign function circuit 73_2n outputs "-1" to the adder 74.

[0070] The adder 74 adds "1" or "-1" input from each of the 2n sign function circuits 73_1 to 73_2n. The adder 74 outputs the calculation result as a value PDO to the LF 80. The above is the configuration of the PD 70.

[0071] 1.3.3 LF (Loop Filter) Next, the internal configuration of the loop filter (LF80) included in the receiving circuit will be described. Fig. 5 is a block diagram showing an example of the configuration of the loop filter in the receiving circuit of the embodiment.

[0072] The LF 80 includes multipliers 81 and 82, adders 83 and 86, a clipping circuit 84, and delay circuits 85 and 87. The multiplier 82, the adder 83, the clipping circuit 84, and the delay circuit 85 function as an integrator.

[0073] The value PDO is input to the multiplier 81. The multiplier 81 multiplies the value PDO by a predetermined multiplier. The multiplier 81 outputs the result of the multiplication to the adder 86.

[0074] The multiplier 82 receives the value PDO as input. The multiplier 82 multiplies the value PDO based on a predetermined multiplier. The multiplier of the multiplier 82 may be equal to the multiplier of the multiplier 81. Alternatively, the multiplier of the multiplier 82 may be different from the multiplier of the multiplier 81. The multiplier 82 outputs the result of the multiplication to the adder 83.

[0075] The adder 83 adds the result of the calculation of the value PDO by the multiplier 82 to the value LFIO of the previous cycle fed back from the delay circuit 85. The adder 83 outputs the result of the addition to the clip circuit 84.

[0076] The clip circuit 84 performs clipping on the calculation result by the adder 83. The clip circuit 84 outputs the result of the clipping to the delay circuit 85. Specifically, if the calculation result by the adder 83 exceeds the upper limit value, the clip circuit 84 outputs the upper limit value to the delay circuit 85. If the calculation result by the adder 83 is below the lower limit value, the clip circuit 84 outputs the lower limit value to the delay circuit 85. If the calculation result by the adder 83 is equal to or greater than the lower limit value and equal to or less than the upper limit value, the clip circuit 84 outputs the calculation result by the adder 83 to the delay circuit 85.

[0077] The delay circuit 85 delays the result of the clipping process by the clipping circuit 84 by, for example, one period, and then outputs the result as a value LFIO to the adders 83 and 86. The value LFIO corresponds to the frequency deviation described above.

[0078] The adder 86 adds the value PDO multiplied by the multiplier 81, the value LFIO, and the value LFO of the previous cycle fed back from the delay circuit 87. The adder 86 outputs the result of the addition as the value LFO to the delay circuit 87 and the PIC90.

[0079] The delay circuit 87 delays the value LFO by, for example, one cycle, and then feeds it back to the adder 86. The above is the configuration of the LF 80.

[0080] 2. Operation of the embodiment Next, the operation of the receiving circuit in the receiving device of the embodiment will be described with reference to a flowchart of FIG.

[0081] When the analog processing circuit 10 starts receiving the signals S0 and / S0 (START), the ADC 20 samples and analog-to-digital (AD) converts the signals S1 and / S1 generated from the signals S0 and / S0 based on the signal CLKa to generate one cycle of the signal X0 (S1). The ADC 20 outputs one cycle of the signal X0 to the aligner 30 via n transmission paths.

[0082] Next, the aligner 30 converts one period of the signal X0 into a signal X1, and outputs it to the OGC 40 via 2n transmission paths (S2).

[0083] Next, the OGC 40 corrects the offset error and gain error for one cycle of the signal X1 to generate a signal X2. The OGC 40 outputs the signal X2 to the FFE 50 (S3). The clock signal CLKb is supplied to the OGC 40. The OGC 40 performs the above-described operation using the frequency of the clock signal CLKb as its operating frequency.

[0084] Next, the FFE50 shapes the waveform of one cycle of the signal X2. After that, the FFE50 extracts the signal X3 and data A1 embedded in the signal X2 from the waveform-shaped one cycle of the signal X2. The signal X3 is a signal related to the clock signal embedded in the signals S0 and / S0 by the host device 2. The FFE50 outputs the signal X3 and data A1 to the PD70 and the data processing circuit 60 (S4). The clock signal CLKb is supplied to the FFE50. The FFE50 performs the above-mentioned operation using the frequency of the clock signal CLKb as its operating frequency.

[0085] Next, the PD70 detects a phase shift of the signal CLKa based on one cycle of the signal X3 and the data A1. The PD70 generates a value PDO corresponding to the detected phase shift. The PD70 outputs the value PDO to the LF 80 (S5). The PD70 is supplied with a clock signal CLKb. The PD70 performs the above-mentioned operations using the frequency of the clock signal CLKb as its operating frequency.

[0086] Next, the LF80 accumulates the value PDO for one cycle to generate the value LFO. The value LFO is a value corresponding to the accumulated value of the phase shift of the signal CLKa for one cycle. The LF80 outputs the value LFO to the PIC90 (S6). The clock signal CLKc is supplied to the LF80. The LF80 performs the above operation using the frequency of the clock signal CLKc as its operating frequency.

[0087] Next, the PIC90 generates a control code PICO based on the value LFO. The control code PICO is a code that controls the generation of a signal PIO in the PI 110. The PIC90 outputs the control code PICO to the PI 110 (S7). The PIC90 is supplied with a clock signal CLKc, just like the LF80. The PIC90 performs the above operations using the frequency of the clock signal CLKc as its operating frequency.

[0088] Next, the PI 110 and the clock generation circuit 120 correct the phase shift of the signal CLKa based on the control code PICO (S8). More specifically, the PI 110 generates a signal PIO whose phase is adjusted using the reference clock signal REF in accordance with the control code PICO. The signal PIO is an n-phase signal whose phase is adjusted based on the control code PICO. The PI 110 outputs the signal PIO to the clock generation circuit 120. Subsequently, the clock generation circuit 120 regenerates the signal CLKa based on the signal PIO. That is, the clock generation circuit 120 generates the signal CLKa whose phase shift has been corrected based on the signal PIO. In other words, the clock generation circuit 120 regenerates the signal CLKa whose phase shift due to the frequency deviation has been reduced. The clock generation circuit 120 supplies the regenerated signal CLKa to the ADC 20.

[0089] Thereafter, the host interface circuit 8 determines whether or not reception of the signals S0 and / S0 has finished based on whether or not the signals S1 and / S1 have been input (S9).

[0090] If reception of the signals S0 and / S0 has not finished (S9; No), the ADC 20 generates the signal X0 of the next cycle based on the recovered signal CLKa (S1), and the processes of S1 to S9 are repeated (CDR loop) until reception of the signals S0 and / S0 finishes.

[0091] When the reception of the signals S0 and / S0 is completed (S9; Yes), the reception operation is completed (end).

[0092] As described above, the clock signal CLKb is supplied to the OGC 40, the FFE 50, the data processing circuit 60, and the PD 70. On the other hand, the clock signal CLKc is supplied to the LF 80 and the PIC 90. The clock signal CLKc has a frequency twice that of the clock signal CLKb. mThe clock signal CLKb has a frequency twice as high. For example, when m=1, the clock signal CLKb has a frequency of 0.8 GHz, and the clock signal CLKc has a frequency twice as high, 1.6 GHz. Therefore, the LF80 and PIC90 can operate at twice the speed of the OGC40, the FFE50, the data processing circuit 60, and the PD70. This allows the cycle for correcting the phase shift of the signal CLKa by the CDR loop to be faster. In other words, the phase shift of the signal CLKa can be corrected twice as frequently. This allows the phase shift due to the frequency deviation occurring in the signal CLKa supplied to the ADC20 to be further reduced.

[0093] 3. Effects of the embodiment According to the semiconductor integrated circuit and the receiving device of the embodiment, it is possible to preferably recover data based on a received signal.

[0094] The effects of the embodiment will be described in detail below.

[0095] In the embodiment, in the DSP 130, the circuits other than the LF 80 and the PIC 90 are operated at a first operating frequency of the clock signal CLKb, and the LF 80 and the PIC 90 are operated at a second operating frequency of the clock signal CLKc. The second operating frequency is twice the first operating frequency. m This is a factor of 2 to the mth power, where m is an integer equal to or greater than 1. This allows for faster integration of phase shifts by the LF80 and faster output of control codes for correcting phase shifts by the PIC90. This also allows for faster timing for correcting the phase shift of the clock signal CLKa supplied to the ADC20. As a result, it is possible to reduce the phase shift caused by the frequency deviation of the clock signal CLKa, making it possible to properly recover data from the received signal.

[0096] 7 and 8 show an example of the relationship between signals S1 and / S1 and clock signal CLKa during AD conversion by the ADC. FIG. 7 is a timing chart showing the relationship between signals S1 and / S1 and clock signal CLKa in the ADC 20 of the embodiment. FIG. 8 is a timing chart showing the relationship between signals S1 and / S1 and clock signal CLKa in an ADC of a comparative example. As described above as the operation of this embodiment, FIG. 7 shows the case where the frequency of signal CLKc is twice the frequency of signal CLKb, while FIG. 8 shows the case where the frequency of signal CLKc is the same as that of signal CLKb. In FIGS. 7 and 8, D0-0, D0-1, ..., D0-79 correspond to the data contained in signals S1 and / S1. The frequency deviation between successive clock signals CLKa is +400 ppm.

[0097] As shown in Fig. 8, during AD conversion of signals S1 and / S1, in the comparative example, a phase shift due to the frequency deviation of 80 clock signals CLKa is accumulated. In contrast, as shown in Fig. 7, in the embodiment, the phase shift due to the accumulated frequency deviation is updated every 40 clock signals CLKa, that is, the phase shift of clock signal CLKa is corrected every 40 clock signals CLKa. As a result, as described above, it is possible to reduce the phase shift due to the frequency deviation occurring in clock signal CLKa, and it is possible to preferably recover data from the received signal.

[0098] In addition, in the embodiment, only the LF80 and PIC90 in the DSP 130 are operated at the second operating frequency, which is higher, and the circuits other than the LF80 and PIC90 are operated at the first operating frequency, which is lower than the second operating frequency. This makes it possible to ease the constraints on operation timing compared to when almost all the circuits in the DSP 130 are operated at the second operating frequency, which is higher.

[0099] Furthermore, in the embodiment, the clock signal CLKb that operates the circuits other than the LF80 and PIC90 in the DSP 130 is generated using the signal PIO that is generated based on the reference clock signal REF. Therefore, it is easy to generate the clock signal CLKc that is supplied to the LF80 and PIC90 using the signal PIO.

[0100] 4.Other Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0101] 1. Information processing system 2...Host device 3. Memory system 4...Memory device 5...Memory controller 6...Control unit 7...Buffer memory 8...Host interface circuit 9...Memory interface circuit 10...Analog processing circuit 20...Analog-to-digital conversion circuit (ADC) 30...Aligners 40...Offset and gain correction circuit (OGC) 50...Feed-forward equalizer (FFE) 60...Data processing circuit 70...Phase detection circuit (PD) 71...Multiplier 72...Adder 73...Sign function circuit 74...Adder 80...Loop filter (LF) 81...Multiplier 82...Multiplier 83...adder 84...Clip circuit 85...Delay circuit 86...adder 87...Delay circuit 90...Phase Interpolator Controller (PIC) 100…Phase-locked loop circuit (PLL) 110...Phase interpolator (PI) 120...Clock generation circuit 130...Digital signal processor (DSP) 131...First digital processing circuit 132...Second digital processing circuit CLKa...clock signal CLKb: Clock signal CLKc: Clock signal

Claims

1. a first converter for sampling a first digital value from an analog signal based on a first clock signal; a second converter for sampling a second digital value from the analog signal based on a second clock signal that is a first phase shift from the first clock signal; a first processing circuit that uses a first frequency of a third clock signal as an operating frequency and calculates a phase shift between the first clock signal and the second clock signal based on the first digital value and the second digital value; The fourth clock signal has a second frequency of the first frequency. ｍ a second processing circuit that uses a second frequency that is m times (m is an integer equal to or greater than 1) as an operating frequency and generates a control signal that corrects a phase shift between the first clock signal and the second clock signal based on the phase shift calculated by the first processing circuit; A semiconductor integrated circuit comprising:

2. The first processing circuit a first circuit that generates a first signal and a second signal from the first digital value and the second digital value, respectively, using the first frequency of the third clock signal as an operating frequency; a second circuit that uses the first frequency of the third clock signal as an operating frequency and detects the phase shift between the first clock signal and the second clock signal from the first signal and the second signal; Including, 2. The semiconductor integrated circuit according to claim 1.

3. The second processing circuit a third circuit that uses the second frequency of the fourth clock signal as an operating frequency to integrate the phase shift detected by the second circuit and calculates an integrated value of the phase shift; a fourth circuit that uses the second frequency of the fourth clock signal as an operating frequency and generates the control signal according to the integrated value calculated by the third circuit; Including, 3. The semiconductor integrated circuit according to claim 2.

4. a first circuit that generates a third signal for correcting a phase shift between the first clock signal and the second clock signal based on the control signal; a second circuit that generates the first clock signal and the second clock signal, the phase shift of which has been corrected, based on the third signal; Further provided with 2. The semiconductor integrated circuit according to claim 1.

5. the first processing circuit includes a circuit for correcting an offset error and a gain error included in the first digital value and the second digital value; 2. The semiconductor integrated circuit according to claim 1.

6. the second frequency of the fourth clock signal is twice the first frequency of the third clock signal; 2. The semiconductor integrated circuit according to claim 1.

7. A semiconductor integrated circuit according to any one of claims 1 to 6; a control circuit for controlling processing of signals output from the semiconductor integrated circuit; A receiving device comprising:

8. Sampling a first digital value from the analog signal based on a first clock signal; sampling a second digital value from the analog signal based on a second clock signal that is a first phase shift from the first clock signal; calculating a phase shift between the first clock signal and the second clock signal based on the first digital value and the second digital value, using a first frequency of a third clock signal as an operating frequency; The fourth clock signal has a second frequency of the first frequency. ｍ generating a control signal for correcting the phase shift between the first clock signal and the second clock signal based on the calculated phase shift, using a second frequency that is m times m (m is an integer equal to or greater than 1) as an operating frequency; A receiving method comprising:

Images