Semiconductor storage device

Abstract

To provide a semiconductor storage device capable of increasing integration density.SOLUTION: A semiconductor storage device according to an embodiment comprises: a structure including a laminate 20 in which a plurality of conductive layers 21 are stacked spaced apart from each other in a first direction; a plate-like structure 40 extending at least to a height level corresponding to the lower surface of the laminate in the first direction and a second direction crossing the first direction in the structure; a first pillar structure functioning as a NAND string and having a structure in which a plurality of layers are stacked from the outer peripheral surface toward the inside; and a second pillar structure 32 not functioning as the NAND string and having a structure in which the plurality of layers are stacked from the outer peripheral surface toward the inside. The material of each layer of the plurality of layers of the second pillar structure is the same as the material of each layer of the plurality of layers of the first pillar structure. A part of the side surface of the plate-like structure aligns with a part of the side surface of the second pillar structure and includes a recess based on a part of the side surface of the second pillar structure.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device. [Background technology]

[0002] In a three-dimensional NAND type nonvolatile semiconductor memory device in which a plurality of memory cells are stacked on a semiconductor substrate, it is desired to increase the degree of integration. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-107673 [Patent Document 2] Japanese Patent Application Laid-Open No. 2010-192531 [Patent Document 3] U.S. Patent Application Publication No. 2020 / 0303397 [Patent Document 4] US Patent Application Publication No. 2015 / 0194435 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device capable of increasing the degree of integration is provided. [Means for solving the problem]

[0005] The semiconductor memory device according to the embodiment includes a structure including a stacked body in which a plurality of conductive layers are stacked in a first direction at a distance from each other, a plate-like structure extending in the structure in the first direction and in a second direction intersecting the first direction to a height level corresponding to at least the height level of the lower surface of the stacked body, a first pillar structure extending in the first direction in the stacked body and functioning as a NAND string, the first pillar structure having a structure in which a plurality of layers including a first semiconductor layer and extending in the first direction are stacked from an outer peripheral surface side toward an inside, and a NAND string extending in the structure in the first direction. A semiconductor memory device comprising: a second pillar structure that does not function as a D-string, the second pillar structure having a structure in which a plurality of layers including a second semiconductor layer and extending in the first direction are stacked from the outer peripheral surface side toward the inside, wherein the material of each of the plurality of layers in the second pillar structure extending from the outer peripheral surface side toward the inside is the same as the material of each of the plurality of layers in the first pillar structure extending from the outer peripheral surface side toward the inside, and a portion of the side of the plate-like structure is aligned with a portion of the side of the second pillar structure and includes a recess based on the portion of the side of the second pillar structure. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a diagram schematically illustrating the overall configuration of a semiconductor memory device according to a first embodiment. [Figure 2] 1 is a cross-sectional view schematically showing a part of the configuration of a memory area of ​​a semiconductor memory device according to a first embodiment. [Figure 3] 2 is a planar pattern diagram schematically showing a part of the configuration of a memory area of ​​the semiconductor memory device according to the first embodiment. FIG. [Figure 4] 2 is a cross-sectional view schematically showing a detailed configuration of a memory cell unit of the semiconductor memory device according to the first embodiment. FIG. [Figure 5] 2 is a cross-sectional view schematically showing a detailed configuration of a memory cell unit of the semiconductor memory device according to the first embodiment. FIG. [Figure 6]2 is a cross-sectional view schematically showing a part of the configuration of the staircase region of the semiconductor memory device according to the first embodiment. FIG. [Figure 7] 3 is a planar pattern diagram schematically showing a part of the configuration of the staircase region of the semiconductor memory device according to the first embodiment. FIG. [Figure 8] 3 is a cross-sectional view schematically showing a detailed configuration of a pillar structure and the like in a flat portion of a stack of the semiconductor memory device according to the first embodiment. FIG. [Figure 9] 3 is a cross-sectional view schematically showing a detailed configuration of a pillar structure and the like in a flat portion of a stack of the semiconductor memory device according to the first embodiment. FIG. [Figure 10A] 3A to 3C are cross-sectional views schematically showing a part of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10B] 3A to 3C are cross-sectional views schematically showing a part of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10C] 3A to 3C are cross-sectional views schematically showing a part of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10D] 3A to 3C are cross-sectional views schematically showing a part of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10E] 3A to 3C are cross-sectional views schematically showing a part of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10F] 3A to 3C are cross-sectional views schematically showing a part of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10G] 3A to 3C are cross-sectional views schematically showing a part of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10H] 3A to 3C are cross-sectional views schematically showing a part of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 11] FIG. 10 is a cross-sectional view schematically showing a part of the configuration of a memory area of ​​a semiconductor memory device according to a second embodiment. [Figure 12] FIG. 10 is a cross-sectional view schematically showing a part of the configuration of a staircase region of a semiconductor memory device according to a second embodiment. [Figure 13A]10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 13B] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 13C] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 13D] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 13E] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 13F] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 13G] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 13H] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 13I] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 13J] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 13K] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 13L] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 13M] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 13N] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 14] FIG. 10 is a cross-sectional view schematically showing a part of the configuration of a memory area of ​​a semiconductor memory device according to a third embodiment. [Figure 15]FIG. 10 is a cross-sectional view schematically showing a part of the configuration of a staircase region of a semiconductor memory device according to a third embodiment. [Figure 16] FIG. 10 is a planar pattern diagram schematically showing a part of the configuration of a staircase region of a semiconductor memory device according to a third embodiment. [Figure 17] 10 is a cross-sectional view schematically showing a detailed configuration of a pillar structure portion and the like in a flat portion of a stack of a semiconductor memory device according to a third embodiment. FIG. [Figure 18] 10 is a cross-sectional view schematically showing a detailed configuration of a pillar structure portion and the like in a flat portion of a stack of a semiconductor memory device according to a third embodiment. FIG. [Figure 19A] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 19B] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 19C] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 19D] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 19E] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 19F] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 19G] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 19H] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 19I] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 19J] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 19K]10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 19L] 10A to 10C are cross-sectional views schematically showing a part of a method for manufacturing a semiconductor memory device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment will be described with reference to the drawings.

[0008] (First embodiment) FIG. 1 is a diagram schematically showing the overall configuration of a semiconductor memory device (NAND-type nonvolatile semiconductor memory device) according to the first embodiment.

[0009] The semiconductor memory device of this embodiment includes a memory region 100 and a staircase region 200 aligned in the Y direction. The memory region 100 and the staircase region 200 are provided with a stacked body and the like, which will be described later.

[0010] The memory region 100 is partitioned into a plurality of blocks in the X direction by a plurality of plate-like structures 40, each extending in the Y direction and the Z direction within the stack. Each block is provided with a plurality of pillar structures, each extending in the Z direction within the stack, as will be described later.

[0011] The staircase region 200 includes a portion of the laminate processed into a staircase shape. In the staircase region 200 shown in FIG. 1, three staircase-processed regions are arranged in the X direction. Each of the three staircase-processed regions includes a staircase portion processed into a staircase shape along the X direction and a staircase portion processed into a staircase shape along the Y direction. In the three staircase-processed regions, a valley-shaped staircase is provided from the outside to the inside. In other words, in the three regions, the height of the laminate is lower on the inside than on the outside.

[0012] In addition, a plurality of plate-like structures 40 extend from the memory region 100 into the staircase region 200, and each of the three regions described above is divided into two parts in the X direction by the plate-like structures 40 extending in the Y direction. The staircase region 200 is provided with a plurality of pillar structures, each extending in the Z direction, as will be described later.

[0013] The X, Y, and Z directions intersect with each other, specifically, the X, Y, and Z directions are perpendicular to each other.

[0014] Furthermore, although the following description shows a case where the stairs are simply ascending or descending, stairs having both ascending and descending sections may also be used.

[0015] 2 is a cross-sectional view schematically showing a part of the configuration of the memory region 100. FIG. 3 is a planar pattern diagram schematically showing a part of the configuration of the memory region 100.

[0016] In the memory region 100, a stacked body 20, a plurality of pillar structures 31, a plurality of plate-like structures 40, etc. are provided on a lower region 10 including a semiconductor or the like that functions as at least a part of a source line for a NAND string.

[0017] The laminate 20 includes a plurality of conductive layers 21 stacked at intervals in the Z direction. More specifically, the laminate 20 includes a plurality of conductive layers 21 and a plurality of insulating layers 22 stacked alternately in the Z direction.

[0018] Each conductive layer 21 functions as a word line or a select gate line for the NAND string. Each insulating layer 22 has the function of insulating adjacent conductive layers 21. The conductive layers 21 are made of a metal material such as tungsten, and the insulating layers 22 are made of an insulating material such as silicon oxide.

[0019] Of the plurality of conductive layers 21, one or more conductive layers 21 on the lower layer side, including the bottom conductive layer 21, function as source-side select gate lines, and one or more conductive layers 21 on the upper layer side, including the top conductive layer 21, function as drain-side select gate lines. The plurality of conductive layers 21 provided between the source-side select gate lines and the drain-side select gate lines function as word lines.

[0020] Each pillar structure 31 extends in the Z direction within the stack 20, reaching the lower region 10, and functions as a main portion of a NAND string. The pillar structure 31 includes a semiconductor layer connected to a semiconductor in the lower region 10 that functions as a source line, and has a structure in which multiple layers extending in the Z direction are stacked from the outer periphery side of the pillar structure 31 toward the inside. Furthermore, the entire pillar structure 31 is separated from the adjacent plate-like structure 40. Specifically, the pillar structure 31 and the adjacent plate-like structure 40 are separated from each other by multiple conductive layers 21 and multiple insulating layers 22.

[0021] The pillar structure 31 is surrounded by a plurality of conductive layers 21 and a plurality of insulating layers 22, and a NAND string is formed by the pillar structure 31 and the plurality of conductive layers 21 surrounding the pillar structure 31. More specifically, a memory cell is formed by the conductive layer 21 functioning as a word line and a portion of the pillar structure 31 surrounded by the conductive layer 21 functioning as the word line. Furthermore, a select transistor is formed by the conductive layer 21 functioning as a select gate line and a portion of the pillar structure 31 surrounded by the conductive layer 21 functioning as the select gate line.

[0022] 4 and 5 are cross-sectional views schematically showing the detailed configuration of a memory cell portion formed by the conductive layer 21 and the pillar structure 31. Fig. 4 is a cross-sectional view parallel to the Z direction, and Fig. 5 is a cross-sectional view perpendicular to the Z direction.

[0023] The pillar structure 31 includes a semiconductor layer 31a, a tunnel insulating layer 31b, a charge storage layer 31c, a block insulating layer 31d, and a core insulating layer 31e, and these multiple layers 31a to 31e extend in the Z direction. The pillar structure 31 has a structure in which the block insulating layer 31d, the charge storage layer 31c, the tunnel insulating layer 31b, the semiconductor layer 31a, and the core insulating layer 31e are stacked in this order from the outer circumferential surface side of the pillar structure 31 toward the inside.

[0024] The semiconductor layer 31a, tunnel insulating layer 31b, charge storage layer 31c, and block insulating layer 31d all have a cylindrical shape, and the core insulating layer 31e has a columnar shape. Specifically, the semiconductor layer 31a surrounds the side surface of the core insulating layer 31e, the tunnel insulating layer 31b surrounds the side surface of the semiconductor layer 31a, the charge storage layer 31c surrounds the side surface of the tunnel insulating layer 31b, and the block insulating layer 31d surrounds the side surface of the charge storage layer 31c.

[0025] For example, the semiconductor layer 31a is formed of silicon, the tunnel insulating layer 31b is formed of silicon oxide, the charge storage layer 31c is formed of silicon nitride, the block insulating layer 31d is formed of silicon oxide, and the core insulating layer 31e is formed of silicon oxide.

[0026] The conductive layer 21 includes a metal layer 21a made of a metal material such as tungsten or molybdenum, and a barrier metal layer 21b made of titanium nitride, etc. On the outside of the conductive layer 21, a metal oxide layer 25 made of aluminum oxide, etc. is provided.

[0027] 2 and 3, each plate-like structure 40 extends in the Y and Z directions within the stack 20 at least to a height level corresponding to the height level of the lower surface of the stack 20. Specifically, each plate-like structure 40 extends in the Z direction, penetrating the lowest conductive layer 21 and the lowest insulating layer 22, to an insulating portion 60 provided in the surface region of the lower region 10. As shown in FIG. 1, a plurality of plate-like structures 40 are arranged in the X direction, and the plurality of plate-like structures 40 divide the plurality of pillar structures 31 into a plurality of blocks in the X direction. The plate-like structures 40 are formed by filling slits (grooves) used in the replacement process described below with a predetermined material (e.g., tungsten).

[0028] An insulating portion 50 including insulating layers 51, 52, and 53 is provided on the stacked body 20 and the pillar structure 31. These insulating layers 51, 52, and 53 are made of silicon oxide or the like.

[0029] Fig. 6 is a cross-sectional view schematically showing part of the configuration of the staircase region 200. Fig. 7 is a planar pattern diagram schematically showing part of the configuration of the staircase region 200.

[0030] In the staircase region 200, a stacked body 20, a plurality of pillar structures 32, a plurality of plate-like structures 40, an insulating layer 70, and the like are provided on the lower region 10.

[0031] The stack 20 is provided continuously from the memory region 100, and as already described, includes a plurality of conductive layers 21 and a plurality of insulating layers 22 alternately stacked in the Z direction. However, as already described, the stack 20 in the staircase region 200 includes a portion processed in a staircase shape along the X direction and a portion processed in a staircase shape along the Y direction. FIGS. 6 and 7 show a region including a staircase portion 20ST processed in a staircase shape along the X direction. The stack 20 in the staircase region 200 also includes a flat portion 20FT extending flat in the X direction from the top surface of the staircase portion 20ST of the stack 20.

[0032] Each pillar structure 32 extends in the Z direction within a structure including the stack 20 and the insulating layer 70, reaching the lower region 10. More specifically, the staircase region 200 is provided with pillar structures 32 (two pillar structures 32 shown on the right side in FIG. 6) that extend in the Z direction through the flat portion 20FT of the stack 20, and pillar structures 32 (two pillar structures 32 shown on the left side in FIG. 6) that extend in the Z direction through the staircase portion 20ST of the stack 20. The pillar structures 32 that extend in the Z direction through the staircase portion 20ST also include portions that extend in the Z direction within the insulating layer 70 that cover the ends of the staircase portion 20ST.

[0033] The relationship between the pattern of the pillar structures 32 and the pattern of the plate-like structures 40 in the flat portion 20FT is substantially the same as the relationship between the pattern of the pillar structures 32 and the pattern of the plate-like structures 40 in the staircase portion 20ST. Therefore, in Fig. 7, the pattern of the flat portion 20FT and the pattern of the staircase portion 20ST are shown in a common diagram.

[0034] The pillar structures 32 provided in the staircase region 200 are provided to support a preliminary stacked body, which will be described later, in the replacement process, and do not function as NAND strings.

[0035] Furthermore, unlike the pillar structures 31 provided in the memory region 100, the pillar structures 32 include portions that are not substantially separated from the adjacent plate-like structures 40. That is, in the staircase region 200, a portion of the side surface of the plate-like structure 40 is aligned with a portion of the side surface of the pillar structure 32, and has a recess based on the portion of the side surface of the pillar structure 32 (a recess based on the shape of the portion of the side surface of the pillar structure 32). Specifically, a portion of the side surface of the plate-like structure 40 along the Y direction and the Z direction is aligned with a portion of the side surface of the pillar structure 32, and includes a recess based on the portion of the side surface of the pillar structure 32. From another perspective, as shown in FIG. 7 , when viewed from the Z direction, the pattern of the plate-like structure 40 includes a recess based on the pattern of the pillar structure 32.

[0036] The pillar structure 32 has a structure in which a plurality of layers including a semiconductor layer and extending in the Z direction are stacked from the outer periphery side of the pillar structure 32 toward the inside.

[0037] 8 and 9 are cross-sectional views schematically showing the detailed configuration of pillar structures 32 and the like in flat portion 20FT of laminate 20. Fig. 8 is a cross-sectional view parallel to the Z direction, and Fig. 9 is a cross-sectional view perpendicular to the Z direction. The basic configuration of pillar structures 32 in staircase portion 20ST of laminate 20 is also substantially the same as the configuration of pillar structures 32 shown in Figs. 8 and 9.

[0038] The pillar structure 32 includes a semiconductor layer 32a, a tunnel insulating layer 32b, a charge storage layer 32c, a block insulating layer 32d, and a core insulating layer 32e, and these multiple layers 32a to 32e extend in the Z direction. The pillar structure 32 has a structure in which the block insulating layer 32d, the charge storage layer 32c, the tunnel insulating layer 32b, the semiconductor layer 32a, and the core insulating layer 32e are stacked in this order from the outer circumferential surface side of the pillar structure 32 toward the inside.

[0039] The semiconductor layer 32a, tunnel insulating layer 32b, charge storage layer 32c, and block insulating layer 32d all have a cylindrical shape, and the core insulating layer 32e has a columnar shape. Specifically, the semiconductor layer 32a surrounds the side surface of the core insulating layer 32e, the tunnel insulating layer 32b surrounds the side surface of the semiconductor layer 32a, the charge storage layer 32c surrounds the side surface of the tunnel insulating layer 32b, and the block insulating layer 32d surrounds the side surface of the charge storage layer 32c.

[0040] Furthermore, the materials of the multiple layers 32a, 32b, 32c, 32d, and 32e of the pillar structure 32 are the same as the materials of the multiple layers 31a, 31b, 31c, 31d, and 31e of the pillar structure 31. That is, the semiconductor layer 32a, the tunnel insulating layer 32b, the charge storage layer 32c, the block insulating layer 32d, and the core insulating layer 32e are formed of the same materials as the semiconductor layer 31a, the tunnel insulating layer 31b, the charge storage layer 31c, the block insulating layer 31d, and the core insulating layer 31e, respectively.

[0041] In addition, a sidewall insulating layer 41 made of silicon oxide is provided on the side surface of the plate-like structure 40 .

[0042] As described above, the basic configuration of the pillar structure 32 is the same as the basic configuration of the pillar structure 31. Note that the thickness of each layer of the pillar structure 31 and the thickness of the corresponding layer of the pillar structure 32 may be the same or different.

[0043] Returning to the explanation of Figures 6 and 7, each plate-like structure 40 extends in the Y and Z directions within a structure including the laminate 20 and the insulating layer 70 to a height level corresponding to at least the height level of the lower surface of the laminate 20.

[0044] Specifically, in the flat portion 20FT of the laminate 20, each plate-like structure 40 extends in the Y and Z directions within the laminate 20, similar to the memory region 100, at least to a height level corresponding to the height level of the lower surface of the laminate 20. More specifically, each plate-like structure 40 extends in the Z direction through the lowest conductive layer 21 and the lowest insulating layer 22 to reach the insulating portion 60 provided in the surface region of the lower region 10.

[0045] In the stepped portion 20ST of the laminate 20, each plate-like structure 40 extends in the Y direction and the Z direction within the insulating layer 70 or within a structure including the laminate 20 and the insulating layer 70 to a height level corresponding to at least the height level of the lower surface of the laminate 20. More specifically, each plate-like structure 40 extends in the Z direction through the stepped portion of the laminate 20 along the Y direction and the insulating layer 70 covering this portion, until it reaches the insulating portion 60 provided in the surface region of the lower region 10.

[0046] Similar to FIG. 2, an insulating portion 50 including insulating layers 51, 52 and 53 is provided on the stack 20 and the pillar structure 32.

[0047] Next, a method for manufacturing a semiconductor memory device according to this embodiment will be described with reference to Figures 10A to 10H. Note that Figures 10A to 10H schematically show the steps of forming the staircase region 200, but the same steps are also performed for the memory region.

[0048] First, as shown in FIG. 10A, a structure including a preliminary stack 20p, an insulating layer 51, and an insulating layer 70 is formed on the lower region 10. The preliminary stack 20p has a structure in which a plurality of insulating layers 22 and a plurality of sacrificial layers 23 are alternately stacked in the Z direction. The insulating layer 22 is formed of silicon oxide, and the sacrificial layer 23 is formed of silicon nitride. The insulating layer 70 is formed so as to cover the stepped ends of the preliminary stack 20p that face each other. In this process, the preliminary stack 20p and the like are similarly formed in the memory region 100.

[0049] 10B, the resist pattern R11 is used as a mask to etch the preliminary stack 20p, the insulating layer 51, and the insulating layer 70 by RIE (reactive ion etching), thereby forming a trench T11 extending in the Y direction. At this time, the surface region of the lower region 10 is also etched, so that the position of the bottom of the trench T11 is lower than the position of the upper surface of the lower region 10. Furthermore, an insulating portion 60 is formed near the bottom of the trench T11. In this process, a trench similar to the trench T11 is also formed in the memory region 100.

[0050] Next, as shown in FIG. 10C, after removing the resist pattern R11, a sacrificial layer S11 is formed on the structure obtained in the step of FIG. 10B. Amorphous silicon is used for the sacrificial layer S11. Subsequently, the sacrificial layer S11 is etched back to obtain a structure in which the trench T11 is filled with the sacrificial layer S11. Furthermore, an insulating layer 52 is formed on the structure thus obtained. In this step, a sacrificial layer similar to the sacrificial layer S11 is also formed in the memory region 100.

[0051] Next, as shown in FIG. 10D, the resist pattern R12 is used as a mask to etch the preliminary stack 20p and the insulating layers 51, 52, and 70 by RIE to form a hole H11. In this etching process, a portion of the sacrificial layer S11 is also etched, changing the shape of the sacrificial layer S11. The surface region of the lower region 10 is also etched, so that the bottom of the hole H11 is lower than the upper surface of the lower region 10. In this process, a hole similar to the hole H11 is also formed in the memory region 100. However, the sacrificial layer corresponding to the sacrificial layer S11 in the memory region 100 is not etched.

[0052] Next, as shown in FIG. 10E, after removing the resist pattern R12, pillar structures 32 are formed in the holes H11. Because a portion of the side surface of the sacrificial layer S11 is exposed by the etching process of FIG. 10D, a portion of the side surface of the pillar structure 32 and a portion of the side surface of the sacrificial layer S11 are aligned with each other. Furthermore, an insulating layer 53 is formed on the structure thus obtained. In this process, pillar structures 31 are similarly formed in the memory region 100. However, in the memory region 100, the pillar structures 31 and the sacrificial layer S11 are spaced apart from each other.

[0053] Next, as shown in FIG. 10F, the insulating layer 52 and the insulating layer 53 are etched using the resist pattern R13 as a mask to expose the upper surface of the sacrificial layer S11.

[0054] Next, as shown in FIG. 10G, after removing the resist pattern R13, the sacrificial layer S11 is removed by wet etching to form a trench T12. This exposes a portion of the side surface of the pillar structure 32. In this process, a trench similar to the trench T12 is also formed in the memory region 100. However, in the memory region 100, the side surface of the pillar structure 31 is not exposed.

[0055] Next, as shown in FIG. 10H, the sacrificial layers 23 are etched through the trenches T12 to form spaces. The spaces are then filled with conductive layers 21, such as tungsten layers. This completes the replacement process of replacing the sacrificial layers 23 with the conductive layers 21. As a result, a stacked body 20 is formed in which a plurality of conductive layers 21 and a plurality of insulating layers 22 are alternately stacked. In this process, a similar replacement process is performed in the memory region 100 to form the stacked body 20.

[0056] Thereafter, the grooves T12 are filled with a metal material such as tungsten to form the plate-like structures 40, thereby obtaining the structures shown in Figures 6 and 7. In addition, in the memory region 100, the structures shown in Figures 2 and 3 are obtained.

[0057] As described above, in this embodiment, the pillar structures 32 provided in the staircase region 200 and not functioning as NAND strings include portions that are not substantially separated from the adjacent plate-like structures 40. That is, a portion of the side surface of the plate-like structure 40 is aligned with a portion of the side surface of the pillar structure 32 and includes a recess based on the portion of the side surface of the pillar structure 32. Therefore, the pillar structures 32 can be provided adjacent to the plate-like structure 40, which makes it possible to increase the integration density of the semiconductor memory device. Furthermore, the pillar structures 32 provided adjacent to the plate-like structure 40 have an improved function of supporting the preliminary stack 20p, in which multiple spaces are formed, during the replacement process.

[0058] In this embodiment, the basic configuration of the pillar structures 32 provided in the staircase region 200 is the same as the basic configuration of the pillar structures 31 provided in the memory region 100 and functioning as NAND strings. Therefore, the pillar structures 32 and the pillar structures 31 can be formed in the same process.

[0059] In this embodiment, a sacrificial layer S11 is formed in the region where the plate-like structure 40 is to be formed, the pillar structure 32 is formed with the sacrificial layer S11 formed, and then the plate-like structure 40 is formed in the groove T12 obtained by removing the sacrificial layer S11. Therefore, as described below, it is possible to accurately form the structure described above.

[0060] If, without forming the sacrificial layer S11, pillar structures 32 having the same basic configuration as pillar structures 31 were formed, and then the plate-like structures 40 were formed so as not to be substantially spaced apart from the pillar structures 32, there is a risk that part of the pillar structures 32 would be damaged by RIE when forming grooves for forming the plate-like structures 40. As a result, there is a risk that an accurate pillar structure 32 would not be obtained. It is also possible to form the pillar structures 32 from silicon oxide or the like, but in this case, there is a risk that the pillar structures 32 would shrink due to heat treatment or the like, and the upper surface of the structure including the stacked body 20 and the insulating layer 70 in the staircase region 200 would sink with respect to the upper surface of the stacked body 20 in the memory region 100.

[0061] In this embodiment, by using the method described above, it is possible to form the plate-like structure 40 without damaging the pillar structure 32. That is, because the sacrificial layer S11 can be easily removed by wet etching or the like, it is possible to form the groove T12 without damaging the pillar structure 32. Therefore, it is possible to accurately form the pillar structure 32 and the plate-like structure 40. Furthermore, by forming the pillar structure 32 including the semiconductor layer 32a that is resistant to shrinkage even by heat treatment or the like, it is possible to suppress sinking of the structure including the stacked body 20 and the insulating layer 70 in the staircase region 200.

[0062] (Second embodiment) Next, a semiconductor memory device (NAND type nonvolatile semiconductor memory device) according to a second embodiment will be described. Note that the basic features are the same as those of the first embodiment, and therefore the description of the features described in the first embodiment will be omitted.

[0063] The overall configuration of the semiconductor memory device according to this embodiment is the same as that shown in FIG. 1, and a description thereof will be omitted.

[0064] 11 is a cross-sectional view schematically showing a part of the configuration of the memory region 100. A planar pattern diagram schematically showing a part of the configuration of the memory region 100 is the same as FIG. 3 of the first embodiment, and therefore is not shown.

[0065] Fig. 12 is a cross-sectional view schematically showing part of the configuration of the staircase region 200. A planar pattern diagram schematically showing part of the configuration of the staircase region 200 is the same as Fig. 7 of the first embodiment, and therefore is not shown.

[0066] 11 and 12, in this embodiment, the laminate 20 includes a laminate portion 20L and a laminate portion 20U provided on the upper side of the laminate portion 20L. Also, the plate-like structure 40 includes a plate-like structure portion 40L and a plate-like structure portion 40U provided on the upper side of the plate-like structure portion 40L.

[0067] In the memory region 100, the pillar structure 31 includes a pillar structure portion 31L and a pillar structure portion 31U provided on the upper side of the pillar structure portion 31L. In the staircase region 200, the pillar structure 32 includes a pillar structure portion 32L and a pillar structure portion 32U provided on the upper side of the pillar structure portion 32L.

[0068] The basic configurations and functions of the laminate 20, the pillar structures 31, the pillar structures 32 and the plate-like structures 40 are the same as those in the first embodiment.

[0069] In the staircase region 200, a flat portion 20FT and a staircase portion 20ST are provided in each of the laminated portion 20L and the laminated portion 20U. The end of the staircase portion 20ST in the laminated portion 20L is covered with an insulating layer 70L, and the end of the staircase portion 20ST in the laminated portion 20U is covered with an insulating layer 70U.

[0070] An intermediate insulating portion 50a is provided between the laminated portion 20L and the laminated portion 20U, and separates the laminated portion 20L from the laminated portion 20U. The intermediate insulating portion 50a includes insulating layers 51, 52, and 53. The thickness of the intermediate insulating portion 50a is greater than the thickness of the conductive layer 21 and the thickness of the insulating layer 22. Furthermore, an upper insulating portion 50b is provided on the laminated portion 20U, the pillar structure portion 31U, and the pillar structure portion 32U. The upper insulating portion 50b includes insulating layers 55, 56, and 57. These insulating layers 51, 52, 53, 55, 56, and 57 are formed of silicon oxide or the like.

[0071] The relationship between the stacked portion 20L, the pillar structure portion 31L, and the plate-like structure portion 40L, and the relationship between the stacked portion 20U, the pillar structure portion 31U, and the plate-like structure portion 40U are all similar to the relationship between the stacked body 20, the pillar structure 31, and the plate-like structure 40 of the first embodiment. Therefore, the configurations of the pillar structure portion 31L, etc. and the pillar structure portion 31U, etc. in the memory region 100 are all similar to the configurations of the pillar structure 31, etc. of the first embodiment shown in FIGS. 4 and 5.

[0072] The relationships among the laminate portion 20L, the pillar structure portion 32L, the plate-like structure portion 40L, and the insulating layer 70L, and the relationships among the laminate portion 20U, the pillar structure portion 32U, the plate-like structure portion 40U, and the insulating layer 70U are all similar to the relationships among the laminate 20, the pillar structure 32, the plate-like structure 40, and the insulating layer 70 of the first embodiment. Therefore, the configurations of the pillar structure portions 32L, etc. and the pillar structure portions 32U, etc. in the staircase region 200 are all similar to the configurations of the pillar structures 32, etc. of the first embodiment shown in FIGS. 8 and 9.

[0073] Next, a method for manufacturing a semiconductor memory device according to this embodiment will be described with reference to Figures 13A to 13N. Figures 13A to 13N schematically show the steps of forming the staircase region 200. In the following description, the memory region will not be mentioned, but as in the first embodiment, the memory region is also formed using the same steps as the steps of forming the staircase region 200.

[0074] The step of Fig. 13A is the same as the step of Fig. 10A in the first embodiment, that is, a structure including a preliminary laminate portion 20Lp, an insulating layer 51, and an insulating layer 70L is formed on the lower region 10.

[0075] 13B is the same as the step of the first embodiment shown in FIG. 10B. That is, using the resist pattern R21 as a mask, the preliminary stacked portion 20Lp, the insulating layer 51, and the insulating layer 70L are etched by RIE to form a trench T21 extending in the Y direction.

[0076] The step of Fig. 13C is the same as the step of Fig. 10C in the first embodiment. That is, a structure is formed in which the trench T21 is filled with the sacrificial layer S21, and then the insulating layer 52 is formed.

[0077] The step of Fig. 13D is similar to the step of Fig. 10D of the first embodiment. That is, using the resist pattern R22 as a mask, the preliminary stacked portion 20Lp and the insulating layers 51, 52, and 70L are etched by RIE to form a hole H21.

[0078] Next, as shown in FIG. 13E, a sacrificial layer S31 is formed in the hole H21. Carbon is used for the sacrificial layer S31. Because a portion of the side surface of the sacrificial layer S21 is exposed by the etching process of FIG. 13D, a portion of the side surface of the sacrificial layer S21 and a portion of the side surface of the sacrificial layer S31 are aligned with each other. Furthermore, an insulating layer 53 is formed on the structure thus obtained.

[0079] Next, as shown in FIG. 13F, a process similar to that of FIG. 13A is performed to form a structure including a preliminary stack portion 20Up, an insulating layer 55, and an insulating layer 70U on the structure obtained in the process of FIG. 13E.

[0080] 13G, a process similar to that of FIG. 13B is performed, in which the preliminary stacked portion 20Up, the insulating layer 52, the insulating layer 53, the insulating layer 55, and the insulating layer 70U are etched by RIE using the resist pattern R23 as a mask to form a groove T22 extending in the Y direction. The upper surface of the sacrificial layer S21 is exposed by this etching process.

[0081] Next, as shown in Figure 13H, a process similar to that shown in Figure 13C is performed to form a structure in which the trench T22 is filled with a sacrificial layer S22. Like the sacrificial layer S21, amorphous silicon is used for the sacrificial layer S22. Furthermore, an insulating layer 56 is formed on the structure thus obtained.

[0082] Next, as shown in FIG. 13I, a process similar to that shown in FIG. 13D is performed. That is, using the resist pattern R24 as a mask, the preliminary stack portion 20Up, the insulating layer 53, the insulating layer 55, the insulating layer 56, and the insulating layer 70U are etched by RIE to form a hole H22. This etching process exposes the upper surface of the sacrificial layer S31.

[0083] 13J, the sacrificial layer S31 is removed by ashing, thereby forming a hole H23 reaching the lower region 10.

[0084] 13K, a pillar structure 32 including pillar structure portion 32L and pillar structure portion 32U is formed in hole H23. Because part of the side surface of sacrificial layer S21 and part of the side surface of sacrificial layer S22 are exposed through hole H23, part of the side surface of pillar structure portion 32L and part of the side surface of sacrificial layer S21 are aligned with each other, and part of the side surface of pillar structure portion 32U and part of the side surface of sacrificial layer S22 are aligned with each other. Furthermore, an insulating layer 57 is formed on the structure obtained in this manner.

[0085] 13L, the resist pattern R25 is used as a mask to etch the insulating layers 56 and 57. This exposes the upper surface of the sacrificial layer S22.

[0086] 13M, the sacrificial layers S21 and S22 are then removed by wet etching to form a trench T23 that reaches the lower region 10. This exposes part of the side surface of the pillar structure portion 32L and part of the side surface of the pillar structure portion 32U.

[0087] Next, as shown in FIG. 13N, the sacrificial layers 23 are etched through the grooves T23 to form spaces. The spaces are then filled with conductive layers 21, such as tungsten layers. This completes the replacement process of replacing the sacrificial layers 23 with the conductive layers 21. As a result, a stack 20 is formed in which the conductive layers 21 and the insulating layers 22 are alternately stacked.

[0088] Thereafter, the trench T23 is filled with a metal material such as tungsten to obtain a structure as shown in Fig. 12. In the memory region 100, a structure as shown in Fig. 11 is obtained.

[0089] As described above, in this embodiment, as in the first embodiment, the pillar structures 32 provided in the staircase region 200 and not functioning as NAND strings include portions that are not substantially separated from the adjacent plate-like structures 40. That is, a portion of the side surface of the plate-like structure portion 40L is aligned with a portion of the side surface of the pillar structure portion 32L and includes a recess based on the portion of the side surface of the pillar structure portion 32L. Similarly, a portion of the side surface of the plate-like structure portion 40U is aligned with a portion of the side surface of the pillar structure portion 32U and includes a recess based on the portion of the side surface of the pillar structure portion 32U. Therefore, as in the first embodiment, the pillar structures 32 can be provided adjacent to the plate-like structure 40, thereby increasing the integration density of the semiconductor memory device. Furthermore, the pillar structures 32 provided adjacent to the plate-like structure 40 have an improved function of supporting the preliminary stacked portions 20Lp and 20Up, which have multiple spaces formed therein, during the replacement process.

[0090] In this embodiment, as in the first embodiment, the basic configuration of the pillar structures 32 provided in the staircase region 200 is the same as the basic configuration of the pillar structures 31 provided in the memory region 100 and functioning as NAND strings. Therefore, the pillar structures 32 and the pillar structures 31 can be formed in the same process.

[0091] Also in this embodiment, similar to the first embodiment, sacrificial layers S21 and S22 are formed in the region where the plate-like structure 40 is to be formed, and the pillar structure 32 is formed with the sacrificial layers S21 and S22 formed. Thereafter, the plate-like structure 40 is formed in the groove T23 obtained by removing the sacrificial layers S21 and S22. Therefore, similar to the first embodiment, it is possible to accurately form the pillar structure 32 and the plate-like structure 40. Furthermore, by forming the pillar structure 32 including the semiconductor layer 32a that is resistant to shrinkage even by heat treatment or the like, it is possible to suppress sinking of the structure including the stacked body 20 and the insulating layers 70L and 70U in the staircase region 200.

[0092] (Third embodiment) Next, a semiconductor memory device (NAND type nonvolatile semiconductor memory device) according to a third embodiment will be described. Note that the basic features are the same as those of the first and second embodiments, and therefore the description of the features described in the first and second embodiments will be omitted.

[0093] The overall configuration of the semiconductor memory device according to this embodiment is the same as that shown in FIG. 1, and a description thereof will be omitted.

[0094] 14 is a cross-sectional view schematically showing a part of the configuration of the memory region 100. A planar pattern diagram schematically showing a part of the configuration of the memory region 100 is the same as FIG. 3 of the first embodiment, and therefore is not shown.

[0095] Fig. 15 is a cross-sectional view schematically showing part of the configuration of the staircase region 200. Fig. 16 is a planar pattern diagram schematically showing part of the configuration of the staircase region 200 (specifically, part of the configuration of the region where the pillar structure portion 32L and the plate-like structure portion 40L are provided).

[0096] 15 and 16, in the present embodiment, similarly to the second embodiment, the stack 20 includes a stack portion 20L and a stack portion 20U, and the plate-like structure 40 includes a plate-like structure portion 40L and a plate-like structure portion 40U. In addition, in the memory region 100, the pillar structure 31 includes a pillar structure portion 31L and a pillar structure portion 31U, and in the staircase region 200, the pillar structure 32 includes a pillar structure portion 32L and a pillar structure portion 32U.

[0097] The basic configurations and functions of the laminate 20, the pillar structures 31, the pillar structures 32 and the plate-like structures 40 are the same as those in the first embodiment.

[0098] Also in this embodiment, as in the second embodiment, a flat portion 20FT and a staircase portion 20ST are provided in each of the laminated portion 20L and the laminated portion 20U in the staircase region 200. The end of the staircase portion 20ST in the laminated portion 20L is covered with an insulating layer 70L, and the end of the staircase portion 20ST in the laminated portion 20U is covered with an insulating layer 70U.

[0099] Also in this embodiment, as in the second embodiment, an intermediate insulating portion 50a is provided between the laminated portion 20L and the laminated portion 20U. The intermediate insulating portion 50a includes insulating layers 51 and 52. The thickness of the intermediate insulating portion 50a is greater than the thickness of the conductive layer 21 and the thickness of the insulating layer 22. Furthermore, upper insulating portions 50b are provided on the laminated portion 20U, the pillar structure portion 31U, and the pillar structure portion 32U. The upper insulating portion 50b includes insulating layers 55 and 56. These insulating layers 51, 52, 55, and 56 are formed of silicon oxide or the like.

[0100] The relationship between the stacked portion 20L, the pillar structure portion 31L, and the plate-like structure portion 40L, and the relationship between the stacked portion 20U, the pillar structure portion 31U, and the plate-like structure portion 40U are all similar to the relationship between the stacked body 20, the pillar structure 31, and the plate-like structure 40 of the first embodiment. Therefore, the configurations of the pillar structure portion 31L, etc. and the pillar structure portion 31U, etc. in the memory region 100 are all similar to the configurations of the pillar structure 31, etc. of the first embodiment shown in FIGS. 4 and 5.

[0101] The relationship between the laminate portion 20U, the pillar structure portion 32U, the plate-like structure portion 40U, and the insulating layer 70U is also similar to the relationship between the laminate 20, the pillar structure 32, the plate-like structure 40, and the insulating layer 70 of the first embodiment. Therefore, the configuration of the pillar structure portion 32U etc. in the staircase region 200 is similar to the configuration of the pillar structure 32 etc. of the first embodiment shown in Figures 8 and 9.

[0102] The basic relationship between the laminate portion 20L, the pillar structure portion 32L, the plate-like structure portion 40L, and the insulating layer 70L is also similar to the relationship between the laminate 20, the pillar structure 32, the plate-like structure 40, and the insulating layer 70 of the first embodiment. However, in this embodiment, the relationship between the pillar structure portion 32L and the plate-like structure portion 40L is slightly different from the relationship between the pillar structure 32 and the plate-like structure 40 of the first embodiment.

[0103] In this embodiment, a part of the side surface of the pillar structure portion 32L (which is also a part of the side surface of the pillar structure 32) is matched with a part of the side surface of the plate-like structure portion 40L (which is also a part of the side surface of the plate-like structure 40), and includes a flat surface based on the part of the side surface of the plate-like structure portion 40L (a flat surface based on the shape of the part of the side surface of the plate-like structure portion 40L). Specifically, a part of the side surface of the pillar structure portion 32L is matched with a part of the side surface of the plate-like structure portion 40L along the Y direction and the Z direction, and includes a flat surface based on the part of the side surface of the plate-like structure portion 40L. In other words, since the side surface of the plate-like structure portion 40L is substantially a flat surface, the part of the side surface of the pillar structure portion 32L has a flat shape based on the flat shape of the side surface of the plate-like structure portion 40L.

[0104] In other words, the flat surface of the side surface of the above-mentioned pillar structure portion 32L is at least included in the area corresponding to the range between the height level corresponding to the height level of the upper surface of the stacked portion 20L and the height level corresponding to the height level of the lower surface of the stacked portion 20L.

[0105] 16, when viewed from another perspective, the pattern of the pillar structure portion 32L includes a straight line portion based on the pattern of the plate-like structure portion 40L when viewed from the Z direction. For example, when viewed from the Z direction, the pattern of the pillar structure portion 32L has a planar shape in which a part of a circle or an ellipse is cut along a straight line extending in the Y direction.

[0106] 17 and 18 are cross-sectional views schematically showing the detailed configuration of the pillar structure portion 32L and the like in the flat portion 20FT of the laminate 20. Fig. 17 is a cross-sectional view parallel to the Z direction, and Fig. 18 is a cross-sectional view perpendicular to the Z direction. The basic configuration of the pillar structure portion 32L in the staircase portion 20ST of the laminate 20 is also similar to the configuration of the pillar structure portion 32L shown in Figs. 17 and 18.

[0107] Although the shape of the pillar structure portion 32L of this embodiment is different from the shape of the pillar structure 32 of the first embodiment shown in Figures 8 and 9, the basic configuration of the pillar structure portion 32L is similar to the configuration of the pillar structure 32 shown in Figures 8 and 9. That is, like the pillar structure 32 shown in Figures 8 and 9, the pillar structure portion 32L includes a semiconductor layer 32a, a tunnel insulating layer 32b, a charge storage layer 32c, a block insulating layer 32d, and a core insulating layer 32e, and these multiple layers 32a to 32e extend in the Z direction. When viewed from the Z direction, the multiple layers 32a, 32b, 32c, and 32d of the pillar structure portion 32L have a planar shape that extends continuously along the entire periphery of the planar shape of the pillar structure portion 32L, which resembles a part of a circle or an ellipse with a cut-out portion, without being cut out on the side facing the plate-like structure portion 40L. Furthermore, these multiple layers 32a to 32e are stacked in the same stacking order as the pillar structure 32 shown in Figures 8 and 9, from the outer peripheral surface side of the pillar structure portion 32L, including the flat side portion facing the plate-like structure 40L, toward the inside.

[0108] Next, a method for manufacturing a semiconductor memory device according to this embodiment will be described with reference to Figures 19A to 19L. Figures 19A to 19L schematically show the steps of forming the staircase region 200. In the following description, the memory region will not be mentioned, but as in the first embodiment, the memory region is also formed using the same steps as the steps of forming the staircase region 200.

[0109] The step of Fig. 19A is the same as the step of Fig. 10A in the first embodiment, that is, a structure including a preliminary laminate portion 20Lp, an insulating layer 51, and an insulating layer 70L is formed on the lower region 10.

[0110] 19B, the resist pattern R31 is used as a mask to etch the preliminary stacked portion 20Lp, the insulating layer 51, and the insulating layer 70L by RIE to form a hole H31. At this time, the surface region of the lower region 10 is also etched, and the position of the bottom surface of the hole H31 becomes lower than the position of the upper surface of the lower region 10.

[0111] 19C, the hole H31 is filled with a sacrificial layer S41. The sacrificial layer S41 is made of a metal material such as tungsten or titanium. Furthermore, an insulating layer 52 is formed on the structure obtained in this manner.

[0112] Next, as shown in FIG. 19D, a process similar to that of FIG. 19A is carried out to form a structure including a preliminary stacked portion 20Up and an insulating layer 70U on the structure obtained in the process of FIG. 19C.

[0113] Next, as shown in FIG. 19E, using the resist pattern R32 as a mask, the preliminary stacked portion 20Lp, the preliminary stacked portion 20Up, the insulating layer 51, the insulating layer 52, the insulating layer 70L, and the insulating layer 70U are etched by RIE to form a trench T31 ​​extending in the Y direction. In this etching process, a portion of the sacrificial layer S41 is also etched, changing the shape of the sacrificial layer S41. The surface region of the lower region 10 is also etched, so that the position of the bottom surface of the trench T31 ​​becomes lower than the position of the upper surface of the lower region 10. Furthermore, an insulating portion 60 is formed near the bottom of the trench T31.

[0114] 19F, the trench T31 ​​is filled with a sacrificial layer S51. The sacrificial layer S51 is made of amorphous silicon. Furthermore, an insulating layer 55 is formed on the structure thus obtained.

[0115] 19G, using the resist pattern R33 as a mask, the preliminary stacked portion 20Up, the insulating layer 52, the insulating layer 55, and the insulating layer 70U are etched by RIE to form a hole H32 that reaches the sacrificial layer S41. In this etching process, a part of the sacrificial layer S51 is also etched, and the shape of the upper part of the sacrificial layer S51 is changed.

[0116] 19H, the sacrificial layer S41 is etched to form a hole H33 that reaches the lower region 10. This etching process exposes part of the side surface of the lower portion of the sacrificial layer S51.

[0117] 19I, a pillar structure 32 including a pillar structure portion 32L and a pillar structure portion 32U is formed in the hole H33. Since a part of the side surface of the sacrificial layer S51 is exposed by the hole H33, a part of the side surface of the pillar structure 32 and a part of the side surface of the sacrificial layer S51 are aligned with each other.

[0118] Next, as shown in Fig. 19J, an insulating layer 56 is formed on the structure obtained in the step of Fig. 19I. Furthermore, using the resist pattern R34 as a mask, the insulating layers 55 and 56 are etched to expose the upper surface of the sacrificial layer S51.

[0119] 19K, the sacrificial layer S51 is then removed by wet etching to form a trench T32 that reaches the lower region 10. This exposes a part of the side surface of the pillar structure 32.

[0120] Next, as shown in FIG. 19L, the sacrificial layers 23 are etched through the trenches T32 to form spaces. The spaces are then filled with conductive layers 21, such as tungsten layers. This completes the replacement process of replacing the sacrificial layers 23 with the conductive layers 21. As a result, a stack 20 is formed in which the conductive layers 21 and the insulating layers 22 are alternately stacked.

[0121] Thereafter, the trench T32 is filled with a metal material such as tungsten to obtain a structure as shown in Fig. 15. In the memory region 100, a structure as shown in Fig. 14 is obtained.

[0122] As described above, in this embodiment, as in the first embodiment, the pillar structures 32 provided in the staircase region 200 and not functioning as NAND strings include portions that are not substantially separated from the adjacent plate-like structures 40. That is, a portion of the side surface of the plate-like structure portion 40U is aligned with a portion of the side surface of the pillar structure portion 32U and includes a recess based on a portion of the side surface of the pillar structure portion 32U. Furthermore, a portion of the side surface of the pillar structure portion 32L is aligned with a portion of the side surface of the plate-like structure portion 40L and includes a flat surface based on a portion of the side surface of the plate-like structure portion 40L. Therefore, as in the first embodiment, the pillar structures 32 can be provided adjacent to the plate-like structure 40, thereby increasing the integration density of the semiconductor memory device. Furthermore, the pillar structures 32 provided adjacent to the plate-like structure 40 have an improved function of supporting the preliminary stacked portions 20Lp and 20Up, which have multiple spaces formed therein, during the replacement process.

[0123] In this embodiment, as in the first embodiment, the basic configuration of the pillar structures 32 provided in the staircase region 200 is the same as the basic configuration of the pillar structures 31 provided in the memory region 100 and functioning as NAND strings. Therefore, the pillar structures 32 and the pillar structures 31 can be formed in the same process.

[0124] Also in this embodiment, as in the first embodiment, a sacrificial layer S51 is formed in the region where the plate-like structure 40 is to be formed, a pillar structure 32 is formed with the sacrificial layer S51 formed, and then the plate-like structure 40 is formed in the groove T32 obtained by removing the sacrificial layer S51. Therefore, as in the first embodiment, it is possible to accurately form the pillar structure 32 and the plate-like structure 40. Furthermore, by forming the pillar structure 32 including the semiconductor layer 32a that is resistant to shrinkage even by heat treatment or the like, it is possible to suppress sinking of the structure including the stacked body 20 and the insulating layers 70L and 70U in the staircase region 200.

[0125] It should be noted that the configuration of the pillar structures 32 provided in the staircase region 200 in each embodiment is not limited to a staircase structure processed in a valley shape from the outside to the inside, and can be applied. For example, pillar structures 32 similar to those in each embodiment may be provided in a staircase region 200 provided with stairs ascending toward the memory region 100 on one or both sides of the memory region 100 in the Y direction. Regardless of the staircase structure applied, the multiple pillar structures 31 and the multiple pillar structures 32 provided in the memory region 100 and the staircase region 200 aligned in the Y direction do not overlap each other when viewed from the X direction.

[0126] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0127] 10...Lower area 20...Laminate 20p...Preliminary laminate 20L, 20U...Laminated part 20Lp, 20Up...Preliminary laminated part 21...conductive layer 21a...metal layer 21b...barrier metal layer 22...insulating layer 23...sacrificial layer 25...Metal oxide layer 31, 32...Pillar structure 31L, 31U, 32L, 32U...pillar structure 31a, 32a...semiconductor layers 31b, 32b...tunnel insulating layers 31c, 32c... Charge storage layer 31d, 32d... Block insulating layer 31e, 32e...Core insulation layer 40... Plate-like structure 40L, 40U... Plate-like structure portion 41... Sidewall insulating layer 50...insulating portion 50a...intermediate insulating portion 50b...upper insulating portion 51, 52, 53, 55, 56, 57...insulating layers 60...Insulation part 70, 70L, 70U...insulating layer S11, S21, S22, S31, S41, S51...sacrificial layers T11, T12, T21, T22, T23, T31, T32...Groove H11, H21, H22, H23, H31, H32, H33...Hall R11~R13, R21~R25, R31~R34...Resist pattern 100...Memory area 200...Stair area

Claims

1. a structure including a stack of multiple conductive layers stacked in a first direction and spaced apart from each other; a plate-like structure extending in the structure in the first direction and a second direction intersecting the first direction to at least a height level corresponding to a height level of the lower surface of the laminate; a first pillar structure extending in the first direction within the stacked body and functioning as a NAND string, the first pillar structure having a structure in which a plurality of layers including a first semiconductor layer and extending in the first direction are stacked from an outer circumferential surface side toward an inside; a second pillar structure extending in the first direction within the structure and not functioning as a NAND string, the second pillar structure including a second semiconductor layer and having a structure in which a plurality of layers extending in the first direction are stacked from an outer circumferential surface side toward an inside; A semiconductor memory device comprising: a material of each of the plurality of layers extending from the outer circumferential surface side toward the inside in the second pillar structure is the same as a material of each of the plurality of layers extending from the outer circumferential surface side toward the inside in the first pillar structure, A portion of the side surface of the plate-like structure is aligned with a portion of the side surface of the second pillar structure and includes a recess based on the portion of the side surface of the second pillar structure. A semiconductor memory device characterized by:

2. a structure including a stack of multiple conductive layers stacked in a first direction and spaced apart from each other; a plate-like structure extending in the structure in the first direction and a second direction intersecting the first direction to at least a height level corresponding to a height level of the lower surface of the laminate; a first pillar structure extending in the first direction within the stacked body and functioning as a NAND string, the first pillar structure having a structure in which a plurality of layers including a first semiconductor layer and extending in the first direction are stacked from an outer circumferential surface side toward an inside; a second pillar structure extending in the first direction within the structure and not functioning as a NAND string, the second pillar structure including a second semiconductor layer and having a structure in which a plurality of layers extending in the first direction are stacked from an outer peripheral surface side facing the plate-like structure toward an inside; A semiconductor memory device comprising: a material of each of the plurality of layers extending from the outer circumferential surface side toward the inside in the second pillar structure is the same as a material of each of the plurality of layers extending from the outer circumferential surface side toward the inside in the first pillar structure, A portion of the side surface of the second pillar structure is aligned with a portion of the side surface of the plate-like structure and includes a flat surface based on the portion of the side surface of the plate-like structure. A semiconductor memory device characterized by:

3. the laminated body includes a first laminated portion in which a plurality of first conductive layers among the plurality of conductive layers are laminated in the first direction, and a second laminated portion provided on an upper layer side of the first laminated portion in which a plurality of second conductive layers among the plurality of conductive layers are laminated in the first direction, The flat surface is at least included in an area corresponding to a range between a height level corresponding to a height level of the upper surface of the first stacked portion and a height level corresponding to a height level of the lower surface of the first stacked portion.

3. The semiconductor memory device according to claim 2.

4. the laminate includes a staircase portion processed in a staircase shape along a third direction intersecting the first direction and the second direction, and a flat portion extending flatly in the third direction from an uppermost surface of the staircase portion, The second pillar structure extends through the flat portion in the first direction.

3. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

5. the laminate includes a staircase portion processed in a staircase shape along a third direction intersecting the first direction and the second direction, and a flat portion extending flatly in the third direction from an uppermost surface of the staircase portion, The second pillar structure extends the step portion in the first direction.

3. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

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