Semiconductor storage device

Abstract

To provide a suitably operating semiconductor storage device.SOLUTION: In a semiconductor storage device 10, a plurality of pad electrodes include a first pad electrode PX (IO0) through which signals are input and output; and second and third pad electrodes PX (VEXTQL) and PX(VSS) to which voltages are supplied. A semiconductor substrate 200 is provided with a first transistor Tr11 and a second transistor Tr12, a first diode Dio11 and a second diode Dio12, and a power supply clamp circuit disposed in a region Repc. Among a plurality of via contact electrodes CC, those provided at positions overlapping the second pad electrode and electrically connected to the first transistor, the first diode, and the power supply clamp circuit are connected in common to a wiring layer d42. Among the plurality of via contact electrodes, those provided at positions overlapping the third pad electrode and electrically connected to the second transistor, the second diode, and the power supply clamp circuit are connected in common to a wiring layer d43.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that includes a semiconductor substrate, multiple conductive layers stacked in a stacking direction intersecting the surface of the semiconductor substrate, semiconductor pillars facing the multiple conductive layers, and a gate insulating layer provided between the conductive layers and the semiconductor pillars. The gate insulating layer includes a memory portion capable of storing data, such as an insulating charge storage film made of silicon nitride (SiN) or a conductive charge storage film made of a floating gate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0285337 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device that operates favorably is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment comprises a semiconductor substrate, a plurality of conductive layers stacked in a stacking direction intersecting the surface of the semiconductor substrate, a semiconductor pillar extending in the stacking direction and facing the plurality of conductive layers, a charge storage film provided between the plurality of conductive layers and the semiconductor pillar, a plurality of pad electrodes provided on the opposite side of the semiconductor substrate in the stacking direction from the plurality of conductive layers, a wiring layer provided between the semiconductor substrate and the plurality of conductive layers, and a plurality of via contact electrodes extending in the stacking direction and provided between the plurality of pad electrodes and the wiring layer, and electrically connected to wiring included in the plurality of pad electrodes and the wiring layer.

[0006] The plurality of pad electrodes include a first pad electrode to which an input signal is input or an output signal is output, a second pad electrode to which a first voltage is supplied, and a third pad electrode to which a second voltage different from the first voltage is supplied.

[0007] The semiconductor substrate is provided with a first transistor and a first diode electrically connected to the first pad electrode and the second pad electrode, a second transistor and a second diode electrically connected to the first pad electrode and the third pad electrode, and a clamp circuit electrically connected to the second pad electrode and the third pad electrode.

[0008] The multiple via contact electrodes include a first via contact electrode, a second via contact electrode, a third via contact electrode, a fourth via contact electrode, a fifth via contact electrode, a sixth via contact electrode, and a seventh via contact electrode. The first via contact electrode is provided at a position overlapping with the first pad electrode when viewed from the stacking direction and is electrically connected to the first pad electrode. The second via contact electrode is provided at a position overlapping with the second pad electrode when viewed from the stacking direction and is electrically connected to the second pad electrode and the first transistor. The third via contact electrode is provided at a position overlapping with the second pad electrode when viewed from the stacking direction and is electrically connected to the second pad electrode and the first diode. The fourth via contact electrode is provided at a position overlapping with the second pad electrode when viewed from the stacking direction and is electrically connected to the second pad electrode and the clamp circuit. The fifth via contact electrode is provided at a position overlapping with the third pad electrode when viewed from the stacking direction and is electrically connected to the third pad electrode and the second transistor. The sixth via contact electrode is provided at a position overlapping with the third pad electrode when viewed from the stacking direction, and is electrically connected to the third pad electrode and the second diode. The seventh via contact electrode is provided at a position overlapping with the third pad electrode when viewed from the stacking direction, and is electrically connected to the third pad electrode and the clamp circuit.

[0009] The wiring layer includes a first wiring commonly connected to the second via contact electrode, the third via contact electrode, and the fourth via contact electrode, and a second wiring commonly connected to the fifth via contact electrode, the sixth via contact electrode, and the seventh via contact electrode. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a schematic circuit diagram showing the configuration of a portion of a memory die MD. [Figure 2] FIG. 2 is a schematic circuit diagram showing a configuration of a part of a peripheral circuit PC. [Figure 3] 1 is a schematic exploded perspective view showing a configuration example of a semiconductor memory device according to a first embodiment. [Figure 4] FIG. 2 is a plan view schematically showing the arrangement of a plurality of external pad electrodes according to the first embodiment. [Figure 5] FIG. 2 is a schematic circuit diagram showing the configuration of a memory die MD. [Figure 6] FIG. 2 is a schematic circuit diagram showing the configuration of a portion of a memory die MD. [Figure 7] FIG. 2 is a schematic circuit diagram showing the configuration of a portion of a memory die MD. [Figure 8] 2 is a schematic cross-sectional view showing the configuration of a portion of a memory die MD. FIG. [Figure 9] 2 is a schematic cross-sectional view showing the configuration of a portion of a memory die MD. FIG. [Figure 10] 2 is a schematic cross-sectional view showing the configuration of a part of the chip CM. FIG. [Figure 11] 1 is a schematic circuit diagram showing a configuration of a semiconductor memory device including a protection circuit according to a first embodiment. [Figure 12] 1 is a schematic layout diagram showing a semiconductor memory device including a protection circuit according to a first embodiment. [Figure 13] FIG. 12 is a perspective view schematically showing the configuration of the circuit diagram shown in FIG. [Figure 14] FIG. 12 is a perspective view schematically showing the configuration of the circuit diagram shown in FIG. [Figure 15]FIG. 13 is a perspective view schematically illustrating the configuration of the circuit diagram shown in FIG. [Figure 16] FIG. 1 is a schematic circuit diagram showing a configuration of a semiconductor memory device including a protection circuit according to a comparative example. [Figure 17] FIG. 10 is a schematic layout diagram showing a semiconductor memory device including a protection circuit according to a comparative example. [Figure 18] FIG. 17 is a perspective view schematically showing the configuration of the circuit diagram shown in FIG. [Figure 19] 2 is a schematic circuit diagram showing a path through which an ESD current Iesd flows according to the first embodiment. FIG. [Figure 20] FIG. 2 is a perspective view schematically illustrating the configuration of a circuit diagram showing a path through which an ESD current Iesd flows according to the first embodiment. [Figure 21] FIG. 10 is a schematic layout diagram showing the circuit configuration of a semiconductor memory device including a protection circuit according to a second embodiment. [Figure 22] FIG. 10 is a perspective view schematically illustrating a circuit configuration of a semiconductor memory device including a protection circuit according to a second embodiment. [Figure 23] FIG. 10 is a schematic circuit diagram showing the configuration of a semiconductor memory device including a protection circuit according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Next, semiconductor memory devices according to embodiments will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. The following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Furthermore, parts common to multiple embodiments are given the same reference numerals, and explanations thereof may be omitted.

[0012] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0013] Furthermore, in this specification, when a first component is said to be "electrically connected" to a second component, the first component may be directly connected to the second component, or the first component may be connected to the second component via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in the OFF state.

[0014] Furthermore, in this specification, when it is said that a first configuration is "connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0015] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0016] In addition, in this specification, a direction along a predetermined plane may be referred to as the first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as the second direction, and a direction that intersects with this predetermined plane may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0017] Furthermore, in this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is referred to as "up," and the direction approaching the substrate along the Z direction is referred to as "lower." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are referred to as side surfaces, etc.

[0018] Furthermore, in this specification, when referring to a configuration, component, etc., "width," "length," or "thickness" in a specific direction, this may mean the width, length, or thickness in a cross section observed using SEM (Scanning Electron Microscopy), TEM (Transmission Electron Microscopy), or the like.

[0019] [First embodiment] [Circuit configuration of memory die MD] FIG. 1 is a schematic circuit diagram showing the configuration of a portion of a memory die MD. As shown in FIG. 1, the memory die MD includes a memory cell array MCA and a peripheral circuit PC. As shown in FIG. 1, the memory cell array MCA includes a plurality of memory blocks BLK. Each of the plurality of memory blocks BLK includes a plurality of string units SU. Each of the plurality of string units SU includes a plurality of memory strings MS. One end of each of the plurality of memory strings MS is connected to the peripheral circuit PC via a bit line BL. The other end of each of the plurality of memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0020] The memory string MS includes a drain-side select transistor STD, a plurality of memory cells MC (memory transistors), and a source-side select transistor STS. The drain-side select transistor STD, the plurality of memory cells MC, and the source-side select transistor STS are connected in series between a bit line BL and a source line SL. Hereinafter, the drain-side select transistor STD and the source-side select transistor STS may be simply referred to as select transistors (STD, STS).

[0021] The memory cells MC are field-effect transistors. Each memory cell MC includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cells MC varies depending on the amount of charge in the charge storage film. Each memory cell MC stores one or more bits of data. A word line WL is connected to the gate electrodes of the memory cells MC corresponding to one memory string MS. Each of these word lines WL is commonly connected to all memory strings MS in one memory block BLK.

[0022] The select transistors (STD, STS) are field-effect transistors. Each select transistor (STD, STS) includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film may include a charge storage layer. A select gate line (SGD, SGS) is connected to the gate electrode of each select transistor (STD, STS). One drain-side select gate line SGD is commonly connected to all memory strings MS in one string unit SU. One source-side select gate line SGS is commonly connected to all memory strings MS in one memory block BLK.

[0023] 2 is a schematic circuit diagram showing a configuration of a portion of the peripheral circuit PC. The peripheral circuit PC includes, for example, a row control circuit RowC, as shown in FIG. 2. The row control circuit RowC includes a plurality of block decode units blkd and a block decoder BLKD.

[0024] The plurality of block decode units blkd correspond to the plurality of memory blocks BLK in the memory cell array MCA. BLK A plurality of transistors T BLK corresponds to a plurality of word lines WL in the memory block BLK. BLK is, for example, a field-effect NMOS transistor. BLK The drain electrode of the transistor T is connected to the word line WL. BLK The source electrode of the transistor T is connected to the wiring CG. The wiring CG is connected to all the block decode units blkd in the row control circuit RowC. BLK The gate electrodes of the transistors T are connected to a signal supply line BLKSEL. A plurality of signal supply lines BLKSEL are provided corresponding to all the block decode units blkd. The signal supply line BLKSEL is connected to all the transistors T BLK is connected to.

[0025] The block decoder BLKD decodes a block address during a read or write operation, and sets one of the signal supply lines BLKSEL to the “H” state and the remaining signal supply lines BLKSEL to the “L” state according to the decoded block address.

[0026] [Memory die MD structure] 3 is a schematic exploded perspective view showing a configuration example of the semiconductor memory device according to this embodiment. As shown in FIG. 3, the memory die MD is a chip C on the memory cell array MCA side. M and peripheral circuit PC side chip C P And, it is equipped with.

[0027] Chip C M On the upper surface of the X Also, chip C M On the underside of I1 Also, chip C P On the top surface of I2 Hereafter, Chip C M Regarding the multiple bonded electrodes P I1 The surface on which the external pad electrodes P are provided is called the front surface. X The surface on which the chip C is provided is called the back surface. P Regarding the multiple bonded electrodes P I2 The surface on which the chip C is provided is called the front surface, and the surface opposite to the front surface is called the back surface. P The surface of the chip C P and the chip C M The back side of the chip C M The surface of the casing is provided above the surface of the casing.

[0028] Chip C M and Chip C P is Chip C M Surface and chip C P The surfaces of the plurality of laminated electrodes P are arranged to face each other. I1 is a plurality of laminated electrodes P I2 are provided corresponding to the plurality of bonded electrodes P I2 The electrode P is placed in a position where it can be attached to the I1 and laminated electrode P I2 That is, Chip C M and Chip C P and functions as a bonding electrode for electrically connecting them.

[0029] In the example of FIG. 3, chip C M The corners a1, a2, a3, and a4 are the chip C P These correspond to the corners b1, b2, b3, and b4.

[0030] 4 is a plan view showing a schematic arrangement of a plurality of external pad electrodes according to this embodiment. M On the upper surface of the X are aligned in the X direction.

[0031] A plurality of external pad electrodes P X A part of the external pad electrode P is used for transferring input and output signals. X , the external pad electrode P X (IO0),P X (IO1),P X (IO2),P X (IO3).... Also, the plurality of external pad electrodes P X A part of the external pad electrode P is used to supply the ground voltage VSS. X , the external pad electrode P X (VSS). In addition, multiple external pad electrodes P X A part of the external pad electrode P is used to supply the driving voltage VEXTQL. X , the external pad electrode P X It is sometimes called (VEXTQL).

[0032] External pad electrodes P used for transferring input and output signals X (IO0),P X (IO1),P X (IO2),P X (IO3)... and an external pad electrode P used for supplying voltage X (VSS),P X (VEXTQL) are alternately arranged in the X direction. For example, in the example of FIG. 4, a plurality of external pad electrodes P are arranged from the −X direction to the +X direction. X The even-numbered ones are external pad electrodes P X (IO0),P X (IO1),P X (IO2),P X (IO3).... In addition, these multiple external pad electrodes P XThe 4n+1th (n is an integer equal to or greater than 0) external pad electrode P X (VSS). In addition, these multiple external pad electrodes P X The 4n+3th one is the external pad electrode P X (VEXTQL) is supported.

[0033] 5 to 7 are schematic circuit diagrams showing a partial configuration of the memory die MD. As shown in FIG. 5, the memory die MD has a plurality of external pad electrodes P X and these external pad electrodes P X Several decoupling capacitors C connected to D and these external pad electrodes P X and an internal circuit IC connected to the

[0034] The plurality of external pad electrodes P shown in the range X1 of FIG. X is a plurality of external pad electrodes P shown in the range X1 of FIG. X The plurality of external pad electrodes P X Some of these are input / output signal lines W that transfer input and output signals. IO0 ,W IO1 ,W IO2 ,W IO3 These multiple input / output signal lines W IO0 ,W IO1 ,W IO2 ,W IO3 ... are connected to a comparator (not shown) included in the internal circuit IC. Input / output signal line W IO0 ,W IO1 ,W IO2 ,W IO3 A driver circuit Drv is connected to each of the terminals .... The driver circuit Drv includes a pull-down circuit PD and a pull-up circuit PU.

[0035] A plurality of external pad electrodes P X A part of the voltage transfer lines W supplies the ground voltage VSS to each component in the memory die MD. VSS Connected to the voltage transfer line WVSS is connected to the internal circuit IC.

[0036] Also, as shown in FIG. 5, a plurality of external pad electrodes P X A part of the voltage transfer line W supplies the drive voltage VEXTQL to each component in the memory die MD. VEXTQL Connected to the voltage transfer line W VEXTQL is connected to the internal circuit IC.

[0037] Voltage transfer line W VSS and input / output signal line W IO0 ,W IO1 ,W IO2 ,W IO3 A pull-down circuit PD is connected between each of the voltage transfer lines W and VSS and input / output signal line W IO0 ,W IO1 ,W IO2 ,W IO3 ...and includes a plurality of transistors Tr12 connected in parallel between them. A signal line PDG is connected to the gate electrode of the transistor Tr12. The transistor Tr12 is, for example, an N-type MOS transistor (NMOS transistor), and functions as a pull-down transistor.

[0038] Also, the voltage transfer line W VEXTQL and input / output signal line W IO0 ,W IO1 ,W IO2 ,W IO3 A pull-up circuit PU is connected between each of the voltage transfer lines W and VEXTQL and input / output signal line W IO0 ,W IO1 ,W IO2 ,W IO3 ...and includes a plurality of transistors Tr11 connected in parallel between them. A signal line PUG is connected to the gate electrode of the transistor Tr11. The transistor Tr11 is, for example, a P-type MOS transistor (PMOS transistor), and functions as a pull-up transistor.

[0039] 6 shows an example in which the driver circuit Drv includes a PMOS transistor Tr11 as a pull-up transistor and an NMOS transistor Tr12 as a pull-down transistor, but is not limited to this. For example, the pull-up circuit PU may be connected to a voltage transfer line W VEXTQL and input / output signal line W IO0 ,W IO1 ,W IO2 ,W IO3 . . may include a plurality of NMOS transistors Tr11' connected in parallel between them. In this case, the driver circuit Drv is configured by an NMOS transistor Tr11' as a pull-up transistor and an NMOS transistor Tr12 as a pull-down transistor.

[0040] Multiple decoupling capacitors C D As shown in Figure 5, the voltage transfer line W VSS and voltage transfer line W VEXTQL is connected in parallel between

[0041] The internal circuit IC includes the memory cell array MCA and the peripheral circuit PC described with reference to FIG. 1. When outputting data, the peripheral circuit PC connects the input / output signal line W IO0 ,W IO1 ,W IO2 ,W IO3 . . . ., the pull-down circuit PD or the pull-up circuit PU corresponding to the input / output signal line W IO0 ,W IO1 ,W IO2 ,W IO3 … is the voltage transfer line W VSS or voltage transfer line W VEXTQL and conduction.

[0042] 8 and 9 are schematic cross-sectional views showing the configuration of a part of the memory die MD. M 10 is a schematic cross-sectional view showing a part of the configuration of the semiconductor pillar 120. Although Fig. 10 shows a YZ cross section, a structure similar to that of Fig. 10 can be observed when a cross section other than the YZ cross section along the central axis of the semiconductor pillar 120 (for example, an XZ cross section) is observed.

[0043] [Chip C M Structure of Chip C M For example, as shown in FIG. SB and the substrate layer L SB The memory cell array layer L MCA and the memory cell array layer L MCA a via contact electrode layer CH provided below the via contact electrode layer CH, a plurality of wiring layers M0 and M1 provided below the via contact electrode layer CH, and a chip laminating electrode layer MB provided below the wiring layers M0 and M1.

[0044] [Chip C M Base layer L SB Structure of For example, as shown in FIG. SB is the memory cell array layer L MCA The semiconductor device includes a conductive layer 100 provided on the upper surface thereof, an insulating layer 101 provided on the upper surface of the conductive layer 100, a back surface wiring layer MA provided on the upper surface of the insulating layer 101, and an insulating layer 102 provided on the upper surface of the back surface wiring layer MA.

[0045] The conductive layer 100 may include, for example, a semiconductor layer such as silicon (Si) doped with an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B), or may include a metal such as tungsten (W), or may include a silicide such as tungsten silicide (WSi).

[0046] The conductive layer 100 functions as part of the source line SL (FIG. 1). The conductive layer 100 is provided corresponding to the memory plane MP. Regions VZ that do not include the conductive layer 100 are provided at the ends of the memory plane MP in the X and Y directions.

[0047] The insulating layer 101 includes, for example, silicon oxide (SiO2).

[0048] The back wiring layer MA includes a plurality of wirings ma, which may include, for example, aluminum (Al).

[0049] Some of the multiple wirings ma function as part of the source lines SL (FIG. 1). These wirings ma are provided corresponding to the memory planes MP. These wirings ma are each electrically connected to the conductive layer 100.

[0050] In addition, some of the wirings ma are connected to the external pad electrodes P X This wiring ma functions as a P The wiring ma is provided in the memory cell array layer L in the region VZ that does not include the conductive layer 100. MCA The wiring ma is connected to a via contact electrode CC in the insulating layer 102. A part of the wiring ma is exposed to the outside of the memory die MD through an opening TV provided in the insulating layer 102.

[0051] The insulating layer 102 is a passivation layer made of an insulating material such as polyimide.

[0052] [Chip C M The memory cell array layer L MCA Memory hole region R MH Structure in As shown in FIG. 6, the memory cell array layer L MCA 8, a plurality of memory blocks BLK arranged in the Y direction are provided. As shown in FIG. 8, an inter-block insulating layer ST made of silicon oxide (SiO2) or the like is provided between two memory blocks BLK adjacent to each other in the Y direction.

[0053] 8, the memory block BLK includes a plurality of conductive layers 110 aligned in the Z direction and a plurality of semiconductor pillars 120 extending in the Z direction. Furthermore, as shown in FIG. 10, a gate insulating film 130 is provided between each of the plurality of conductive layers 110 and the plurality of semiconductor pillars 120.

[0054] The conductive layer 110 has a generally plate-like shape extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W) or molybdenum (Mo). The conductive layer 110 may also include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An interlayer insulating layer 111 such as silicon oxide (SiO2) is provided between the multiple conductive layers 110 arranged in the Z direction.

[0055] Of the multiple conductive layers 110, one or more conductive layers 110 located in the uppermost layer function as the gate electrode of the source-side select transistor STS (FIG. 1) and the source-side select gate line SGS (see FIG. 8). These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0056] Additionally, the plurality of conductive layers 110 positioned below these function as gate electrodes and word lines WL of the memory cells MC (FIG. 1). These plurality of conductive layers 110 are electrically independent for each memory block BLK.

[0057] Furthermore, one or more conductive layers 110 located below this function as the gate electrodes of the drain side select transistors STD and the drain side select gate lines SGD.

[0058] The semiconductor pillars 120 each function as channel regions for the memory cells MC and select transistors (STD, STS) included in one memory string MS (FIG. 1). The semiconductor pillars 120 include, for example, polycrystalline silicon (Si). The semiconductor pillars 120 have a substantially cylindrical shape, and an insulating layer 125 (FIG. 10) made of silicon oxide or the like is provided in the center. The outer peripheries of the semiconductor pillars 120 are each surrounded by a plurality of conductive layers 110, and face these conductive layers 110.

[0059] Furthermore, an impurity region (not shown) is provided at the upper end of the semiconductor pillar 120. This impurity region is connected to the conductive layer 100 (see FIG. 8). This impurity region contains, for example, an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B).

[0060] An impurity region (not shown) is provided at the lower end of the semiconductor pillar 120. This impurity region is connected to the bit line BL via a via contact electrode ch and a via contact electrode Vy. This impurity region contains an N-type impurity such as phosphorus (P).

[0061] 10 , the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 stacked between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film 131 and the block insulating film 133 include, for example, silicon oxide (SiO2), silicon oxynitride (SiON), or the like. The charge storage film 132 includes, for example, a film capable of storing charges, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer circumferential surface of the semiconductor pillar 120 excluding the contact portion between the semiconductor pillar 120 and the conductive layer 100.

[0062] 10 shows an example in which the gate insulating film 130 includes a charge storage film 132 made of silicon nitride or the like. However, the gate insulating film 130 may include a floating gate made of polycrystalline silicon or the like containing N-type or P-type impurities, for example.

[0063] [Chip C M The memory cell array layer L MCA Hookup Area R HU Structure in As shown in Figure 9, the hook-up area R HU A plurality of via contact electrodes CC are provided in the conductive layer 110. Each of the plurality of via contact electrodes CC extends in the Z direction and is connected to the conductive layer 110 at its upper end.

[0064] [Chip C M The memory cell array layer L MCA The surrounding area R P Structure in Surrounding area R P For example, as shown in FIG. 8, an external pad electrode P X A plurality of via contact electrodes CC are provided corresponding to the external pad electrodes P. X is connected to.

[0065] [Structure of via contact electrode layer CH] The via contact electrodes ch included in the via contact electrode layer CH are, for example, MCA Internal configuration and chip C P The device is electrically connected to at least one of the components.

[0066] The via-contact electrode layer CH includes a plurality of via-contact electrodes ch as a plurality of wirings. These via-contact electrodes ch may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The via-contact electrodes ch are provided corresponding to the plurality of semiconductor pillars 120 and are connected to the lower ends of the plurality of semiconductor pillars 120.

[0067] [Chip C M [Structure of wiring layers M0 and M1] The wirings included in the wiring layers M0 and M1 are, for example, the memory cell array layer L MCA Internal configuration and chip C P The device is electrically connected to at least one of the components.

[0068] The wiring layer M0 includes a plurality of wirings m0. These wirings m0 may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). Some of the wirings m0 function as bit lines BL. The bit lines BL are, for example, aligned in the X direction as shown in FIG. 9 and extend in the Y direction as shown in FIG. 8.

[0069] The wiring layer M1 includes a plurality of wirings m1, as shown in Fig. 8. These wirings m1 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The wiring pattern in the wiring layer M1 will be described later.

[0070] [Chip bonding electrode layer MB structure] The plurality of wirings included in the chip bonding electrode layer MB are, for example, MCA Internal configuration and chip C P The device is electrically connected to at least one of the components.

[0071] The chip bonding electrode layer MB is made up of a plurality of bonding electrodes P I1 These multiple laminated electrodes P I1 is a barrier conductive film p such as titanium nitride (TiN) I1B and metal films such as copper (Cu) I1M The film may include a laminated film of the above.

[0072] [Chip C P Structure of Chip C P The chip C is provided with a plurality of block decode units blkd and block decoders BLKD, which have been described with reference to FIG. P The decoupling capacitor C D , a pull-up circuit PU and a pull-down circuit are provided.

[0073] Chip C P As shown in FIG. 8, for example, the semiconductor device includes a semiconductor substrate 200, an electrode layer GC provided above the semiconductor substrate 200, wiring layers D0, D1, D2, D3, and D4 provided above the electrode layer GC, and a chip bonding electrode layer DB provided above the wiring layers D0, D1, D2, D3, and D4.

[0074] [Chip C P Structure of semiconductor substrate 200] The semiconductor substrate 200 includes P-type silicon (Si) containing P-type impurities such as boron (B). The surface of the semiconductor substrate 200 is provided with an N-type well region 200N containing N-type impurities such as phosphorus (P), a P-type well region 200P containing P-type impurities such as boron (B), a semiconductor substrate region 200S in which the N-type well region 200N and the P-type well region 200P are not provided, and an insulating region 200I. A portion of the P-type well region 200P is provided in the semiconductor substrate region 200S, and a portion of the P-type well region 200P is provided in the N-type well region 200N. The N-type well region 200N, the P-type well region 200P provided in the N-type well region 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S each function as part of a plurality of transistors Tr and a plurality of capacitors that constitute the peripheral circuit PC.

[0075] [Chip C P Electrode layer GC structure] An electrode layer GC is provided on the upper surface of the semiconductor substrate 200 via an insulating layer 200G. The electrode layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 200. Furthermore, each region of the semiconductor substrate 200 and the plurality of electrodes gc included in the electrode layer GC are connected to a via contact electrode CS.

[0076] The N-type well region 200N of the semiconductor substrate 200, the P-type well region 200P provided in the N-type well region 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S each function as channel regions of a plurality of transistors Tr constituting the peripheral circuit PC and one electrode of a plurality of capacitors, etc.

[0077] The plurality of electrodes gc included in the electrode layer GC function as gate electrodes of the plurality of transistors Tr constituting the peripheral circuit PC, the other electrodes of the plurality of capacitors, and the like.

[0078] The via contact electrode CS extends in the Z direction, and its lower end is connected to the upper surface of the semiconductor substrate 200 or the electrode gc. An impurity region containing N-type impurities or P-type impurities is provided at the connection portion between the via contact electrode CS and the semiconductor substrate 200. The via contact electrode CS may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0079] [Chip C P [Structure of wiring layers D0, D1, D2, D3, D4] For example, as shown in FIG. 8, a plurality of wirings included in D0, D1, D2, D3, and D4 are, for example, a memory cell array layer L MCA Internal configuration and chip C P The device is electrically connected to at least one of the components.

[0080] The wiring layers D0, D1, and D2 each include a plurality of wirings d0, d1, and d2, which may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0081] The wiring layers D3 and D4 include a plurality of wirings d3 and d4, respectively, which may include a barrier conductive film such as titanium nitride (TiN), tantalum nitride (TaN), or a laminated film of tantalum nitride (TaN) and tantalum (Ta), and a laminated film of a metal film such as copper (Cu).

[0082] [Chip bonding electrode layer DB structure] The plurality of wirings included in the chip bonding electrode layer DB are, for example, MCA Internal configuration and chip C P The device is electrically connected to at least one of the components.

[0083] The chip bonding electrode layer DB is made up of a plurality of bonding electrodes P I2 These multiple laminated electrodes P I2is a barrier conductive film p such as titanium nitride (TiN), tantalum nitride (TaN), or a laminated film of tantalum nitride (TaN) and tantalum (Ta). I2B and metal films such as copper (Cu) I2M The film may include a laminated film of the above.

[0084] Here, the bonded electrode P I1 and laminated electrode P I2 In particular, metal films such as copper (Cu) I1M ,p I2M When using the metal film p I1M and metal film p I2M However, the bonded electrode P due to the misalignment of the bonding position is I1 and laminated electrode P I2 Distortion of the bonded shape, barrier conductive film p I1B ,p I2B The bonded structure can be confirmed by the positional misalignment (the occurrence of discontinuous areas on the side). I1 and adhesive electrode P I2 When the laminated electrode P is formed by the damascene method, each side surface has a tapered shape. I1 and laminated electrode P I2 The cross section of the bonded electrode P along the Z direction has a non-rectangular shape, with the side walls not being linear. I1 and laminated electrode P I2 When these are bonded together, the bottom, side, and top surfaces of each Cu that forms them are covered with barrier metal. In contrast, in a typical wiring layer using Cu, an insulating layer (such as SiN or SiCN) that functions to prevent oxidation of Cu is provided on the top surface of the Cu, and no barrier metal is provided. For this reason, it is possible to distinguish it from a typical wiring layer even if there is no misalignment in the bonding.

[0085] [Protection circuit] If the difference between the amount of charge stored in the memory cell MC and the amount of charge stored in the test equipment or the like is large, electrostatic discharge (ESD) occurs, and the external pad electrode P XThe electrostatic discharge model includes, for example, the charged device model (CDM), the machine model (MM), and the human body model (HBM).

[0086] The semiconductor memory device according to this embodiment includes a protection circuit to prevent the internal circuits (such as the memory cell array MCA in FIG. 1) of the semiconductor memory device from being damaged by such electrostatic discharge.

[0087] 11 is a schematic circuit diagram showing the configuration of a semiconductor memory device 10 including a protection circuit according to this embodiment, in which some components are omitted.

[0088] The semiconductor memory device 10 including the protection circuit according to this embodiment has an external pad electrode P X (VSS) and external pad electrode P X (IO0) and the external pad electrode P X (VEXTQL), a power clamp which is a clamp circuit, transistors Tr11 and Tr12 which have been described with reference to FIG. 6, and protection diodes Dio11 and Dio12 which are protection elements.

[0089] The semiconductor memory device 10 further includes a resistor Rc11, a resistor Rc12, a resistor Rc13, a resistor Rc14, a resistor Rc15, a resistor Rc16, a resistor Rc17, a resistor Rc18, a resistor Rc19, a resistor Rc20, a resistor Rc21, a resistor Rc22, a resistor Rc23, and a resistor Rc24.

[0090] FIG. 11 further shows a node nd1, a node nd1′, a node nd2, a node nd3, a node nd4, a node nd5, a node nd6, a node nd7, a node nd8, and a node nd9.

[0091] The resistors Rc11 and Rc12 are connected to the external pad electrode P XThe resistors Rc11 and Rc12 are electrically connected between the external pad electrode P (IO0) and the nodes nd1 and nd1'. X The nodes nd1 and nd1', as well as nodes nd2 and nd9 described later, correspond to the resistances of the input / output signal lines W described with reference to FIGS. IO0 are part of and electrically common.

[0092] Resistors Rc14, Rc15, and Rc16 are connected to the external pad electrode P X (VEXTQL) and the nodes nd3, nd4, and nd5. Here, the resistors Rc14, Rc15, and Rc16 are connected to the external pad electrode P X (VEXTQL) and the nodes nd3, nd4, and nd5 correspond to the resistors provided between them. Note that the nodes nd3, nd4, and nd5 correspond to the resistors provided between the voltage transfer line W (VEXTQL) and the nodes nd3, nd4, and nd5, which are described with reference to FIGS. VEXTQL are part of and electrically common.

[0093] Resistors Rc18, Rc19, and Rc20 are connected to the external pad electrode P X (VSS) and the nodes nd6, nd7, and nd8. Here, the resistors Rc18, Rc19, and Rc20 are connected to the external pad electrodes P X (VSS) and the nodes nd6, nd7, and nd8 correspond to the resistors provided between the voltage transfer line W (VSS) and the nodes nd6, nd7, and nd8. VSS are part of and electrically common.

[0094] The resistor Rc21 is electrically connected between the node nd3 and the node nd4. The resistor Rc22 is electrically connected between the node nd4 and the node nd5. Here, the resistors Rc21 and Rc22 are connected to the voltage transfer line W described with reference to FIGS. 5 and 6. VEXTQLThe parasitic resistance (internal resistance) of the via contact electrode CC has a resistance value that is sufficiently small compared to the resistance value of the via contact electrode CC, for example.

[0095] The resistor Rc23 is electrically connected between the node nd6 and the node nd7. The resistor Rc24 is electrically connected between the node nd7 and the node nd8. Here, the resistors Rc23 and Rc24 are connected to the voltage transfer line W described with reference to FIGS. SS The parasitic resistance (internal resistance) of the via contact electrode CC has a resistance value that is sufficiently small compared to the resistance value of the via contact electrode CC, for example.

[0096] One of the source and drain (one end) of the transistor Tr11 is electrically connected to the node nd2 via a resistor Rc13, and the other of the source and drain (the other end) of the transistor Tr11 is electrically connected to the node nd3. Here, the resistor Rc13 is a parasitic resistance (internal resistance) of a wiring that electrically connects the one of the source and drain (one end) of the transistor Tr11 to the node nd2, and has a resistance value that is sufficiently smaller than the resistance value of the via contact electrode CC, for example.

[0097] The anode of the protection diode Dio11 is electrically connected to the node nd2, and the cathode of the protection diode Dio11 is electrically connected to the node nd4. Here, the protection diode Dio11 is, for example, a PN diode.

[0098] The power clamp is electrically connected between the node nd5 and the node nd6. When the applied voltage exceeds a predetermined value, the power clamp clamps the external pad electrode P X (VEXTQL) and external pad electrode P X The power clamp is an element that shorts out the power supply voltage (VSS). The power clamp is configured, for example, by a diode, and may be configured by a resistance capacitor triggered metal oxide semiconductor (RCTMOS) circuit.

[0099] One of the source and drain (one end) of the transistor Tr12 is electrically connected to the node nd8, and the other of the source and drain (the other end) of the transistor Tr12 is electrically connected to the node nd9 via a resistor Rc17. Here, the resistor Rc17 is a parasitic resistance (internal resistance) of a wiring that electrically connects the other of the source and drain (the other end) of the transistor Tr12 to the node nd9, and has a resistance value that is sufficiently smaller than the resistance value of the via contact electrode CC, for example.

[0100] The anode of the protection diode Dio12 is electrically connected to the node nd7, and the cathode of the protection diode Dio12 is electrically connected to the node nd9. Here, the protection diode Dio12 is, for example, a PN diode.

[0101] Fig. 12 is a schematic layout diagram showing a semiconductor memory device 10 including a protection circuit according to this embodiment. Figs. 13 to 15 are perspective views showing the configuration of the circuit diagram shown in Fig. 12. Some components are omitted in Figs. 12 and 13. Furthermore, some of the structure shown in Fig. 13 is omitted in Figs. 14 and 15.

[0102] FIG. 12 shows the external pad electrode P X (IO0) area, external pad electrode P X (VEXTQL) area and external pad electrode P X The (VSS) region is indicated by a dotted line.

[0103] As shown in FIG. 12, the external pad electrode P X The region Recc is arranged at one end side (bottom side in the drawing) of the region (IO0) in the Y direction. As shown in FIG. 13, in this region Recc, the external pad electrode P X A plurality of via contact electrodes CC are arranged in the X direction along one end of (IO0) in the Y direction.

[0104] 12, the regions Redio11 and Redio12 are arranged side by side in the X direction at a position overlapping with the region Recc when viewed from the Z direction. The region Redio11 is arranged so as to overlap the external pad electrode P X (VEXTQL) side, and the area Redio12 is the external pad electrode P X 13, the protection diodes Dio11 and Dio12 described with reference to FIG.

[0105] 12, one side of the regions Redio11 and Redio12 in the Y direction (external pad electrode P X On the opposite side to the IO0 region, an area Repc is arranged. As shown in FIG. 13, the area Repc on the semiconductor substrate 200 is provided with the power clamp circuit described with reference to FIG. 11.

[0106] Also, as shown in FIG. 12, the external pad electrode P X External pad electrode P in the X direction of the (VEXTQL) area X 13, the area Recc is also arranged in the area on the side (IO0) and one side in the Y direction (the lower side in the figure). X A plurality of via contact electrodes CC are arranged in the Y direction along one end in the X direction of (VEXTQL). Also, a plurality of via contact electrodes CC are arranged in the X direction along one end in the Y direction.

[0107] 12, a region Retr11 is arranged at a position overlapping with the region Recc when viewed from the Z direction. As shown in Fig. 13, the region Retr11 on the semiconductor substrate 200 is provided with a plurality of transistors Tr11 described with reference to Figs. 6 and 11.

[0108] Also, as shown in FIG. 12, the external pad electrode P X External pad electrode P in the X direction of the (VSS) area XThe area Recc is also arranged in the area on the (IO0) side and the area on one side in the Y direction (the lower side in the figure). As shown in FIG. 13, in this area Recc, the external pad electrode P X A plurality of via contact electrodes CC are arranged in the Y direction along one end in the X direction of (VSS). Also, a plurality of via contact electrodes CC are arranged in the X direction along one end in the Y direction.

[0109] 12, a region Retr12 is arranged at a position overlapping with the region Recc when viewed from the Z direction. As shown in Fig. 13, the region Retr12 on the semiconductor substrate 200 is provided with a plurality of transistors Tr12 described with reference to Figs. 6 and 11.

[0110] In this embodiment, the wiring layer D4 described with reference to FIGS. 8 and 9 includes wirings d41, d42, and d43 as part of the wiring d4.

[0111] Wiring d41 is the input / output signal line W IO0 The wiring d41 functions as an external pad electrode P X 15, the portion extending in the X direction overlaps with the regions Redio11 and Redio12 when viewed from the Z direction, and is electrically connected to the protection diodes Dio11 and Dio12. The portion extending in the Y direction overlaps with the regions Retr11 and Retr12 when viewed from the Z direction, and is electrically connected to the transistors Tr11 and Tr12.

[0112] Wiring d42 is the voltage transfer line W VEXTQL The wiring d42 functions as an external pad electrode P X 15, the portion extending in the Y direction overlaps with the region Retr11 when viewed from the Z direction, and is electrically connected to the transistor Tr11. One of the pair of portions extending in the X direction is connected to the external pad electrode PX The pair of portions is provided along another part of the region Recc corresponding to (VEXTQL). One of the pair of portions overlaps with the region Redio11 when viewed from the Z direction and is electrically connected to the protection diode Dio11. The other of the pair of portions extending in the X direction overlaps with the region Repc when viewed from the Z direction and is electrically connected to the power supply clamp circuit.

[0113] Wiring d43 is the voltage transfer line W VSS The wiring d43 functions as an external pad electrode P X 15, the portion extending in the Y direction overlaps with the region Retr12 when viewed from the Z direction, and is electrically connected to the transistor Tr12. One of the pair of portions extending in the X direction is connected to the external pad electrode P X The pair of portions extends along another part of the region Recc corresponding to (VSS). One of the pair of portions overlaps with the region Redio12 when viewed from the Z direction and is electrically connected to the protection diode Dio12. The other of the pair of portions extending in the X direction overlaps with the region Repc when viewed from the Z direction and is electrically connected to the power supply clamp circuit.

[0114] [Comparative Example] Next, a semiconductor memory device 90 according to a comparative example will be described with reference to FIGS. 16 to 18. FIG. 16 is a schematic circuit diagram showing the configuration of a semiconductor memory device 90 including a protection circuit according to a comparative example. FIG. 17 is a schematic layout diagram showing a semiconductor memory device 90 including a protection circuit according to a comparative example. FIG. 18 is a perspective view showing the configuration of the circuit diagram shown in FIG. 16. Some components are omitted in FIGS. 16 to 18.

[0115] 16, in a semiconductor memory device 90 including a protection circuit according to the comparative example, the nodes nd3, nd4, and nd5 are not commonly connected, and the nodes nd6, nd7, and nd8 are not commonly connected.

[0116] 16 also shows a node nd91 connected to one (one end) of the source and drain of the transistor Tr11, and a node nd91 connected to an external pad electrode P X (IO0), a resistor Rc25 electrically connected between the node nd92 and the external pad electrode P X The resistors Rc25 and Rc26 are connected between the external pad electrode P X This corresponds to the resistors provided between (IO0) and nodes nd91 and nd92.

[0117] In the comparative example, the external pad electrode P X (IO0),P X Between (VEXTQL), there are provided a current path including a resistor Rc14, a transistor Tr11, and a resistor Rc25, and a current path including a resistor Rc15, a protection diode Dio11, and a resistor Rc26. These two current paths are electrically independent.

[0118] 16 also shows a node nd93 connected to one of the source and drain (one end) of the transistor Tr12, and a node between the node nd93 and the external pad electrode P X (IO0), a resistor Rc27 electrically connected between the node nd94 and the external pad electrode P X The resistors Rc27 and Rc28 are connected between the external pad electrode P X This corresponds to the resistors provided between (IO0) and nodes nd93 and nd94.

[0119] In the comparative example, the external pad electrode P X (IO0),P XBetween VSS and VSS, there is provided a current path including a resistor Rc20, a transistor Tr12, and a resistor Rc27, and a current path including a resistor Rc19, a protection diode Dio12, and a resistor Rc28. These two current paths are electrically independent.

[0120] In the comparative example, the external pad electrode P X (VEXTQL),P X A current path including a resistor Rc18, a power clamp circuit, and a resistor Rc16 is provided between the power supply terminals (VSS) and (VSS). This current path is electrically independent from any of the current paths described above.

[0121] 17, in the comparative example, the region Recc in which the plurality of via contact electrodes CC are provided is located on the outer pad electrode P X The external pad electrode P X They are arranged on both ends of the (IO0) area in the X direction.

[0122] In the comparative example, the region Redio12 where the protective element is provided is located on the external pad electrode P X The external pad electrode P X One end of the (IO0) area in the X direction (in the figure, the external pad electrode P X (VSS) area side).

[0123] Also, as shown in FIG. 18, in the comparative example, a plurality of wires d4 in the wiring layer D4 are independent for each of the nodes nd3, nd4, nd5, nd6, nd7, nd8, nd91, nd92, nd93, and nd94.

[0124] In recent years, the ESD resistance of transistors, which are the elements to be protected, has been reduced due to the thinning of the transistors, making it necessary to ensure ESD resistance. To ensure ESD resistance, it is preferable to reduce the impedance of the protection circuit to the ESD current and reduce the voltage applied to the elements to be protected.

[0125] However, in three-dimensional stacked memories such as NAND flash memories, the presence of high-resistance via contact electrodes CC between the external pad electrodes and the circuit is one factor that increases the impedance against ESD current.

[0126] For example, the external pad electrode P X Considering the case where a surge voltage having a positive magnitude is applied to (IO0), in the comparative example, as shown in FIGS. 16 and 18, X From (IO0), via contact electrode CC (resistor Rcc26), wiring d4 (node ​​nd92), protection diode Dio11, wiring d4 (node ​​nd4), via contact electrode CC (resistor Rcc15), external pad electrode P X (VEXTQL), via contact electrode CC (resistor Rcc16), wiring d4 (node ​​nd5), clamp circuit, wiring d4 (node ​​nd6), via contact electrode CC (resistor Rc18), and external pad electrode P X (VSS) in this order, the ESD current I esd is playing.

[0127] In addition, the ESD current I esd Therefore, the voltage at one electrode of the transistor Tr12 is applied to the external pad electrode P X Similarly, the voltage of the other electrode of the transistor Tr12 is equal to the voltage of the external pad electrode P X (VSS).

[0128] Therefore, in the comparative example, the ESD current I esd When this occurs, the voltage applied to the transistor Tr12, which is the protected element, is approximately the sum of the voltage Vf associated with the protection diode Dio11, the voltage Vc associated with the clamp circuit, and the voltage Vrcc associated with the resistors Rc26, Rc15, Rc16, and Rc18.

[0129] Here, with the increasing integration density of semiconductor memory devices, the length of the via contact electrodes CC in the Z direction is increasing. Accordingly, the resistance values ​​of the resistors Rc26, Rc15, Rc16, and Rc18 corresponding to the via contact electrodes CC are increasing. Accordingly, the ESD current I esd As a result of this, the voltage applied to the transistor Tr12, which is an unprotected element, is increasing.

[0130] [Effects of the semiconductor memory device according to the first embodiment] In the semiconductor memory device 10 according to the first embodiment, the nodes nd3, nd4, and nd5 are electrically connected in common. The nodes nd6, nd7, and nd8 are electrically connected in common. Furthermore, the nodes nd1, nd1', nd2, and nd9 are electrically connected in common.

[0131] In such a configuration, the external pad electrode P X Considering the case where a surge voltage having a positive magnitude is applied to (IO0), for example, as shown in FIGS. 11, 13, and 14, X From (IO0), a via contact electrode CC (a parallel circuit of resistors Rc11 and Rc12), a wiring d41 (nodes nd1 and nd1'), a protection diode Dio11, a wiring d42 (nodes nd4 and nd5), a clamp circuit, a wiring d43 (node ​​nd6), a via contact electrode CC (resistor Rc18), and an external pad electrode P X (VSS) in this order, the ESD current I esd is playing.

[0132] In addition, the ESD current I esd does not flow through transistor Tr12, which is an unprotected element. Therefore, the voltage of one electrode of transistor Tr12 becomes equal to node nd9. Similarly, the voltage of the other electrode of transistor Tr12 becomes equal to node nd8.

[0133] Therefore, in the first embodiment, the ESD current I esdThe voltage applied to the transistor Tr12, which is the protected element, due to the occurrence of ESD current I is approximately the sum of the voltage Vf related to the protection diode Dio11 and the voltage Vc related to the clamp circuit. esd Therefore, the voltage applied to the transistor Tr12, which is the protected element, does not include the voltage Vrcc associated with the resistors Rc26, Rc15, Rc16, and Rc18 of the via contact electrode CC, which have high resistance. esd This makes it possible to significantly reduce the voltage applied to the transistor Tr12, which is the protected element, due to the occurrence of

[0134] It should be noted that an IR drop due to the parasitic resistance (internal resistance) of the resistors Rc13 and Rc17 shown in FIG. 11, ie, the wiring d41 (FIG. 13), reduces the effect of the degradation of ESD resistance.

[0135] 12 to 15, in this embodiment, the protection diode Dio11 and the transistor Tr11 are provided adjacent to each other, thereby shortening the length of the wiring d41 in the Y direction and reducing the parasitic resistance of the wiring d41 (the resistance value of the resistor Rc13). Also, the protection diode Dio12 and the transistor Tr12 are provided adjacent to each other, thereby shortening the length of the wiring d41 in the Y direction and reducing the parasitic resistance of the wiring d41 (the resistance value of the resistor Rc17).

[0136] Also, as shown in FIG. 13, the external pad electrode P X The current flowing through the resistor Rc13 is reduced by providing the protection diode Dio11 closer to the transistor Tr11 than to the via contact electrode CC that electrically connects the external pad electrode P (IO0) and the wiring d41. X The current flowing through the resistor Rc17 is reduced by providing the protection diode Dio12 closer to the transistor Tr12 than to the via contact electrode CC that electrically connects (IO0) and the wiring d41.

[0137] In this way, it is possible to suppress the influence of the IR drop due to the parasitic resistance (internal resistance) of the resistors Rc13 and Rc17, that is, the wiring d41 (FIGS. 13 and 15).

[0138] FIG. 19 shows the ESD current I esd 20 is a schematic circuit diagram showing a path through which the ESD current I flows according to the first embodiment. esd FIG. 2 is a perspective view showing a schematic configuration of a circuit diagram illustrating a path through which

[0139] In the configuration of the first embodiment, the external pad electrode P X Considering the case where a negative surge voltage is applied to (IO0), as shown in FIGS. 19 and 20, X From (VEXTQL), the via contact electrode CC (resistor Rc16), the wiring d43 (node ​​nd5), the clamp circuit, the wiring d43 (nodes nd6 and nd7), the protection diode Dio12, the wiring d41 (nodes nd1 and nd1'), the via contact electrode CC (parallel circuit of resistors Rc11 and Rc12), and the external pad electrode P X (IO0) in this order, the ESD current I esd is playing.

[0140] Therefore, when a positive surge voltage is applied, the ESD current I esd The path through which the ESD current I flows and the ESD current I when a negative surge voltage is applied esd In the path through which the current flows, the wiring d41 (nodes nd1 and nd1') and the via contact electrode CC (parallel circuit of resistors Rc11 and Rc12) can be included in common. This allows the external pad electrode P X The number of via contact electrodes CC connected to the external pad electrode P (IO0) can be reduced. X By reducing the number of via contact electrodes CC connected to (IO0), the external pad electrode P XThis can reduce the parasitic capacitance of (IO0), speed up communication between the memory die MD and the external controller die, and improve the operating speed of the memory system.

[0141] [Second embodiment] The semiconductor memory device 10 according to the second embodiment is basically configured in the same manner as the semiconductor memory device 10 according to the first embodiment.

[0142] FIG. 21 is a schematic layout diagram showing a semiconductor memory device 10A including a protection circuit according to this embodiment. FIG. 22 is a perspective view showing a schematic circuit configuration of a semiconductor memory device 10A including a protection circuit according to a second embodiment. FIG. 23 is a schematic circuit diagram showing a configuration of a semiconductor memory device including a protection circuit according to the second embodiment. Some configurations are omitted in FIGS. 21 to 23. In the following description, parts similar to those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0143] As described with reference to FIG. 12, in the first embodiment, the external pad electrode P X External pad electrode P in the X direction of the (VEXTQL) area X The area Recc is arranged in the area on the side (IO0). X External pad electrode P in the X direction of the (VSS) area X The area Recc is located in the area on the side (IO0).

[0144] On the other hand, as shown in FIG. 21, in the second embodiment, the external pad electrode P X External pad electrode P in the X direction of the (VEXTQL) area X 22, in the second embodiment, the external pad electrode P X External pad electrode P in the X direction of the (VEXTQL) area X In the region on the side (IO0), no via contact electrode CC is provided.

[0145] In addition, as shown in FIG. 21, in the second embodiment, the external pad electrode P X External pad electrode P in the X direction of the (VSS) area X 22, in the second embodiment, the external pad electrode P X External pad electrode P in the X direction of the (VSS) area X In the region on the side (IO0), no via contact electrode CC is provided.

[0146] [Effects of the semiconductor memory device according to the second embodiment] In the second embodiment, the external pad electrode P X External pad electrode P in the X direction of the (VEXTQL) area X In this configuration, the external pad electrode P X The distance from the via contact electrode CC connected to (VSS) to the connection portion of the wiring d43 with the transistor Tr12 is larger than that in the first embodiment. X The ESD current I when a positive surge voltage is applied to (IO0) esd The path through which this current flows is connected to the transistor Tr12 to be protected via resistor Rc24 (Figure 23). This reduces the voltage applied to transistor Tr12 when ESD occurs, further improving the ESD resistance of transistors Tr12 and other transistors.

[0147] [Other embodiments] In the above embodiment, an example has been described in which the technology described in this specification is applied to a NAND flash memory. However, the technology described in this specification can also be applied to configurations other than semiconductor memory devices, such as a three-dimensional NOR flash memory. Furthermore, the technology described in this specification can also be applied to configurations of semiconductor devices other than semiconductor memory devices.

[0148] Furthermore, in the above embodiment, the transistor Tr11 has been described as a PMOS transistor, but it is also possible to realize the transistor Tr11 as an NMOS transistor.

[0149] In the above embodiment, the layout of each component is illustrated with reference to FIGS. 17 and 21. However, the specific layout of each component can be adjusted as appropriate. For example, components that are arranged in overlapping positions when viewed from the Z direction in FIGS. 17 and 21 may be arranged in non-overlapping positions. Even in such a case, the components can be routed by any of the multiple wiring layers arranged between the via contact electrodes CC and the semiconductor substrate 200.

[0150] In the above embodiment, an example has been described in which the lower ends of the via contact electrodes CC are commonly connected using multiple wirings d4 in the wiring layer D4. However, the wiring that commonly connects the lower ends of the via contact electrodes CC may be wiring included in a wiring layer other than the wiring layer D4. Furthermore, the lower ends of the via contact electrodes CC may be commonly connected using wirings included in multiple wiring layers.

[0151] [others] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0152] 110...conductive layer, 120...semiconductor layer, 130...gate insulating film, 151, 152, 153...portions, 200...semiconductor substrate, C M ,C P...chip, CC...via contact electrode, Dio11, Dio12...protection diode, nd1, nd2, nd3, nd4, nd5, nd6, nd7, nd8, nd9...node, Rc11, Rc12, Rc13, Rc14, Rc15, Rc16, Rc17, Rc18, Rc19, Rc20...resistor, Tr, Tr11, Tr12...transistor, BL...bit line, WL...word line, MC...memory cell, M0, M1, D0, D1, D2, D3, D4, d41, d42, d43, d44, d45, d46, d47...wiring layer, MB, DB...chip bonding electrode layer, Gm1...wiring group, m1, m1a, m1b...wiring, P I1 ,P I2 ...Laminated electrode.

Claims

1. a semiconductor substrate; a plurality of conductive layers stacked in a stacking direction intersecting the surface of the semiconductor substrate; a semiconductor pillar extending in the stacking direction and facing the plurality of conductive layers; a charge storage film provided between the plurality of conductive layers and the semiconductor pillars; a plurality of pad electrodes provided on the plurality of conductive layers on the opposite side of the semiconductor substrate in the stacking direction; a wiring layer provided between the semiconductor substrate and the plurality of conductive layers; a plurality of via contact electrodes extending in the stacking direction, provided between the plurality of pad electrodes and the wiring layer, and electrically connected to the plurality of pad electrodes and wiring included in the wiring layer; Equipped with The plurality of pad electrodes are a first pad electrode to which an input signal is input or to which an output signal is output; a second pad electrode to which a first voltage is supplied; a third pad electrode to which a second voltage different from the first voltage is supplied; Including, The semiconductor substrate is a first transistor and a first diode electrically connected to the first pad electrode and the second pad electrode; a second transistor and a second diode electrically connected to the first pad electrode and the third pad electrode; a clamp circuit electrically connected to the second pad electrode and the third pad electrode; is established, The plurality of via contact electrodes are a first via contact electrode provided at a position overlapping with the first pad electrode when viewed from the stacking direction and electrically connected to the first pad electrode; a second via contact electrode provided at a position overlapping with the second pad electrode when viewed from the stacking direction, the second via contact electrode being electrically connected to the second pad electrode and the first transistor; a third via contact electrode provided at a position overlapping with the second pad electrode when viewed from the stacking direction, the third via contact electrode being electrically connected to the second pad electrode and the first diode; a fourth via contact electrode provided at a position overlapping with the second pad electrode when viewed from the stacking direction, the fourth via contact electrode being electrically connected to the second pad electrode and the clamp circuit; a fifth via contact electrode provided at a position overlapping with the third pad electrode when viewed from the stacking direction, the fifth via contact electrode being electrically connected to the third pad electrode and the second transistor; a sixth via contact electrode provided at a position overlapping with the third pad electrode when viewed from the stacking direction, the sixth via contact electrode being electrically connected to the third pad electrode and the second diode; a seventh via contact electrode that is provided at a position that overlaps with the third pad electrode when viewed from the stacking direction, and is electrically connected to the third pad electrode and the clamp circuit; Including, The wiring layer is a first wiring connected in common to the second via contact electrode, the third via contact electrode, and the fourth via contact electrode; a second wiring commonly connected to the fifth via contact electrode, the sixth via contact electrode, and the seventh via contact electrode; A semiconductor memory device comprising:

2. the wiring layer further includes a third wiring connected in common to the first via contact electrode, the first transistor, the first diode, the second transistor, and the second diode; the first transistor and the first diode are connected in parallel between the first wiring and the third wiring, The second transistor and the second diode are connected in parallel between the second wiring and the third wiring.

2. The semiconductor memory device according to claim 1.

3. the first transistor is an N-channel MOS transistor or a P-channel MOS transistor, The second transistor is an N-channel MOS transistor.

2. The semiconductor memory device according to claim 1.

4. When viewed from the stacking direction, the first diode is provided closer to the first via contact electrode than the first transistor.

2. The semiconductor memory device according to claim 1.

5. When viewed from the stacking direction, the first diode is provided closer to the clamp circuit than the first transistor.

2. The semiconductor memory device according to claim 1.

6. The clamp circuit It consists of a diode, 2. The semiconductor memory device according to claim 1.

7. The clamp circuit It is composed of an RCTMOS (Resistance Capacitor Triggered Metal Oxide Semiconductor) circuit.

2. The semiconductor memory device according to claim 1.

8. a resistor electrically connected in series between the first via contact electrode and the first transistor; 2. The semiconductor memory device according to claim 1.

9. The first pad electrode, the second pad electrode, and the third pad electrode are The third pad electrode, the first pad electrode, and the second pad electrode are arranged in this order in a first direction intersecting the stacking direction.

2. The semiconductor memory device according to claim 1.

10. a first semiconductor chip and a second semiconductor chip connected to each other via a plurality of bonding electrodes; The first semiconductor chip the semiconductor substrate; a plurality of first adhesive electrodes that are part of the plurality of adhesive electrodes; Equipped with the plurality of conductive layers; The second semiconductor chip is the semiconductor pillar; the charge storage film; the plurality of pad electrodes; the plurality of via contact electrodes; a plurality of second adhesive electrodes that are another part of the plurality of adhesive electrodes; Equipped with The first semiconductor chip and the second semiconductor chip are arranged such that the first bonding electrodes face the second bonding electrodes.

2. The semiconductor memory device according to claim 1.

11. a semiconductor substrate; a plurality of conductive layers stacked in a stacking direction intersecting the surface of the semiconductor substrate; a semiconductor pillar extending in the stacking direction and facing the plurality of conductive layers; a charge storage film provided between the plurality of conductive layers and the semiconductor pillars; a plurality of pad electrodes provided on the plurality of conductive layers on the opposite side of the semiconductor substrate in the stacking direction; a wiring layer provided between the semiconductor substrate and the plurality of conductive layers; a plurality of via contact electrodes extending in the stacking direction, provided between the plurality of pad electrodes and the wiring layer, and electrically connected to the plurality of pad electrodes and wiring included in the wiring layer; Equipped with The plurality of pad electrodes are a first pad electrode to which an input signal is input or to which an output signal is output; a second pad electrode to which a first voltage is supplied; a third pad electrode to which a second voltage different from the first voltage is supplied; Including, The semiconductor substrate is a first transistor and a first diode electrically connected to the first pad electrode and the second pad electrode; a second transistor and a second diode electrically connected to the first pad electrode and the third pad electrode; a clamp circuit electrically connected to the second pad electrode and the third pad electrode; is established, The plurality of via contact electrodes are a first via contact electrode provided at a position overlapping with the first pad electrode when viewed from the stacking direction and electrically connected to the first pad electrode; a second via contact electrode provided at a position overlapping with the second pad electrode when viewed from the stacking direction, the second via contact electrode being electrically connected to the second pad electrode and the clamp circuit; a third via contact electrode provided at a position overlapping with the third pad electrode when viewed from the stacking direction, the third via contact electrode being electrically connected to the third pad electrode and the clamp circuit; Including, The wiring layer is a first wiring extending in a direction intersecting the stacking direction so as to overlap with the first transistor and the first diode as viewed from the stacking direction, and connected to the second via contact electrode; a second wiring extending in a direction intersecting the stacking direction so as to overlap the second transistor and the second diode when viewed from the stacking direction, and connected to the third via contact electrode; A semiconductor memory device comprising:

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