Memory device

Abstract

To provide a memory device capable of achieving an increase in capacity while suppressing an increase in size.SOLUTION: A memory device (1, 1A, 1B, 1C) includes: a plurality of memory chips (2, 2A, 2B, 2K, 2L, 2M, 2N, 5, 6) having the same structure and stacked in a first direction (D1); and a plurality of lead frames (11-18) disposed to be adjacent to the memory chips (2, 2A, 2B, 2K, 2L, 2M, 2N) in a second direction (D2) intersecting with the first direction (D1) and connected to a plurality of pads (201-206), respectively, included in each of the memory chips (2, 2A, 2B, 2K, 2L, 2M, 2N, 5, 6). The electrode pads (201-208) connected to the same lead frames (11-18) of each of the memory chips (2, 2A, 2B, 2K, 2L, 2M, 2N, 5, 6) are the electrode pads (201-208) of the same type.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The invention disclosed herein relates to memory devices. [Background technology]

[0002] The semiconductor memory circuit proposed in Patent Document 1 is configured by integrating a transistor pair, each of which is a memory cell for storing one bit of data, and which includes a first transistor and a second transistor having a higher on-state current than the first transistor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-103158

[0004] [overview] Increasing the storage capacity of the semiconductor storage circuit proposed in Patent Document 1 increases the area of ​​the memory array and the size of the semiconductor storage circuit, and also requires a jig that can accommodate the new size for testing before shipping.

[0005] The memory device disclosed in this specification includes a plurality of memory chips having the same structure and stacked in a first direction, and a plurality of lead frames arranged adjacent to the memory chips in a second direction intersecting the first direction and configured to be connected to a plurality of electrode pads provided on each of the memory chips, wherein the electrode pads connected to the same lead frame of each of the memory chips are configured to be the same type of electrode pads. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the overall configuration of a memory device. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a memory chip. [Figure 3] FIG. 3 is a flowchart showing the procedure for selecting the upper or lower memory chip. [Figure 4] FIG. 4 is a block diagram showing the configuration of the selection determination unit of the control circuit. [Figure 5] FIG. 5 is a diagram showing the operating state of the upper memory chip when the upper memory chip is selected for a read operation. [Figure 6] FIG. 6 is a diagram showing the operating state of the lower memory chip when the upper memory chip is selected for a read operation. [Figure 7] FIG. 7 is a diagram showing the operating state of the upper memory chip when the lower memory chip is selected for a read operation. [Figure 8] FIG. 8 is a diagram showing the operating state of the lower memory chip when the lower memory chip is selected for a read operation. [Figure 9] FIG. 9 is a diagram showing a memory device according to a first modified example. [Figure 10] FIG. 10 is a side view of a memory chip used in the memory device of the second modified example. [Figure 11] FIG. 11 is a block diagram of a selection decision unit of a memory device having four memory chips. [Figure 12] FIG. 12 is a diagram showing an example of chip identification information in the case where there are four memory chips.

[0007] [Detailed explanation] In this specification, directions are defined based on the memory device 1 shown in FIG. 1. In the memory device 1 shown in FIG. 1, the thickness direction of the paper surface is defined as the first direction D1. In addition, in the memory device 1 shown in FIG. 1, the left-right direction is defined as the second direction D2, and the up-down direction is defined as the third direction D3. In other words, the second direction D2 is a direction that intersects with the first direction D1, and the third direction D3 is a direction that intersects with the first direction D1 and the second direction D2. In addition, in the memory device 1 shown in FIG. 1, the first direction D1, the second direction D2, and the third direction D3 are all perpendicular to each other.

[0008] <Memory device> 1 is a block diagram showing an example of the overall configuration of a memory device 1. The memory device 1 shown in FIG. 1 includes a die bond frame 10, lead frames 11 to 18, two memory chips 2, a package 3, and bonding wires 4.

[0009] The die bond frame 10 is a plate-shaped member. The die bond frame 10 holds two memory chips 2. The two memory chips 2 are arranged side by side in a first direction D1. The two memory chips 2 may be distinguished as an upper memory chip 2A and a lower memory chip 2B.

[0010] The lead frames 11 to 18 are arranged adjacent to the die bond frame 10 in the second direction D2. In the memory device 1 shown in Fig. 1, the lead frames 11 to 14 are arranged on the left side of the die bond frame 10, i.e., on one side in the second direction D2. The lead frames 15 to 18 are arranged on the right side of the die bond frame 10, i.e., on the other side in the second direction D2.

[0011] <Memory chip 2> The memory chip 2 will be described with reference to the drawings. Fig. 2 is a block diagram showing an example configuration of the memory chip 2. The memory chip 2 shown in Fig. 2 has a memory array 21, an X decoder 22, a Y decoder 23, a sense amplifier 24, and a control circuit 26. Note that the memory chip 2 may be configured as a single IC (Integrated Circuit) by integrating the memory array 21, the X decoder 22, the Y decoder 23, the sense amplifier 24, the output buffer 25, and the control circuit 26.

[0012] The memory array 21 has m gate lines GL (= word lines) laid in the X-axis direction (second direction), 2n bit lines BL laid in the Y-axis direction (third direction), and a plurality (= m × n) of memory cells CELL arranged in a matrix along the gate lines GL and bit lines BL.

[0013] The X decoder (row decoder) 22 drives the gate line GL in response to an instruction from the control circuit 26. The Y decoder (column decoder) 23 drives the bit line BL in response to an instruction from the control circuit 26. Data "0" or data "1" is stored in the memory cell.

[0014] Each memory chip 2 arranged on the die bond frame 10 has six electrode pads 201 to 206. In the memory chip 2 used in the memory device 1, the six electrode pads 201 to 206 are arranged on one side (the left side in FIG. 1) of the memory array 21 in the second direction D2. The six electrode pads 201 to 206 are arranged side by side in the third direction D3.

[0015] In the memory chip 2, a drive voltage VDD for driving the memory chip 2 is supplied to the electrode pad 201. A reference voltage VSS is supplied to the electrode pad 206. In the memory chip 2 of this embodiment, the reference voltage VSS is a ground voltage, but is not limited to this. A wide range of voltages can be used as the reference for the memory device 1.

[0016] Furthermore, a serial input signal conforming to a conventionally known communication method called a Serial Peripheral Interface (SPI) is supplied to the memory chip 2 via electrode pads 202 to 204. In the following description, when a value contained in a signal is referred to as "0" or "1," it is understood that this is taken to mean a low level or a high level, respectively.

[0017] The electrode pads 202 to 204 are connected to the control circuit 26. A chip select signal CSB is supplied to the electrode pad 202. A serial clock signal SCK is supplied to the electrode pad 203. Furthermore, a serial input signal SI is supplied to the electrode pad 204.

[0018] The control circuit 26 of each memory chip 2 starts driving in response to the chip select signal CSB. After that, the standby state of each of the X decoder 22 and the Y decoder 23 is released. The control circuit 26 serves as a block that switches each block between standby and non-standby.

[0019] The sense amplifier 24 also outputs a serial output signal SO corresponding to the value of the data stored in the memory cell CELL. The sense amplifier 24 is connected to an electrode pad 205. The serial output signal SO output from the sense amplifier 24 is supplied to the electrode pad 205.

[0020] 1, the upper memory chip 2A is disposed so as to be shifted in the second direction D2 with respect to the memory chip 2B. By shifting the upper memory chip 2A with respect to the memory chip 2B, it is possible to access the electrode pads 201-206 of the memory chip 2B. This makes it possible to connect bonding wires 4 to the electrode pads 201-206 of the upper memory chip 2A and the electrode pads 201-206 of the memory chip 2B, respectively. Note that in a configuration in which bonding wires 4 are connected to the electrode pads 201-206 that are vertically stacked, the upper memory chip 2A and the lower memory chip 2B may be disposed so as to completely overlap each other.

[0021] Electrode pads 201 of each of the two memory chips 2A and 2B are connected to lead frame 18 via bonding wires 4. Electrode pad 202 is connected to lead frame 11. Electrode pad 203 is connected to lead frame 12. Electrode pad 204 is connected to lead frame 13. Electrode pad 205 is connected to lead frame 14. Electrode pad 206 is connected to lead frame 15. The connections between the electrode pads 201 to 206 and the lead frames 11 to 18 are merely examples, and the present invention is not limited to this configuration.

[0022] The die bond frame 10 having the memory chip 2 and the lead frames 11 to 18 to which the electrode pads 201 to 206 of the memory chip 2 are connected by bonding wires 4 are sealed in a package 3 made of an insulating material such as resin.

[0023] The control circuits 26 of the upper memory chip 2A and the lower memory chip 2B each include a selection determination unit 27 that determines whether the memory chip is selected or not. The selection determination unit 27 determines whether the memory chip is selected or not based on information of a specific bit (most significant bit WA16) of the address specification part included in the serial input signal SI (read command or write command).

[0024] When the value of the most significant bit WA16 is "1", selection determination unit 27 of control circuit 26 of upper memory chip 2A determines that upper memory chip 2A has been selected. When the value of the most significant bit WA16 is "0", selection determination unit 27 of control circuit 26 of lower memory chip 2B determines that lower memory chip 2B has been selected.

[0025] Next, the operation of selection determination unit 27 of control circuit 26 when memory chip 2 is selected will be described with reference to the drawings. Fig. 3 is a flowchart showing the procedure for selecting upper memory chip 2A or lower memory chip 2B.

[0026] 3, before the selection determination operation is performed, the memory chip 2 waits in a standby state (step S101). In this state, a chip select signal CSB is input to the control circuit 26 of the memory chip 2. In response to the chip select signal CSB, the selection determination unit 27 starts the selection determination operation (step S102). As shown in FIG. 5 and other figures described later, the operation of the selection determination unit 27 starts when the chip select signal CSB falls from a high level to a low level.

[0027] Thereafter, the selection determination unit 27 acquires chip identification information from the sense amplifier 24 (step S103). The selection determination unit 27 also acquires data of the most significant bit WA16 of the address designation part of the serial input signal SI (step S104).

[0028] Then, the selection determination unit 27 compares the chip identification information with the data of the most significant bit WA16 (step S105). If the chip identification information and the data of the most significant bit WA16 are the same (Yes in step S105), the selection determination unit 27 determines that the memory chip 2 is selected (step S106). Thereafter, in accordance with the instruction written in the serial input signal SI, the control circuit 26 executes a read operation to read data from the memory cell CELL or a write operation to write data to the memory cell CELL (step S107). Thereafter, the control circuit 26 returns the memory chip 2 to the standby state (step S101).

[0029] If the chip identification information and the data of the most significant bit WA16 are different (No in step S105), selection determination unit 27 determines that memory chip 2 is not selected (step S108). Control circuit 26 returns memory chip 2 to the standby state (step S101).

[0030] The memory device 1 determines which of the two memory chips 2A, 2B has been selected based on the value of the most significant bit WA16 of the address specification part of the serial input signal SI, and then executes a read or write operation in the selected memory chip 2A, 2B.

[0031] Next, details of the selection determination unit 27 of the control circuit 26 will be described with reference to the drawings. Fig. 4 is a block diagram showing the configuration of the selection determination unit 27 of the control circuit 26.

[0032] The memory chip 2 is provided with an identification information storage area 20 for storing chip identification information for identifying the memory chip 2. In the memory device 1, the chip identification information of the memory chip 2A is “1” and the chip identification information of the memory chip 2B is “0.” The sense amplifier 24 is configured to be able to access the identification information storage area 20 and to be able to acquire the chip identification information from the identification information storage area 20.

[0033] As shown in FIG. 4, the selection determination unit 27 includes a chip identification information latch circuit 271, a specific bit data latch circuit 272, a comparison circuit 273, and an error detection circuit 274.

[0034] The chip identification information latch circuit 271 is connected to the sense amplifier 24. The sense amplifier 24 outputs chip identification information for identifying the memory chip 2.

[0035] The chip identification information latch circuit 271 receives an identification information set signal CHIP_INFO_REG_SET. The chip identification information latch circuit 271 also receives chip identification information from the sense amplifier 24 and holds the chip identification information based on the identification information set signal CHIP_INFO_REG_SET. The chip identification information latch circuit 271 then outputs a chip selection signal CHIP_ADDRESS at the held level. The chip identification information latch circuit 271 is, for example, a flip-flop. Chip identification information is input to an input terminal, and the identification information set signal CHIP_INFO_REG_SET is input to a set terminal. The chip identification information latch circuit 271 holds the chip identification information when the identification information set signal CHIP_INFO_REG_SET goes high.

[0036] The specific bit data latch circuit 272 holds the data of a specific bit (the most significant bit WA16) of the addressing section of the serial input signal SI included in the serial input signal SI, here "0" or "1". The specific bit data latch circuit 272 outputs an identifying data signal WA16_DETECT according to the data of the most significant bit WA16. The identifying data signal WA16_DETECT is at a high level when the data of the most significant bit WA16 is "1", and at a low level when the data of the most significant bit WA16 is "0". The specific bit data latch circuit 272 is, for example, a flip-flop.

[0037] The comparison circuit 273 receives the chip selection signal CHIP_ADDRESS from the chip identification information latch circuit 271 and the identification data signal WA16_DETECT from the specific bit data latch circuit 272. The comparison circuit 273 compares the chip selection signal CHIP_ADDRESS with the identification data signal WA16_DETECT and outputs the result to the error detection circuit 274.

[0038] The comparison circuit 273 outputs a low-level error detection signal CHIP_DETECT_ERR when the chip selection signal CHIP_ADDRESS and the identification data signal WA16_DETECT are both high or low. Also, the comparison circuit 273 outputs a high-level error detection signal CHIP_DETECT_ERR when the chip selection signal CHIP_ADDRESS and the identification data signal WA16_DETECT are at different levels (see FIGS. 5 to 8, which will be described later). The comparison circuit 273 is, for example, an XOR circuit.

[0039] The error detection circuit 274 outputs a system reset signal SYS_RESET in response to the error detection signal CHIP_DETECT_ERR output from the comparison circuit 273. When the error detection signal CHIP_DETECT_ERR is at a high level, the error detection circuit 274 outputs a high-level system reset signal SYS_RESET. When a high-level system reset signal SYS_RESET is output, the control circuit 26 transitions the system to a standby state. When the system reset signal SYS_RESST output from the error detection circuit 274 is at a low level, the control circuit 26 continues to operate.

[0040] The following describes in detail the operation of the control circuit 26 of the upper memory chip 2A and the control circuit 26 of the lower memory chip 2B when the upper memory chip 2A is selected, with reference to the drawings. Figure 5 is a diagram showing the operating state of the upper memory chip 2A when the upper memory chip 2A is selected for a read operation. Figure 6 is a diagram showing the operating state of the lower memory chip 2B when the upper memory chip 2A is selected for a read operation.

[0041] 5 and 6, a chip select signal CSB is input to the control circuit 26 of each of the memory chips 2A and 2B. In the control circuit 26 of each of the memory chips 2A and 2B, the serial clock signal SCK begins to alternate between low and high levels at the timing when the chip select signal CSB falls to low level.

[0042] Thereafter, the sense amplifier enable signal SAMP_EN falls, releasing the standby state of the sense amplifier 24. After the sense amplifier enable signal SAMP_EN falls, the Y decoder enable signal YDEC_EN and the X decoder enable signal XDEC_EN rise, releasing the standby states of the X decoder 22 and the Y decoder 23. As shown in Figures 5 and 6, after the sense amplifier enable signal SAMP_EN falls, a serial input signal SI is input to each of the memory chips 2A and 2B.

[0043] The first few bits (e.g., 8 bits) of the serial input signal SI are an instruction code, and include information on whether the operation performed by the serial input signal SI is a read operation or a write operation. The next few bits (e.g., 24 bits) are an address specification section. This is the end of the serial input signal SI that specifies a read operation. On the other hand, the serial input signal SI that specifies a write operation includes several bits (e.g., 8 bits) of input data after the address specification section.

[0044] 5 and 5, in each memory chip 2A, 2B, the sense amplifier 24 outputs chip identification information during the period from the falling edge of the sense amplifier enable signal SAMP_EN until the X decoder 22 and the Y decoder 23 are again in the standby state. The chip identification information latch circuit 271 holds the chip identification information when it receives the identification information set signal CHIP_INFO_REG_SET at a high level.

[0045] As shown in FIG. 5, in the upper memory chip 2A, the chip identification information latch circuit 271 outputs a high-level chip selection signal CHIP_ADDRESS.

[0046] When the upper memory chip 2A is selected, the data of the most significant bit WA16 of the addressing section of the serial input signal SI is "1." Therefore, as shown in Fig. 5, the data of the most significant bit WA16 of "1" is input to the specific bit data latch circuit 272 of the upper memory chip 2A. Then, at the timing when the system clock SCK rises to a high level during the period when the data of the most significant bit WA16 of the addressing section of the serial input signal SI is acquired, the specific bit data latch circuit 272 outputs a high-level identification data signal WA16_DETECT.

[0047] 5, when the system clock SCK rises to high level during the period when the data of the most significant bit WA16 of the address specification part of the serial input signal SI is acquired, the chip selection signal CHIP_ADDRESS and the identification data signal WA16_DETECT both go to high level. As a result, the comparison circuit 273 outputs a low-level error detection signal CHIP_DETECT_ERR to the error detection circuit 274.

[0048] As a result, a low-level system reset signal SYS_RESET is output from the error detection circuit 274. Then, the control circuit 26 of the upper memory chip 2A pulls XDEC_EN and YDEC_EN down to low level. This allows information to be read from the memory cells of the upper memory chip 2A. Thereafter, the data read from the memory cells is output as a serial output signal SO via the sense amplifier 24.

[0049] 6, in the lower memory chip 2B, a high-level identification information set signal CHIP_INFO_REG_SET is input to the chip identification information latch circuit 271. As a result, the chip identification information latch circuit 271 holds the chip identification information from the sense amplifier 24 and outputs a low-level chip selection signal CHIP_ADDRESS.

[0050] Furthermore, when the upper memory chip 2A is selected, the data of the most significant bit WA16 of the addressing section of the serial input signal SI is "1." Therefore, as shown in Fig. 6, the data of the most significant bit WA16 of "1" is input to the specific bit data latch circuit 272 of the lower memory chip 2B. Then, at the timing when the system clock SCK rises to a high level during the period when the data of the most significant bit WA16 of the addressing section of the serial input signal SI is acquired, the specific bit data latch circuit 272 outputs a high-level identification data signal WA16_DETECT.

[0051] 6, when the system clock SCK rises to high level during the period when the data of the most significant bit WA16 of the address specification part of the serial input signal SI is acquired, the chip selection signal CHIP_ADDRESS is low level and the identification data signal WA16_DETECT is high level. Therefore, the comparison circuit 273 outputs a high level error detection signal CHIP_DETECT_ERR to the error detection circuit 274.

[0052] The error detection circuit 274 outputs a high-level system reset signal SYS_RESET, which causes the control circuit 26 of the lower memory chip 2B to reset the system and enter a standby state.

[0053] Next, the details of the operation of the control circuit 26 of the upper memory chip 2A and the control circuit 26 of the lower memory chip 2B when the lower memory chip 2B is selected will be described with reference to the drawings. Figure 7 is a diagram showing the operating state of the upper memory chip 2A when the lower memory chip 2B is selected for a read operation. Figure 8 is a diagram showing the operating state of the lower memory chip 2B when the lower memory chip 2B is selected for a read operation.

[0054] When the lower memory chip 2B is selected, the data of the most significant bit WA16 of the address specification section of the serial input signal SI becomes "0." Therefore, in the upper memory chip 2A, a low-level identification data signal WA16_DETECT is output from the specific bit data latch circuit 272. As a result, a high-level chip selection signal CHIP_ADDRESS and a low-level identification data signal WA16_DETECT are input to the comparison circuit 273 of the upper memory chip 2A. Therefore, a high-level error detection signal CHIP_DETECT_ERR is output from the comparison circuit 273, and a high-level system reset signal SYS_RESET is output from the error detection circuit 274. As a result, the control circuit 26 of the upper memory chip 2A resets the system and enters a standby state.

[0055] Furthermore, in the lower memory chip 2B, a low-level identification data signal WA16_DETECT is output from the specific bit data latch circuit 272. As a result, a low-level chip selection signal CHIP_ADDRESS and a low-level identification data signal WA16_DETECT are input to the comparison circuit 273 of the upper memory chip 2A. As a result, a low-level error detection signal CHIP_DETECT_ERR is output from the comparison circuit 273, and a low-level system reset signal SYS_RESET is output from the error detection circuit 274.

[0056] Then, the control circuit 26 of the lower memory chip 2B pulls down XDEC_EN and YDEC_EN to low level. This causes information to be read from the memory cells of the lower memory chip 2B. Thereafter, the data read from the memory cells is output as a serial output signal SO via the sense amplifier 24.

[0057] The above-mentioned operation has been explained as an operation for selecting memory chip 2A or memory chip 2B during a read operation, in which data is read from memory array 21 of upper memory chip 2A or memory array 21 of lower memory chip 2B. During a write operation, the same operation can be used to select either memory chip 2A or memory chip 2B.

[0058] This configuration allows the memory capacity of the memory device 1 to be increased without increasing the area of ​​the memory array 21. This makes it possible to provide a memory device with a large memory capacity using a conventional frame. Furthermore, because a conventional frame can be used, the equipment for performing wafer tests can be standardized regardless of the memory capacity. Furthermore, because the memory capacity of the memory device 1 is divided between two memory chips 2, even if an abnormality occurs in the wafer state, the area to be discarded can be reduced. This makes it possible to improve yield.

[0059] Furthermore, by switching between two memory chips, the capacity of the charge pump circuit can be kept small, which makes it possible to reduce noise and power consumption. Furthermore, it is possible to increase the memory capacity without using a miniaturization process.

[0060] <First Modification> A memory device 1A of the first modified example will be described with reference to the drawings. FIG. 9 is a diagram showing the memory device 1A of the first modified example. As shown in FIG. 9, a memory chip 5 is used in the memory device 1A. The memory chip 5 has electrode pads 201 to 206 on both sides of the memory array 21 in the second direction D2. Other than this, the memory chip 5 has the same configuration as the memory chip 2. Therefore, the same parts of the memory chip 5 as those of the memory chip 2 are denoted by the same reference numerals, and detailed description of the same parts will be omitted.

[0061] As shown in Fig. 9, the memory chip 5 has electrode pads 201-206 on each side of the memory array 21 in the second direction D2. As shown in Fig. 9 and other figures, in the memory device 1, the eight lead frames 11-18 are arranged in a row of four on each side of the memory chip 2. The lead frames 11-14 arranged on the left side are connected to the left electrode pads 201-206 with bonding wires 4. The lead frames 15-18 arranged on the right side are connected to the right electrode pads 201-206 with bonding wires 4. In this way, the bonding wires 4 can be shortened.

[0062] <Second Modification> A memory device 1B of the second modified example will be described with reference to the drawings. FIG. 10 is a side view of a memory chip 6 used in the memory device 1B of the second modified example. As shown in FIG. 10, in the memory chip 6, the electrode pads 201-206 arranged on the right side of the memory array 21 in the second direction D2 are arranged on the underside in the first direction D1. Other than this, the memory chip 6 has the same configuration as the memory chip 5. Therefore, the same parts of the memory chip 6 as those in the memory chip 5 are denoted by the same reference numerals, and detailed descriptions of the same parts will be omitted.

[0063] 10, the electrode pads 201-206 arranged on the right side of the memory chip 6 are located on the lower surface in the first direction D1. With this configuration, the upper memory chip 6 is arranged to the right of the lower memory chip 6, so that the electrode pads 201-206 can be exposed to the outside. This makes it easier to connect bonding wires 4 to the electrode pads 201-206, facilitating manufacturing.

[0064] <Third Modification> The above-described memory devices 1, 1A, and 1B are configured to have two memory chips 2, 5, and 6. However, the number of memory chips is not limited to two, and may be three or more. A configuration having three or more memory chips 2 will be described with reference to the drawings.

[0065] Fig. 11 is a block diagram of the selection determination unit 28 of a memory device 1C having four memory chips 2. Fig. 12 is a diagram showing an example of chip identification information when four memory chips 2 are included.

[0066] 11, the control circuit 26 of the memory device 1C has a selection determination unit 28. The selection determination unit 28 has a chip identification information latch circuit 281, a specific bit data latch circuit 282, a comparison circuit 283, and an error detection circuit 274.

[0067] The memory device 1C has four memory chips 2. The four memory chips 2 are referred to as memory chips 2K, 2L, 2M, and 2N. In a configuration having four memory chips 2 like this, it is not possible to identify the memory chips 2 using only the value of one bit (the most significant bit) of the addressing section of the serial input signal SI. Therefore, when using a memory device 1C having four memory chips 2, identification is performed using the value of two bits (the two most significant bits) of the addressing section of the serial input signal SI.

[0068] 12, the chip identification information of memory chip 2K is (0, 0), the chip identification information of memory chip 2L is (0, 1), the chip identification information of memory chip 2M is (1, 0), and the chip identification information of memory chip 2N is (1, 1). Then, selection determination unit 28 of control circuit 26 determines the selected memory chip according to the value of the most significant bit WA16 of the address specification part of serial input signal SI and the value of the next bit WA15.

[0069] The chip identification information latch circuit 281 is configured to hold chip identification information composed of two values. The specific bit data latch circuit 282 is configured to hold the value of the most significant bit WA16 and the data of the next bit WA15 as a set of data. The comparator circuit 283 is configured to compare the binary chip identification information with a combination of the value of the most significant bit WA16 and the value of the next bit WA15, and output a low-level error detection signal CHIP_DETECT_ERR only when there is a perfect match.

[0070] A description will be given of an example of the selection determination unit 28. In the following description, the first value of the chip identification information consisting of two values ​​is referred to as a first identification value h1, and the second value is referred to as a second identification value h2.

[0071] 11, the chip identification information latch circuit 281 of the selection determination unit 28 has a first latch circuit 281A and a second latch circuit 281B. The first latch circuit 281A receives a first identification value h1 and holds the first identification value h1. The second latch circuit 281B receives a second identification value h2 and holds the second identification value h2.

[0072] Similarly, the specific bit data latch circuit 282 has a first latch circuit 282A and a second latch circuit 282B. The value of the most significant bit WA16 is input to the first latch circuit 282A, and the value of the most significant bit WA16 is held therein. The value of the next most significant bit WA15 is input to the second latch circuit 282B, and the value of the next most significant bit WA15 is held therein.

[0073] The comparison circuit 283 has a first comparison circuit 283A, a second comparison circuit 283B, and an OR circuit 283C. The first comparison circuit 283A compares the output of the first latch circuit 281A of the chip identification information latch circuit 281 with the output of the first latch circuit 282A of the specific bit data latch circuit 282. The first comparison circuit 283A outputs "0" if the input data have the same value, and outputs "1" if the input data have different values.

[0074] The second comparison circuit 283B compares the output of the second latch circuit 281B of the chip identification information latch circuit 281 with the output of the second latch circuit 282B of the specific bit data latch circuit 282. The second comparison circuit 283B outputs "0" if the input data have the same value, and outputs "1" if the values ​​are different.

[0075] The OR circuit 283C receives the output of the first comparison circuit 283A and the output of the second comparison circuit 283B. The OR circuit 283C outputs a low-level error detection signal CHIP_DETECT_ERR when the output of the first comparison circuit 283A and the output of the second comparison circuit 283B are both "0", and outputs a high-level error detection signal CHIP_DETECT_ERR in other cases. The error detection signal CHIP_DETECT_ERR output from the OR circuit 283C is input to the error detection circuit 274. The error detection circuit 274 has the same configuration as the error detection circuit 274 of the selection determination unit 27, and a detailed description thereof will be omitted.

[0076] By using the selection determination unit 28 configured in this manner, it is possible to select a memory chip in the memory device 1C having four memory chips 2K, 2L, 2M, and 2N, and perform a read operation or a write operation on the selected memory chip.

[0077] The number of memory chips is not limited to the above-mentioned 2 and 4. There is no limit to the number as long as it can be identified using the bits of the addressing part of the serial input signal SI. In further explanation, by using an n-bit value for chip identification information, nIt is possible to identify up to 100 memory chips.

[0078] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0079] <Additional Notes> The various embodiments described above will be generally described below.

[0080] The memory devices (1, 1A, 1B, 1C) described above have the same structure and include a plurality of memory chips (2, 2A, 2B, 2K, 2L, 2M, 2N, 5, 6) stacked in a first direction (D1), and a plurality of lead frames (11-18) arranged adjacent to the memory chips (2, 2A, 2B, 2K, 2L, 2M, 2N) in a second direction (D2) intersecting the first direction (D1) and configured to be connected to each of a plurality of pads (201-206) provided on each memory chip (2, 2A, 2B, 2K, 2L, 2M, 2N, 5, 6), The electrode pads (201 to 208) connected to the same lead frame (11 to 18) of each memory chip (2, 2A, 2B, 2K, 2L, 2M, 2N, 5, 6) are configured to be the same type of electrode pads (201 to 208) (first configuration).

[0081] In the memory device (1A) of the first configuration, the memory chip (2) has a configuration (second configuration) in which the same type of electrode pads (201 to 206) are arranged on both sides of the memory array (21).

[0082] In the memory device (1, 1A, 1B, 1C) of the first or second configuration, the memory chip (2, 2A, 2B, 2K, 2L, 2M, 2N, 5, 6) is configured (third configuration) to determine whether or not it has been selected as the memory chip (2, 2A, 2B, 2K, 2L, 2M, 2N, 5, 6) on which the write operation or read operation is to be performed, based on information in specific bits (WA16, WA15, 6) of the address specification section included in a write command received during a write operation to write information and a read command received during a read operation to read information.

[0083] In the memory device (1A, 1B, 1C) of the third configuration, chip identification information for identifying itself is stored (fourth configuration).

[0084] In the memory device (1, 1A, 1B, 1C) of the fourth configuration described above, each memory chip (2, 2A, 2B, 2K, 2L, 2M, 2N, 5, 6) is configured (fifth configuration) to read chip identification information stored in each memory chip (2, 2A, 2B, 2K, 2L, 2M, 2N, 5, 6) during command execution, and compare it with information in specific bits (WA16, WA15, 6) of the address specification section included in the write command or read command to determine whether the memory chip (2, 2A, 2B, 2K, 2L, 2M, 2N, 5, 6) on which the write operation or read operation is to be performed is selected.

[0085] In a memory device (1, 1A, 1B, 1C) having any of the third to fifth configurations described above, the unselected memory chips (2, 2A, 2B, 2K, 2L, 2M, 2N, 5, 6) are configured to wait in a standby state (sixth configuration).

[0086] In the memory device (1B) of any of the first to sixth configurations, each memory chip (6) is configured (seventh configuration) to be stacked and shifted so that at least a portion of each type of electrode pad (201 to 206) is exposed on one side of the first direction (D1). [Explanation of symbols]

[0087] 1, 1A, 1B, 1C memory devices 2, 2A, 2B, 2K, 2L, 2M, 2N, 5, 6 memory chips 3 packages 4 Bonding Wire 10 Die bond frame 11~18 Lead frame 20 Identification information storage area 21 Memory Array 22X Decoder 23 Y decoder 24 Sense Amplifier 25 Output Buffer 26 Control circuit 27 Selection decision section 271 Chip identification information latch circuit 272 Specific bit data latch circuit 273 Comparison circuit 274 Error Detection Circuit 28 Selection decision section 281 Chip identification information latch circuit 281A First latch circuit 281B Second latch circuit 282 Specific bit data latch circuit 282A First latch circuit 282B Second latch circuit 283 Comparison circuit 283A 1st comparison circuit 283B 2nd comparison circuit 283C OR circuit 201~206 Electrode pads

Claims

1. a plurality of memory chips having the same structure and stacked in a first direction; a plurality of lead frames arranged adjacent to the memory chips in a second direction intersecting the first direction and configured to be connected to a plurality of electrode pads provided on each of the memory chips, A memory device configured such that the electrode pads connected to the same lead frame of each of the memory chips are of the same type.

2. 2. The memory device according to claim 1, wherein the memory chip is configured such that the same type of electrode pads are arranged on both sides of a memory array.

3. The memory device of claim 1, wherein the memory chip is configured to determine whether it has been selected as the memory chip on which the write operation or read operation is to be performed based on information in a specific bit of the address specification section contained in a write command received during a write operation to write information and a read command received during a read operation to read information.

4. 4. The memory device of claim 3, wherein each of the memory chips is configured to store chip identification information for identifying itself.

5. The memory device of claim 4, wherein each of the memory chips is configured to read chip identification information stored in each of the memory chips during command execution and compare it with information in a specific bit of the address specification section included in the write command or read command to determine whether it has been selected as the memory chip on which the write operation or read operation is to be performed.

6. 4. The memory device of claim 3, wherein the unselected memory chips are configured to wait in a standby state.

7. 2. The memory device according to claim 1, wherein the memory chips are stacked with a shift so that at least a portion of each type of electrode pad is exposed on one side in the first direction.

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