Wiring board and manufacturing method of wiring board

Abstract

To provide a wiring board capable of high-speed transmission and also capable of achieving adhesion to an insulating layer.SOLUTION: A wiring board includes a substrate, and a plurality of conductor layers formed on the substrate, and has a smooth surface region having a smooth surface of the conductor layers, and a rough surface region having a rough surface of the conductor layers. The conductor layer having the surface with the smooth surface region includes a surface of a high-speed transmission wiring, and the conductor layer having the surface with the rough surface region includes a solid pattern or a regular wiring. A manufacturing method of the wiring board according to the present invention includes steps of: forming a seed layer on the substrate; forming the plurality of conductor layers on the seed layer by electroplating; performing a process of removing the seed layer exposed between the conductor layers by a laser process (hereinafter, referred to as "laser process removal"); and performing a process of removing different seed layers exposed between the conductor layers by a wet process (hereinafter, referred to as "wet process removal") .SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] Circuit boards, which have conductor wiring formed on them, are used as electronic circuits with various functions by mounting electronic components on them. In recent years, the miniaturization and high performance of electronic circuits have led to faster and finer wiring on circuit boards, and the use of more layers. Accordingly, the conductor wiring on boards must be formed into multiple conductor layers with different widths, pattern shapes, and layouts depending on their function: high-speed transmission wiring for high-speed transmission, standard wiring such as power supply wiring, and solid patterns (plane layers) for grounding. For example, high-speed transmission wiring is required to be finely tailored to high speeds. Furthermore, to stabilize the characteristic impedance of the wiring, the pattern is formed adjacent to, and preferably surrounded by, a solid pattern with a stable potential. In contrast, standard wiring can have a line width suitable for low-speed transmission, and the pattern does not need to be adjacent to a solid pattern. A solid pattern is typically formed using a wide, flat conductor layer.

[0003] Another example of multilayering is a build-up multilayer wiring board. Figure 1 is a cross-sectional view of an example of a build-up multilayer wiring board. A first build-up layer, a second build-up layer, and a third build-up layer are stacked on top of a core layer (positive direction of the z-axis). A solder resist layer is then formed on top of the third build-up layer, and electronic components are mounted by adhering solder balls (not shown) to the exposed ball pads. Note that in Figure 1, build-up layers are also stacked below the core layer (negative direction of the z-axis) via through-holes, but this description is omitted. Conductor layers (wiring, plane layers) are formed on the insulating layers (substrates) in the core layer and each buildup layer, and the conductor layers in different buildup layers are connected to each other by vias.

[0004] The semi-additive process is known as a method for forming a fine conductor layer on a substrate. In general, the semi-additive process involves forming a plating resist pattern on a substrate on which a thin metal film that serves as a plating seed layer has been deposited by electroless plating or sputtering, followed by electrolytic plating to grow a conductor layer pattern that will become a circuit. Thereafter, the plating resist is removed, and then the seed layer between the conductor layers is removed to produce a wiring board.

[0005] If chemical etching is used to remove the seed layer, the width of the wiring pattern will be narrowed, and furthermore, the surface of the conductor layer that comes into contact with the etching solution will become uneven, so if used as high-speed transmission wiring, there will be a problem that the skin effect will cause a delay in the current on the surface, degrading the high-speed transmission characteristics.To address this, Patent Document 1 and Patent Document 2 disclose a method for manufacturing a wiring board in which a seed layer formed on the entire surface of the substrate is irradiated with a laser (laser ablation) to remove the seed layer in a predetermined pattern, and then electrolytic plating is performed on the remaining seed layer pattern. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2020 / 003881 [Patent Document 2] Japanese Patent Application Publication No. 7-66533 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the prior art of Patent Document 1 or Patent Document 2, the laser irradiation area is generally small compared to the area of ​​the seed layer to be removed, so removal takes time, and if the laser irradiation time is long, the substrate is heated, causing thermal damage and warping, which cannot be adequately addressed. Furthermore, while laser irradiation can maintain high-speed transmission characteristics while keeping the conductor layer surface smooth, laminating an insulating layer on a conductor layer with a smooth surface can result in insufficient adhesive strength, leading to peeling, and the prior art does not disclose any awareness of this problem. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a wiring board that is capable of high-speed transmission and also provides adhesion to an insulating layer. [Means for solving the problem]

[0008] In order to solve the above problems, one representative wiring board of the present invention has a substrate and a plurality of conductor layers formed on the substrate, and is provided with a smooth surface region where the surface of the conductor layer is smooth and a rough surface region where the surface of the conductor layer is rough. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a wiring board that is capable of achieving high-speed transmission characteristics and also has good adhesion to an insulating layer. Problems, configurations, and effects other than those described above will become apparent from the following description of the preferred embodiments. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a cross-sectional view of an example of a build-up multilayer wiring board. [Figure 2] FIG. 2 is a schematic diagram of a wiring board according to Comparative Example 1. As shown in FIG. [Figure 3A] FIG. 3A is a schematic diagram showing a procedure for manufacturing a wiring substrate by a wet process in Comparative Example 1. As shown in FIG. [Figure 3B] FIG. 3B is a schematic diagram showing a procedure for manufacturing a wiring substrate by a wet process in Comparative Example 1. As shown in FIG. [Figure 4] Figure 4 shows SEM images of the smooth and rough areas of the surface of the conductor layer. [Figure 5] FIG. 5 is a schematic diagram showing a wet process in a modified example of Comparative Example 1. In FIG. [Figure 6] FIG. 6 is a schematic diagram showing the procedure for manufacturing a wiring board by a laser process in Comparative Example 2. In FIG. [Figure 7] FIG. 7 is a schematic diagram of the wiring board according to the first embodiment. [Figure 8A] FIG. 8A is a schematic diagram showing a procedure for manufacturing a wiring substrate by a laser process and a wet process in Example 1. FIG. [Figure 8B] FIG. 8B is a schematic diagram showing a procedure for manufacturing a wiring substrate by a laser process and a wet process in Example 1. [Figure 9A] FIG. 9A is a schematic diagram showing a procedure for manufacturing a wiring substrate by a wet process and a laser process in Example 2. [Figure 9B] FIG. 9B is a schematic diagram showing a procedure for manufacturing a wiring substrate by a wet process and a laser process in Example 2. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the present invention is not limited to this embodiment. In addition, in the description of the drawings, the same parts are designated by the same reference numerals.

[0012] In disclosing the embodiments, directions indicated by the x-axis, y-axis, and z-axis shown on the drawings may be used to indicate directions. Unless otherwise specified, a "plan view" refers to a surface viewed from the z-axis direction, and a "cross-sectional view" refers to a cross-sectional view cut along a plane parallel to the z-axis. Furthermore, "upper" and "upper" refer to the positive direction of the z-axis, and "lower" and "lower" refer to the negative direction of the z-axis.

[0013] In the disclosure of the embodiments, the term "wiring" does not only refer to a linear conductor layer, but also includes a planar pattern such as a solid pattern. A solid pattern is also called a plane layer, a plane pattern, a ground (GND) plane, a power plane, or a polygon pattern.

[0014] In the disclosure of the embodiments, "high-speed transmission" means having a transmission characteristic of 1 GHz or more, and "low-speed transmission" means having a transmission characteristic of less than 1 GHz.

[0015] (Comparative Example 1) First, comparative example 1 will be described. FIG. 2 is a schematic diagram of a wiring board according to comparative example 1. FIG. 2(a) is a plan view, and FIG. 2(b) is a cross-sectional view taken along the line pp. A seed layer 20 is formed on a substrate 10, and a conductor layer 30 is formed on top of that. Multiple conductor layers 30 exist depending on their functions, and in the example of FIG. 2, high-speed transmission wiring 30A, a solid pattern 30B, and normal wiring 30C are formed. The high-speed transmission wiring 30A is wiring for high-speed transmission, the solid pattern 30B is a ground pattern for grounding, and the normal wiring 30C is wiring for low-speed transmission or for connecting to the ground or power supply. Note that FIG. 2(b) shows an example in which the conductor layer 30 is formed by a wet process, which will be described later, and the surface is rough. Normally, wiring is arranged on the substrate 10 according to function, and the high-speed transmission wiring 30A and the solid pattern 30B are arranged adjacent to each other in the high-speed transmission wiring arrangement section (coplanar structure section) 70 so that the high-speed transmission wiring 30A is surrounded by the solid pattern 30B. In addition, the normal wiring 30C is arranged collectively in the wiring pattern arrangement section 80.

[0016] The substrate 10 is made of insulating resins (also called build-up resins) such as epoxy resin, BT (bismaleimide-triazine) resin, maleimide resin, polyimide, and liquid crystal polymer. Insulating resins have different dielectric constants and dielectric loss tangents that affect transmission characteristics depending on the material. Higher values ​​of dielectric constant and dielectric loss tangent have lower transmission characteristics (high frequencies are less likely to pass through), while lower values ​​have higher transmission characteristics.

[0017] The seed layer 20 is made of a conductive material to supply power to the substrate surface when forming the conductor layer 30 by electroplating. Copper is a common material, but other materials that can be used include aluminum, chromium, titanium, nickel, and tin. The conductor layer 30 is formed by electrolytic plating and is typically made of copper, with aluminum, chromium, titanium, nickel, tin, etc. Preferably, it is made of the same material as the seed layer 20. The high-speed transmission wiring 30A and the normal wiring 30C generally have a width of 10 to 100 μm and a thickness of 10 to 30 μm. The solid pattern 30B generally has a width of 100 μm or more and a thickness of 10 to 30 μm.

[0018] A description will be given of a method for manufacturing a wiring board according to Comparative Example 1. Figures 3A and 3B (sometimes collectively referred to as Figure 3) are schematic diagrams showing the procedure for manufacturing a wiring board by a semi-additive process in Comparative Example 1. First, a substrate 10 (insulating resin layer) is prepared (FIG. 3A(a)). Next, a copper seed layer 20 is formed over the entire surface of the substrate 10 in predetermined locations. This can be done using a wet process involving immersion in an electroless plating solution for a certain period of time, or a dry process using sputtering. In either case, the layer is formed to a predetermined thickness between 50 nm and 100 nm (FIG. 3A(b)). Next, a method for forming the plating resist 40 will be described. The plating resist 40 is a photosensitive dry film resist, often of the alkaline-developable type, which masks only the areas that will not be copper-plated when a conductor layer is formed on the seed layer 20 by electrolytic copper plating. First, a sheet-like dry film resist is applied as the plating resist 40 to the entire surface of the seed layer 20 using a roll laminator. Photosensitive dry film resists include negative-type and alkaline-developable resists, and the appropriate type is selected depending on the pattern shape, etc. Next, the plating resist 40 is exposed to light in a pattern using an exposure device (not shown). The exposure device uses a mercury lamp as a light source to expose the resist to light that includes g-line, h-line, and / or i-line. In addition, a photomask (not shown) is placed in the exposure device, where the light-shielding portions of the transparent substrate are patterned with metal chromium or the like to expose the resist to light in the shape of the conductor pattern. Next, the exposed plating resist 40 is baked together with the substrate 10, and then developed. The developer used may be an aqueous solution of sodium hydroxide, potassium hydroxide, sodium carbonate, or the like, or an aqueous amine-based solution. The development process involves immersing the substrate 10 in the developer in a developing device, or exposing it to a shower of developer, which dissolves the plating resist 40 in the areas where plating is desired. The substrate 10 is then washed with water, yielding plating resist 40 with the same shape as the conductor pattern formed on the photomask (FIG. 3A(c)). Next, copper plating is performed in an electrolytic copper plating tank (not shown). A power supply line is connected to the seed layer 20, and the substrate 10 is placed in the electrolytic copper plating tank filled with a plating solution mainly composed of copper sulfate. A predetermined amount of power is then supplied from an external power supply to the power supply line connected to the seed layer 20 and to a counter electrode placed in the plating solution. Copper is then deposited in the exposed areas of the seed layer 20 where the plating resist 40 is not formed, forming high-speed transmission wiring 30A, solid pattern 30B, and ordinary wiring 30C (FIG. 3A(d)). The high-speed transmission wiring 30A, solid pattern 30B, and ordinary wiring 30C (collectively referred to as the conductor layer 30) formed by electrolytic plating have smooth surface regions. Next, the plating resist 40 is removed. A stripper is used to remove the plating resist 40. This stripper has the same components as the developer described above. The difference between the stripper and developer is mainly in concentration, with the stripper having a higher concentration. As with development, the plating resist 40 is removed by immersion in the stripper, or by exposure to a shower of stripper. The substrate 10 is then washed with water to reveal the conductor layer 30 (Figure 3A(e)).

[0019] Next, the seed layer 20 exposed between the conductor layers 30 is removed. The high-speed transmission wiring 30A, solid pattern 30B, and normal wiring 30C of the conductor layer 30 will not function as independent wiring if the seed layer 20 formed on one surface of the substrate 10 remains, so it is necessary to remove the seed layer 20 exposed between the high-speed transmission wiring 30A, solid pattern 30B, and normal wiring 30C. Because the seed layer is approximately 100 nm thick, the etching process can be completed in a very short time, from 30 seconds to 1 minute, which is why it is also called flash etching. Flash etching is performed by immersing the substrate in an etching solution or by exposing the substrate to a shower of etching solution (Fig. 3B(f)). The etching solution used can be MEC Corporation's MEC Bright (registered trademark) QE series. In flash etching, the thickness of the seed layer 20 is approximately 100 nm, while the thickness of the conductor layer 30 is approximately 10 μm, which is a difference of nearly 100 times in thickness, so the degree to which the conductor layer 30 is eroded by the etching solution during the above period is negligible. In this way, the high-speed transmission wiring 30A, the solid pattern 30B, and the normal wiring 30C of the conductor layer 30 are insulated from one another (FIG. 3B(g)). Thereafter, an insulating resin is laminated on the substrate 10 so as to cover the surfaces of the high-speed transmission wiring 30A, the solid pattern 30B, the normal wiring 30C and the substrate surface, thereby forming an insulating layer 50 (FIG. 3B(h)).

[0020] Here, the relationship between the surface roughness of the conductor layer 30 and the transmission characteristics and adhesiveness will be explained. Figure 4 is an SEM image of a portion of the smooth and rough regions on the surface of the conductor layer. Figure 4(a) shows an image of a smooth surface area after copper electroplating (copper electroplating) and the plating resist have been peeled off (see Figure 3A(e)). The surface roughness (Ra) at this time is usually 20 to 40 nm. Figure 4(b) shows an image of the roughened area after flash etching of a conductor layer formed by electrolytic copper plating to remove the seed layer (electroless copper) (see Figure 3B(g)). Typically, the surface roughness (Ra) at this stage is 85 to 120 nm. If necessary, the conductor layer surface can be subjected to a roughening treatment (CZ treatment) to adjust the surface roughness to a range of approximately 110 to 700 nm. This roughening treatment is carried out by immersing the surface in a treatment solution, as with flash etching, or by exposing the surface to a shower of treatment solution. A CZ treatment solution (e.g., CZ8101 or 8201 manufactured by MEC) is used as the roughening treatment solution. In the disclosure of the embodiments, the term "rough region" refers to a surface region of a conductor layer with a surface roughness (Ra) of 85 nm or more, and the term "smooth region" refers to a surface region of a conductor layer with a surface roughness of less than 85 nm. The OLYMPUS LEXT OLS4100 laser microscope can be used to measure the surface roughness of the conductor layer. The measurement conditions were in accordance with the roughness measurement mode Ra (JIS 19954), and the measurement region was 300 μm.

[0021] 3B(g), the surface of the wiring board of Comparative Example 1 was subjected to CZ processing, forming a roughened area with a surface roughness (Ra) of 130 to 500 nm in the conductor layer 30. As a result, the transmission characteristics of the high-speed transmission wiring 30A were inadequate as it was unable to achieve high-speed transmission characteristics of 1 GHz or more. The measurement equipment used to measure transmission characteristics was the Keysight Technologies 8722ES network analyzer. The measurement conditions were to form a measurement pattern with a microstrip line structure, and to measure S11 at 500MHz, 1GHz, and 3GHz using a prober for measuring transmission characteristics (transmission loss).

[0022] Regarding the adhesiveness between the conductor layer 30 and the insulating layer 50 in Comparative Example 1, sufficient adhesive strength was obtained due to the anchor effect between the rough surface region of the conductor layer surface and the insulating resin.

[0023] (Modification of Comparative Example 1) In Comparative Example 1, a modified example will be described in which a protective resist 60 is formed on the high-speed transmission wiring 30A after the plating resist is peeled off after being formed by an electrolytic copper plating process. Fig. 5 is a schematic diagram showing another wet process for removing the seed layer 20 in the modified example of Comparative Example 1. FIG. 5(a) shows Comparative Example 1, in which after the patterning of the conductor layer 30 (see FIG. 3A(e)), the surface of the high-speed transmission wiring 30A in particular is covered with a protective resist 60, and then the wiring substrate is subjected to a wet process using an etching solution to remove the seed layer 20. Other procedures are the same as those in Comparative Example 1. Furthermore, the protective resist 60 may be formed on a portion of the surface of the adjacent solid pattern 30B, as long as it does not cover the seed layer 20 exposed between the solid patterns 30B adjacent to the high-speed transmission wiring 30A. In a modified example, the protective resist 60 may also be formed to cover the side surfaces of the high-speed transmission wiring 30A and the solid pattern 30B, as long as it does not cover the seed layer 20 exposed between the solid patterns 30B adjacent to the high-speed transmission wiring 30A. The same material as the plating resist 40 used in the semi-additive process can be suitably used for the protective resist 60. If the protective resist 60 is peeled off after removing the seed layer 20 with an etching solution, the surface of the high-speed transmission wiring 30A remains smooth, making it possible to ensure high-speed transmission characteristics. However, with this method, the protective resist 60 is stacked on the side, so the removed portion of the seed layer 20 (see W in Figure 5(a)) becomes narrower, resulting in insufficient insulation between the wirings. On the other hand, to ensure the removal width of the seed layer 20, it is necessary to considerably widen the gap (opening) between the high-speed transmission wiring 30A and the solid pattern 30B, which creates the problem of making design difficult in high-density wiring.

[0024] The modified example shown in FIG. 5(b) is similar to the modified example shown in FIG. 5(a), except that the protective resist 60 is formed so that the contour edges of the surfaces are exposed on the top surfaces of the high-speed transmission wiring 30A and the solid pattern 30B. In this case, too, if the protective resist 60 is peeled off after removing the seed layer 20 with an etching solution, the top surface of the high-speed transmission wiring 30A remains generally smooth, thereby ensuring high-speed transmission characteristics. Furthermore, compared to the modified example shown in FIG. 5(a), this method can avoid narrowing the removed portion of the seed layer 20 (see W in FIG. 5(b)). However, this method results in the conductor on the side surface of the conductor layer 30 being scraped off. Furthermore, undercuts occur on the side surface of the conductor layer 30, which can lead to the problem of peeling of the conductor layer 30.

[0025] (Comparative Example 2) A description will be given of a method for manufacturing a wiring board according to Comparative Example 2. Fig. 6 is a schematic diagram showing the procedure for manufacturing a wiring board by a laser process in Comparative Example 2. Since the process is the same as Comparative Example 1 except for the matters specifically described in Fig. 6, details will be omitted. First, as in Comparative Example 1, a substrate 10 (insulating resin layer) is prepared (FIG. 6(a)). Next, a copper seed layer 20 is uniformly formed over the entire surface of the substrate 10 in predetermined locations using a wet process by electroless plating or a dry process by sputtering (FIG. 6(b)). Next, a laser is irradiated from the laser head of a laser processing machine at predetermined locations (laser ablation) to remove the seed layer 20 (FIG. 6(c)). Next, electrolytic plating is performed on the remaining seed layer 20 to obtain the high-speed transmission wiring 30A, solid pattern 30B, and ordinary wiring 30C, which are the patterns of the conductor layer 30 (FIG. 6(d)). Thereafter, an insulating layer 50 is laminated on the substrate 10 so as to cover the surfaces of the high-speed transmission wiring 30A, solid pattern 30B, and ordinary wiring 30C, as well as the surface of the substrate (FIG. 6(e)).

[0026] The light source of the laser processing machine used to remove the seed layer 20 can be a CO2 laser, a UV-YAG laser (third harmonic, fourth harmonic), an excimer laser, or the like. In Comparative Example 2, a processing device using a UV-YAG laser as a light source was used, the laser irradiation spot was set to 50 μmΦ, a laser processing program was created, and the processing area was raster scanned according to the program to remove the seed layer 20. The substrate after the seed layer 20 removal process was subjected to acid washing to remove debris produced by the laser processing.

[0027] The high-speed transmission wiring 30A, which is a conductor layer with a smooth surface area created by a laser process, was able to achieve good high-speed transmission characteristics of 1 GHz or more. No problems were observed with the electrical characteristics of the solid pattern 30B and the normal wiring 30C. On the other hand, when laminating the insulating layer 50, a smooth surface does not provide sufficient adhesive strength between the insulating layer 50 and the surface due to the anchor effect, and a problem occurs in that the insulating layer 50 peels off significantly, particularly when the surface of the solid pattern 30B, which has a large contact area with the insulating layer 50, is smooth (see Figure 6(e)).

[0028] Example 1 Example 1 will be described. FIG. 7 is a schematic diagram of a wiring board according to Example 1. FIG. 7(a) is a plan view, and FIG. 7(b) is a cross-sectional view taken along line qq (details will be described later). A seed layer 120 is formed on a substrate 100, and a conductor layer 130 is formed thereon. There may be multiple conductor layers 130 depending on the function, and in the example of FIG. 7, high-speed transmission wiring 130A, a solid pattern 130B, and normal wiring 130C are formed. These wirings may be collectively referred to as conductor layer 130. The function, arrangement, material, etc. of conductor layer 130 are the same as those of Comparative Example 1, so details will be omitted.

[0029] A method for manufacturing a wiring board according to Example 1 will be described. Figures 8A and 8B (sometimes collectively referred to as Figure 8) are schematic diagrams showing the procedure for manufacturing a wiring board by a laser process and a wet process in Example 1. The procedure for pattern-forming the conductor layer 130 on the seed layer 120 is the same as in Comparative Example 1, so a description thereof will be omitted (see Figures 3A(a) to (e)). Therefore, the procedure for removing the seed layer 120 exposed between the conductor layers 130 in a state where the conductor layer 130 has been formed on the seed layer 120 (Figure 8A(a)) will be described first. First, similar to the laser process of Comparative Example 2 (see FIG. 6(c)), the seed layer 120 is removed by irradiating the seed layer exposed between the high-speed transmission wiring 130A and the solid pattern 130B with a laser (laser ablation) (FIG. 8A(b)). By removing the seed layer 120, the high-speed transmission wiring 130A is insulated from the adjacent solid pattern 130B while maintaining a smooth surface created by electrolytic plating (FIG. 8A(c)). Next, as shown in FIG. 7(a), a protective resist 160 is formed within the solid pattern 130B to cover the area surrounded by the perimeter S that surrounds the high-speed transmission wiring 130A (FIG. 8A(d)). The area surrounded by the perimeter S includes at least the high-speed transmission wiring 130A and the area where the seed layer 20 is removed by the laser process. FIG. 8A(d) shows a line segment rr connecting the intersection of the perimeter S and qq. The protective resist 160 can be made of the same material as the protective resist 60 used in the modified example of Comparative Example 1.

[0030] Next, the exposed seed layer 120 not covered with the protective resist 160 is removed using an etching solution in the same manner as in the wet process of Comparative Example 1 (see FIG. 3B(f)) (FIG. 8B(e)). As in Comparative Example 1, a roughening treatment may be performed using a CZ treatment solution during etching, if necessary. By removing the seed layer 120, the solid pattern 130B and the ordinary wiring 130C are insulated from each other (FIG. 8B(f)). At this time, the surface of the conductor layer 130 covered with the protective resist 160 (the high-speed transmission wiring 130A and a part of the solid pattern 130B) remains smooth, but the other surfaces of the conductor layer 130 (the solid pattern 130B and the ordinary wiring 130C) become rough. Next, the protective resist 160 is removed using a stripping solution (FIG. 8B(g)). Thereafter, an insulating layer 150 is laminated on the substrate 10 so as to cover the surfaces of the high-speed transmission wiring 130A, the solid pattern 130B, the ordinary wiring 130C, and the substrate surface (FIG. 8B(h)).

[0031] Example 2 A description will be given of Example 2. Example 2 is similar to Example 1 except that the order of the laser process and the wet process in the manufacturing method of the wiring board is different from that of Example 1, so the description will focus on the differences. 9A and 9B (sometimes collectively referred to as FIG. 9) are schematic diagrams illustrating the procedure for manufacturing a wiring substrate using a wet process and a laser process in Example 2. The procedure for removing the seed layer 120 exposed between the conductor layers 130, which are formed on the seed layer 120 (FIG. 9A(a)), will be described. First, as shown in FIG. 7(a), a protective resist 160 is formed in the solid pattern 130B so as to cover the area surrounded by the perimeter S that surrounds the high-speed transmission wiring 130A (FIG. 9A(b)). FIG. 9A(b) shows a line segment rr connecting the intersection of the perimeter S and qq. Next, the exposed seed layer 120 not covered by the protective resist 160 is removed by immersion in an etching solution in the same manner as in the wet process of Comparative Example 1 (see FIG. 3B(f)). As in Comparative Example 1, a roughening treatment using a CZ treatment solution may be performed during etching, if necessary. Next, the protective resist 160 is removed with a stripping solution. By removing the seed layer 120, the solid pattern 130B and the ordinary wiring 130C are insulated from each other (FIG. 9A(d)). At this time, the surface of the conductor layer 130 (the high-speed transmission wiring 130A and part of the solid pattern 130B) that was covered with the protective resist 160 remains smooth, but the other surfaces of the conductor layer 130 (the solid pattern 130B and the ordinary wiring 130C) become rough.

[0032] Next, similar to the laser process of Comparative Example 2 (see FIG. 6(c)), a laser is irradiated (laser ablation) onto the seed layer exposed between the high-speed transmission wiring 130A and the solid pattern 130B of the conductor layer 130, thereby removing the seed layer 120 (FIG. 9B(e)). By removing the seed layer 120, the high-speed transmission wiring 130A is insulated from the adjacent solid pattern 130B while maintaining a smooth surface created by electrolytic plating (FIG. 9B(f)). Thereafter, an insulating layer 150 is laminated on the substrate 10 so as to cover the surfaces of the high-speed transmission wiring 130A, the solid pattern 130B, the ordinary wiring 130C, and the substrate surface (FIG. 9B(g)).

[0033] According to Examples 1 and 2, the laser process is limited to the seed layer 120 exposed between the high-speed transmission wiring 130A and the solid pattern 130B surrounded by the perimeter S in Fig. 7(a), thereby reducing the irradiation area and irradiation time and making it possible to avoid thermal damage. On the other hand, the wet process is performed on the seed layer 120 in the remaining wide exposed region, and since etching of a wide area is possible in a short time by immersing the substrate in the etching solution, the seed layer 120 can be removed efficiently.

[0034] In addition, by using laser irradiation to remove the seed layer 120 exposed around the high-speed transmission wiring 130A, the surface of the high-speed transmission wiring 130A is maintained smooth (Ra of 20 to 40 nm), making it possible to ensure the high-speed transmission characteristics of the wiring. On the other hand, if the surface of most of the conductive layer that spreads over a plane such as solid pattern 130B has sufficient surface roughness, when insulating layer 150 is provided, the anchor effect improves adhesion and makes it less likely to peel off. Therefore, to ensure sufficient adhesive strength between a planar conductor layer such as the solid pattern 130B and the insulating resin, it is desirable for Ra to be 120 nm or greater. Therefore, to further increase Ra, a treatment using a roughening treatment solution is performed. Although the greater the degree of roughening treatment, the stronger the adhesive strength, it is desirable to optimize the amount of roughening treatment depending on the thickness of the conductor layer 30 of the wiring board. It is desirable for the surface roughness of the conductor layer 30 (excluding the high-speed transmission wiring 130A) to be 150 to 500 nm.

[0035] Thus, according to an embodiment of the present invention, by combining a laser process and a wet process in the seed layer 120 removal process, it is possible to improve processing efficiency without thermal damage, and obtain a wiring substrate that has improved adhesion to the insulating layer and can prevent peeling while maintaining the high-speed transmission characteristics of the high-speed transmission wiring.

[0036] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present invention. For example, the wiring formed on the wiring board can be applied to wiring other than high speed transmission wiring, solid patterns, and normal wiring, and the arrangement and number are not limited to those in the examples of the embodiment.

[0037] The following are examples of possible embodiments of the present invention, but the present invention is not limited to these. (Aspect 1) A substrate; a plurality of conductor layers formed on the substrate; The surface of the conductor layer is characterized by comprising a smooth surface region where the surface is smooth and a rough surface region where the surface of the conductor layer is rough. Wiring board. (Aspect 2) 2. The wiring board according to claim 1, wherein the surface of the high-speed transmission wiring is included in the smooth surface region. (Aspect 3) 3. The wiring board according to claim 1, wherein the surface of a solid pattern or a regular wiring is included in the roughened area. (Aspect 4) 4. The wiring board according to any one of aspects 1 to 3, wherein the smooth region has a surface roughness (Ra) of less than 85 nm, preferably 20 to 40 nm, and the rough region has a surface roughness (Ra) of 120 nm or more, preferably 150 to 500 nm. (Aspect 5) 5. The wiring board according to any one of aspects 1 to 4, further comprising an insulating layer on the conductor layer. (Aspect 6) A build-up multilayer wiring board comprising the wiring board according to any one of the first to fifth embodiments. (Aspect 7) forming a seed layer on the substrate; forming a plurality of conductor layers on the seed layer by electroplating; performing a process of removing the seed layer exposed between the conductor layers by a laser process (hereinafter referred to as "laser process removal"); performing a treatment to remove the different seed layers exposed between the conductor layers by a wet process (hereinafter referred to as "wet process removal"); A method for manufacturing a wiring board. (Aspect 8) performing a laser process removal on the seed layer exposed between the high-speed transmission wiring and the solid pattern; wet process removal is performed on the seed layer exposed between the solid pattern and the normal wiring or between the normal wirings; 8. The method for manufacturing a wiring board according to claim 7. (Aspect 9) 9. The method for producing a wiring board according to embodiment 8, wherein the laser process removal is followed by wet process removal. (Aspect 10) 9. The method for producing a wiring board according to embodiment 8, wherein the wet process removal is followed by laser process removal. (Aspect 11) 11. The method for manufacturing a wiring board according to any one of aspects 8 to 10, further comprising forming a protective resist to cover the surface of the high-speed transmission wiring and the area to be removed by a laser process before the wet process removal. [Explanation of symbols]

[0038] 10, 100...board 20, 120...seed layer 30, 130...conductor layers 30A, 130A...High-speed transmission wiring 30B, 130B...solid pattern 30C, 130C…normal wiring 40...Plating resist 50, 150...insulating layer 60, 160...Protective Resist 70...High-speed transmission wiring arrangement section (coplanar structure section) 80...Wiring pattern placement section

Claims

1. A substrate; a plurality of conductor layers formed on the substrate; The surface of the conductor layer is characterized by comprising a smooth surface region where the surface is smooth and a rough surface region where the surface of the conductor layer is rough. Wiring board.

2. 2. The wiring board according to claim 1, wherein the surface of the high-speed transmission wiring is included in the smooth surface area.

3. 2. The wiring board according to claim 1, wherein the surface of a solid pattern or a normal wiring is included in the roughened area.

4. The wiring board according to any one of claims 1 to 3, wherein the surface roughness (Ra) of the smooth surface region is less than 85 nm, preferably 20 to 40 nm, and the surface roughness (Ra) of the rough surface region is 120 nm or more, preferably 150 to 500 nm.

5. 4. The wiring board according to claim 1, further comprising an insulating layer on the conductor layer.

6. A build-up multilayer wiring board comprising the wiring board according to any one of claims 1 to 3.

7. forming a seed layer on the substrate; forming a plurality of conductor layers on the seed layer by electroplating; performing a process of removing the seed layer exposed between the conductor layers by a laser process (hereinafter referred to as "laser process removal"); performing a treatment to remove the different seed layers exposed between the conductor layers by a wet process (hereinafter referred to as "wet process removal"); A method for manufacturing a wiring board.

8. performing a laser process removal on the seed layer exposed between the high-speed transmission wiring and the solid pattern; wet process removal is performed on the seed layer exposed between the solid pattern and the normal wiring or between the normal wirings; 8. The method for manufacturing a wiring board according to claim 7.

9. 9. The method for manufacturing a wiring board according to claim 8, wherein the removal by a wet process is carried out after the removal by a laser process.

10. 9. The method for manufacturing a wiring board according to claim 8, wherein the removal by a laser process is carried out after the removal by a wet process.

11. 11. The method for manufacturing a wiring board according to claim 8, further comprising forming a protective resist so as to cover the surface of the high-speed transmission wiring and the area to be removed by a laser process before performing the wet process removal.

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