Method for manufacturing semiconductor storage device and semiconductor storage device

Abstract

To provide a semiconductor storage device capable of achieving high integration density, and a manufacturing method thereof.SOLUTION: A DRAM memory cell array 101, which is a semiconductor storage device, includes: a monocrystalline silicon substrate 10; a monocrystalline silicon layer 12 including a first n-type impurity region 12a, a second n-type impurity region 12b, and a p-type impurity region 12c; a gate electrode layer 14 facing a third portion P3 located between a first portion P1 and a second portion P2 of the monocrystalline silicon layer; a gate insulation film 16; a wiring layer 18 in contact with the first portion of the monocrystalline silicon layer; a storage node electrode 20; a capacitor insulation film 22; a plate electrode 24; a contact electrode 26; a first interlayer insulation layer 28; and a second interlayer insulation layer 30. The monocrystalline silicon layer, the gate electrode layer, and the gate insulation film constitute a transistor. In addition, the storage node electrode, the capacitor insulation film, and the plate electrode in contact with the second portion P2 of the monocrystalline silicon layer constitute a capacitor.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a method for manufacturing a semiconductor memory device and a semiconductor memory device. [Background technology]

[0002] To achieve high integration of Dynamic Random Access Memory (DRAM), memory cells can be arranged three-dimensionally. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0102394 [Patent Document 2] US Patent Application Publication No. 2022 / 0005810 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment of the present invention is to achieve a high degree of integration of a semiconductor memory device. [Means for solving the problem]

[0005] A method for manufacturing a semiconductor memory device according to an embodiment includes forming a first film of a first material in a first direction of a single crystal silicon substrate, forming a second film of a second material different from the first material in the first direction of the first film, forming a third film of a third material different from the second material in the first direction of the second film, forming a first opening that penetrates the third film, the second film, and the first film and reaches the single crystal silicon substrate, forming a first single crystal silicon layer in contact with the single crystal silicon substrate in the first opening, and forming a first single crystal silicon layer in contact with the single crystal silicon substrate. A second opening is formed through the second film, the second film is etched from the side of the second opening to form a first recess portion reaching the first single crystal silicon layer, a second single crystal silicon layer is formed in the first recess portion and in contact with the first single crystal silicon layer, a wiring layer is formed in contact with a first portion of the second single crystal silicon layer, a capacitor is formed in contact with a second portion of the second single crystal silicon layer, and a gate electrode layer is formed facing a third portion of the second single crystal silicon layer between the first portion and the second portion. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 2 is an equivalent circuit diagram of a memory cell array of the semiconductor memory device according to the first embodiment. [Figure 2] 1 is a schematic cross-sectional view of a semiconductor memory device according to a first embodiment. [Figure 3] 1 is a schematic cross-sectional view of a semiconductor memory device according to a first embodiment. [Figure 4] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 5] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 6] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 7] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 8] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 9]5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 11] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 12] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 13] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 14] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 15] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 16] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 17] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 18] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 19] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 20] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 21] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 22] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 23] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 24] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to a modified example of the first embodiment. [Figure 25] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to a modified example of the first embodiment. [Figure 26] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to a modified example of the first embodiment. [Figure 27]5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to a modified example of the first embodiment. [Figure 28] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to a modified example of the first embodiment. [Figure 29] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to a modified example of the first embodiment. [Figure 30] FIG. 10 is an equivalent circuit diagram of a memory cell array of a semiconductor memory device according to a second embodiment. [Figure 31] FIG. 10 is a schematic cross-sectional view of a semiconductor memory device according to a second embodiment. [Figure 32] FIG. 10 is a schematic cross-sectional view of a semiconductor memory device according to a second embodiment. [Figure 33] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 34] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 35] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 36] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 37] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 38] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 39] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 40] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 41] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 42] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 43] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 44] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 45]5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 46] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 47] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 48] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 49] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 50] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 51] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the third embodiment. [Figure 52] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the third embodiment. [Figure 53] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the third embodiment. [Figure 54] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the third embodiment. [Figure 55] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the third embodiment. [Figure 56] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same or similar components will be denoted by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0008] Furthermore, in this specification, the terms "upper" and "lower" may be used for convenience. "Upper" and "lower" are terms that indicate relative positions within the drawings, and are not terms that define the positional relationship with respect to gravity.

[0009] Qualitative and quantitative analysis of the chemical composition of the components constituting the semiconductor memory device in this specification can be performed by, for example, secondary ion mass spectroscopy (SIMS), energy dispersive X-ray spectroscopy (EDX), electron energy loss spectroscopy (EELS), etc. Furthermore, for example, a transmission electron microscope (TEM) can be used to measure the thickness of the components constituting the semiconductor memory device, the distance between the components, etc. Furthermore, a TEM can be used to evaluate the crystallinity and crystal defect density of the components constituting the semiconductor memory device.

[0010] (First embodiment) A method for manufacturing a semiconductor memory device according to a first embodiment includes forming a first film of a first material in a first direction of a single crystal silicon substrate, forming a second film of a second material different from the first material in the first direction of the first film, forming a third film of a third material different from the second material in the first direction of the second film, forming a first opening that penetrates the third film, the second film, and the first film and reaches the single crystal silicon substrate, forming a first single crystal silicon layer in contact with the single crystal silicon substrate in the first opening, and forming a second single crystal silicon layer in contact with the single crystal silicon substrate. a second opening penetrating the second film, etching the second film from the side of the second opening to form a first recess portion reaching the first single crystal silicon layer, forming a second single crystal silicon layer in the first recess portion and in contact with the first single crystal silicon layer, forming a wiring layer in contact with a first portion of the second single crystal silicon layer, forming a capacitor in contact with the second portion of the second single crystal silicon layer, and forming a gate electrode layer facing a third portion of the second single crystal silicon layer between the first portion and the second portion.

[0011] A semiconductor memory device according to a first embodiment includes a single-crystal silicon substrate, a single-crystal silicon layer extending along a surface of the single-crystal silicon substrate and spaced apart from the single-crystal silicon substrate, a wiring layer electrically connected to a first portion of the single-crystal silicon layer, a capacitor electrically connected to a second portion of the single-crystal silicon layer, and a gate electrode layer facing a third portion of the single-crystal silicon layer between the first and second portions. The first portion has a higher crystal defect density than the third portion.

[0012] The semiconductor memory device of the first embodiment is a DRAM. The DRAM of the first embodiment has a three-dimensional structure in which memory cells are arranged three-dimensionally. The DRAM of the first embodiment is a DRAM in which word lines are provided in a direction perpendicular to a substrate.

[0013] FIG. 1 is an equivalent circuit diagram of a memory cell array of a semiconductor memory device according to a first embodiment. The DRAM of the first embodiment includes a memory cell array 101. FIG. 1 schematically shows the wiring structure within the memory cell array 101. The memory cell array 101 of the first embodiment has a three-dimensional structure in which a plurality of memory cells MC are arranged three-dimensionally. Although FIG. 1 illustrates an example in which there are 12 memory cells MC, the number of memory cells included in the memory cell array 101 is not limited to 12.

[0014] Hereinafter, the z direction shown in FIG. 1 is an example of a first direction. The x direction is an example of a second direction. The y direction is an example of a third direction. The y direction intersects with the x direction. The z direction intersects with the x and y directions. For example, the x and y directions are perpendicular to each other. For example, the z direction is perpendicular to the x and y directions.

[0015] The memory cell array 101 includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL. Each memory cell MC includes a transistor TR and a capacitor CA.

[0016] The word lines WL extend in the z direction, and the bit lines extend in the y direction.

[0017] The word line WL is electrically connected to the gate electrode of the transistor TR. The bit line BL is electrically connected to one of the source and drain electrodes of the transistor TR. The other of the source and drain electrodes of the transistor TR is electrically connected to one of the electrodes of the capacitor CA.

[0018] The memory cell MC stores data by storing charge in a capacitor CA. Data is written and read by turning on a transistor TR.

[0019] One memory cell MC can be selected by selecting one bit line BL and one word line WL. For example, by applying a desired voltage to the bit line BL and a voltage to the word line WL, the transistor TR is turned on and data is written to the memory cell MC. Also, for example, by turning on the transistor TR, a voltage change on the bit line BL corresponding to the amount of charge stored in the capacitor CA is detected and data from the memory cell MC is read.

[0020] 2 and 3 are schematic cross-sectional views of the semiconductor memory device of the first embodiment, each of which includes two memory cells MC.

[0021] Fig. 2 is an xz cross section, Fig. 3 is an xy cross section, and Fig. 3 is an AA' cross section of Fig. 2.

[0022] The memory cell array 101 of the DRAM of the first embodiment includes a single crystal silicon substrate 10, a single crystal silicon layer 12, a gate electrode layer 14, a gate insulating film 16, a wiring layer 18, a storage node electrode 20, a capacitor insulating film 22, a plate electrode 24, a contact electrode 26, a first interlayer insulating layer 28, a second interlayer insulating layer 30, and a third interlayer insulating layer 32.

[0023] The single crystal silicon layer 12 includes a first n-type impurity region 12a, a second n-type impurity region 12b, and a p-type impurity region 12c.

[0024] The single-crystal silicon layer 12, the gate electrode layer 14, and the gate insulating film 16 constitute a transistor TR. The storage node electrode 20, the capacitor insulating film 22, and the plate electrode 24 constitute a capacitor CA.

[0025] The single crystal silicon substrate 10 is single crystal silicon. The single crystal silicon substrate 10 contains, for example, p-type impurities. The single crystal silicon substrate 10 is, for example, a p-type substrate. The normal direction to the surface of the single crystal silicon substrate 10 is the z direction. The normal direction to the surface of the single crystal silicon substrate 10 is the first direction.

[0026] The single crystal silicon layer 12 is single crystal silicon. The single crystal silicon layer 12 extends in a direction along the surface of the single crystal silicon substrate 10. The single crystal silicon layer 12 extends, for example, in a second direction. The single crystal silicon layer 12 is separated from the single crystal silicon substrate 10 in the first direction.

[0027] The single-crystal silicon layer 12 includes a first n-type impurity region 12 a, a second n-type impurity region 12 b, and a p-type impurity region 12 c. The p-type impurity region 12 c is provided between the first n-type impurity region 12 a and the second n-type impurity region 12 b.

[0028] The first n-type impurity region 12a contains n-type impurities. The first n-type impurity region 12a is n-type silicon. The second n-type impurity region 12b contains n-type impurities. The second n-type impurity region 12b is n-type silicon. The p-type impurity region 12c contains p-type impurities. The p-type impurity region 12c is p-type silicon.

[0029] The single crystal silicon layer 12 has a first portion P1, a second portion P2, and a third portion P3. The third portion P3 is provided between the first portion P1 and the second portion P2. The first portion P1, the second portion P2, and the third portion P3 are, for example, regions surrounded by dotted lines in FIGS. 1 and 2.

[0030] The first portion P1 includes, for example, a first n-type impurity region 12a, the second portion P2 includes, for example, a second n-type impurity region 12b, and the third portion P3 includes, for example, a p-type impurity region 12c.

[0031] The crystal defect density of the first portion P1 is higher than the crystal defect density of the third portion P3, and is, for example, 10 to 1000 times the crystal defect density of the third portion P3.

[0032] The crystal defect density of the first n-type impurity region 12a is higher than the crystal defect density of the p-type impurity region 12c and is, for example, 10 to 1000 times the crystal defect density of the p-type impurity region 12c.

[0033] The gate electrode layer 14 extends in a normal direction to the surface of the single crystal silicon substrate 10. The gate electrode layer 14 extends in a first direction. The gate electrode layer 14 corresponds to the word line WL.

[0034] The gate electrode layers 14 are provided in the third direction on both sides of the single crystal silicon layer 12. For example, the single crystal silicon layer 12 is provided between two gate electrode layers 14 having the same potential.

[0035] The gate electrode layer 14 faces the single crystal silicon layer 12. The gate electrode layer 14 faces the third portion P3 of the single crystal silicon layer 12. The gate electrode layer 14 faces the p-type impurity region 12c of the single crystal silicon layer 12.

[0036] The gate electrode layer 14 is a conductor, and is, for example, polycrystalline silicon containing conductive impurities.

[0037] The gate insulating film 16 is provided between the gate electrode layer 14 and the single-crystal silicon layer 12. The gate insulating film 16 is provided between the gate electrode layer 14 and the third portion P3 of the single-crystal silicon layer 12. The gate insulating film 16 is provided between the gate electrode layer 14 and the p-type impurity region 12c of the single-crystal silicon layer 12.

[0038] The gate insulating film 16 is an insulator, such as silicon oxide.

[0039] The wiring layer 18 extends in a direction along the surface of the single crystal silicon substrate 10. The wiring layer 18 extends, for example, in a third direction. The wiring layer 18 corresponds to the bit line BL.

[0040] The wiring layer 18 is electrically connected to the first portion P1 of the single crystal silicon layer 12. The wiring layer 18 is electrically connected to the first n-type impurity region 12a of the single crystal silicon layer 12. The wiring layer 18 is in contact with the first portion P1 of the single crystal silicon layer 12. The wiring layer 18 is in contact with the first n-type impurity region 12a of the single crystal silicon layer 12.

[0041] The wiring layer 18 is a conductor. The wiring layer 18 is, for example, a metal. The wiring layer 18 includes, for example, tungsten.

[0042] The storage node electrode 20 is electrically connected to the second portion P2 of the single crystal silicon layer 12. The storage node electrode 20 is electrically connected to the second n-type impurity region 12b of the single crystal silicon layer 12. The storage node electrode 20 is in contact with the second portion P2 of the single crystal silicon layer 12. The storage node electrode 20 is in contact with the second n-type impurity region 12b of the single crystal silicon layer 12.

[0043] The storage node electrode 20 is a conductor, such as a metal, such as titanium nitride.

[0044] The capacitor insulating film 22 is provided between the storage node electrode 20 and the plate electrode 24. The capacitor insulating film 22 contacts the storage node electrode 20 and the plate electrode 24.

[0045] The capacitor insulating film 22 is an insulator. The capacitor insulating film 22 includes, for example, an insulator having a higher dielectric constant than silicon dioxide. The capacitor insulating film 22 includes, for example, a so-called high-k insulator.

[0046] The capacitor insulating film 22 includes, for example, zirconium oxide or aluminum oxide, or a combination of zirconium oxide and aluminum oxide.

[0047] The plate electrode 24 is a conductor, such as a metal, such as titanium nitride.

[0048] The contact electrode 26 extends in a normal direction to the surface of the single crystal silicon substrate 10. The contact electrode 26 extends in a first direction. The contact electrode 26 is in contact with the single crystal silicon substrate 10, for example.

[0049] The contact electrode 26 is electrically connected to the first portion P1 of the single crystal silicon layer 12. The contact electrode 26 is in contact with the first portion P1 of the single crystal silicon layer 12. The first portion P1 of the single crystal silicon layer 12 includes a p-type impurity region 12c. The contact electrode 26 is electrically connected to the p-type impurity region 12c of the single crystal silicon layer 12. The contact electrode 26 is in contact with the p-type impurity region 12c of the single crystal silicon layer 12.

[0050] The contact electrode 26 has a function of fixing the potential of the p-type impurity region 12 c of the single-crystal silicon layer 12 .

[0051] The contact electrode 26 is a conductor. The contact electrode 26 is, for example, a semiconductor or a metal. If the contact electrode 26 is a semiconductor, the contact electrode 26 is, for example, heavily doped polycrystalline silicon. If the contact electrode 26 is a metal, the contact electrode 26 includes, for example, tungsten, titanium, tantalum, or titanium nitride.

[0052] The first interlayer insulating layer 28, the second interlayer insulating layer 30, and the third interlayer insulating layer 32 are insulators. The first interlayer insulating layer 28, the second interlayer insulating layer 30, and the third interlayer insulating layer 32 are, for example, silicon oxide, silicon nitride, or silicon oxide. The first interlayer insulating layer 28, the second interlayer insulating layer 30, and the third interlayer insulating layer 32 may include, for example, a semiconductor.

[0053] Next, an example of a method for manufacturing the semiconductor memory device of the first embodiment will be described.

[0054] An example of a method for manufacturing the semiconductor memory device of the first embodiment includes forming a first film of a first material in a first direction of a single crystal silicon substrate, forming a second film of a second material different from the first material in the first direction of the first film, forming a third film of a third material different from the second material in the first direction of the second film, forming a first opening that penetrates the third film, the second film, and the first film and reaches the single crystal silicon substrate, forming a first single crystal silicon layer in contact with the single crystal silicon substrate in the first opening, and forming a third opening. a second opening penetrating the first film and the second film is formed; the second film is etched from the side of the second opening to form a first recess reaching the first single crystal silicon layer; a second single crystal silicon layer in contact with the first single crystal silicon layer is formed in the first recess; a wiring layer in contact with a first portion of the second single crystal silicon layer is formed; a capacitor in contact with a second portion of the second single crystal silicon layer is formed; and a gate electrode layer facing a third portion of the second single crystal silicon layer between the first and second portions is formed.

[0055] In addition, in one example of a method for manufacturing the semiconductor memory device of the first embodiment, the second material is amorphous silicon or polycrystalline silicon, and after forming the first opening and before forming the first single-crystal silicon layer, an oxide film is formed on the surface of the second film exposed on the side surface of the first opening to form the first recess portion, and after etching the second film, the oxide film is removed.

[0056] In addition, in one example of the method for manufacturing the semiconductor memory device of the first embodiment, a fourth film made of a fourth material different from the second material and the third material is formed between the second film and the third film, and after forming the second single-crystal silicon layer, the first single-crystal silicon layer in the first opening is removed, and after removing the first single-crystal silicon layer, the fourth film is etched from the side of the first opening to form a second recessed portion. A wiring layer is formed in the second recessed portion.

[0057] Below, we will explain an example where the first material is silicon oxide, the second material is amorphous silicon, the third material is silicon oxide, and the fourth material is silicon nitride. In this case, the first material and the third material are the same material.

[0058] 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, and 23 are schematic cross-sectional views showing a manufacturing method of the semiconductor memory device of the first embodiment.

[0059] Figures 4 to 23 are cross sections corresponding to Figure 2. Figures 4 to 23 are xz cross sections.

[0060] First, a first silicon oxide film 41a, a first amorphous silicon film 42a, a first silicon nitride film 43a, a second silicon oxide film 41b, a second amorphous silicon film 42b, a second silicon nitride film 43b, and a third silicon oxide film 41c are formed in this order in a first direction on a single crystal silicon substrate 10 (FIG. 4).

[0061] A first silicon oxide film 41a is formed on the surface of the single crystal silicon substrate 10. A first amorphous silicon film 42a is formed on the first silicon oxide film 41a. A first silicon nitride film 43a is formed on the first amorphous silicon film 42a. A second silicon oxide film 41b is formed on the first silicon nitride film 43a. A second amorphous silicon film 42b is formed on the second silicon oxide film 41b. A second silicon nitride film 43b is formed on the second amorphous silicon film 42b. A third silicon oxide film 41c is formed on the second silicon nitride film 43b.

[0062] The first silicon oxide film 41a, the first amorphous silicon film 42a, the first silicon nitride film 43a, the second silicon oxide film 41b, the second amorphous silicon film 42b, the second silicon nitride film 43b, and the third silicon oxide film 41c are formed by, for example, a chemical vapor deposition method (CVD method).

[0063] The first silicon oxide film 41a is an example of a first film. The first amorphous silicon film 42a is an example of a second film. The second silicon oxide film 41b is an example of a third film. The first silicon nitride film 43a is an example of a fourth film.

[0064] The first silicon oxide film 41a, the second silicon oxide film 41b, and a part of the third silicon oxide film 41c will eventually become the first interlayer insulating layer 28. Furthermore, the first silicon nitride film 43a and a part of the second silicon nitride film 43b will finally become the second interlayer insulating layer 30.

[0065] Next, a first opening 44 is formed which penetrates the third silicon oxide film 41c, the second silicon nitride film 43b, the second amorphous silicon film 42b, the second silicon oxide film 41b, the first silicon nitride film 43a, the first amorphous silicon film 42a, and the first silicon oxide film 41a and reaches the single crystal silicon substrate 10 (FIG. 5).

[0066] The first opening 44 is formed by, for example, lithography and reactive ion etching (RIE).

[0067] Next, a first oxide film 45a is formed on the surface of the single-crystal silicon substrate 10 exposed at the bottom of the first opening 44. Also, a second oxide film 45b is formed on the surface of the first amorphous silicon film 42a exposed at the side of the first opening 44 and on the surface of the second amorphous silicon film 42b exposed at the side of the first opening 44 (FIG. 6). The second oxide film 45b is an example of an oxide film.

[0068] The first oxide film 45a and the second oxide film 45b are formed by, for example, thermal oxidation. The first oxide film 45a at the bottom of the opening and the second oxide film 45b formed on the amorphous silicon side are formed simultaneously, but the second oxide film 45b formed on the amorphous silicon side is formed relatively thicker.

[0069] Next, the first oxide film 45a at the bottom of the first opening 44 is removed (FIG. 7). The first oxide film 45a is removed by, for example, dry etching or wet etching, while the second oxide film 45b is left.

[0070] Next, a first single crystal silicon layer 46 is formed in the first opening 44 in contact with the single crystal silicon substrate 10 (FIG. 8). The first single crystal silicon layer 46 is formed using the single crystal silicon substrate 10 as a seed crystal. The first single crystal silicon layer 46 is, for example, undoped single crystal silicon that does not contain conductive impurities.

[0071] The first single-crystal silicon layer 46 is formed by, for example, solid phase epitaxial growth. When using solid phase epitaxial growth, for example, the first opening 44 is filled with an amorphous silicon layer. Then, heat treatment is performed to form single-crystal silicon grown from the substrate.

[0072] Alternatively, the first monocrystalline silicon layer 46 may be formed using, for example, vapor phase epitaxial growth.

[0073] Alternatively, the first single-crystal silicon layer 46 may be formed by, for example, a vapor-liquid-solid (VLS) method. When the VLS method is used, a metal or metal compound is formed as a catalyst, and single-crystal silicon is grown by vapor-phase epitaxial growth using the catalyst as a nucleus. The catalyst may be, for example, gold (Au), indium (In), tin (Sb), or indium tin oxide. The catalyst is grown on the bottom of the first opening 44 in FIG. 7 and is formed by, for example, an atomic layer deposition (ALD) method, a CVD method, or a sputtering method. The VLS method allows for rapid seed crystal growth.

[0074] Next, a second opening 47 is formed through the third silicon oxide film 41c, the second silicon nitride film 43b, the second amorphous silicon film 42b, the second silicon oxide film 41b, the first silicon nitride film 43a, and the first amorphous silicon film 42a (FIG. 9). The surface of the single-crystal silicon substrate 10 is not exposed at the bottom of the second opening 47.

[0075] The second opening 47 is formed by, for example, lithography and RIE.

[0076] Next, the first amorphous silicon film 42a and the second amorphous silicon film 42b are selectively etched from the side surface of the second opening 47 to form a first recess 48 (FIG. 10). The second oxide film 45b is exposed at the back of the first recess 48. The first amorphous silicon film 42a and the second amorphous silicon film 42b are etched using, for example, a dry etching method or a wet etching method.

[0077] Next, the second oxide film 45b is removed (FIG. 11). The second oxide film 45b is removed by, for example, wet etching. The first single-crystal silicon layer 46 is exposed at the back of the first recess 48.

[0078] Next, a second single crystal silicon layer 49 is formed in the first recess 48 in contact with the first single crystal silicon layer 46 (FIG. 12). The second single crystal silicon layer 49 is formed using the first single crystal silicon layer 46 as a seed crystal. The second single crystal silicon layer 49 is, for example, p-type single crystal silicon containing p-type impurities. A portion of the second single crystal silicon layer 49 will eventually become the single crystal silicon layer 12 shown in FIGS. 2 and 3.

[0079] The second single crystal silicon layer 49 is formed by, for example, vapor phase epitaxial growth.

[0080] The second single-crystal silicon layer 49 is formed using, for example, a VLS method. When using the VLS method, a metal or metal compound is formed as a catalyst, and single-crystal silicon is formed using the catalyst as a nucleus. The catalyst is, for example, gold (Au), indium (In), tin (Sb), or indium tin oxide. Here, since the catalyst needs to be formed on the exposed surface of the first single-crystal silicon layer 46 on the inner sidewall of the first recess portion 48, the catalyst is selectively attached to the exposed surface side of the seed crystal silicon using, for example, an ALD method or a CVD method.

[0081] Next, the second opening 47 is filled with a silicon oxide film 50 (FIG. 13).

[0082] Next, the first single crystal silicon layer 46 in the first opening 44 is removed (FIG. 14). The first single crystal silicon layer 46 is removed by, for example, dry etching or wet etching.

[0083] Next, a part of the first silicon nitride film 43a and a part of the second silicon nitride film 43b are etched from the side surface of the first opening 44 to form a second recess portion 51 (FIG. 15). The first silicon nitride film 43a and the second silicon nitride film 43b are removed by, for example, wet etching.

[0084] Next, a first n-type impurity region 12a is formed in the second single-crystal silicon layer 49 (FIG. 16). The first n-type impurity region 12a is formed by using, for example, a vapor phase diffusion method.

[0085] When forming the first n-type impurity region 12a, for example, a mask material (not shown) is used to cover the corners of the second single crystal silicon layer 49 and the surface of the single crystal silicon substrate 10 at the bottom of the first opening 44.

[0086] The n-type impurities introduced into the first n-type impurity region 12a are activated by, for example, performing a heat treatment at a high temperature for a short time.

[0087] Next, the wiring layer 18 is formed in the second recess portion 51 (FIG. 17). The wiring layer 18 contacts the first portion P1 of the second single-crystal silicon layer 49. The wiring layer 18 contacts the first n-type impurity region 12a. The wiring layer 18 is formed in the second recess portion 51 by, for example, using a CVD method and a dry etching method.

[0088] Next, the second recessed portion 51 is filled with a silicon oxide film 52 (FIG. 18). The filling of the second recessed portion 51 with the silicon oxide film 52 is performed by using, for example, a CVD method and a dry etching method.

[0089] Next, the contact electrode 26 is formed in the first opening 44 (FIG. 19). The contact electrode 26 is formed by, for example, the CVD method.

[0090] Thereafter, grooves are formed by a method not shown in the drawings to divide the second single-crystal silicon layer 49 in the y direction. The formed grooves are used to form the gate insulating film 16 and the gate electrode layer 14 extending in the first direction. The gate electrode layer 14 is formed so as to face the third portion P3 of the second single-crystal silicon layer 49.

[0091] Next, the silicon oxide film 50 in the second opening 47 is removed (FIG. 20). The silicon oxide film 50 is removed by, for example, wet etching.

[0092] Next, the second single crystal silicon layer 49 is selectively etched from the side surface of the second opening 47 to form a third recess 53 (FIG. 21). The second single crystal silicon layer 49 is etched using, for example, a dry etching method or a wet etching method.

[0093] Next, the second n-type impurity region 12b is formed in the second portion P2 of the second single-crystal silicon layer 49 (FIG. 22). The second n-type impurity region 12b is formed by using, for example, a vapor phase diffusion method.

[0094] Next, a storage node electrode 20, a capacitor insulating film 22, and a plate electrode 24 are formed in the third recess portion 53 (FIG. 23). The storage node electrode 20 contacts the second portion P2 of the second single-crystal silicon layer 49. A capacitor CA formed by the storage node electrode 20, the capacitor insulating film 22, and the plate electrode 24 contacts the second portion P2 of the second single-crystal silicon layer 49. The storage node electrode 20, the capacitor insulating film 22, and the plate electrode 24 are formed by using, for example, a CVD method.

[0095] By the above manufacturing method, the memory cell array 101 of the DRAM of the first embodiment is formed.

[0096] Next, the operation and effects of the semiconductor memory device of the first embodiment will be described.

[0097] In the DRAM of the first embodiment, the memory cells MC are arranged three-dimensionally, which allows for a high degree of integration.

[0098] Furthermore, in the DRAM of the first embodiment, the crystal defect density of the first portion P1 of the single crystal silicon layer 12 is higher than the crystal defect density of the third portion P3. When the single crystal silicon layer 12 is manufactured using an epitaxial growth method, defects from the initial stage of growth of the single crystal silicon remain in the portion close to the first single crystal silicon layer 46 serving as the seed crystal, resulting in a high crystal defect density. The first portion P1 is closer to the first single crystal silicon layer 46 serving as the seed crystal than the third portion P3, and therefore has a high crystal defect density.

[0099] The first portion P1, which has a high density of crystal defects, functions as, for example, a gettering site for metal contamination in the single-crystal silicon layer 12. This reduces junction leakage and improves charge retention characteristics of the DRAM of the first embodiment. The first portion P1 is located on the opposite side of the storage node electrode 20, where charge is retained, from the second portion P2. Therefore, even if there is an increase in junction leakage due to the crystal defects in the first portion P1 itself, it does not affect the charge retention characteristics of the DRAM.

[0100] For example, if a VLS method using a metal or metal compound as a catalyst is used to form the first single crystal silicon layer 46 or the second single crystal silicon layer 49, there is a risk of increasing metal contamination in the single crystal silicon layer 12. Therefore, particularly when the single crystal silicon layer 12 is manufactured using the VLS method, the effect of improving the charge retention characteristics by providing the first portion P1 becomes significant.

[0101] From the viewpoint of improving the charge retention characteristics, the crystal defect density of the first portion P1 is preferably 10 times or more the crystal defect density of the third portion P3.

[0102] Furthermore, in the first portion P1 having a high density of crystal defects, diffusion of impurities in the single crystal silicon is promoted, which makes it possible to shorten the heat treatment time or reduce the heat treatment temperature when forming the first n-type impurity region 12a, for example.

[0103] In the DRAM manufacturing method of the first embodiment, a first single-crystal silicon layer 46 is used as a seed crystal to simultaneously form a plurality of single-crystal silicon layers 12 stacked in a first direction. This improves the uniformity of the plurality of single-crystal silicon layers 12 stacked in the first direction. Furthermore, the manufacturing time for forming the single-crystal silicon layers 12 is shortened.

[0104] Furthermore, in the method for manufacturing a DRAM according to the first embodiment, the first single crystal silicon layer 46 and the second single crystal silicon layer 49 are formed in different steps. Compared to when the first single crystal silicon layer 46 and the second single crystal silicon layer 49 are formed in the same step, the uniformity of growth in the second direction of the multiple second single crystal silicon layers 49 stacked in the first direction is improved.

[0105] Therefore, according to the DRAM manufacturing method of the first embodiment, it is possible to manufacture a DRAM having a three-dimensional structure with stable characteristics in a short manufacturing time.

[0106] From the viewpoint of shortening the manufacturing time, it is preferable to form the first single crystal silicon layer 46 or the second single crystal silicon layer 49 by the VLS method, which has a high growth rate of single crystal silicon.

[0107] The method for forming the first single crystal silicon layer 46 and the method for forming the second single crystal silicon layer 49 may be the same process method or different process methods.

[0108] (Variation) The method for manufacturing a semiconductor memory device according to the modified example of the first embodiment differs from the method for manufacturing a semiconductor memory device according to the first embodiment in that the second material is silicon nitride and the fourth material is amorphous silicon.

[0109] 24, 25, 26, 27, 28, and 29 are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to a modification of the first embodiment.

[0110] Figures 24 to 29 are cross sections corresponding to Figure 2. Figures 24 to 29 are xz cross sections.

[0111] First, a first silicon oxide film 61a, a first silicon nitride film 62a, a first amorphous silicon film 63a, a second silicon oxide film 61b, a second silicon nitride film 62b, a second amorphous silicon film 63b, and a third silicon oxide film 61c are formed in this order in a first direction on the single crystal silicon substrate 10 (FIG. 24).

[0112] A first silicon oxide film 61a is formed on the surface of the single crystal silicon substrate 10. A first silicon nitride film 62a is formed on the first silicon oxide film 61a. A first amorphous silicon film 63a is formed on the first silicon nitride film 62a. A second silicon oxide film 61b is formed on the first amorphous silicon film 63a. A second silicon nitride film 62b is formed on the second silicon oxide film 61b. A second amorphous silicon film 63b is formed on the second silicon nitride film 62b. A third silicon oxide film 61c is formed on the second amorphous silicon film 63b.

[0113] The first silicon oxide film 61a, the first silicon nitride film 62a, the first amorphous silicon film 63a, the second silicon oxide film 61b, the second silicon nitride film 62b, the second amorphous silicon film 63b, and the third silicon oxide film 61c are formed by, for example, a CVD method.

[0114] The first silicon oxide film 61a is an example of a first film. The first silicon nitride film 62a is an example of a second film. The second silicon oxide film 61b is an example of a third film. The first amorphous silicon film 63a is an example of a fourth film.

[0115] The first silicon oxide film 61a, the second silicon oxide film 61b, and a portion of the third silicon oxide film 61c will eventually become the first interlayer insulating layer 28. Furthermore, the first amorphous silicon film 63a and a portion of the second amorphous silicon film 63b will finally become the second interlayer insulating layer 30. The first amorphous silicon film 63a and a portion of the second amorphous silicon film 63b will finally become the second interlayer insulating layer 30, for example, in a state where at least a portion of them is nitrided.

[0116] Next, a first opening 44 is formed that penetrates the third silicon oxide film 61c, the second amorphous silicon film 63b, the second silicon nitride film 62b, the second silicon oxide film 61b, the first amorphous silicon film 63a, the first silicon nitride film 62a, and the first silicon oxide film 61a and reaches the single crystal silicon substrate 10 (Figure 25).

[0117] The first opening 44 is formed by, for example, lithography and reactive ion etching (RIE).

[0118] Next, a first single crystal silicon layer 46 is formed in the first opening 44 in contact with the single crystal silicon substrate 10 (FIG. 26). The first single crystal silicon layer 46 is formed using the single crystal silicon substrate 10 as a seed crystal. The first single crystal silicon layer 46 is, for example, undoped single crystal silicon that does not contain conductive impurities.

[0119] The first single crystal silicon layer 46 is formed by, for example, vapor phase epitaxial growth.

[0120] The first single-crystal silicon layer 46 is formed by, for example, a VLS method. When using the VLS method, single-crystal silicon is formed using a metal or a metal compound as a catalyst. The catalyst is, for example, gold (Au), indium (In), tin (Sb), or indium tin oxide. The catalyst is formed by, for example, an ALD method, a CVD method, or a sputtering method.

[0121] The first single-crystal silicon layer 46 is formed by, for example, solid phase epitaxial growth. When using solid phase epitaxial growth, for example, an amorphous silicon layer is filled into the first opening 44. Then, a heat treatment is performed to form single-crystal silicon.

[0122] Next, a second opening 47 is formed through the third silicon oxide film 61c, the second amorphous silicon film 63b, the second silicon nitride film 62b, the second silicon oxide film 61b, the first amorphous silicon film 63a, and the first silicon nitride film 62a (FIG. 27). The surface of the single-crystal silicon substrate 10 is not exposed at the bottom of the second opening 47.

[0123] The second opening 47 is formed by, for example, lithography and RIE.

[0124] Next, the first silicon nitride film 62a and the second silicon nitride film 62b are selectively etched from the side surface of the second opening 47 to form the first recess 48 (FIG. 28). The first single-crystal silicon layer 46 is exposed at the back of the first recess 48. The first silicon nitride film 62a and the second silicon nitride film 62b are etched using, for example, a dry etching method or a wet etching method.

[0125] Next, a second single crystal silicon layer 49 is formed in the first recess 48 in contact with the first single crystal silicon layer 46 (FIG. 29). The second single crystal silicon layer 49 is formed using the first single crystal silicon layer 46 as a seed crystal. The second single crystal silicon layer 49 is, for example, p-type single crystal silicon containing p-type impurities. A portion of the second single crystal silicon layer 49 will eventually become the single crystal silicon layer 12.

[0126] The second single crystal silicon layer 49 is formed by, for example, vapor phase epitaxial growth.

[0127] The second single crystal silicon layer 49 is formed by, for example, a VLS method. When using the VLS method, single crystal silicon is formed using a metal or a metal compound as a catalyst. The catalyst is, for example, gold (Au), indium (In), tin (Sb), or indium tin oxide. The catalyst is formed by, for example, an ALD method, a CVD method, or a sputtering method.

[0128] Thereafter, a wiring layer 18 is formed in contact with the first portion P1 of the second single crystal silicon layer 49 using the same manufacturing method as in the first embodiment. Also, a gate electrode layer 14 is formed so as to face the third portion P3 of the second single crystal silicon layer 49 using the same manufacturing method as in the first embodiment. Also, a capacitor CA is formed in contact with the second portion P2 of the second single crystal silicon layer 49 using the same manufacturing method as in the first embodiment.

[0129] By the manufacturing method of the above modification, the memory cell array 101 of the DRAM of the first embodiment is formed.

[0130] As described above, according to the first embodiment and the modified example, it is possible to achieve a high degree of integration of the semiconductor memory device.

[0131] (Second embodiment) The method for manufacturing a semiconductor memory device according to the second embodiment differs from the method for manufacturing a semiconductor memory device according to the first embodiment in that a fourth film made of a fourth material different from the first and second materials is formed between the first and second films, a fifth film made of a fifth material identical to the fourth material is formed between the second and third films, the first single-crystal silicon layer is formed, and then the first single-crystal silicon layer in the first opening is removed. After the first single-crystal silicon layer is removed, the fourth film and the fifth film are etched from the side of the first opening to form a second recess, and a gate electrode layer is formed in the second recess. Hereinafter, some of the details that overlap with the first embodiment may be omitted.

[0132] The semiconductor memory device of the second embodiment is a DRAM. The DRAM of the second embodiment has a three-dimensional structure in which memory cells are arranged three-dimensionally. The DRAM of the second embodiment is a DRAM in which bit lines are provided in a direction perpendicular to the substrate.

[0133] FIG. 30 is an equivalent circuit diagram of a memory cell array of a semiconductor memory device according to the second embodiment. The DRAM of the second embodiment includes a memory cell array 201. FIG. 30 schematically shows the wiring structure within the memory cell array 201. The memory cell array 201 of the second embodiment has a three-dimensional structure in which a plurality of memory cells MC are arranged three-dimensionally. While FIG. 30 illustrates a case in which there are 12 memory cells MC, the number of memory cells included in the memory cell array is not limited to 12.

[0134] Hereinafter, the z direction shown in FIG. 30 is an example of a first direction. The x direction is an example of a second direction. The y direction is an example of a third direction. The y direction intersects with the x direction. The z direction intersects with the x and y directions. For example, the x and y directions are perpendicular to each other. For example, the z direction is perpendicular to the x and y directions.

[0135] The memory cell array 201 includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL. Each memory cell MC includes a transistor TR and a capacitor CA.

[0136] The bit lines BL extend in the z direction, and the word lines extend in the y direction.

[0137] The word line WL is electrically connected to the gate electrode of the transistor TR. The bit line BL is electrically connected to one of the source and drain electrodes of the transistor TR. The other of the source and drain electrodes of the transistor TR is electrically connected to one of the electrodes of the capacitor CA.

[0138] The memory cell MC stores data by storing charge in a capacitor CA. Data is written and read by turning on a transistor TR.

[0139] One memory cell MC can be selected by selecting one bit line BL and one word line WL. For example, by applying a desired voltage to the bit line BL and a voltage to the word line WL, the transistor TR is turned on and data is written to the memory cell MC. Also, for example, by turning on the transistor TR, a voltage change on the bit line BL corresponding to the amount of charge stored in the capacitor CA is detected and data from the memory cell MC is read.

[0140] 31 and 32 are schematic cross-sectional views of a semiconductor memory device according to the second embodiment, each of which includes two memory cells MC.

[0141] Fig. 31 is an xz cross section, Fig. 32 is an xy cross section, and Fig. 32 is a BB' cross section of Fig. 31.

[0142] The memory cell array 201 of the DRAM of the second embodiment includes a single crystal silicon substrate 10, a single crystal silicon layer 12, a gate electrode layer 14, a gate insulating film 16, a wiring layer 18, a storage node electrode 20, a capacitor insulating film 22, a plate electrode 24, a first interlayer insulating layer 28, a second interlayer insulating layer 30, and a third interlayer insulating layer 32.

[0143] The single crystal silicon substrate 10 includes an n-type impurity region 10a.

[0144] The single crystal silicon layer 12 includes a first n-type impurity region 12a, a second n-type impurity region 12b, and a p-type impurity region 12c.

[0145] The single-crystal silicon layer 12, the gate electrode layer 14, and the gate insulating film 16 constitute a transistor TR. The storage node electrode 20, the capacitor insulating film 22, and the plate electrode 24 constitute a capacitor CA.

[0146] The single crystal silicon substrate 10 is single crystal silicon. The single crystal silicon substrate 10 contains, for example, p-type impurities. The single crystal silicon substrate 10 is, for example, a p-type substrate. The normal direction to the surface of the single crystal silicon substrate 10 is the z direction. The normal direction to the surface of the single crystal silicon substrate 10 is the first direction.

[0147] The single crystal silicon substrate 10 includes an n-type impurity region 10a, which is in contact with the wiring layer 18.

[0148] The single crystal silicon layer 12 is single crystal silicon. The single crystal silicon layer 12 extends in a direction along the surface of the single crystal silicon substrate 10. The single crystal silicon layer 12 extends, for example, in a second direction. The single crystal silicon layer 12 is separated from the single crystal silicon substrate 10 in the first direction.

[0149] The single-crystal silicon layer 12 includes a first n-type impurity region 12 a, a second n-type impurity region 12 b, and a p-type impurity region 12 c. The p-type impurity region 12 c is provided between the first n-type impurity region 12 a and the second n-type impurity region 12 b.

[0150] The first n-type impurity region 12a contains n-type impurities. The first n-type impurity region 12a is n-type silicon. The second n-type impurity region 12b contains n-type impurities. The second n-type impurity region 12b is n-type silicon. The p-type impurity region 12c contains p-type impurities. The p-type impurity region 12c is p-type silicon.

[0151] The single crystal silicon layer 12 has a first portion P1, a second portion P2, and a third portion P3. The third portion P3 is provided between the first portion P1 and the second portion P2. The first portion P1, the second portion P2, and the third portion P3 are respectively surrounded by dotted lines in FIGS. 31 and 32.

[0152] The first portion P1 includes, for example, a first n-type impurity region 12a, the second portion P2 includes, for example, a second n-type impurity region 12b, and the third portion P3 includes, for example, a p-type impurity region 12c.

[0153] The crystal defect density of the first portion P1 is higher than the crystal defect density of the third portion P3, and is, for example, 10 to 1000 times the crystal defect density of the third portion P3.

[0154] The crystal defect density of the first n-type impurity region 12a is higher than the crystal defect density of the p-type impurity region 12c and is 10 to 1000 times the crystal defect density of the p-type impurity region 12c.

[0155] The gate electrode layer 14 extends in a direction along the surface of the single crystal silicon substrate 10. The gate electrode layer 14 extends, for example, in a third direction. The gate electrode layer 14 corresponds to the word line WL.

[0156] The gate electrode layers 14 are provided in the first direction on both sides of the single crystal silicon layer 12. For example, the single crystal silicon layer 12 is provided between two gate electrode layers 14 having the same potential.

[0157] The gate electrode layer 14 faces the single crystal silicon layer 12. The gate electrode layer 14 faces the third portion P3 of the single crystal silicon layer 12. The gate electrode layer 14 faces the p-type impurity region 12c of the single crystal silicon layer 12.

[0158] The gate electrode layer 14 is a conductor, and is, for example, polycrystalline silicon containing conductive impurities.

[0159] The gate insulating film 16 is provided between the gate electrode layer 14 and the single-crystal silicon layer 12. The gate insulating film 16 is provided between the gate electrode layer 14 and the third portion P3 of the single-crystal silicon layer 12. The gate insulating film 16 is provided between the gate electrode layer 14 and the p-type impurity region 12c of the single-crystal silicon layer 12.

[0160] The gate insulating film 16 is an insulator, such as silicon oxide.

[0161] The wiring layer 18 extends in a normal direction to the surface of the single crystal silicon substrate 10. The wiring layer 18 extends in a first direction. The wiring layer 18 corresponds to the bit line BL.

[0162] The wiring layer 18 is electrically connected to the first portion P1 of the single crystal silicon layer 12. The wiring layer 18 is electrically connected to the first n-type impurity region 12a of the single crystal silicon layer 12. The wiring layer 18 is in contact with the first portion P1 of the single crystal silicon layer 12. The wiring layer 18 is in contact with the first n-type impurity region 12a of the single crystal silicon layer 12.

[0163] The wiring layer 18 is in contact with, for example, the single crystal silicon substrate 10. The wiring layer 18 is in contact with, for example, the n-type impurity region 10a of the single crystal silicon substrate 10.

[0164] The wiring layer 18 is a conductor. The wiring layer 18 is, for example, a metal. The wiring layer 18 includes, for example, tungsten.

[0165] The storage node electrode 20 is electrically connected to the second portion P2 of the single crystal silicon layer 12. The storage node electrode 20 is electrically connected to the second n-type impurity region 12b of the single crystal silicon layer 12. The storage node electrode 20 is in contact with the second portion P2 of the single crystal silicon layer 12. The storage node electrode 20 is in contact with the second n-type impurity region 12b of the single crystal silicon layer 12.

[0166] The storage node electrode 20 is a conductor, such as a metal, such as titanium nitride.

[0167] The capacitor insulating film 22 is provided between the storage node electrode 20 and the plate electrode 24. The capacitor insulating film 22 contacts the storage node electrode 20 and the plate electrode 24.

[0168] The capacitor insulating film 22 is an insulator. The capacitor insulating film 22 includes, for example, an insulator having a higher dielectric constant than silicon dioxide. The capacitor insulating film 22 includes, for example, a so-called high-k insulator.

[0169] The capacitor insulating film 22 includes, for example, zirconium oxide or aluminum oxide, or a combination of zirconium oxide and aluminum oxide.

[0170] The plate electrode 24 is a conductor, such as a metal, such as titanium nitride.

[0171] The first interlayer insulating layer 28, the second interlayer insulating layer 30, and the third interlayer insulating layer 32 are insulators. The first interlayer insulating layer 28, the second interlayer insulating layer 30, and the third interlayer insulating layer 32 are, for example, silicon oxide, silicon nitride, or silicon oxide. The first interlayer insulating layer 28, the second interlayer insulating layer 30, and the third interlayer insulating layer 32 may include, for example, a semiconductor.

[0172] Next, an example of a method for manufacturing the semiconductor memory device according to the second embodiment will be described.

[0173] An example of a method for manufacturing the semiconductor memory device of the second embodiment includes forming a first film of a first material in a first direction of a single crystal silicon substrate, forming a second film of a second material different from the first material in the first direction of the first film, forming a third film of a third material different from the second material in the first direction of the second film, forming a first opening that penetrates the third film, the second film, and the first film and reaches the single crystal silicon substrate, forming a first single crystal silicon layer in contact with the single crystal silicon substrate in the first opening, and forming a third film and A second opening is formed through the second film, the second film is etched from the side of the second opening, a first recess portion is formed that reaches the first single-crystal silicon layer, a second single-crystal silicon layer is formed in the first recess portion and in contact with the first single-crystal silicon layer, a wiring layer is formed in contact with a first portion of the second single-crystal silicon layer, a capacitor is formed in contact with the second portion of the second single-crystal silicon layer, and a gate electrode layer is formed that faces a third portion of the second single-crystal silicon layer between the first portion and the second portion.

[0174] In addition, in one example of a method for manufacturing a semiconductor memory device according to the second embodiment, the second material is amorphous silicon or polycrystalline silicon, and after forming the first opening and before forming the first single-crystal silicon layer, an oxide film is formed on the surface of the second film exposed on the side surface of the first opening, and when forming the first recess portion, the second film is etched and then the oxide film is removed.

[0175] In addition, in one example of a method for manufacturing a semiconductor memory device according to the second embodiment, a fourth film made of a fourth material different from the first and second materials is formed between the first and second films, a fifth film made of a fifth material identical to the fourth material is formed between the second and third films, a second single-crystal silicon layer is formed, and then the first single-crystal silicon layer in the first opening is removed. After the first single-crystal silicon layer is removed, the fourth film and the fifth film are etched from the side of the first opening to form a second recess. A gate electrode layer is formed in the second recess.

[0176] In addition, in one example of the method for manufacturing the semiconductor memory device of the second embodiment, when forming the second single-crystal silicon layer, a first n-type impurity region, a p-type impurity region, and a second n-type impurity region are formed in this order from the side closer to the first single-crystal silicon layer, and the gate electrode layer faces the p-type impurity region.

[0177] The following description will be given taking as an example a case where the first material is silicon oxide, the second material is amorphous silicon, the third material is silicon oxide, and the fourth and fifth materials are silicon nitride, where the first and third materials are the same material.

[0178] 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, and 50 are schematic cross-sectional views showing a manufacturing method of the semiconductor memory device of the second embodiment.

[0179] Figures 33 to 50 are cross sections corresponding to Figure 31. Figures 33 to 50 are xz cross sections.

[0180] First, a first silicon oxide film 71a, a first silicon nitride film 72a, a first amorphous silicon film 73a, a second silicon nitride film 72b, a second silicon oxide film 71b, a third silicon nitride film 72c, a second amorphous silicon film 73b, a fourth silicon nitride film 72d, and a third silicon oxide film 71c are formed in this order in a first direction on the single crystal silicon substrate 10 (Figure 33).

[0181] A first silicon oxide film 71a is formed on the surface of the single crystal silicon substrate 10. A first silicon nitride film 72a is formed on the first silicon oxide film 71a. A first amorphous silicon film 73a is formed on the first silicon nitride film 72a. A second silicon nitride film 72b is formed on the first amorphous silicon film 73a. A second silicon oxide film 71b is formed on the second silicon nitride film 72b. A third silicon nitride film 72c is formed on the second silicon oxide film 71b. A second amorphous silicon film 73b is formed on the third silicon nitride film 72c. A fourth silicon nitride film 72d is formed on the second amorphous silicon film 73b. A third silicon oxide film 71c is formed on the fourth silicon nitride film 72d.

[0182] The first silicon oxide film 71a, the first silicon nitride film 72a, the first amorphous silicon film 73a, the second silicon nitride film 72b, the second silicon oxide film 71b, the third silicon nitride film 72c, the second amorphous silicon film 73b, the fourth silicon nitride film 72d, and the third silicon oxide film 71c are formed by, for example, a CVD method.

[0183] The first silicon oxide film 71a is an example of a first film. The first amorphous silicon film 73a is an example of a second film. The second silicon oxide film 71b is an example of a third film. The first silicon nitride film 72a is an example of a fourth film. The second silicon nitride film 72b is an example of a fifth film.

[0184] The first silicon oxide film 71a, the second silicon oxide film 71b, and a portion of the third silicon oxide film 71c will eventually become the first interlayer insulating layer 28. Furthermore, the first silicon nitride film 72a, the second silicon nitride film 72b, the third silicon nitride film 72c, and a portion of the fourth silicon nitride film 72d will finally become the second interlayer insulating layer 30.

[0185] The first amorphous silicon film 73a and the second amorphous silicon film 73b are patterned by a method not shown so as to be divided in the y direction.

[0186] Next, a first opening 44 is formed which penetrates the third silicon oxide film 71c, the fourth silicon nitride film 72d, the second amorphous silicon film 73b, the third silicon nitride film 72c, the second silicon oxide film 71b, the second silicon nitride film 72b, the first amorphous silicon film 73a, the first silicon nitride film 72a, and the first silicon oxide film 71a and reaches the single crystal silicon substrate 10 (FIG. 34).

[0187] The first opening 44 is formed by, for example, lithography and reactive ion etching (RIE).

[0188] Next, a first oxide film 45a is formed on the surface of the single-crystal silicon substrate 10 exposed at the bottom of the first opening 44. Also, a second oxide film 45b is formed on the surface of the first amorphous silicon film 42a exposed at the side of the first opening 44 and on the surface of the second amorphous silicon film 42b exposed at the side of the first opening 44 (FIG. 35). The second oxide film 45b is an example of an oxide film.

[0189] The first oxide film 45a and the second oxide film 45b are formed by, for example, thermal oxidation.

[0190] Next, the first oxide film 45a at the bottom of the first opening 44 is removed (FIG. 36). The first oxide film 45a is removed by, for example, dry etching or wet etching, while the second oxide film 45b is left.

[0191] Next, a first single crystal silicon layer 46 is formed in the first opening 44 in contact with the single crystal silicon substrate 10 (FIG. 37). The first single crystal silicon layer 46 is formed using the single crystal silicon substrate 10 as a seed crystal. The first single crystal silicon layer 46 is, for example, undoped single crystal silicon that does not contain conductive impurities.

[0192] The first single-crystal silicon layer 46 is formed by, for example, solid phase epitaxial growth. When using solid phase epitaxial growth, for example, an amorphous silicon layer is filled into the first opening 44. Then, a heat treatment is performed to form single-crystal silicon.

[0193] Alternatively, the first monocrystalline silicon layer 46 may be formed using, for example, vapor phase epitaxial growth.

[0194] Furthermore, as a method for accelerating vapor phase epitaxial growth, the first single crystal silicon layer 46 is formed using, for example, a vapor-liquid-solid (VLS) method. When using the VLS method, a metal or metal compound is formed as a catalyst, and single crystal silicon is formed around the catalyst as a nucleus. The catalyst is, for example, gold (Au), indium (In), tin (Sb), or indium tin oxide. The catalyst is formed using, for example, an ALD method, a CVD method, or a sputtering method.

[0195] The first single-crystal silicon layer 46 is formed by, for example, solid phase epitaxial growth. When using solid phase epitaxial growth, for example, an amorphous silicon layer is filled into the first opening 44. Then, a heat treatment is performed to form single-crystal silicon.

[0196] Next, a second opening 47 is formed penetrating the third silicon oxide film 71c, the fourth silicon nitride film 72d, the second amorphous silicon film 73b, the third silicon nitride film 72c, the second silicon oxide film 71b, the second silicon nitride film 72b, and the first amorphous silicon film 73a (FIG. 38). The surface of the single-crystal silicon substrate 10 is not exposed at the bottom of the second opening 47.

[0197] The second opening 47 is formed by, for example, lithography and RIE.

[0198] Next, the first amorphous silicon film 73a and the second amorphous silicon film 73b are selectively etched from the side surface of the second opening 47 to form the first recess 48 (FIG. 39). The second oxide film 45b is exposed at the back of the first recess 48. The first amorphous silicon film 73a and the second amorphous silicon film 73b are etched using, for example, a dry etching method or a wet etching method.

[0199] Next, the second oxide film 45b is removed (FIG. 40). The second oxide film 45b is removed by, for example, wet etching. The first single-crystal silicon layer 46 is exposed at the back of the first recess 48.

[0200] Next, a second single crystal silicon layer 49 is formed in the first recess 48 in contact with the first single crystal silicon layer 46 (FIG. 41). The second single crystal silicon layer 49 is formed using the first single crystal silicon layer 46 as a seed crystal.

[0201] When forming the second single crystal silicon layer 49, the first n-type impurity region 12a, the p-type impurity region 12c, and the second n-type impurity region 12b are formed in this order from the side closest to the first single crystal silicon layer 46. For example, the impurity conductivity type is switched by switching the doping gas used when growing the second single crystal silicon layer 49. A part of the second single crystal silicon layer 49 will eventually become the single crystal silicon layer 12.

[0202] It is also possible to switch only the impurity concentration without switching the impurity conductivity type when forming the second single-crystal silicon layer 49. For example, by changing only the p-type impurity concentration in the portion that ultimately faces the gate electrode layer 14, it is possible to adjust the threshold voltage of the transistor TR.

[0203] Furthermore, after forming the second single-crystal silicon layer 49, it is also possible to dope and activate impurities of a conductivity type different from that of the initial single-crystal silicon using a technique such as vapor-phase doping, as in the first embodiment. Also, in the second embodiment, impurity-doped polycrystalline silicon may be brought into contact with the exposed surface to be formed, and the impurities may be diffused by thermal diffusion.

[0204] The second single crystal silicon layer 49 is formed by, for example, vapor phase epitaxial growth.

[0205] The second single-crystal silicon layer 49 may also be formed using, for example, a VLS method. When using the VLS method, a metal or metal compound is formed as a catalyst, and single-crystal silicon is formed using the catalyst as a nucleus. The catalyst is, for example, gold (Au), indium (In), tin (Sb), or indium tin oxide. In this case, since the catalyst needs to be formed on the exposed surface of the first single-crystal silicon layer 46 on the inner sidewall of the first recess portion 48, the catalyst is selectively attached to the exposed surface of the seed crystal silicon using, for example, an ALD method or a CVD method.

[0206] Next, the second opening 47 is filled with a silicon oxide film 50 (FIG. 42).

[0207] Next, the first single crystal silicon layer 46 in the first opening 44 is removed (FIG. 43). The first single crystal silicon layer 46 is removed by, for example, dry etching or wet etching.

[0208] Next, the first silicon nitride film 72a, the second silicon nitride film 72b, the third silicon nitride film 72c, and the fourth silicon nitride film 72d are etched from the side surface of the first opening 44 to form the second recess portion 51 (FIG. 44). The first silicon nitride film 72a, the second silicon nitride film 72b, the third silicon nitride film 72c, and the fourth silicon nitride film 72d are removed by, for example, wet etching.

[0209] Next, a gate insulating film 16 and a gate electrode layer 14 are formed in the second recess portion 51 (FIG. 45). The gate insulating film 16 contacts the third portion P3 of the second single crystal silicon layer 49. The gate insulating film 16 contacts the p-type impurity region 12c of the second single crystal silicon layer 49. The gate electrode layer 14 faces the third portion P3 of the second single crystal silicon layer 49. The gate electrode layer 14 faces the p-type impurity region 12c of the second single crystal silicon layer 49.

[0210] The gate insulating film 16 and the gate electrode layer 14 are formed in the second recess portion 51 by, for example, the CVD method and the dry etching method.

[0211] Next, the second recessed portion 51 is filled with a silicon oxide film 52 (FIG. 46). The filling of the second recessed portion 51 with the silicon oxide film 52 is performed by using, for example, a CVD method and a dry etching method.

[0212] Next, an n-type impurity region 10a is formed in the single-crystal silicon substrate 10 at the bottom of the first opening 44. The n-type impurity region 10a is formed, for example, by ion implantation. As in the first embodiment, this impurity region can be doped and activated with impurities of a different conductivity type from that of the initial single-crystal silicon using a technique such as gas-phase doping. Alternatively, polycrystalline silicon doped with conductive impurities can be brought into contact with the exposed surface to be formed, diffused by thermal diffusion, and then the polycrystalline silicon can be peeled off.

[0213] The n-type impurities introduced into the single crystal silicon substrate 10 are activated by, for example, performing a heat treatment at a high temperature for a short time.

[0214] Next, the wiring layer 18 is formed in the first opening 44 (FIG. 47). The wiring layer 18 is formed by, for example, the CVD method.

[0215] Next, the silicon oxide film 50 in the second opening 47 is removed (FIG. 48). The silicon oxide film 50 is removed by, for example, wet etching.

[0216] Next, the second single crystal silicon layer 49 is selectively etched from the side surface of the second opening 47 to form a third recess 53 (FIG. 49). The second single crystal silicon layer 49 is etched using, for example, a dry etching method or a wet etching method.

[0217] Next, a storage node electrode 20, a capacitor insulating film 22, and a plate electrode 24 are formed in the third recess portion 53 (FIG. 50). The storage node electrode 20 contacts the second portion P2 of the second single-crystal silicon layer 49. A capacitor CA formed by the storage node electrode 20, the capacitor insulating film 22, and the plate electrode 24 contacts the second portion P2 of the second single-crystal silicon layer 49. The storage node electrode 20, the capacitor insulating film 22, and the plate electrode 24 are formed by using, for example, a CVD method.

[0218] By the above manufacturing method, the memory cell array 201 of the DRAM of the second embodiment is formed.

[0219] In the DRAM of the second embodiment, the memory cells MC are arranged three-dimensionally, which allows for a high degree of integration.

[0220] Furthermore, in the DRAM of the second embodiment, the crystal defect density of the first portion P1 of the single-crystal silicon layer 12 is higher than the crystal defect density of the third portion P3. Therefore, similar to the DRAM of the first embodiment, for example, the charge retention characteristics are improved.

[0221] Furthermore, according to the DRAM manufacturing method of the second embodiment, similar to the DRAM manufacturing method of the first embodiment, it is possible to manufacture a DRAM with a stable three-dimensional structure in a short manufacturing time.

[0222] (Variation) The method for manufacturing a DRAM according to the modified example of the second embodiment differs from the method for manufacturing a DRAM according to the second embodiment in that the second material is silicon nitride, and the fourth and fifth materials are amorphous silicon. According to the method for manufacturing a DRAM according to the modified example of the second embodiment, like the method for manufacturing a DRAM according to the second embodiment, it is possible to manufacture a DRAM with a stable three-dimensional structure in a short manufacturing time.

[0223] As described above, according to the second embodiment and the modified example, it is possible to achieve a high degree of integration of the semiconductor memory device.

[0224] (Third embodiment) The method for manufacturing the semiconductor memory device of the third embodiment differs from the method for manufacturing the modified semiconductor memory device of the first embodiment in that the fourth film is not formed. Hereinafter, some of the description overlapping with the first embodiment may be omitted.

[0225] An example of a method for manufacturing the semiconductor memory device of the third embodiment includes forming a first film of a first material in a first direction of a single crystal silicon substrate, forming a second film of a second material different from the first material in the first direction of the first film, forming a third film of a third material different from the second material in the first direction of the second film, forming a first opening that penetrates the third film, the second film, and the first film and reaches the single crystal silicon substrate, forming a first single crystal silicon layer in contact with the silicon substrate in the first opening, and forming a third film, A second opening is formed through the second film, the second film is etched from the side of the second opening to form a first recess portion that reaches the first single-crystal silicon layer, a second single-crystal silicon layer that contacts the first single-crystal silicon layer is formed in the first recess portion, a wiring layer that contacts a first portion of the second silicon layer is formed, a capacitor that contacts a second portion of the second silicon layer is formed, and a gate electrode layer that faces a third portion of the second single-crystal silicon layer between the first portion and the second portion is formed.

[0226] In the following, an example will be described in which the first material is silicon oxide, the second material is silicon nitride, and the third material is silicon oxide. In this case, the first material and the third material are the same material.

[0227] 51, 52, 53, 54, 55, and 56 are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device of the third embodiment.

[0228] First, a first silicon oxide film 81a, a first silicon nitride film 82a, a second silicon oxide film 81b, a second silicon nitride film 82b, and a third silicon oxide film 81c are formed in this order in a first direction on a single crystal silicon substrate 10 (Figure 51).

[0229] A first silicon oxide film 81a is formed on the surface of the single crystal silicon substrate 10. A first silicon nitride film 82a is formed on the first silicon oxide film 81a. A second silicon oxide film 81b is formed on the first silicon nitride film 82a. A second silicon nitride film 82b is formed on the second silicon oxide film 81b. A third silicon oxide film 81c is formed on the second silicon nitride film 82b.

[0230] The first silicon oxide film 81a, the first silicon nitride film 82a, the second silicon oxide film 81b, the second silicon nitride film 82b, and the third silicon oxide film 81c are formed by, for example, a CVD method.

[0231] The first silicon oxide film 81a is an example of a first film, the first silicon nitride film 82a is an example of a second film, and the second silicon oxide film 81b is an example of a third film.

[0232] Next, a first opening 44 is formed that penetrates the third silicon oxide film 81c, the second silicon nitride film 82b, the second silicon oxide film 81b, the first silicon oxide film 81a, and the first silicon oxide film 81a to reach the single crystal silicon substrate 10 (Figure 52).

[0233] The first opening 44 is formed by, for example, lithography and reactive ion etching (RIE).

[0234] Next, a first single crystal silicon layer 46 is formed in the first opening 44 in contact with the single crystal silicon substrate 10 (FIG. 53). The first single crystal silicon layer 46 is formed using the single crystal silicon substrate 10 as a seed crystal. The first single crystal silicon layer 46 is, for example, undoped single crystal silicon that does not contain conductive impurities.

[0235] The first single-crystal silicon layer 46 is formed by, for example, solid phase epitaxial growth. When using solid phase epitaxial growth, for example, an amorphous silicon layer is filled into the first opening 44. Then, a heat treatment is performed to form single-crystal silicon.

[0236] The first single crystal silicon layer 46 may also be formed using, for example, a vapor phase epitaxial growth method.

[0237] The first single crystal silicon layer 46 is formed by, for example, a VLS method. When using the VLS method, a metal or metal compound is formed as a catalyst, and single crystal silicon is formed around the catalyst as a nucleus. The catalyst is, for example, gold (Au), indium (In), tin (Sb), or indium tin oxide. The catalyst is formed by, for example, an ALD method, a CVD method, or a sputtering method.

[0238] Next, a second opening 47 is formed penetrating the third silicon oxide film 81c, the second silicon nitride film 82b, the second silicon oxide film 81b, and the first silicon nitride film 82a (FIG. 54). The surface of the single crystal silicon substrate 10 is not exposed at the bottom of the second opening 47.

[0239] The second opening 47 is formed by, for example, lithography and RIE.

[0240] Next, the first silicon nitride film 82a and the second silicon nitride film 82b are selectively etched from the side surface of the second opening 47 to form the first recess 48 (FIG. 55). The first single-crystal silicon layer 46 is exposed at the back of the first recess 48. The first silicon nitride film 82a and the second silicon nitride film 82b are etched using, for example, a dry etching method or a wet etching method.

[0241] Next, a second single crystal silicon layer 49 is formed in the first recess 48 in contact with the first single crystal silicon layer 46 (FIG. 56). The second single crystal silicon layer 49 is formed using the first single crystal silicon layer 46 as a seed crystal. The second single crystal silicon layer 49 is, for example, p-type single crystal silicon containing p-type impurities.

[0242] The second single crystal silicon layer 49 has a first portion P1, a second portion P2, and a third portion P3. The third portion P3 is provided between the first portion P1 and the second portion P2. A part of the second single crystal silicon layer 49 will eventually become the single crystal silicon layer 12.

[0243] The second single crystal silicon layer 49 is formed by, for example, vapor phase epitaxial growth.

[0244] The second single-crystal silicon layer 49 is formed using, for example, a VLS method. When using the VLS method, a metal or metal compound is used as a catalyst to form single-crystal silicon using the catalyst as a nucleus. The catalyst is, for example, gold (Au), indium (In), tin (Sb), or indium tin oxide. Here, since the catalyst needs to be formed on the exposed surface of the first single-crystal silicon layer 46 on the inner sidewall of the first recess portion 48, the catalyst is selectively attached to the exposed surface of the seed crystal silicon using, for example, an ALD method or a CVD method.

[0245] Thereafter, a wiring layer is formed in contact with the first portion P1 of the second single crystal silicon layer 49. A capacitor is formed in contact with the second portion P2 of the second single crystal silicon layer 49. A gate electrode layer is formed facing a third portion P3 between the first portion P1 and the second portion P2 of the second single crystal silicon layer 49. The wiring layer, capacitor, and gate electrode layer may be formed in any order.

[0246] By the above manufacturing method, the memory cell array of the DRAM of the third embodiment is formed.

[0247] According to the DRAM manufacturing method of the third embodiment, like the DRAM manufacturing method of the first embodiment, it is possible to manufacture a DRAM with a stable three-dimensional structure in a short manufacturing time.

[0248] (Variation) The method for manufacturing a DRAM according to the modified example of the third embodiment differs from the method for manufacturing a DRAM according to the third embodiment in that the second material is amorphous silicon. According to the method for manufacturing a DRAM according to the modified example of the third embodiment, it is possible to manufacture a DRAM with a stable three-dimensional structure in a short manufacturing time, as with the method for manufacturing a DRAM according to the third embodiment.

[0249] As described above, according to the third embodiment and the modified example, it is possible to achieve a high degree of integration of the semiconductor memory device.

[0250] In the first to third embodiments, the first material and the third material are the same, but the first material and the third material may be different.

[0251] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0252] 10 Single crystal silicon substrate 12 Single crystal silicon layer 12a first n-type impurity region 12b Second n-type impurity region 12c p-type impurity region 14 gate electrode layer 16 Gate insulating film 18 wiring layer 41a First silicon oxide film (first film) 41b Second silicon oxide film (third film) 42a First amorphous silicon film (second film) 43a First silicon nitride film (fourth film) 44 First Opening 45b Second oxide film (oxide film) 46 First single crystal silicon layer 47 Second Opening 48 First recess 49 Second single crystal silicon layer 51 Second recess 61a First silicon oxide film (first film) 61b Second silicon oxide film (third film) 62a First silicon nitride film (second film) 63a First amorphous silicon film (fourth film) 71a First silicon oxide film (first film) 71b Second silicon oxide film (third film) 72a First silicon nitride film (fourth film) 72b Second silicon nitride film (fifth film) 73a First amorphous silicon film (second film) 81a First silicon oxide film (first film) 81b Second silicon oxide film (third film) 82a First silicon nitride film (second film) CA Capacitor P1 First part P2 Second part P3 Third Part

Claims

1. forming a first film of a first material in a first direction on a single crystal silicon substrate; forming a second film of a second material different from the first material in the first direction of the first film; forming a third film of a third material different from the second material in the first direction of the second film; forming a first opening that penetrates the third film, the second film, and the first film and reaches the single crystal silicon substrate; forming a first single-crystal silicon layer in contact with the single-crystal silicon substrate in the first opening; forming a second opening through the third film and the second film; etching the second film from a side surface of the second opening to form a first recess portion reaching the first single-crystal silicon layer; forming a second single-crystal silicon layer in contact with the first single-crystal silicon layer in the first recess; forming a wiring layer in contact with the first portion of the second single-crystal silicon layer; forming a capacitor in contact with a second portion of the second single crystal silicon layer; forming a gate electrode layer facing a third portion of the second single-crystal silicon layer between the first portion and the second portion;

2. 2. The method for manufacturing a semiconductor memory device according to claim 1, wherein said first single crystal silicon layer is formed by solid phase epitaxial growth.

3. 2. The method for manufacturing a semiconductor memory device according to claim 1, wherein said first single crystal silicon layer is formed by vapor phase epitaxial growth.

4. 2. The method for manufacturing a semiconductor memory device according to claim 1, wherein said first single crystal silicon layer is formed by using a Vapor-Liquid-Solid (VLS) method.

5. 2. The method for manufacturing a semiconductor memory device according to claim 1, wherein said second single crystal silicon layer is formed by vapor phase epitaxial growth.

6. 2. The method for manufacturing a semiconductor memory device according to claim 1, wherein said second single crystal silicon layer is formed by using a Vapor-Liquid-Solid (VLS) method.

7. 2. The method for manufacturing a semiconductor memory device according to claim 1, wherein, when forming said second single crystal silicon layer, an impurity concentration or an impurity conductivity type in said second single crystal silicon layer is changed during the formation of said second single crystal silicon layer.

8. When forming the second single-crystal silicon layer, a first n-type impurity region, a p-type impurity region, and a second n-type impurity region are formed in this order from the side closest to the first single-crystal silicon layer; 2. The method for manufacturing a semiconductor memory device according to claim 1, wherein said gate electrode layer faces said p-type impurity region.

9. the second material is amorphous silicon or polycrystalline silicon; forming an oxide film on a surface of the second film exposed on a side surface of the first opening before forming the first single-crystal silicon layer; 2. The method for manufacturing a semiconductor memory device according to claim 1, wherein, when forming said first recessed portion, said second film is etched and then said oxide film is removed.

10. forming a fourth film made of a fourth material different from the second material and the third material between the second film and the third film; After forming the second single-crystal silicon layer, removing the first single-crystal silicon layer in the first opening; after removing the first single-crystal silicon layer, etching the fourth film from the side surface of the first opening to form a second recess portion; 2. The method for manufacturing a semiconductor memory device according to claim 1, wherein said wiring layer is formed in said second recessed portion.

11. forming a fourth film made of a fourth material different from the first material and the second material between the first film and the second film; forming a fifth film made of a fifth material identical to the fourth material between the second film and the third film; After forming the second single-crystal silicon layer, removing the first single-crystal silicon layer in the first opening; after removing the first single crystal silicon layer, etching the fourth film and the fifth film from the side surface of the first opening to form a second recess portion; 2. The method for manufacturing a semiconductor memory device according to claim 1, wherein said gate electrode layer is formed in said second recessed portion.

12. a single crystal silicon substrate; a single-crystal silicon layer extending in a direction along the surface of the single-crystal silicon substrate and spaced apart from the single-crystal silicon substrate; a wiring layer electrically connected to a first portion of the single crystal silicon layer; a capacitor electrically connected to a second portion of the single crystal silicon layer; a gate electrode layer facing a third portion of the single crystal silicon layer between the first portion and the second portion, A semiconductor memory device, wherein the first portion has a higher crystal defect density than the third portion.

13. 13. The semiconductor memory device according to claim 12, wherein said first portion includes a first n-type impurity region, said second portion includes a second n-type impurity region, and said third portion includes a p-type impurity region.

14. 13. The semiconductor memory device according to claim 12, wherein the crystal defect density of said first portion is at least ten times as high as the crystal defect density of said third portion.

15. 13. The semiconductor memory device according to claim 12, further comprising a gate insulating film provided between said gate electrode layer and said third portion.

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