Conformally plated through-via in glass

Abstract

To provide a multilayer substrate with a glass core layer sandwiched therebetween, the multilayer substrate being used in a semiconductor package.SOLUTION: In a semiconductor package, a glass core includes a through-hole or through-glass via (TGV). The TGV is defined by a shape similar to an hourglass, has a first diameter 110 at the upper surface 101 and the first diameter at the lower surface 103, and has a smaller second diameter 114 therebetween. A sidewall in the periphery of the TGV is plated with a thin conformal conductive material 112 from the upper surface to the lower surface, thereby forming cavities 122, 124 therein. The cavities form a bridge 116 by the conductive material at the second diameter. The TGV and an optionally selected cavity have an insulating material therein. A conductive contact extends across the TGV at the upper surface and electrically connects with the conductive material.SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001] Glass layers are often used to provide better mechanical / dimensional stability, rigidity, and to improve track density in semiconductor packages when compared to traditional epoxy-fiberglass composites. To transfer signals from the top to the bottom of the glass layer, the glass layer is typically perforated with through vias, or "through-glass vias (TGVs)." However, the brittle quality of glass and the ineffective copper deposition in TGVs continue to present technical challenges in manufacturing and operation. Accordingly, improved architectures and methods for transferring signals through glass layers are desirable. [Brief explanation of the drawings]

[0002] [Figure 1] 1 provides a simplified cross-sectional view of an embodiment of a conformally plated through glass via according to various embodiments.

[0003] [Figure 2] 1A-1C illustrate various exemplary stages in the fabrication of a conformally plated through glass via according to various embodiments. [Figure 3] 1A-1C illustrate various exemplary stages in the fabrication of a conformally plated through glass via according to various embodiments. [Figure 4] 1A-1C illustrate various exemplary stages in the fabrication of a conformally plated through glass via according to various embodiments. [Figure 5] 1A-1C illustrate various exemplary stages in the fabrication of a conformally plated through glass via according to various embodiments.

[0004] [Figure 6] 1 illustrates an exemplary use case of a conformally plated through glass via according to various embodiments. [Figure 7] 1 illustrates an exemplary use case of a conformally plated through glass via according to various embodiments.

[0005] [Figure 8] 1 illustrates an exemplary method for conformally plated through glass vias according to various embodiments.

[0006] [Figure 9] FIG. 1 is a top view of a wafer and die that may be included in a microelectronic assembly according to any of the embodiments disclosed herein.

[0007] [Figure 10] 1 is a simplified cross-sectional side view illustrating the implementation of an integrated circuit on a die that may be included in various embodiments according to any of the embodiments disclosed herein.

[0008] [Figure 11] FIG. 1 is a cross-sectional side view of a microelectronic assembly that may include any of the embodiments disclosed herein.

[0009] [Figure 12] FIG. 1 is a block diagram of an exemplary electrical device that may include any of the embodiments disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0010] Semiconductor packages may include multi-layer substrates with a "glass core" or sandwiched layers of glass. The glass layers have holes (also called through vias or through-glass vias (TGVs)) extending therethrough to accommodate the transfer of electrical signals between the silicon substrates on their top and bottom surfaces. The glass layers provide mechanical / directional stability and rigidity in the semiconductor package and can increase track density; however, the brittle nature of glass and the difficulty of effective copper deposition in TGVs continue to present technical challenges in manufacturing and operation.

[0011] Some solutions have involved depositing buffer or liner layers on the sidewalls of TGVs to improve copper deposition in the TGVs. However, these solutions are vulnerable to bending and temperature stresses. Additionally, while TGVs are often shown with vertical walls, in reality, they are more likely to taper from the top to the center and from the bottom to the center, exhibiting an hourglass shape. This taper, when filled with conductive material, creates a "pinch point" at the center. The pinch point phenomenon can adversely limit performance and power density.

[0012] The embodiments described herein provide a technical solution to these technical challenges in the form of conformally plated through-glass vias. Implementation of the architectures and methods described herein can be readily detected using SEM and / or TEM images, as described below. These concepts are developed in more detail below.

[0013] Exemplary embodiments are described below in conjunction with the following drawings, in which like numerals indicate like elements. Unless otherwise noted, the figures are not necessarily to scale, but may depend on the spatial orientation and relative positioning of features. As will be understood, certain terms such as "ceiling" and "floor," as well as "upper," "uppermost," "lower," "above," "below," "bottom," and "top," refer to directions based on viewing the figure to which reference is made. Furthermore, terms such as "front," "back," "rear," "side," "vertical," and "horizontal" may describe the orientation and / or location of portions of a component within a consistent, but arbitrary, frame of reference made clear by reference to text and associated figures describing the described component. Such terms may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0014] As used herein, the term "adjacent" refers to layers or components that are in direct physical contact with each other, with no layers or components between them. For example, layer X adjacent to layer Y refers to a layer that is in direct physical contact with layer Y. In contrast, as used herein, the phrase "located on" (alternatively, "located under," "located above / over," or "located next to," in the context of a first layer or component disposed on a second layer or component) includes (i) configurations in which a first layer or component is directly physically attached (i.e., adjacent) to a second layer, and (ii) components and configurations in which a first layer or component is attached (e.g., coupled) to a second layer or component via one or more intervening layers or components.

[0015] The following detailed description is not intended to limit the application and uses of the disclosed technology. It may be apparent that novel embodiments may be practiced without all of the details described herein. For simplicity, well-known structures and devices may be shown in block diagram form to facilitate their description.

[0016] Figures 1 through 7 include many repeated objects. Unless otherwise noted, similar objects, whether labeled or not, are intended to perform the same function or to be the same feature across multiple images. Additionally, while the objects in Figures 1 through 7 are not to scale, the various relationships and orientations shown in the images are intentional, as described herein.

[0017] FIG. 1 provides a simplified cross-sectional view of an embodiment of a conformally plated through glass via. A layer of glass 102, or "glass core," can be patterned with a plurality of through holes, also referred to as through glass vias (TGVs). Embodiments 100 and 130 illustrate one of at least one TGV that can be present in the layer of glass 102. The layer of glass 102 has a top surface 101 and a bottom surface 103. The layer of glass 102 can have a thickness 126 (Z height) ranging from about 20 microns to about 1.5 millimeters, + / - 10%.

[0018] The glass layer 102 may comprise glass (as used herein, glass may be an alkali-free alkaline earth boroaluminosilicate glass, such as a glass containing aluminum, oxygen, boron, silicon, and an alkaline earth metal (e.g., beryllium, magnesium, calcium, strontium, barium, radium), such as a glass containing SiO, AlO, BO, and MgO), or a photosensitive glass (optically processable glass or photostructurable glass). In some embodiments, the photosensitive glass may be a glass belonging to the lithium silicate family of glasses (e.g., a glass containing lithium, silicon, and oxygen) containing metal particles, such as gold, silver, or other suitable metal particles. In some embodiments, the glass layer 102 or glass core may comprise multiple glass sheets bonded together with an adhesive layer. In various embodiments, for example, the substrate (see, for example, the illustrations in FIGS. 6 and 7) has a Z height (thickness) in the range of approximately 0.1 millimeters (mm) to 15 mm.

[0019] At least one through hole or through glass via (TGV) is formed in the layer of glass 102. The through hole extends downward from the top surface 101 to the bottom surface 103 as shown, and has an axis perpendicular to the top surface. The TGV is a volume from which glass has been removed and in which a conductive material is disposed sufficient to enable electrical communication from the top surface 101 to the bottom surface 103. Accordingly, the through hole is characterized by a first diameter 110 at the top surface 101 and a sidewall associated with the first diameter 110 at the bottom surface 103. As shown in embodiments 100 and 130, the axis of the TGV is substantially perpendicular to the top surface 101 of the layer of glass 102.

[0020] The shape of the TGV reflects the technique used to create it. In embodiment 130, the sidewalls have a slope (angle 120) measured from the plane of the top surface 101, where the through-hole narrows as it traces toward a center point, which has a second diameter 114 smaller than the first diameter. In embodiments, the second diameter is at least 10% smaller than the first diameter, and in ideal cases can grow up to 100%. The slope in the sidewalls in embodiment 130 can be the result of using laser etching to create the TGV: in this approach, the top surface 101 is laser etched to approximately the center point, and the bottom surface is similarly laser etched to the center point. This results in a somewhat hourglass-shaped TGV, as shown, with a corresponding slope in the sidewalls in the bottom half of the TGV. The center point can be midway (plus or minus 15%) between the top and bottom surfaces. In contrast, in an ideal cylindrical TGV, as shown in embodiment 100, the through-hole has a first diameter 110 continuously from the upper surface 101 to the lower surface 103.

[0021] The conductive material 104 conforms to the sidewalls of the cavity and is adjacent to a non-conductive liner layer 252 between the copper (conductive material) and the glass. The conductive material 104 is continuous from the top surface to the bottom surface. The conductive material does not completely fill the TGV. In embodiment 100, the conductive material has a thickness that remains the same from the top surface to the bottom surface, represented by first diameter 110 minus diameter 108, where diameter 108 is the diameter of cavity 106, which extends continuously from top surface 101 to bottom surface 103. The conductive material forms at least one cavity within the TGV.

[0022] In practice, the techniques used to form the TGV may more frequently produce the sidewall shape of embodiment 130. In embodiment 130, the sidewalls are tapered or sloped inward at angle 120, as shown. This is possible because a laser is used to create the TGV, and the laser tapers as it passes through the material. Also in embodiment 130, the thickness 118 of the conductive material 112 varies from the top surface 101 to the bottom surface 103 to a center point; this is shown with thickness 118-1 near the center point and thickness 118-2 at the top surface 101. The conductive material 112 forms a bridge 116 at the center point, as shown. The bridge 116 forms a floor for cavity 122, thereby also forming a second cavity 124 within the TGV volume between the bridge 116 and the bottom surface 103.

[0023] In practice, the TGVs and optional cavities similarly created in the layer of glass may have insulating material inside, and the TGVs may have conductive contacts or pads extending across them and electrically attached to the conductive material on the sidewalls. A description of the fabrication of these features and further fabrication steps is described below in connection with Figures 1 through 8.

[0024] Implementation of these embodiments can be identified by visually inspecting a cross-sectional TEM or SEM image as shown in embodiment 130 and observing thickness variations in conductive material 112 (also measured by moving up and down the Z axis as illustrated and described) and bridges 116 created by conductive material 112, as illustrated and described.

[0025] Various embodiments can also be distinguished by visually inspecting top-view or plan-view TEM or SEM images. For example, in embodiment 130, comparing planar slices made horizontally at A, B, and C will reveal rings of conductive material 112 that either have different outer diameters and inner diameters or are solid, as in bridge 116. A calculation of the cross-sectional area of ​​each of these images (at A, B, and C) will result in the same number (plus or minus 15%).

[0026] These visually observable features shown in embodiment 130 are advantageous because having conductive material at the surface of the glass is generally positively associated with the mechanical stress experienced therein; for example, the more copper there is on or near the surface of the glass, the greater the stress generally. The embodiment advantageously reduces the amount of conductive material on the top surface (and bottom surface).

[0027] Figures 2-5 are simplified cross-sectional views of various exemplary stages in the manufacture of conformally plated through glass vias according to various embodiments. Figures 6-7 are simplified cross-sectional views of various exemplary use cases for conformally plated through glass vias according to various embodiments. Figure 8 shows an exemplary method 800 for conformally plated through glass vias.

[0028] Image 200 shows a layer of glass 202 prior to the creation of the TGV and cavities. In embodiments that produce a panel at a time, the X length and corresponding Y length (defining an area in a top or plan view) of the layer of glass can range from a first length (e.g., X) in the range of 10 millimeters to 700 millimeters and a second length (e.g., Y) in the range of 10 millimeters to 700 millimeters, where the first length is perpendicular to the second length. The composition of glass 202 is as described above in connection with FIG. 1.

[0029] Image 230 shows (at 802) through-holes or TGVs created in layer of glass 202. As mentioned above, the laser changes the glass chemistry, allowing regions to be preferentially etched away, resulting in the tapering, as described in connection with embodiment 130. In image 230, a first TGV 232-1 / 330-1 and a second TGV 232-2 / 330-2 are shown. In reality, TGVs 232-1 and 232-2 may be two of multiple TGVs. An optional cavity 234 may also be created at this stage. The optional cavity 234 may be large enough (e.g., minimum diameter 306) to fit an IC die or other component at a later manufacturing stage.

[0030] As shown in image 250, at 804, a liner layer 252 is added. The liner layer is adjacent to and conformal with the glass material in the glass layer. The liner layer 252 can have a thickness anywhere between 15 nanometers and 10 microns. The thickness of the liner layer 252 depends on the method used to deposit it. For example, using a chemical vapor deposition (CVD) process for silicon nitride, the liner layer 252 can be very thin, such as 20 nanometers (+ / - 5 nanometers). In other embodiments, the liner can be a slit-coated dielectric material or polymer such as polyethylene, which can then be between 50 nanometers and 10 microns (+ / - 10%).

[0031] Image 300 shows seeds 302 deposited at 806. The seeds are the first layer of conductive material 112 that is conformally deposited across the top and bottom surfaces, in the TGVs, and in the cavities to aid in electroplating. In various embodiments, the seeds are copper. In some embodiments, the seeds 302 are hybrid seeds including layers of ruthenium, then copper, then titanium, then copper, etc. The hybrid seeds may be deposited using CVD, and the thickness 303 of the seed or hybrid seed layer may be 10 nanometers to 15 microns (+ / - 10%). At 806, bridges (bridges 116) are formed in TGVs 330-1 and 330-2. The area indicated by the dashed circle 304 is understood to have the features and orientation described in connection with embodiment 130 of FIG. 1 . In embodiments including optional cavity 332, one skilled in the art will understand that diameter 306 may be too large (e.g., cavity 332 may have a diameter ranging between 1 and 30 millimeters) to form a bridge across it.

[0032] Image 350 shows the layer of glass from 300 laminated (at 808) with an insulating material 352. In various embodiments, the insulating material is a dielectric material. As shown, the cavity formed in the conductive material or seed 302 is filled with the insulating material 352 at 808. The optional cavity 332 is also filled with the insulating material. The dielectric material can have a thickness of 100 nanometers to 20 microns (+ / - 10%).

[0033] The dielectric material can be any suitable nitride or oxide, such as SiOx, silicon dioxide (SiO2), SiOxNy, carbon-doped silicon dioxide (C-doped SiO2, also known as CDO or organosilicate glass, a material containing silicon, oxygen, and carbon), fluorine-doped silicon dioxide (F-doped SiO2, also known as fluorosilicate glass, a material containing fluorine, silicon, and oxygen), hydrogen-doped silicon dioxide (H-doped SiO2, a material containing silicon, oxygen, and hydrogen), etc. In some embodiments, the dielectric layer comprises a photo-imageable dielectric (PID). In some embodiments, the dielectric material comprises Ajinomoto Build-Up film (ABF), which is a material comprising an organic resin matrix with different types of fillers (e.g., silica fillers of different sizes or hollow fillers of different sizes) to control the coefficient of thermal expansion (CTE) and / or electrical properties (e.g., dielectric constant (Dk) and / or dissipation factor (insertion loss) (Df)).

[0034] In some embodiments, it is advantageous for the dielectric material to have a CTE that matches that of a component attached to it, such as an integrated circuit die (e.g., matches the CTE of silicon), or that matches the substrate or PCB. In some embodiments, the dielectric material can have a CTE that is close to that of silicon (e.g., within 10%). In other embodiments, the dielectric material can be any type of epoxy molding compound.

[0035] At 810, chemical mechanical polishing (CMP) may be performed to expose the conductive material 112 on the sidewalls of the TGVs and to remove some of the insulating material to expose approximately 20 microns (+ / −10%) of seed or conductive material 112 to facilitate electroplating in the next fabrication stage. Once the CMP process is complete, a conductive plate 402 may be electrically attached over the planarized top surface, as shown in image 400. In some embodiments, the conductive plate 402 comprises copper. Note that TGVs 430-1 and 430-2 now have insulating material within their cavities, as does the larger optional cavity 432.

[0036] In 812, conductive plate 402 is then patterned and etched to create conductive contacts or pads for any TGVs for subsequent vias to be provided and attached. After patterning and etching, conductive plate 402 and seed 302 are removed accordingly, as shown in image 450. Note that conductive contact 452-1 is electrically attached to the sidewall of TGV 430-1 on the upper surface, capping the cavity filled with insulating material; and conductive contact 452-3 is also attached to the sidewall of TGV 430-1 on the lower surface, capping the cavity filled with insulating material. Similarly, conductive contact 452-2 is electrically attached to the sidewall of TGV 430-2 on the upper surface, capping the cavity filled with insulating material; and conductive contact 452-4 is also attached to the sidewall of TGV 430-2 on the lower surface, capping the cavity filled with insulating material. In some embodiments, the conductive contacts on the bottom surface are referred to as conductive pads to distinguish them from the conductive contacts on the top surface. Note that optional cavity 432 is a region filled with insulating material and has seed or hybrid seed sidewalls 454. In practice, the insulating material from this optional cavity 432 may be removed, such as by laser drilling or ablation, so that an integrated circuit or component may be placed and electrically attached therein, for example, during construction of a system or package assembly. This sidewall 454 (which may surround an integrated circuit or other component) is a distinguishing feature that indicates implementation of the methods and apparatus described herein.

[0037] Some non-limiting examples of ICs and components that may be placed in cavity 432 include memory or high bandwidth memory, trench capacitors, central processing units, photonic integrated circuits, graphics processing units, and the like.

[0038] At 814, the layer of glass with conformally plated TGVs may be subject to further fabrication and assembly. In a simplified example, as shown in image 500, the embodiment from image 450 may have a silicon substrate built on its top surface (e.g., at 504) or its bottom surface (e.g., at 506). Continuing with this simplified example, in images 600 and 700, the embodiment from image 450 is shown attached or sandwiched between substrates: substrate 604 / 704 includes a redistribution layer (RDL) or one or more dielectric layers 608 / 708 having conductive traces 628 / 728 and vias 626 / 726 patterned therein on the top surface, and substrate 606 / 706 includes a redistribution layer (RDL) or one or more dielectric layers 608 / 708 having conductive traces 628 and vias 626 patterned therein on the bottom surface.

[0039] The dielectric material may be one of the dielectric or insulating materials described above. The conductive material used for the RDL traces 628 and vias 626 may include a metal (e.g., copper, aluminum, nickel, cobalt, iron, tin, gold, silver, or a combination thereof) or another suitable conductive material.

[0040] Optional cavity 432 is open to be filled with an IC, PIC, or other component and electrically attached to 610 / 710 and 612 / 712 as known in the art. As intended, conformally plated through vias in the provided glass layer provide landings and contacts for the vias, providing an electrical path from the top surface 603 / 703 of the substrate to the bottom surface 605 / 705 of the substrate.

[0041] In FIG. 7 , a first IC and a second IC were attached to top surface 703, and bottom surface 705 had solder attached in openings created therefor. Dies IC1 and IC2 may be unpackaged integrated circuit dies and may alternatively be referred to as chips, chiplets, chip composites, or chiplet composites. While the terms die, chip, and chiplet may be used interchangeably, the term chiplet is sometimes used to refer to an integrated circuit die that implements a subset of the functionality of a larger integrated circuit component. While the illustration shows chiplets as having uniform dimensions, in reality, chiplet dimensions (lateral dimensions as well as thickness) and shape may vary from chiplet to chiplet; chiplets may also vary by type / function (e.g., compute, memory, I / O, power management (controlling the supply of power and / or providing power to components)).

[0042] In further manufacturing steps, the dies IC1 and IC2 may be stabilized within an encapsulant, such as molding compound, a dielectric material, a metal, a ceramic, a plastic, or a combination thereof. An underfill may also be applied beneath IC1 and IC2 to surround the solder bumps. A variety of underfill materials may be used, and they are generally non-conductive (electrically) and reduce thermomechanical stresses. The underfill material may take the form of a liquid prepolymer with a filler such as silica, alumina, or boron nitride. The underfill may be cured to solidify it.

[0043] Additionally, as part of the thermal management solution, a thermal conduction layer interface material (TIM) (not shown) may be disposed over the encapsulant and / or over the die. The TIM may be any suitable material, such as a silver particle-filled thermal compound, thermal grease, phase change material, indium foil, or graphite sheet. The thermal management solution may be a conformal solution that accommodates differences in the height of the integrated circuit die to which the thermal management solution provides cooling. For example, the thermal management solution may include a substantially planar cooling component with a TIM of varying thickness between the cooling component and the integrated circuit die. In another example, the cooling component is non-planar, and the profile of the cooling component may vary depending on the thickness of the integrated circuit die to which the cooling component provides cooling. In such an embodiment, the TIM may have a substantially uniform thickness between the cooling component and the integrated circuit die, which may have varying thicknesses. The thermal management solution may also include an integrated heat spreader.

[0044] Thus, various non-limiting embodiments of conformally plated through vias in glass have been described. The embodiments show distinct features in SEM images, including but not limited to, cavities inside TGVs with insulating material therein, conductive material that varies in thickness along the sidewalls of the TGV but maintains a consistent planar cross-sectional area, a bridge of conductive material at the center point of the TGV, and walls of conductive seed material around the periphery of the cavity that houses an IC or other component. The following description provides additional details and context for various die and various package assemblies and device configurations that can be produced based on or using the provided embodiments.

[0045] 9 is a top view of a wafer 900 and dies 902 that may be included in any of the embodiments disclosed herein. Wafer 900 may be composed of a semiconductor material and may include one or more dies 902 formed on the surface of wafer 900. After fabrication of integrated circuit components on wafer 900 is complete, wafer 900 may undergo a singulation process in which dies 902 are separated from one another to provide individual "chips" or destined for packaged integrated circuit components. Individual dies 902 that include integrated circuit components may include one or more transistors (e.g., part of transistor 1040 in FIG. 10 , described below), support circuitry for transferring electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 900 or die 902 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND gates, OR gates, NAND gates, or NOR gates), or any other suitable circuit elements. Additionally, multiple devices may be combined on a single die 902. For example, a memory array formed by multiple memory devices may be formed on the same die 902 as a processor unit (e.g., processor unit 1202 of FIG. 12 ) or other logic configured to store information in the memory devices or execute instructions stored in the memory array. In some embodiments, die 902 may be attached to a wafer 900 including other dies, and the wafer 900 is subsequently singulated; this manufacturing procedure is referred to as a die-to-wafer assembly technique.

[0046] 10 is a side cross-sectional view of an integrated circuit 1000 that may be included in any of the embodiments disclosed herein. One or more of the integrated circuits 1000 may be included in one or more dies 902 (FIG. 9). The integrated circuits 1000 may be formed on a die substrate 1002 (e.g., wafer 900 of FIG. 9) and may be included in a die (e.g., die 902 of FIG. 9).

[0047] The die substrate 1002 may be a semiconductor substrate composed of a semiconductor material system, including, for example, an n-type or p-type material system (or a combination of both). The die substrate 1002 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1002 may be formed using alternative materials, which may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additional materials classified as II-VI, III-V, or IV may also be used to form the die substrate 1002. While a few examples of materials from which the die substrate 1002 may be formed are described here, any material capable of serving as the foundation for the integrated circuit 1000 may be used. Die substrate 1002 can be part of a singulated die (eg, die 902 in FIG. 9) or a wafer (eg, wafer 900 in FIG. 9).

[0048] The integrated circuit 1000 may include one or more device layers 1004 disposed on a die substrate 1002. The device layer 1004 may include features of one or more transistors 1040 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 1002. The transistors 1040 may include, for example, one or more source and / or drain (S / D) regions 1020, a gate 1022 for controlling the flow of current between the S / D regions 1020, and one or more S / D contacts 1024 for transferring electrical signals to and from the S / D regions 1020.

[0049] The gate 1022 may be formed of at least two layers: a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve its quality if a high-k material is used.

[0050] A gate electrode may be formed in the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1040 is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, may be included for other purposes.

[0051] For PMOS transistors, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals described below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals described above with reference to PMOS transistors (e.g., for work function tuning).

[0052] In some embodiments, when viewed as a cross-section of the transistor 1040 along the source-channel-drain direction, the gate electrode may include a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 1002 and two sidewall portions substantially perpendicular to the top surface of the die substrate 1002. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate 1002 and include no sidewall portions substantially perpendicular to the top surface of the die substrate 1002. In other embodiments, the gate electrode may include a combination of U-shaped and planar non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0053] In some embodiments, pairs of sidewall spacers may be formed on opposing sides of the gate stack to surround the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and include deposition and etching processes. In some embodiments, multiple spacer pairs may be used; for example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0054] The S / D regions 1020 may be formed in the die substrate 1002 adjacent to the gates 1022 of the individual transistors 1040. The S / D regions 1020 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 1002 to form the S / D regions 1020. An annealing process that activates the dopants and diffuses them further into the die substrate 1002 may follow the ion-implantation process. In the latter process, the die substrate 1002 may first be etched to form recesses at the locations of the S / D regions 1020. An epitaxial deposition process may then be performed to fill the recesses with the material used to fabricate the S / D regions 1020. In some implementations, the S / D regions 1020 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D regions 1020 may be formed using one or more alternative semiconductor materials, such as germanium or III-V materials or alloys. In further embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D regions 1020.

[0055] Electrical signals, such as power and / or input / output (I / O) signals, may be transferred to and / or from devices (e.g., transistor 1040) in device layer 1004 via one or more interconnect layers (shown in FIG. 10 as interconnect layers 1006-1010) disposed on device layer 1004. For example, conductive features (e.g., gate 1022 and S / D contacts 1024) in device layer 1004 may be electrically coupled to interconnect structures 1028 in interconnect layers 1006-1010. One or more interconnect layers 1006-1010 may form a metallization stack (also referred to as an "ILD stack") 1019 of integrated circuit 1000.

[0056] The interconnect structures 1028 may be arranged within the interconnect layers 1006-1010 to transfer electrical signals according to a variety of designs, and in particular, the arrangement is not limited to the particular configuration of the interconnect structures 1028 shown in Figure 10. Although a particular number of interconnect layers 1006-1010 are shown in Figure 10, embodiments of the present disclosure include integrated circuits having more or fewer interconnect layers than those shown.

[0057] In some embodiments, the interconnect structure 1028 may include lines 1028a and / or vias 1028b filled with a conductive material, such as metal. The lines 1028a may be arranged to transfer electrical signals in a planar direction substantially parallel to the surface of the die substrate 1002 on which the device layer 1004 is formed. For example, the lines 1028a may transfer electrical signals in an into-page and / or across-page direction. The vias 1028b may be arranged to transfer electrical signals in a planar direction substantially perpendicular to the surface of the die substrate 1002 on which the device layer 1004 is formed. In some embodiments, the vias 1028b may electrically couple together the lines 1028a of different interconnect layers 1006-1010.

[0058] As shown in FIG. 10 , the interconnect layers 1006-1010 can include a dielectric material 1026 disposed between interconnect structures 1028. In some embodiments, the dielectric material 1026 disposed between the interconnect structures 1028 in different ones of the interconnect layers 1006-1010 can have different compositions; in other embodiments, the composition of the dielectric material 1026 between the different interconnect layers 1006-1010 can be the same. The device layer 1004 can also include a dielectric material 1026 disposed between the transistor 1040 and the bottom layer of the metallization stack. The dielectric material 1026 included in the device layer 1004 can have a different composition than the dielectric material 1026 included in the interconnect layers 1006-1010; in other embodiments, the composition of the dielectric material 1026 in the device layer 1004 can be the same as the dielectric material 1026 included in any one of the interconnect layers 1006-1010.

[0059] A first interconnect layer 1006 (referred to as metal 1 or "M1") may be formed directly on the device layer 1004. In some embodiments, as shown, the first interconnect layer 1006 may include lines 1028a and / or vias 1028b. The lines 1028a of the first interconnect layer 1006 may be coupled to contacts (e.g., S / D contacts 1024) of the device layer 1004. The vias 1028b of the first interconnect layer 1006 may be coupled to lines 1028a of the second interconnect layer 1008.

[0060] A second interconnect layer 1008 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1006. In some embodiments, the second interconnect layer 1008 may include vias 1028b to couple lines of interconnect structures 1028 of the second interconnect layer 1008 with lines 1028a of the third interconnect layer 1010. Although the lines 1028a and vias 1028b are structurally depicted as lines within individual interconnect layers for clarity, the lines 1028a and vias 1028b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process) in some embodiments.

[0061] The third interconnect layer 1010 (referred to as metal 3 or "M3") (and additional interconnect layers, if desired) may be formed successively on the second interconnect layer 1008 according to similar techniques and configurations described in connection with the second interconnect layer 1008 or the first interconnect layer 1006. In some embodiments, interconnect layers "higher" in the metallization stack 1019 in the integrated circuit 1000 (i.e., further away from the device layer 1004) may be thicker than underlying interconnect layers in the metallization stack 1019, with the lines 1028a and vias 1028b in the higher interconnect layers being thicker than those in the lower interconnect layers.

[0062] The integrated circuit 1000 may include a solder resist material 1034 (e.g., polyimide or a similar material) and one or more conductive contacts 1036 formed on the interconnect layers 1006-1010. In FIG. 10, the conductive contacts 1036 are shown to take the form of bond pads. The conductive contacts 1036 may be electrically coupled to the interconnect structure 1028 and configured to transfer electrical signals of the transistor 1040 to an external device. For example, a solder bond may be formed on the one or more conductive contacts 1036 to mechanically and / or electrically couple an integrated circuit die including the integrated circuit 1000 to another component (e.g., a printed circuit board). The integrated circuit 1000 may include additional or alternative structures for transferring electrical signals from the interconnect layers 1006-1010; for example, the conductive contacts 1036 may include other similar features (e.g., posts) that transfer electrical signals to an external component.

[0063] In some embodiments in which integrated circuit 1000 is a double-sided die, integrated circuit 1000 may include another metallization stack (not shown) on an opposing side of device layer 1004. This metallization stack may include multiple interconnect layers such as those described above with reference to interconnect layers 1006-1010 to provide conductive paths (e.g., including conductive lines and vias) between device layer 1004 and conductive contacts 1036 to additional conductive contacts (not shown) on the opposing side of integrated circuit 1000.

[0064] In other embodiments in which integrated circuit 1000 is a double-sided die, integrated circuit 1000 may include one or more through-silicon vias (TSVs) that extend through die substrate 1002; these TSVs may make contact with device layer 1004 and may provide conductive paths between device layer 1004 and additional conductive contacts (not shown) on the opposite side of integrated circuit 1000 from conductive contacts 1036. In some embodiments, the TSVs extending through the substrate may be used to transfer power and ground signals from conductive contacts 1036 on the opposite side of integrated circuit 1000 to transistor 1040 and any other components integrated on the integrated circuit 1000 die, and metallization stack 1019 may be used to transfer I / O signals from conductive contacts 1036 to transistor 1040 and any other components integrated on the integrated circuit 1000 die.

[0065] Multiple integrated circuits 1000 may be stacked with one or more TSVs in each stacked device providing a connection between one of the devices and any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies may be stacked on top of a base integrated circuit die, with TSVs in the HBM die providing a connection between the individual HBM and base integrated circuit dies. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine-pitch solder bumps (microbumps).

[0066] 11 is a side cross-sectional view of a microelectronic assembly 1100 that may include any of the embodiments disclosed herein. The microelectronic assembly 1100 includes multiple integrated circuit components disposed on a circuit board 1102 (which may be a motherboard, system board, main board, etc.). The microelectronic assembly 1100 may include components disposed on a first side 1140 of the circuit board 1102 and an opposing second side 1142 of the circuit board 1102; generally, components may be disposed on one or both of the sides 1140 and 1142.

[0067] In some embodiments, the circuit board 1102 may be a printed circuit board (PCB) that includes multiple metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Each metal layer includes conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to transfer electrical signals (optionally in conjunction with other metal layers) between components coupled to the circuit board 1102. In other embodiments, the circuit board 1102 may be a non-PCB substrate. The microelectronic assembly 1100 shown in FIG. 11 includes a package-on-interposer structure 1136 coupled to a first surface 1140 of the circuit board 1102 by a coupling component 1116. The bonding components 1116 may electrically and mechanically couple the package-on-interposer structure 1136 to the circuit board 1102 and may include solder balls (as shown in FIG. 11), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical bonding structure.

[0068] The package-on-interposer structure 1136 may include an integrated circuit component 1120 coupled to the interposer 1104 by a coupling component 1118. The coupling component 1118 may take any suitable form for the application, such as the formations described above with reference to the coupling component 1116. While a single integrated circuit component 1120 is shown in FIG. 11 , multiple integrated circuit components may be coupled to the interposer 1104; indeed, additional interposers may be coupled to the interposer 1104. The interposer 1104 may provide an intervening substrate used to bridge the circuit board 1102 and the integrated circuit component 1120.

[0069] Integrated circuit component 1120 may be a packaged or unpackaged integrated circuit component that includes one or more integrated circuit dies (e.g., die 902 of FIG. 9, integrated circuit 1000 of FIG. 10) and / or one or more other suitable components.

[0070] The unpackaged integrated circuit component 1120 includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 1104. In embodiments in which the integrated circuit component 1120 includes multiple integrated circuit dies, the dies can be of the same type (a homogeneous multi-die integrated circuit component) or two or more different types (a heterogeneous multi-die integrated circuit component). In addition to including one or more processor units, the integrated circuit component 1120 can include additional components such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as the processor unit or on one or more integrated circuit dies separate from the integrated circuit die containing the processor unit. These separate integrated circuit dies can be referred to as "chiplets." In embodiments in which the integrated circuit component includes multiple integrated circuit dies, interconnections between the dies can be provided by a package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate, or a combination thereof. A packaged multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0071] The interposer 1104 may spread connections to a wider pitch or reroute connections to different connections. For example, the interposer 1104 may couple an integrated circuit component 1120 to a set of ball grid array (BGA) conductive contacts of the coupling component 1116 for coupling to the circuit board 1102. In the embodiment shown in FIG. 11 , the integrated circuit component 1120 and the circuit board 1102 are attached to opposite sides of the interposer 1104; in other embodiments, the integrated circuit component 1120 and the circuit board 1102 may be attached to the same side of the interposer 1104. In some embodiments, three or more components may be interconnected using the interposer 1104.

[0072] In some embodiments, the interposer 1104 may be formed as a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the interposer 1104 may be formed of a polymeric material such as epoxy, glass-reinforced epoxy, epoxy with inorganic filler, ceramic material, or polyimide. In some embodiments, the interposer 1104 may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 1104 may include, but is not limited to, metal interconnects 1108 and vias 1110 including through-hole vias 1110-1 (extending from the first surface 1150 of the interposer 1104 to the second surface 1154 of the interposer 1104), blind vias 1110-2 (extending from the first or second surface 1150 or 1154 of the interposer 1104 to an internal metal layer), and buried vias 1110-3 (connecting the internal metal layers).

[0073] In some embodiments, the interposer 1104 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections on a first side of the silicon interposer to an opposing second side of the silicon interposer. In some embodiments, the interposer 1104 including a silicon interposer may further include one or more transfer layers for transferring connections on the first side of the interposer 1104 to the opposing second side of the interposer 1104.

[0074] The interposer 1104 may further include embedded devices 1114, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on the interposer 1104. The package-on-interposer structure 1136 may take the form of any package-on-interposer structure known in the art.

[0075] Integrated circuit assembly 1100 may include an integrated circuit component 1124 coupled to a first surface 1140 of circuit board 1102 by a coupling component 1122. Coupling component 1122 may take the form of any of the embodiments described above with reference to coupling component 1116, and integrated circuit component 1124 may take the form of any of the embodiments described above with reference to integrated circuit component 1120.

[0076] 11 includes a package-on-package structure 1134 coupled to a second surface 1142 of a circuit board 1102 by a coupling component 1128. The package-on-package structure 1134 may include an integrated circuit component 1126 and an integrated circuit component 1132 coupled together by a coupling component 1130 such that the integrated circuit component 1126 is disposed between the circuit board 1102 and the integrated circuit component 1132. The coupling components 1128 and 1130 may take the form of any of the embodiments of the coupling component 1116 described above, and the integrated circuit components 1126 and 1132 may take the form of any of the embodiments of the integrated circuit component 1120 described above. The package-on-package structure 1134 may be configured according to any of the package-on-package structures known in the art.

[0077] FIG. 12 is a block diagram of an exemplary electrical device 1200 that may include one or more of the embodiments disclosed herein. For example, any suitable components of electrical device 1200 may include microelectronic assembly 1100, integrated circuit component 1120, integrated circuit 1000, integrated circuit die 902, or one or more of the structures disclosed herein. While numerous components are shown in FIG. 12 as being included in electrical device 1200, any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in electrical device 1200 may be mounted on one or more motherboards, mainboards, printed circuit boards, or system boards. In some embodiments, one or more of these components are fabricated on a single system-on-a-chip (SoC) die. In various embodiments, electrical device 3000 is enclosed by or integrated with a housing.

[0078] 12, but electrical device 1200 may include interface circuitry for coupling to one or more components. For example, electrical device 1200 may not include display device 1206, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 1206 may be coupled. In another set of examples, electrical device 1200 may not include audio input device 1224 or audio output device 1208, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which audio input device 1224 or audio output device 1208 may be coupled.

[0079] Electrical device 1200 may include one or more processor units 1202 (e.g., one or more processor units). As used herein, the terms “processor unit,” “processing unit,” or “processor” may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1202 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptoprocessors (specialized processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. As such, the processor unit may be referred to as an XPU (or xPU).

[0080] The electrical device 1200 may include memory 1204, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), static random-access memory (SRAM), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change voltage-free memory), solid-state memory, and / or a hard drive. In some embodiments, the memory 1204 may include memory located on the same integrated circuit die as the processor unit 1202. This memory may be used as cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), Last Level Cache (LLC)), and may include embedded dynamic random-access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).

[0081] In some embodiments, electrical device 1200 may include one or more processor units 1202 that are heterogeneous or asymmetric relative to other processor units 1202 in electrical device 1200. There may be various differences between processor units 1202 in a system in terms of a spectrum of metrics of merit, including architectural, microarchitectural, thermal, power consumption characteristics, etc. These differences may effectively manifest themselves as asymmetries and heterogeneities among processor units 1202 in electrical device 1200.

[0082] In some embodiments, electrical device 1200 may include a communications component 1212 (e.g., one or more communications components). For example, communications component 1212 may manage wireless communications to transfer data to and from electrical device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data using modulated electromagnetic radiation over a non-solid medium. The term "wireless" does not imply that the associated device does not include any wiring, although this may not be the case in some embodiments.

[0083] Communications component 1212 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), the IEEE 802.16 standard (e.g., the IEEE 802.16-2005 amendment), any amendments, updates, and / or revisions (e.g., Institute for Electrical and Electronic Engineers (IEEE) standards including the Long-Term Evolution (LTE) project with the Advanced LTE project, the Ultra-Mobile Broadband (UMB) project (also referred to as "3GPP2"), etc.). Broadband Wireless Access (BWA) networks compatible with IEEE 802.16 are commonly referred to as WiMAX networks. The acronym stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed IEEE 802.16 standard compliance and interoperability testing. Communications component 1212 may operate in accordance with a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.Communications component 1212 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communications component 1212 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. Communications component 1212 may operate in accordance with other wireless protocols in other embodiments. Electrical device 1200 may include an antenna 1222 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0084] In some embodiments, the communication component 1212 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., the IEEE 802.3 Ethernet standard). As described above, the communication component 1212 may include multiple communication components. For example, a first communication component 1212 may be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication component 1212 may be dedicated to longer-range wireless communications, such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication component 1212 may be dedicated to wireless communications, and the second communication component 1212 may be dedicated to wired communications.

[0085] Electrical device 1200 may include battery / power circuitry 1214. Battery / power circuitry 1214 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of electrical device 1200 to an energy source (e.g., AC line power) separate from electrical device 1200.

[0086] Electrical device 1200 may include a display device 1206 (or corresponding interface circuitry, as described above), which may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0087] Electrical device 1200 may include audio output device 1208 (or corresponding interface circuitry, as described above), which may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, headset, or earbud.

[0088] Electrical device 1200 may include audio input device 1224 (or corresponding interface circuitry, as described above). Audio input device 1224 may include any embedded or wired or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a musical instrument digital interface (MIDI) output). Electrical device 1200 may include a Global Navigation Satellite System (GNSS) device 1218 (or corresponding interface circuitry, as described above), such as a Global Positioning System (GPS) device. GNSS device 1218 may be in communication with a satellite-based system and may determine the geolocation of electrical device 1200 based on information received from one or more GNSS satellites, as is known in the art.

[0089] Electrical device 1200 may include another output device(s) 1210 (or corresponding interface circuitry, as described above). Examples of other output devices 1210 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0090] The electrical device 1200 may include other input devices 1220 (or corresponding interface circuitry, as described above). Examples of other input devices 1220 may include an accelerometer, a gyroscope, a compass, an imaging device (e.g., a monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, a proximity sensor, a microphone, a barcode reader, a Quick Response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmogram) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0091] Electrical device 1200 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray, or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, a smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system that is part of a vehicle, a smart consumer electronics appliance, a consumer electronics product or device, or manufacturing equipment). In some embodiments, electrical device 1200 may be any other electronic device that processes data. In some embodiments, electrical device 1200 may include multiple discrete physical components. Given the range of devices that electrical device 1200 may appear as in various embodiments, in some embodiments electrical device 1200 may be referred to as a computing device or a computing system.

[0092] While at least one embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist. It should also be understood that the disclosed embodiments are merely examples, and are not intended to limit the scope, applicability, or configuration of the present disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing embodiments of the disclosed embodiments. Various changes may be made in the function and arrangement of elements without departing from the scope of the present disclosure, as set forth in the appended claims and their legal equivalents.

[0093] As used herein, the term "electronic component" may refer to an active electronic circuit (e.g., a processing unit, a memory, a storage device, a FET) or a passive electronic circuit (e.g., a resistor, an inductor, a capacitor).

[0094] As used herein, the term "integrated circuit component" may refer to an electronic component constructed in semiconductor material to perform a function. An integrated circuit (IC) component may include one or more of any computing system components described or mentioned herein or any other computing system component, such as a processor unit (e.g., a system-on-chip (SoC) processor core, a graphics processor unit (GPU), an accelerator, a chipset processor), an I / O controller, a memory, or a network interface controller, and may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0095] A non-limiting example of an unpackaged integrated circuit component includes a single monolithic integrated circuit die; the die may include solder bumps attached to contacts on the die. When present on the die, the solder bumps or other conductive contacts may allow the die to be directly attached to a printed circuit board (PCB) or other substrate.

[0096] A non-limiting example of a packaged integrated circuit component includes one or more integrated circuit dies mounted on a package substrate, with the integrated circuit dies and package substrate encapsulated in a casing material such as metal, plastic, glass, or ceramic. Often the casing includes an integrated heat spreader (IHS); packaged integrated circuit components often have bumps, leads, or pins attached to the package substrate (either directly or by wires attaching the bumps, leads, or pins to the package substrate) for mounting the packaged integrated circuit component to a printed circuit board (or motherboard or base board) or another component.

[0097] As used herein, phrases such as “embodiments,” “various embodiments,” “some embodiments,” and the like indicate that some embodiments may have some, all, or none of the features described for other embodiments. “First,” “second,” “third,” and the like describe a common subject and indicate various instances of the same subject being referenced; unless specifically stated, they do not imply a given sequence, whether temporally or spatially, in ranking order, or in any other manner. In patent application terminology, “connected” refers to elements that are in direct physical or electrical contact with each other, and “coupled” refers to elements that cooperate or interact with each other, and coupled elements may or may not be in direct physical or electrical contact. Furthermore, terms such as “comprising,” “including,” and “having” are used synonymously to indicate a non-exclusive inclusion.

[0098] As used in this application and in the claims, a list of items connected by the terms "at least one of" or "one or more of" can mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" can mean A; B; C; A and B; A and C; B and C; or A, B, and C. Similarly, the phrase "one or more of A, B, and C" can mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0099] As used in this application and in the claims, the phrase "individual of" or "respective of" followed by a list of enumerated or described items as having a characteristic, feature, etc. means that every item in the list has the described or listed characteristic, feature, etc. For example, the phrase "individual of A, B, or C includes a sidewall" or "each of A, B, or C includes a sidewall" means that A includes a sidewall, B includes a sidewall, and C includes a sidewall.

[0100] Any theories of operation, scientific principles, or other theoretical explanations presented herein with reference to the devices or methods of the present disclosure are provided for purposes of better understanding and are not intended to be limiting in scope, and the devices and methods in the appended claims are not limited to those devices and methods that function in the manner described by such theories of operation.

[0101] The following examples relate to additional embodiments of the techniques disclosed herein.

[0102] [example]

[0103] Example 1 is an apparatus comprising: a layer of glass defined by an upper surface and a lower surface; a through hole formed in the layer of glass extending downwardly from the upper surface to the lower surface and having an axis perpendicular to the upper surface; the through hole characterized by a sidewall having a first diameter at the upper surface and the first diameter at the lower surface; a conductive material conformal to the sidewall from the upper surface to the lower surface and defining a cavity therein; an insulating material within the cavity; and a conductive contact at the upper surface extending across the through hole and electrically connected to the conductive material.

[0104] Example 2 includes the subject matter of example 1, wherein the cavity extends from the upper surface to the lower surface and the insulating material is continuous from the upper surface to the lower surface.

[0105] Example 3 includes the subject matter of example 1, wherein the through hole is further characterized by a second diameter between the upper surface and the lower surface, the second diameter being at least 20% smaller than the first diameter.

[0106] Example 4 includes the subject matter of any one of Examples 1 to 3, wherein the conductive material has a cross-sectional area measured perpendicular to the axis, the cross-sectional area varying by less than 10% between the upper surface and the lower surface.

[0107] Example 5 includes the subject matter of any one of Examples 1, 3, or 4, wherein the conductive material has a thickness measured perpendicularly from the sidewall, and the thickness at the upper and lower surfaces is at least 20% less than the thickness at a center point between the upper and lower surfaces.

[0108] Example 6 includes the subject matter of example 5, further comprising a bridge formed by the conductive material between the upper surface and the lower surface.

[0109] Example 7 includes the subject matter of Example 6, wherein the bridge forms a floor in the cavity, creating an additional cavity between the bridge and the lower surface; and further includes the insulating material in the additional cavity.

[0110] Example 8 includes the subject matter of Example 1 or Example 7, further comprising a conductive pad extending across the through hole in the lower surface and electrically connected to the conductive material.

[0111] Example 9 includes the subject matter of any one of Examples 1 to 8, wherein the conductive material comprises a layer of ruthenium, then a layer of copper, then a layer of titanium, followed by a layer of copper.

[0112] Example 10 includes the subject matter of any one of Examples 1 to 8, wherein the conductive material and the conductive contacts comprise copper.

[0113] Example 11 includes the subject matter of any one of Examples 1 to 10, wherein the insulating material is a dielectric material.

[0114] Example 12 is a semiconductor package comprising: a semiconductor substrate having a plurality of dielectric layers and a redistribution layer therein; conductive vias in the semiconductor substrate, the conductive vias electrically connected to the redistribution layer and exposed at a bottom surface of the semiconductor substrate; a layer of glass attached to the bottom surface of the semiconductor substrate, the layer of glass having a plurality of through-glass vias; wherein the through-glass vias include tapered sidewalls conformally plated with a conductive material; in the tapered sidewalls, the conductive material forms respective cavities having an insulating material therein; and conductive contacts on the layer of glass, the conductive contacts extending across the through-glass vias; and wherein the conductive vias are electrically attached to the conductive contacts.

[0115] Example 13 includes the subject matter of Example 12, wherein the conductive material forms a bridge within the through-glass via at the tapered sidewall.

[0116] Example 14 includes the subject matter of Example 12 or Example 13, wherein at the tapered sidewall, the conductive material has a first thickness at the upper surface of the glass layer and a second thickness that is greater than the first thickness at a center point between the upper and lower surfaces of the glass layer.

[0117] Example 15 includes the subject matter of Example 12 or Example 13, wherein the through glass via is formed about an axis orthogonal to a top surface of the layer of glass; wherein, at the tapered sidewall, the conductive material has a cross-sectional area measured perpendicular to the axis; and between the top surface and the bottom surface, the cross-sectional area of ​​the conductive material in the TGV varies by less than 10%.

[0118] Example 16 includes the subject matter of any one of Examples 12 to 15, further comprising: an integrated circuit die attached to the upper surface of the semiconductor substrate; and an electrical path from the integrated circuit die to the lower surface of the layer of glass through a through-glass via of the plurality of through-glass vias.

[0119] Example 17 is a method comprising creating through glass vias (TGVs) in a layer of glass; depositing a liner layer on the layer of glass having the TGVs; depositing a hybrid layer over the liner layer having ruthenium, then copper, then titanium, followed by copper; causing the hybrid layer to form a cavity in the TGV with a bridge therein; laminating a dielectric material over the hybrid layer; and causing the dielectric material to fill at least a portion of the cavity above the bridge in the TGV.

[0120] Example 18 includes the subject matter of Example 17, further comprising: removing the dielectric material to expose the hybrid layer; attaching a conductive plate to the hybrid layer; and etching the conductive plate to create respective conductive contacts for individual TGVs.

[0121] Example 19 includes the subject matter of Example 18, further comprising attaching a first silicon substrate to an upper surface of the layer of glass and a second silicon substrate to a lower surface of the layer of glass.

[0122] Example 20 includes the subject matter of Example 19, further comprising attaching an integrated circuit (IC) die to the first silicon substrate and creating an electrical path from the IC die to conductive contacts on a bottom surface of the second silicon substrate. [Other possible items] [Item 1] a layer of glass defined by an upper surface and a lower surface; a through hole formed in the layer of glass extending downwardly from the upper surface to the lower surface and having an axis perpendicular to the upper surface; the through hole is characterized by a sidewall having a first diameter at the upper surface and the first diameter at the lower surface; a conductive material conformal to the sidewall from the upper surface to the lower surface and defining a cavity therein; an insulating material within the cavity; and a conductive contact extending across the through hole on the top surface and electrically connected to the conductive material; An apparatus comprising: [Item 2] Item 2. The device of item 1, wherein the cavity extends from the upper surface to the lower surface, and the insulating material is continuous from the upper surface to the lower surface. [Item 3] Item 10. The device of item 1, wherein the through hole is further characterized by a second diameter between the upper surface and the lower surface, the second diameter being at least 20% smaller than the first diameter. [Item 4] Item 10. The apparatus of item 1, wherein the conductive material has a cross-sectional area measured perpendicular to the axis, the cross-sectional area varying by less than 10% between the upper surface and the lower surface. [Item 5] Item 10. The device of item 1, wherein the conductive material has a thickness measured perpendicularly from the sidewalls, the thickness at the upper and lower surfaces being at least 20% less than the thickness at a center point between the upper and lower surfaces. [Item 6] Item 10. The device of item 1, further comprising a bridge formed by the conductive material between the upper surface and the lower surface. [Item 7] the bridge forms a floor in the cavity, creating an additional cavity between the bridge and the lower surface; 7. The device of claim 6, further comprising the insulating material in the additional cavity. [Item 8] Item 8. The device of item 7, further comprising a conductive pad extending across the through hole in the lower surface and electrically connected to the conductive material. [Item 9] Item 10. The device of item 1, wherein the conductive material comprises a layer of ruthenium, then a layer of copper, then a layer of titanium, followed by a layer of copper. [Item 10] Item 1 . The device of item 1 , wherein the conductive material and the conductive contacts comprise copper. [Item 11] Item 1, wherein the insulating material is a dielectric material. [Item 12] a semiconductor substrate having a plurality of dielectric layers and a redistribution layer therein; a conductive via in the semiconductor substrate, the conductive via being electrically connected to a redistribution layer and exposed at a bottom surface of the semiconductor substrate; a layer of glass attached to the bottom surface of the semiconductor substrate, the layer of glass having a plurality of through-glass vias; wherein the through glass via includes tapered sidewalls conformally plated with a conductive material; At the tapered sidewalls, the conductive material forms respective cavities having insulating material therein; and a conductive contact on the layer of glass, the conductive contact extending across a through-glass via; wherein the conductive vias are electrically attached to the conductive contacts. A semiconductor package comprising: [Item 13] Item 13. The semiconductor package of item 12, wherein the conductive material forms a bridge within the through-glass via at the tapered sidewall. [Item 14] Item 13. The semiconductor package of item 12, wherein the conductive material in the tapered sidewall has a first thickness at the top surface of the glass layer and a second thickness greater than the first thickness at a center point between the top and bottom surfaces of the glass layer. [Item 15] The through glass via is formed about an axis perpendicular to a top surface of the layer of glass; wherein at said tapered sidewall, said conductive material has a cross-sectional area measured perpendicular to said axis; Item 13. The semiconductor package of item 12, wherein the cross-sectional area of ​​the conductive material in the TGV varies by less than 10% between the upper surface and the lower surface. [Item 16] an integrated circuit die attached to a top surface of the semiconductor substrate; and an electrical path from the integrated circuit die to the underside of the layer of glass through a through-glass via of the plurality of through-glass vias; Item 13. The semiconductor package of item 12, further comprising: [Item 17] creating through glass vias (TGVs) in the layer of glass; depositing a liner layer on the layer of glass having the TGVs; depositing a hybrid layer over the liner layer having ruthenium, then copper, then titanium, followed by copper; causing the hybrid layer to form cavities in the TGV with bridges therein; laminating a dielectric material onto the hybrid layer; and allowing the dielectric material to fill at least a portion of the cavity above the bridge in the TGV. A method for providing the above. [Item 18] removing the dielectric material to expose the hybrid layer; attaching a conductive plate to the hybrid layer; and etching the conductive plate to create respective conductive contacts for each individual TGV; Item 18. The method of item 17, further comprising: [Item 19] Item 19. The method of item 18, further comprising attaching a first silicon substrate to an upper surface of the layer of glass and a second silicon substrate to a lower surface of the layer of glass. [Item 20] 20. The method of claim 19, further comprising attaching an integrated circuit (IC) die to the first silicon substrate and creating an electrical path from the IC die to conductive contacts on the underside of the second silicon substrate.

Claims

1. a layer of glass defined by an upper surface and a lower surface; a through hole formed in the layer of glass extending downwardly from the upper surface to the lower surface and having an axis perpendicular to the upper surface; the through hole is characterized by a sidewall having a first diameter at the upper surface and the first diameter at the lower surface; a conductive material conforming to the sidewall from the upper surface to the lower surface and defining a cavity therein; an insulating material within the cavity; and a conductive contact extending across the through hole on the top surface and electrically connected to the conductive material; An apparatus comprising:

2. The device of claim 1 , wherein the cavity extends from the upper surface to the lower surface, and the insulating material is continuous from the upper surface to the lower surface.

3. 10. The device of claim 1, wherein the through hole is further characterized by a second diameter between the upper surface and the lower surface, the second diameter being at least 20% smaller than the first diameter.

4. 4. The apparatus of claim 1, wherein the conductive material has a cross-sectional area measured perpendicular to the axis, the cross-sectional area varying by less than 10% between the upper and lower surfaces.

5. 4. The device of claim 1, wherein the conductive material has a thickness measured perpendicularly from the sidewalls, the thickness at the upper and lower surfaces being at least 20% less than the thickness at a midpoint between the upper and lower surfaces.

6. 5. The device of claim 4, wherein the conductive material has a thickness measured perpendicularly from the sidewalls, the thickness at the upper and lower surfaces being at least 20% less than the thickness at a center point between the upper and lower surfaces.

7. The device of claim 1 , further comprising a bridge formed by the conductive material between the upper surface and the lower surface.

8. the bridge forms a floor in the cavity, creating an additional cavity between the bridge and the lower surface; The apparatus of claim 7 further comprising the insulating material in the additional cavity.

9. The apparatus of claim 1 , further comprising a conductive pad extending across the through hole in the lower surface and electrically connected to the conductive material.

10. The apparatus of claim 8 , further comprising a conductive pad extending across the through hole in the lower surface and electrically connected to the conductive material.

11. 10. The device of claim 1, wherein the conductive material comprises a layer of ruthenium, then a layer of copper, then a layer of titanium, followed by a layer of copper.

12. 9. The device of claim 8, wherein the conductive material comprises a layer of ruthenium, then a layer of copper, then a layer of titanium, followed by a layer of copper.

13. 13. The device of claim 1 or claim 12, wherein the conductive material and the conductive contacts comprise copper.

14. The device of claim 1 , wherein the insulating material is a dielectric material.

15. a semiconductor substrate having a plurality of dielectric layers and a redistribution layer therein; a conductive via in the semiconductor substrate, the conductive via electrically connected to a redistribution layer and exposed at a bottom surface of the semiconductor substrate; a layer of glass attached to the bottom surface of the semiconductor substrate, the layer of glass having a plurality of through-glass vias; wherein the through glass via includes tapered sidewalls that are conformally plated with a conductive material; At the tapered sidewalls, the conductive material forms respective cavities having insulating material therein; and a conductive contact on the layer of glass, the conductive contact extending across a through-glass via; wherein the conductive vias are electrically attached to the conductive contacts. A semiconductor package comprising:

16. 16. The semiconductor package of claim 15, wherein the conductive material forms a bridge within the through-glass via at the tapered sidewall.

17. 16. The semiconductor package of claim 15, wherein the conductive material at the tapered sidewall has a first thickness at the top surface of the glass layer and a second thickness greater than the first thickness at a center point between the top and bottom surfaces of the glass layer.

18. 17. The semiconductor package of claim 16, wherein the conductive material at the tapered sidewalls has a first thickness at the top surface of the glass layer and a second thickness greater than the first thickness at a center point between the top and bottom surfaces of the glass layer.

19. the through glass via is formed about an axis perpendicular to a top surface of the layer of glass; wherein at said tapered sidewall, said conductive material has a cross-sectional area measured perpendicular to said axis; 16. The semiconductor package of claim 15, wherein the cross-sectional area of ​​the conductive material in the TGV varies by less than 10% between the top surface and the bottom surface.

20. an integrated circuit die attached to a top surface of the semiconductor substrate; and an electrical path from the integrated circuit die to the underside of the layer of glass through a through-glass via of the plurality of through-glass vias; The semiconductor package of claim 15 further comprising:

21. an integrated circuit die attached to a top surface of the semiconductor substrate; and an electrical path from the integrated circuit die to the underside of the layer of glass through a through-glass via of the plurality of through-glass vias; 20. The semiconductor package of claim 19, further comprising:

22. creating a through glass via (TGV) in the layer of glass; depositing a liner layer over the layer of glass having the TGV; depositing a hybrid layer over the liner layer comprising ruthenium, then copper, then titanium, followed by copper; causing the hybrid layer to form cavities in the TGV with bridges therein; laminating a dielectric material onto the hybrid layer; and allowing the dielectric material to fill at least a portion of the cavity above the bridge in the TGV. A method for providing the above.

23. removing the dielectric material to expose the hybrid layer; attaching a conductive plate to the hybrid layer; and etching the conductive plate to create respective conductive contacts for each TGV; 23. The method of claim 22, further comprising:

24. 24. The method of claim 23, further comprising attaching a first silicon substrate to an upper surface of the layer of glass and a second silicon substrate to a lower surface of the layer of glass.

25. 25. The method of claim 24, further comprising attaching an integrated circuit (IC) die to the first silicon substrate and creating an electrical path from the IC die to conductive contacts on a bottom surface of the second silicon substrate.

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