Lamination semiconductor package

Abstract

To provide a lamination semiconductor package capable of addressing a security attack in the case where a multi-chip mounting for mounting a plurality of IC chips to a substrate is performed.SOLUTION: Function chips 2 and 3 are mounted to a security chip 1 providing an embedded wiring conductor to a first surface. The security chip 1 is flipping-mounted to a resin interposer 4. In addition, the resin interposer to which the function ship 2, the function chip 3, and the security chip 1 are mounted is mounted to a print substrate.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a stacked semiconductor package that can deal with security attacks when multi-chip mounting is performed in which multiple IC chips are mounted on a substrate. [Background technology]

[0002] Conventionally, multi-chip packaging has been known, in which multiple IC (Integrated Circuit) chips are packaged in one package. In such multi-chip packaging, the electrical signal wiring connecting the IC chips and the power supply wiring supplying power to the IC chips are sometimes exposed to the outside of the IC chip. This may make external attacks possible on connection paths such as security chips.

[0003] For this reason, conventional techniques are known to prevent attacks on such security chips, etc. For example, Patent Document 1 discloses a technique for a back-surface buried wiring structure that prevents security attacks such as noise monitoring and fault injection via the back-surface semiconductor substrate of an IC chip, and detects physical attacks from the back side, i.e., exposure attacks. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-110293 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the technology disclosed in Patent Document 1 has a problem in that the backside of the IC chip is exposed when flip-chip mounting is performed, which mounts the electronic circuit side of the IC chip on a wiring board. This may result in the device being unable to cope with sophisticated attacks, such as a bypass attack that creates a bypass circuit for the wiring on the backside, or an attack that involves approaching a probe to the side.

[0006] The present invention has been made to solve the problems (issues) associated with the above-mentioned conventional technology, and aims to provide a stacked semiconductor package that can deal with security attacks when performing multi-chip mounting in which multiple IC chips are mounted on a substrate. [Means for solving the problem]

[0007] In order to solve the above-mentioned problems and achieve the object, the present invention is characterized by comprising: a first semiconductor substrate having a first surface on which a predetermined electronic circuit is formed, and a second surface opposite to the first surface on which a plurality of first IO pad conductors formed by predetermined embedded wiring conductors are formed; a second semiconductor substrate having an electronic circuit surface on which a predetermined electronic circuit is formed, and a plurality of second IO pad conductors formed by predetermined surface wiring conductors are bonded to the second surface; and a circuit board having the second IO pad conductors formed on a third surface bonded to the second surface of the first semiconductor substrate, and the second IO pad conductors formed on a fourth surface bonded to a predetermined printed circuit board. [Effects of the Invention]

[0008] According to the present invention, it is possible to deal with security attacks when multi-chip mounting is performed in which a plurality of IC chips are mounted on a substrate. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a perspective view showing the configuration of a stacked semiconductor package according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view of the stacked semiconductor package taken along line AA in FIG. [Figure 3] FIG. 3 is a diagram showing a first surface of the functional chip shown in FIG. [Figure 4] FIG. 4 is a diagram showing the first and second faces of the security chip shown in FIG. [Figure 5] FIG. 5 is an explanatory diagram illustrating Cu-Cu bonding used to join the functional chips 2 and 3 and the security chip 1 shown in FIG. [Figure 6] FIG. 6 is a cross-sectional view showing the configuration of a stacked semiconductor package according to the second embodiment. [Figure 7] FIG. 7 is a diagram showing an example of a method for manufacturing a semiconductor chip having embedded wiring conductors. DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, various embodiments of the stacked semiconductor package according to the present invention will be described in detail with reference to the accompanying drawings.

[0011] [Embodiment 1] First, an outline of the stacked semiconductor package according to the present embodiment 1 will be described. In the present embodiment 1, a stacked semiconductor package that can deal with security attacks by mounting a functional chip 2 and a functional chip 3 on an IO pad conductor arranged on the back side of the surface on which the electronic circuit of the security chip 1 is formed will be described.

[0012] <Overview of stacked semiconductor packages> Fig. 1 is a perspective view showing the configuration of a stacked semiconductor package according to embodiment 1. The stacked semiconductor package shown in Fig. 1 includes a security chip 1, functional chips 2 and 3, a resin interposer 4, a printed circuit board 5, and wiring conductors 6. The security chip 1, functional chips 2 and 3, and resin interposer 4 each have two surfaces parallel to the XY plane of Fig. 1.

[0013] The security chip 1 has an IO pad conductor 15a (not shown) formed by an embedded wiring conductor 11a on a first surface of a semiconductor substrate, and an electronic circuit formed on a second surface opposite to the first surface. The embedded wiring conductor 11a will be described later. The functional chips 2 and 3 are IC chips that realize certain functions with electronic circuits.

[0014] The functional chips 2 and 3 are flip-chip mounted on the first surface of the security chip 1 via a plurality of IO pad conductors 15c (not shown) formed by surface wiring conductors on the electronic circuit surfaces 14 of the functional chips 2 and 3. Such flip-chip mounting is a mounting technique in which bare chips, which are obtained by cutting a semiconductor into chips, are flipped (inverted) and mounted.

[0015] The resin interposer 4 is a substrate used to expand the spacing of the multiple IO pad conductors arranged at fine intervals on the IC chip to a spacing that allows them to be mounted on a printed circuit board. The printed circuit board 5 is a substrate made of resin or ceramic, and is used to connect multiple semiconductor packages and apply power supply voltage from an external source. The wiring conductors 6 are wiring that supplies power supply voltage to the IC chip and transmits signals.

[0016] The security chip 1, on which the functional chips 2 and 3 are flip-chip mounted, is flip-chip mounted on a resin interposer 4. The resin interposer 4, on which the functional chips 2, 3 and security chip 1 are flip-chip mounted, is then mounted on a printed circuit board 5.

[0017] <Stacked semiconductor package configuration> Next, a description will be given of the configuration of the stacked semiconductor package according to the present embodiment 1. Fig. 2 is a cross-sectional view of the stacked semiconductor package taken along line AA in Fig. 1. As shown in Fig. 2, the stacked semiconductor package includes a security chip 1, a functional chip 2, a functional chip 3, a resin interposer 4, and a printed circuit board 5.

[0018] The security chip 1 has an IO pad conductor 15b (not shown) formed by embedded wiring conductors 11a on a first surface of the semiconductor substrate, and a plurality of IO pad conductors 15a formed by electronic circuits and surface wiring conductors on a second surface (electronic circuit surface 14) that is the reverse side of the first surface. The embedded wiring conductors 11a are formed by digging grooves in the security chip 1 by etching and embedding metal in the grooves to form wiring, and are connected to the electronic circuit on the first surface through at least one via conductor 11b.

[0019] Furthermore, a passive circuit may be formed by embedded wiring conductors 11a on the first surface of the security chip 1. The electronic circuit formed on the second surface of the security chip 1 is a circuit that can be formed by CMOS process technology or other process technology, and includes multiple circuit elements such as transistors, diodes, capacitors, resistors, and inductors. The electronic circuit of the security chip 1 includes, for example, a secure processor, a cryptographic accelerator, and a random number generation circuit to encrypt signals flowing on a data bus within the package.

[0020] The functional chips 2 and 3 have a plurality of IO pad conductors 15c formed by electronic circuits and surface wiring conductors on the electronic circuit surface 14 of the semiconductor substrate. The functional chips 2 and 3 have, for example, an application processor and memory, an AI processor and sensors, etc. formed as electronic circuits.

[0021] The resin interposer 4 has a plurality of IO pad conductors 15d formed by surface wiring conductors on a third surface to which the second surface of the security chip 1 is joined, and a plurality of IO pad conductors 15e formed by surface wiring conductors on a fourth surface to which the printed circuit board 5 is joined. The printed circuit board 5 has a plurality of IO pad conductors 15f formed by surface wiring conductors on the surface on which the resin interposer 4 is mounted.

[0022] The functional chips 2 and 3 are flip-chip mounted using Cu-Cu bonding so that a plurality of IO pad conductors 15c formed by surface wiring conductors on the electronic circuit surfaces 14 of the functional chips 2 and 3 are electrically connected to a plurality of IO pad conductors 15b (not shown) formed by embedded wiring conductors 11a on the first surface of the security chip 1. Cu-Cu bonding will be described later.

[0023] The security chip 1 on which the functional chips 2 and 3 are flip-chip mounted is flip-chip mounted using solder bumps 12a so that a plurality of IO pad conductors 15a formed by surface wiring conductors on the second surface of the security chip 1 are electrically connected to a plurality of IO pad conductors 15d formed by surface wiring conductors on the resin interposer 4. Note that the resin interposer 4 has already been described, so a detailed description thereof will be omitted here.

[0024] The resin interposer 4 on which the functional chip 2, the functional chip 3, and the security chip 1 are mounted is mounted on the printed circuit board 5 using solder bumps 12b so that a plurality of IO pad conductors 15e formed by surface wiring conductors on the resin interposer 4 are electrically connected to a plurality of IO pad conductors 15f formed by surface wiring conductors on the printed circuit board 5, thereby forming a stacked semiconductor package. Note that the printed circuit board 5 has already been described, so a detailed description thereof will be omitted here.

[0025] <Example of functional circuit on functional chip> Next, examples of functional circuits of the functional chips 2 and 3 will be described. Fig. 3 is a diagram showing the electronic circuit surface of the functional chip shown in Fig. 2. As shown in Fig. 3(a), the functional chip 2 includes an application processor 21, a memory 22, a secure data bus 23, and a plurality of IO pad conductors 15c formed by surface wiring conductors. The application processor 21 is equipped with functions such as a CPU core, media processing, system management, power management, and memory control.

[0026] The memory 22 stores an operating system, application programs, etc. for operating the application processor 21. The secure data bus 23 is a data bus for transmitting and receiving data, etc., to and from the functional chip 3 and security chip 1, and encrypted data is transmitted and received to ensure security. The IO pad conductor 15c is a pad conductor for applying a power supply voltage to the functional chip 2 from the outside and a pad conductor for inputting and outputting data to and from the secure data bus.

[0027] 3(b), the functional chip 3 includes an AI processor 24, a sensor 25, a secure data bus 23, and a plurality of IO pad conductors 15c formed by surface wiring conductors. The AI ​​processor 24 is a processor having a CNN (Convolutional Neural Network) inference function used in image recognition, for example. The sensor 25 has a sensor function of collecting data to be input to the AI ​​processor 24. The secure data bus 23 and the IO pad conductors 15c have already been described, so a detailed description thereof will be omitted here.

[0028] <Example of security chip functional circuit> Next, an example of a functional circuit of the security chip 1 will be described. Fig. 4 is a diagram showing the first and second surfaces of the security chip 1 shown in Fig. 2. As shown in Fig. 4(a), the first surface of the security chip 1 has a plurality of IO pad conductors 15b formed by embedded wiring conductors 11a for mounting the functional chips 2 and 3. Note that a passive circuit such as meander wiring may be formed on the first surface of the security chip 1 by the embedded wiring conductors 11a.

[0029] As shown in FIG. 4(b), the second surface of the security chip 1 includes an attack detection circuit 26, a cryptographic accelerator 27, a secure processor and memory 28, a random number generation circuit 29, a clock generation circuit 30, a power supply circuit 31, power supply wiring 32, ground wiring 33, a secure data bus 23, and a plurality of IO pad conductors 15a formed by surface wiring conductors.

[0030] The attack detection circuit 26 is a circuit for detecting attacks such as internal signal reading by approaching a probe from outside the IC chip. The cryptographic accelerator 27 is a circuit dedicated to encryption and decryption processes, which require heavy processing. The secure processor and memory 28 is a processor that controls the entire security chip 1, which performs encryption and decryption, and has programs stored in its memory.

[0031] The random number generation circuit 29 is a circuit that generates random numbers necessary for encryption and decryption. The clock generation circuit 30 is a circuit that generates a clock for operating the digital circuits inside the security chip 1. The power supply circuit 31 is a circuit that supplies power to the digital circuits inside the security chip 1, and supplies power to each digital circuit through the power supply wiring 32 and the ground wiring 33. The IO pad conductor 15a is a pad conductor for applying an external power supply voltage to the security chip 1 and a pad conductor for inputting and outputting data of the secure data bus. Regarding the secure data bus 23, since it has already been described, a detailed description thereof is omitted here.

[0032] <Cu-Cu bonding> Next, the Cu-Cu bonding used when implementing the security chip 1, the functional chip 2, and the functional chip 3 will be described. FIG. 5 is an explanatory diagram for explaining the Cu-Cu bonding used for the connection between the functional chips 2 and 3 shown in FIG. 2 and the security chip 1. As shown in FIG. 5, the IO pad conductor 15c is formed on the electronic circuit surface 14 of the functional chip 3 and is connected to the electronic circuit. Also, the embedded wiring conductor 11a is formed on the first surface of the security chip 1 and is connected to the electronic circuit formed on the second surface (electronic circuit surface 14) of the security chip 1 via at least one via conductor 11b.

[0033] The plurality of IO pad conductors 15c and the embedded wiring conductors 11a are formed of Cu (copper) as the material, and bonding at room temperature is possible by using surface-activated bonding between Cu and Cu. In the Cu-Cu bonding using surface-activated bonding, since the liquid phase is not used, it is advantageous for narrowing the pitch of the IO pad conductors.

[0034] As described above, in this embodiment 1, functional chips 2 and 3 are flip-chip mounted on security chip 1 having embedded wiring conductors on its first surface, and security chip 1 is flip-chip mounted on resin interposer 4. Furthermore, the resin interposer on which functional chip 2, functional chip 3 and security chip 1 are mounted is mounted on a printed circuit board. Therefore, the wiring conductors for power supply and signal transmission are not exposed, making it possible to deal with external security attacks.

[0035] [Embodiment 2] However, the above-described first embodiment cannot prevent side channel attacks on the security chip 1. Therefore, the second embodiment describes a stacked semiconductor package having a structure in which the security chip is mounted on the second surface, which is the back surface of the electronic circuit surface 14 on which the electronic circuit of the functional chip having embedded wiring conductors is formed, thereby concealing the security chip on the second surface of the functional chip.

[0036] The structure of the stacked semiconductor package according to embodiment 2 will be described. Fig. 6 is a cross-sectional view showing the configuration of the stacked semiconductor package according to embodiment 2. As shown in Fig. 6, the stacked semiconductor package includes a functional chip 7, a security chip 8, a resin interposer 4, and a printed circuit board 5.

[0037] The functional chip 7 has an electronic circuit formed on a first surface (electronic circuit surface 14) of the semiconductor substrate, and a plurality of IO pad conductors 15g formed by embedded wiring conductors 11a on a second surface, which is the first backside surface. The embedded wiring conductor 11a is connected to the electronic circuit on the first surface through at least one via conductor 11b. The security chip 8 has an electronic circuit formed on the electronic circuit surface 14 of the semiconductor substrate, and a plurality of IO pad conductors 15h (not shown) are formed on the electronic circuit surface 14 by surface wiring conductors. As with the security chip 1, the electronic circuit of the security chip 8 includes, for example, a secure processor, a cryptographic accelerator, a random number generation circuit, and the like.

[0038] The security chip 8 is mounted by Cu-Cu bonding so that some of the multiple IO pad conductors 15g formed by embedded wiring conductors 11a on the second surface of the functional chip 7 are electrically connected to multiple IO pad conductors 15h (not shown) formed by surface wiring conductors on the electronic circuit surface 14 of the security chip 8.

[0039] The functional chip 7 on which the security chip 8 is mounted is mounted by solder bumps 12a so that some of the multiple IO pad conductors 15g formed by embedded wiring conductors 11a on the second surface of the functional chip 7 are electrically connected to multiple IO pad conductors 15d formed by surface wiring conductors on the resin interposer 4. Furthermore, the resin interposer 4 is mounted on the printed circuit board 5 by solder bumps 12b so that multiple IO pad conductors 15e formed by surface wiring conductors on the resin interposer 4 are electrically connected to multiple IO pad conductors 15f formed by surface wiring conductors on the printed circuit board 5.

[0040] <Manufacture of semiconductor chips with buried wiring conductors> Next, a method for inexpensively manufacturing semiconductor chips having embedded wiring conductors 11a for the security chip 1 and the functional chip 7 will be briefly described. FIG. 7 is a diagram showing an example of a method for manufacturing a semiconductor chip having embedded wiring conductors. As shown in FIG. 7(a), grooves are formed in a first semiconductor substrate 9a by etching, and metal is embedded in the grooves to form embedded wiring conductors 11a. Then, as shown in FIG. 7(b), an electronic circuit is formed on a first surface of a second semiconductor substrate 9b, and holes are formed from a second surface of the second semiconductor substrate 9b by etching, and metal is embedded in the holes to form via conductors 11b.

[0041] Then, as shown in Figure 7(c), the first semiconductor substrate 9a and the second semiconductor substrate 9b are bonded together so that the embedded wiring conductor 11a formed in the first semiconductor substrate 9a and the via conductor 11b formed on the second surface of the second semiconductor substrate 9b are electrically connected.

[0042] Then, as shown in FIG. 7(d), the semiconductor substrate on the surface of the first semiconductor substrate 9a on which the embedded wiring conductors 11a are not formed is etched to expose the embedded wiring conductors 11a, thereby manufacturing a semiconductor chip 10 having the embedded wiring conductors.

[0043] By manufacturing the semiconductor chip in this manner, the semiconductor chip 10 having the embedded wiring conductors 11a can be manufactured inexpensively.

[0044] As described above, in this embodiment 2, a security chip 8 that realizes security-related functions by electronic circuits is mounted on the first surface of the semiconductor substrate using Cu-Cu bonding on the second surface of a functional chip 7 that has an electronic circuit formed on the first surface of the semiconductor substrate and an IO pad conductor 15g using embedded wiring conductor 11a formed on the second surface, and the functional chip 7 is mounted on the resin interposer 4 using solder bumps 12a, and the resin interposer 4 is further mounted on the printed circuit board 5 using other solder bumps 12b.Therefore, security attacks can be countered by concealing the security chip 8 on the back surface of the functional chip 7.

[0045] The configurations illustrated in the above embodiments are merely functional schematics and are not necessarily physically configured as shown. In other words, the distribution and integration of each device is not limited to that illustrated, and all or part of the devices can be functionally or physically distributed and integrated in any unit depending on various loads, usage conditions, etc. [Industrial Applicability]

[0046] The stacked semiconductor package according to the present invention is suitable for dealing with security attacks when multi-chip mounting is performed in which a plurality of IC chips are mounted on a substrate. [Explanation of symbols]

[0047] 1, 8 Security Chip 2, 3, 7 Functional Chips 4 Resin interposer 5 Printed circuit board 6 Wiring conductor 9a, 9b semiconductor substrate 10 Semiconductor chip with buried wiring conductors 11a Buried wiring conductor 11b Via conductor 12a, 12b Solder bumps 14 Electronic circuit side 15a, 15b, 15c, 15d IO pad conductors 15e, 15f, 15g, 15h IO pad conductors 21 Application Processors 22 Memory 23 Secure Data Bus 24 AI processors 25 sensors 26 Attack detection circuit 27 Cryptographic Accelerators 28 Secure Processor & Memory 29 Random Number Generator 30 Clock generation circuit 31 Power supply circuit 32 Power wiring 33 Ground wiring

Claims

[Claim 1] a first semiconductor substrate having a first surface on which a predetermined electronic circuit is formed, and a plurality of first IO pad conductors formed by predetermined buried wiring conductors on a second surface that is the reverse side of the first surface; a second semiconductor substrate having an electronic circuit surface on which a predetermined electronic circuit is formed, and bonding a plurality of second IO pad conductors formed by predetermined surface wiring conductors to the second surface; a circuit board in which the second IO pad conductor is formed on a third surface to be joined to the second surface of the first semiconductor substrate, and the second IO pad conductor is formed on a fourth surface to be joined to a predetermined printed circuit board; 1. A stacked semiconductor package comprising:

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