Integrated circuit package comprising interposer with glass layer and embedded die

Abstract

To bond multiple dies together at a fine pitch required to achieve a desired interconnect density.SOLUTION: A microelectronic assembly 100 includes: a first layer having dies 114-1 and 114-2 surrounded by an insulating material 133; a second layer on the first layer having conductive paths 196 through a dielectric material, the conductive paths 196 including a conductive trace and a conductive via having an inverted-trapezoid shape; and a third layer on the second layer having a glass layer and a conductive through-glass via (TGV 110), wherein the conductive TGV 110 is electrically coupled to the conductive paths 196, and the dies 114-1 and 114-2 are electrically coupled to the conductive TGV 110 by the conductive paths 196.SELECTED DRAWING: Figure 1A

Description

[Background technology]

[0001] Electronic circuits are commonly called integrated circuits (ICs) when they are fabricated on wafers of semiconductor material such as silicon. Wafers with such ICs are typically cut into many individual dies. These dies, along with other electronic components such as resistors, capacitors, and inductors, may be packaged into IC packages containing one or more dies. IC packages may be integrated onto electronic systems, such as consumer electronic systems. Some ICs have a specific function, such as memory or processing. Some other ICs have multiple functions, such as systems-on-chips (SOCs), in which all or most components of a computer or other electronic system are integrated onto a single monolithic die. [Brief explanation of the drawings]

[0002] The embodiments will be readily understood from the following detailed description in combination with the accompanying drawings, in which like structural elements are designated by like reference numerals to facilitate this description, and in which the embodiments are illustrated by way of example, and not by way of limitation, in the several views of the accompanying drawings.

[0003] [Figure 1A] 1 is a schematic cross-sectional view of an exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 1B] 1 is a schematic cross-sectional view of an exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0004] [Figure 2] 1 is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0005] [Figure 3] 1 is a schematic cross-sectional view of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0006] [Figure 4] 1 is a schematic cross-sectional view of yet another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0007] [Figure 5A] 1B-1D are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 1A according to some embodiments of the present disclosure. [Figure 5B] 1B-1D are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 1A according to some embodiments of the present disclosure. [Figure 5C] 1B-1D are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 1A according to some embodiments of the present disclosure. [Figure 5D] 1B-1D are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 1A according to some embodiments of the present disclosure. [Figure 5E] 1B-1D are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 1A according to some embodiments of the present disclosure. [Figure 5F] 1B-1D are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 1A according to some embodiments of the present disclosure. [Figure 5G] 1B-1D are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 1A according to some embodiments of the present disclosure.

[0008] [Figure 6A] 1C-1D are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 1B according to some embodiments of the present disclosure. [Figure 6B] 1C-1D are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 1B according to some embodiments of the present disclosure. [Figure 6C] 1C-1D are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 1B according to some embodiments of the present disclosure.

[0009] [Figure 7A]3A-3C are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 2 according to some embodiments of the present disclosure. [Figure 7B] 3A-3C are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 2 according to some embodiments of the present disclosure. [Figure 7C] 3A-3C are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 2 according to some embodiments of the present disclosure. [Figure 7D] 3A-3C are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 2 according to some embodiments of the present disclosure.

[0010] [Figure 8A] 4A-4C are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 3 according to some embodiments of the present disclosure. [Figure 8B] 4A-4C are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 3 according to some embodiments of the present disclosure. [Figure 8C] 4A-4C are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 3 according to some embodiments of the present disclosure. [Figure 8D] 4A-4C are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 3 according to some embodiments of the present disclosure.

[0011] [Figure 9A] 5A-5C are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 4 according to some embodiments of the present disclosure. [Figure 9B] 5A-5C are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 4 according to some embodiments of the present disclosure. [Figure 9C] 5A-5C are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 4 according to some embodiments of the present disclosure. [Figure 9D] 5A-5C are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 4 according to some embodiments of the present disclosure. [Figure 9E]5A-5C are simplified cross-sectional views illustrating stages in the manufacture of the exemplary microelectronic assembly of FIG. 4 according to some embodiments of the present disclosure.

[0012] [Figure 10] FIG. 1 is a cross-sectional view of a device package that may include one or more microelectronic assemblies according to any of the embodiments disclosed herein.

[0013] [Figure 11] FIG. 1 is a cross-sectional side view of a device assembly that may include one or more microelectronic assemblies according to any of the embodiments disclosed herein.

[0014] [Figure 12] FIG. 1 is a block diagram of an exemplary computing device that may include one or more microelectronic assemblies according to any of the embodiments disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0015] For purposes of illustrating the IC packages described herein, it is important to understand the phenomena that may be at play during IC assembly and packaging. The following basic information may be considered a foundation upon which the present disclosure may be properly explained. Such information is provided for illustrative purposes only and, therefore, should not be construed as limiting the broad scope of the present disclosure and its potential applications.

[0016] Die partitioning, in which multiple smaller dies are coupled together with high-density interconnects, can achieve smaller form factors and higher yields than using a single monolithic die. The increasing functionality required of semiconductor dies in multi-chip packages and the accompanying need for fine inter-die interconnects in the face of high costs and low manufacturing device yields due to transistor shrinks have led to novel packaging approaches, such as hyperchip stacking (using silicon interposers), silicon bridges (e.g., embedded multi-die interconnect bridges (EMIBs)), and 2.5D / 3D heterogeneous integration. Heterogeneous integration uses packaging techniques in which different chips with different functions are integrated into a package using lateral connections, as in 2.5D packaging architectures, or through-connects, as in 3D packaging architectures. While these designs differ significantly between 2.5D and 3D packaging architectures, both are intended to improve package performance by focusing primarily in two directions: (1) reducing the x,y dimensions (e.g., form factor) of the package, for example, through chip stacking using thinner chips, and (2) increasing input / output (I / O) density for multi-chip integration. However, bonding multiple dies together at the fine pitch required to achieve the desired interconnect density has been limited in conventional approaches.

[0017] One approach to achieving finer pitches involves the incorporation of glass layers. The structures and assemblies disclosed herein may include a glass layer, also referred to herein as a "glass core," with vias extending through the glass core for front-to-back connections. Compared to traditional epoxy cores, glass cores offer several advantages, including higher through-glass via (TGV) density, lower signal loss, and lower total thickness variation (TTV), among others. The glass core may be held within a substrate (e.g., permanently) or temporarily included (e.g., as a removable carrier). The low TTV of less than or equal to 10 microns associated with the glass makes it possible to meet stringent via-pad overlay requirements, such as an average of less than or equal to +4 sigma for fine pitch scaling down to 2 / 2 microns (i.e., 2 micron line width with 2 micron line spacing). The TTV of such glass cores may be approximately 2 microns to 3 microns, enabling suitable 2.5D and 3D packaging architectures. Glass processing techniques known in the art, including laser patterning, can be used to achieve the desired results.

[0018] The glass layer may be held within the substrate and may include cavity structures (e.g., blind cavities and through cavities) for mounting the EMIB. Incorporating through-substrate vias (TSVs) into the EMIB (also referred to as "EMIB-T") allows power to be transferred from the bottom of the cavity through the EMIB, reducing the number of transfer layers required through the substrate and typically improving yield. However, assembling the EMIB into a multi-die IC package remains challenging due to the desire for reduced package size and increased I / O density. Furthermore, if any portion of the substrate is non-functional (e.g., a low-cost, high-risk transfer layer), high-cost components (e.g., the EMIB) are scrapped. Disclosed herein are embodiments in which the high-cost EMIB and IC die are finally assembled after redistribution layer (RDL) formation or disassembled from the package substrate by being assembled into an interposer electrically coupled to the package substrate. Various of the embodiments disclosed herein may help reduce the cost and complexity of assembling multi-die IC packages over conventional approaches and increase the reliability and functionality of these IC packages in use.

[0019] Thus, disclosed herein is a microelectronic assembly that may comprise: a first layer having an insulating material and a die surrounded by the insulating material; a second layer on the first layer, the second layer having a dielectric material and a conductive path through the dielectric material, wherein the conductive path includes a conductive trace and a conductive via having an inverted trapezoid shape; and a third layer on the second layer, the third layer having a glass layer and a conductive through-glass via (TGV), wherein the conductive TGV is electrically coupled to the conductive path, and the die is electrically coupled to the conductive TGV by the conductive path.

[0020] The structures, assemblies, packages, methods, devices, and systems of the present disclosure may each have several innovative aspects, none of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described herein are set forth in the following description and accompanying drawings.

[0021] In the following detailed description, various aspects of exemplary implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.

[0022] The terms "circuit" and "circuitry" mean one or more passive and / or active electrical and / or electronic components arranged to cooperate with each other to provide a desired function. These terms also refer to analog circuits, digital circuits, hardwired circuits, programmable circuits, microcontroller circuits, and / or any other type of physical hardware electrical and / or electronic component.

[0023] The term "integrated circuit" means a circuit integrated into a monolithic semiconductor or similar material.

[0024] In some embodiments, the IC die disclosed herein may include a substantially single-crystalline semiconductor, such as silicon or germanium, as a substrate on which an integrated circuit is fabricated using conventional semiconductor processing methods. The semiconductor substrate may include, for example, an N-type or P-type material. The die may include, for example, a crystalline substrate formed using bulk silicon (or other bulk semiconductor material) or a semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) structure. In some other embodiments, the substrate of one or more of the IC die may include alternative materials that may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-N, III-V, II-VI, or IV materials. In still other embodiments, the substrate may comprise a compound semiconductor having, for example, a first sublattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from Group V of the periodic table (e.g., P, As, Sb). In still other embodiments, the substrate may comprise an intrinsic IV or III-V semiconductor material or alloy that is not intentionally doped with any electrically active impurities; in alternative embodiments, nominal impurity dopant levels may be present. In still other embodiments, the die may comprise an amorphous material such as a polymer; for example, the substrate may comprise a silica-filled epoxy. In other embodiments, the substrate may comprise a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, zinc indium oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide.Generally, the substrate may comprise one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, zinc indium oxide, nickel oxide, niobium oxide, copper peroxide (IGZO), indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten sulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum, gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, magnesium, and the like. Although several examples of materials for the die are described herein, any material or structure that can serve as a foundation (e.g., substrate) upon which the IC circuits and structures described herein can be built is within the spirit and scope of the present disclosure.

[0025] Unless otherwise specified, an IC die described herein includes one or more IC structures (or simply, "ICs") that implement (i.e., are configured to perform) a particular function. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuitry (e.g., ICs that implement one or more of: memory devices, memory arrays, control logic configured to control the memory devices and arrays, etc.). In another such example, the term "computational die" may be used to describe a die that includes one or more ICs that implement logic / computational circuitry (e.g., ICs that implement one or more of: input / output (I / O) functions, arithmetic operations, data pipelines, etc.).

[0026] In another example, the terms "package" and "IC package" are synonymous, as are the terms "die" and "IC die." Note that the terms "chip," "chiplet," "die," and "IC die" are used interchangeably herein.

[0027] The term "optical structure" includes configurations fabricated within an IC to receive, convert, and / or transmit optical signals as described herein, which may include optical conductors such as waveguides, electromagnetic radiation sources such as lasers and light-emitting diodes (LEDs), and electro-optical devices such as photodetectors.

[0028] In various embodiments, any photonic integrated circuit (PIC) described herein may include a semiconductor material, e.g., an N-type or P-type material. The PIC may include a crystalline substrate formed, for example, using bulk silicon (or other bulk semiconductor material) or an SOI structure (or generally, a semiconductor-on-insulator structure). In some embodiments, the PIC may be formed using alternative materials that may or may not be combined with silicon, including, but not limited to, lithium niobate, indium phosphide, silicon dioxide, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride, or gallium antimonide, or other combinations of III-N or IV materials. In some embodiments, the PIC may include an amorphous material, such as a polymer. In some embodiments, the PIC may be formed on a printed circuit board (PCB). In some embodiments, the PIC may be heterogeneous, comprising a carrier material (such as glass or silicon carbide) as a substrate with a thin semiconductor layer overlying an active surface containing transistors and similar components. While several examples of materials for PICs are described herein, any material or structure that can serve as a foundation upon which a PIC may be built is within the spirit and scope of the present disclosure.

[0029] Unless otherwise specified, the term "insulating" means "electrically insulating" and the term "conducting" means "electrically conducting." When referring to optical signals and / or devices, components, and elements that operate on or use optical signals, the term "conducting" can also mean "optically conducting."

[0030] The terms "oxide," "carbide," "nitride," and the like refer to compounds containing oxygen, carbon, nitrogen, and the like, respectively.

[0031] The term "high-k dielectric" refers to a material that has a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material that has a lower dielectric constant than silicon oxide.

[0032] The term "insulating material" refers to a substantially electrically non-conductive solid material (and / or a liquid material that solidifies after processing as described herein). They may include, by way of example and not limitation, organic polymers and plastics, and inorganic materials such as ionic crystals, porcelain, glass, silicon and alumina, or combinations thereof. They may include dielectric materials, highly polarizable materials, and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of the present disclosure. Further examples of insulating materials are materials such as underfills and molds or mold-like materials used in packaging applications, including, for example, materials used in organic interposers, package supports, and other such components.

[0033] In various embodiments, elements associated with an IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, elements associated with an IC may include those monolithically integrated within the IC, mounted on the IC, or connected to the IC. The ICs described herein may be either analog or digital and may be used in multiple applications, such as microprocessors, optoelectronic circuits, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The ICs described herein may be used in a single IC die or as part of a chipset to perform one or more related functions within a computer.

[0034] In various embodiments of the present disclosure, the transistors described herein may be field-effect transistors (FETs), such as metal-oxide-semiconductor (MOS) FETs (MOSFETs). Generally, FETs are three-terminal devices that include source, drain, and gate terminals and use an electric field to control the current flowing through the device. FETs typically include a gate stack that includes a channel material, source and drain regions disposed within and / or above the channel material, and a gate electrode material, alternatively referred to as a "work function" material, disposed above a portion of the channel material between the source and drain regions (the "channel portion"), and optionally a gate dielectric material between the gate electrode material and the channel material.

[0035] In a general sense, an “interconnect” refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components, facilitating the communication of electrical signals therebetween; an optical interconnect provides an optical connection between two optical components, facilitating the communication of optical signals therebetween. As used herein, both electrical and optical interconnects are included in the term “interconnect.” The nature of the interconnects being described should be understood herein with reference to their associated signal media. Thus, when used with reference to an electronic device, such as an IC, that operates using electrical signals, the term “interconnect” describes any element formed of a conductive material that provides electrical connection to one or more elements associated with the IC and / or between various such elements. In such instances, the term “interconnect” can refer to both conductive traces (sometimes also referred to as “lines,” “wires,” “metal lines,” or “trenches”) and conductive vias (sometimes also referred to as “vias” or “metal vias”). In some cases, conductive traces and vias may be referred to as “conductive traces” and “conductive vias,” respectively, to emphasize that these elements include a conductive material, such as a metal. Similarly, when used in reference to a device that also operates with optical signals, such as a PIC, "interconnect" may also describe any element formed of an optically conductive material to provide an optical connection to one or more elements associated with the PIC. In such instances, the term "interconnect" may refer to optical waveguides (e.g., structures that guide and confine light waves), including optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0036] The term "waveguide" refers to any structure that functions to guide the propagation of light from one location to another, typically through a substrate material such as silicon or glass. In various examples, waveguides can be formed from silicon, doped silicon, silicon nitride, glasses such as silica (e.g., silicon dioxide or SiO), and borosilicate (e.g., 70-80 wt% SiO, 7-13 wt% BO, 4-8 wt% NaO or KO, and 2-8 wt% AlO), among others. Waveguides can be formed using a variety of techniques, including, but not limited to, forming the waveguide in situ. For example, in some embodiments, waveguides can be formed in situ in glass using low-temperature glass-to-glass bonding or by laser direct writing. In situ formed waveguides can have low-loss characteristics.

[0037] The term "conductive trace" may be used to describe conductive elements isolated by insulating materials. Within an IC die, such insulating materials include interlayer low-k dielectrics disposed within the IC die. Within package substrates and printed circuit boards (PCBs), such insulating materials include organic materials such as Ajinomoto Build-Up Film (ABF), polyimide, or epoxy resin. Such conductive lines are typically arranged in several levels or layers of a metallization stack.

[0038] The term "conductive via" may be used to describe a conductive element that interconnects two or more conductive lines on different levels of a metallization stack. To this end, the via may be disposed substantially perpendicular to the plane of an IC die / chip or support structure above which the IC structure is disposed, and may interconnect two conductive lines on adjacent levels or two conductive lines on non-adjacent levels.

[0039] The term "package substrate" may be used to describe any substrate material that facilitates packaging together any collection of semiconductor dies and / or other electrical components, such as passive electrical components. As used herein, a package substrate may be formed of any material, including, but not limited to, insulating materials such as resin-impregnated glass fiber (e.g., PCB or printed wiring board (PWB)), glass, ceramic, silicon, silicon carbide, etc. Additionally, as used herein, a package substrate may refer to a substrate that includes build-up layers (e.g., ABF layers).

[0040] The term "metallization stack" may be used to refer to a stack of one or more interconnects for providing connections to different circuit components of an IC die / chip and / or package substrate.

[0041] As used herein, the term "pitch" of an interconnect refers to the center-to-center distance between adjacent interconnects.

[0042] In the context of a stack of dies bonded to one another or a die bonded to a package substrate, the term “interconnect” can also refer to die-to-die (DTD) interconnects and die-to-package substrate (DTPS) interconnects, respectively. DTD interconnects can also be referred to as first-level interconnects (FLI). DTPS interconnects can also be referred to as second-level interconnects (SLI). While not specifically shown in all of the figures herein to avoid cluttering the drawings, when a DTD or DTPS interconnect is described, a surface of a first die may include a first set of conductive contacts, and a surface of a second die or package substrate may include a second set of conductive contacts. Thus, one or more conductive contacts of the first set may be electrically and mechanically coupled to some of the conductive contacts of the second set by the DTD or DTPS interconnect. In some embodiments, the pitch of the DTD interconnects may differ from the pitch of the DTPS interconnects, while in other embodiments, these pitches may be substantially the same.

[0043] It will be appreciated that one or more levels of underfill (e.g., an organic polymer material such as benzotriazole, imidazole, polyimide, or epoxy) may be provided within the IC packages described herein and may not be labeled to avoid overcomplicating the drawings. In various embodiments, the levels of underfill may comprise the same or different insulating materials. In some embodiments, the levels of underfill may comprise a thermosetting epoxy containing silicon oxide particles; in some embodiments, the levels of underfill may comprise any suitable material capable of performing underfill functions, such as supporting the die and reducing thermal stress on the interconnects. In some embodiments, the selection of the underfill material may be based on design considerations, such as form factor, size, stress, operating conditions, etc.; in other embodiments, the selection of the underfill material may be based on material properties and processing conditions, such as cure temperature, glass transition temperature, viscosity, and chemical resistance, among other factors; in some embodiments, the selection of the underfill material may be based on both design and processing considerations.

[0044] In some embodiments, one or more levels of solder resist (e.g., liquid epoxy, liquid photoimageable polymer, dry film photoimageable polymer, acrylic, solvent) may be provided within the IC packages described herein and may not be labeled or shown to avoid cluttering the drawings. The solder resist may be a liquid or dry film material including a photoimageable polymer. In some embodiments, the solder resist may be non-photoimageable.

[0045] The terms "substantially," "close," "approximately," "near," and "about" generally refer to being within + / - 20% of a target value (e.g., within + / - 5% or 10% of a target value) based on the context of a particular value described herein or known in the art.

[0046] For example, terms indicating the orientation of various elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between these elements, generally refer to within + / - 5% to 20% of a target value, based on the context of specific values ​​described herein or known in the art.

[0047] The term "connected" means a direct connection (which may be one or more of a mechanical, electrical and / or thermal connection) between the things connected without any intermediate devices, while the term "coupled" means either a direct connection between the things connected or a connection through one or more passive or active intermediate devices.

[0048] The description uses the phrases "in one embodiment" or "in an embodiment," which each may refer to one or more of the same or different embodiments.

[0049] Furthermore, the terms "comprises," "includes," "having," and the like, as used with respect to the embodiments of the present disclosure, are synonymous.

[0050] Although the present disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side," such descriptions are used for ease of description and are not intended to limit the application of the disclosed embodiments.

[0051] As used herein, the terms "over," "under," "between," and "on" refer to the relative location of one layer of material or component with respect to another layer or component. For example, a layer disposed above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Furthermore, a layer disposed between two layers may be in direct contact with one or both of the two layers or may have one or more intervening layers. In contrast, a first layer described as being "on" a second layer refers to a layer that is in direct contact with the second layer. Similarly, unless explicitly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent feature or may have one or more intervening layers.

[0052] As used herein, the term "location" refers to position, location, placement and / or arrangement, rather than any particular method of formation.

[0053] The term "between" when used in reference to a measurement range includes the ends of the measurement range.

[0054] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). As used herein, the designation A / B / C means (A), (B), and / or (C).

[0055] Although certain elements may be referred to in the singular herein, such elements may include multiple subelements. For example, a "conductive material" may include one or more conductive materials. In another example, a "dielectric material" may include one or more dielectric materials.

[0056] Unless otherwise specified, the use of ordinal numbers such as "first," "second," "third," etc. to describe a common object merely indicates that different instances of a similar object are being referred to and is not intended to imply that the objects so described must be in a given order in time, space, ranking, or in any other manner.

[0057] In the following detailed description, references are made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0058] The accompanying drawings are not necessarily drawn to scale.

[0059] In these drawings, the same reference numbers refer to the same or similar elements / materials shown, unless otherwise stated, such that the description of a given referenced element / material provided in the context of one of these drawings is applicable to other drawings in which the same referenced element / material may be shown.

[0060] Additionally, while in these drawings, schematic views of some of the exemplary structures of the various devices and assemblies described herein may be shown with precise angles and straight lines, it should be understood that such schematic views may not reflect actual process limitations that may cause features to appear less than “ideal,” for example, when any of the structures described herein are inspected using images from an appropriate characterization tool, such as a scanning electron microscope (SEM) image, a transmission electron microscope (TEM) image, or a non-contact profilometer. In such images of actual structures, possible processing and / or surface defects may also be visible, such as surface roughness, curvature or contour misalignment, pits or scratches, edges of materials that are not perfectly straight, tapered vias or other openings, unintentional rounding of corners or variations in thickness of different material layers, accidental kinks, edges, or combinatorial misalignments within crystalline regions, and / or accidental misalignment defects of single atoms or groups of atoms. Other defects not listed here but common within the field of device manufacturing and / or packaging may be present.

[0061] It should be noted that in these figures, various components (e.g., interconnects) are shown as aligned (e.g., at their respective interfaces) solely for ease of illustration; in reality, some or all of them may be misaligned. Additionally, there may be other components not shown in the figures to avoid complexity, such as bond pads, landing pads, metallization, etc., present in the assembly. Furthermore, these figures are intended to show the relative placement of components within the assembly; generally, such assemblies may include other components not shown (e.g., various interface layers or various other components associated with optical functionality, electrical connections, or thermal mitigation). For example, in some further embodiments, the assemblies shown in these figures may include more dies along with other electrical components. Additionally, while these figures show some components of the assemblies as being flat rectangular or formed as cuboids, this is solely for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and in some cases unavoidable due to, the manufacturing processes used to fabricate the various components.

[0062] In these drawings, particular numbers and arrangements of structures and components are presented for illustrative purposes; in various embodiments, any desired number or arrangement of such structures and components may be present.

[0063] Furthermore, unless otherwise specified, the structures shown in these figures may take any suitable form or shape depending on material properties, manufacturing processes and operating conditions.

[0064] For convenience, where there are collections of drawings designated by different letters (e.g., Figures 1A and 1B), such collections may be referred to herein without those letters (e.g., "Figure 1"). Similarly, where there are collections of reference numerals designated by different numbers and / or letters (e.g., 148-1, 148-2), such collections may be referred to herein without those numbers (e.g., "148").

[0065] Various operations may be described sequentially as multiple separate actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiment. Various additional operations may be performed and / or described operations may be omitted in additional embodiments. Illustrative Embodiments

[0066] 1A is a schematic cross-sectional view of an exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. The exemplary microelectronic assembly 100 may include an interposer 104, also referred to herein as a “substrate,” having multiple layers and embedded dies 114-1, 114-2. In particular, the interposer 104 may include dies 114-1, 114-2 surrounded by insulating material 133 in a first layer, a redistribution layer (RDL) 148 having conductive paths 196 through a dielectric material in a second layer above the first layer, and cores 103 and through-glass vias (TGVs) 110 in a third layer above the second layer. The microelectronic assembly 100 may also include top dies 114-3, 114-4, 114-5, and 114-6 electrically coupled to the dies 114-1 and 114-2 by interconnects 150, through the core 103 by TGVs 110, through the RDLs 148 by conductive paths 196, and by interconnects 120.

[0067] The material of the core 103 may include glass, such as bulk transparent glass, and may also be referred to herein as a "glass layer." As used herein, the term "core" refers to a structure (e.g., a portion of a glass layer) of any glass material, such as quartz, silica, fused silica, silicate glass (e.g., borosilicate, aluminosilicate, aluminoborosilicate), soda-lime glass, soda-lime-silica, BOROFLOAT glass, lead borate glass, photosensitive glass, non-photosensitive glass, or ceramic glass. In particular, the core 103 may be a bulk glass or a solid volume / layer of glass, facing a material that may contain glass particles, such as, for example, a glass fiber-reinforced polymer. Such glass materials are typically non-crystalline and often transparent amorphous solids. In some embodiments, the core 103 may be an amorphous solid glass layer. In some embodiments, core 103 may include silicon and oxygen, as well as any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, core 103 may include a material, such as any of the materials described above, having a weight percent silicon of at least about 0.5%, e.g., between about 0.5% and 50%, between about 1% and 48%, or at least about 23%. For example, if core 103 is fused silica, the weight percent silicon may be about 47%. In some embodiments, core 103 may include at least 23% silicon and / or at least 26% oxygen by weight, and in some further embodiments, core 103 may further include at least 5% aluminum by weight. In some embodiments, the core 103 may include any of the materials described above and may further include one or more additives, such as Al2O3, BO, MgO, CaO, SrO, BaO, SnO2, Na2O, KO, SrO, PO, ZrO2, Li2O, Ti, and Zn. In some embodiments, the core 103 may be a layer of glass that does not include an organic binder or organic material.Core 103 may be distinguished from, for example, a PCB substrate "prepreg" or "RF4" core, which typically comprises glass fibers embedded in a resinous organic material such as epoxy. In some embodiments, a cross-section of core 103 in the xz, yz, and / or xy planes of the exemplary coordinate system shown in FIG. 1A may be substantially rectangular. In some embodiments, thickness 191 of core 103 may be between 100 microns and 2 millimeters (i.e., between 200 microns and 1 millimeter).

[0068] The TGV 110 may have any suitable size and shape. The TGV 110 is shown in FIG. 1A as having straight, parallel edges; however, in various embodiments, the TGV 110 may have a tapered or angled profile (e.g., where the TGV 110 has a narrower diameter toward the center of the core 103 and a thicker diameter toward the top and bottom of the core 103) depending on the processing conditions for producing the TGV 110. The TGV 110 may be formed using any suitable process, including, for example, laser drilling via openings through the core 103 and depositing a conductive material in the openings. The TGV 110 may be formed of any suitable conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys. In some embodiments, the pitch of the TGV 110 may be between 10 microns and 200 microns (e.g., between 50 microns and 150 microns). In some embodiments, the diameter (eg, x and y dimensions) of an individual TGV 110 may be between 5 microns and 200 microns (eg, between 20 microns and 75 microns).

[0069] The microelectronic assembly 100 may further include an RDL 148 on the bottom surface of the core 103. The RDL 148 may include conductive paths 196 (e.g., including conductive traces and / or conductive vias, as shown) through the dielectric material electrically coupled to the TGVs 110 within the core 103. The RDL 148 may be fabricated using any suitable technique, such as a semi-additive process, a subtractive etching technique, or other conventional substrate packaging techniques. In some embodiments, the dielectric material of the RDL 148 may include a build-up film with or without fillers, an oxide-based material (e.g., silicon dioxide, silicon oxynitride, or spin-on oxide), or a low-k and ultra-low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymer dielectrics). In some embodiments, the dielectric material of the RDL 148 may include a bismaleimide triazine (BT) resin, a polyimide material, an epoxy material (e.g., a glass-reinforced epoxy matrix material or an epoxy build-up film), or a molding material. The conductive vias of the RDL 148 may have an inverted trapezoidal shape (e.g., an upside-down V-shape) with a smaller cross section (e.g., x-y dimensions) at the top (e.g., the portion toward the core 103) than at the bottom (e.g., the portion toward the insulating material 133).

[0070] 1A may also include insulating material 133 that encapsulates dies 114-1, 114-2 (e.g., around dies 114-1, 114-2) and conductive pillars 152. Insulating material 133 may be on the bottom surface of RDL 148. Die 114-1 may further include TSVs 115 that may be electrically coupled to package substrate 102 by interconnects 190. Dies 114-1, 114-2 may be electrically coupled to conductive paths 196 within RDL 148 by interconnects 120. Interconnects 120 may include any suitable interconnect, including solder or other formations as shown in FIG. 1A (e.g., described below with reference to interconnect 150) or hybrid joints as shown in FIG. 1B (e.g., described below with reference to interconnect 106). In some embodiments, the insulating material 133 may be a molding material, a resin material, or an epoxy material, such as an organic polymer containing inorganic silicon oxide or aluminum oxide particles. In some embodiments, the insulating material may include an underfill material or build-up film that does not include a filler. In some embodiments (not shown), other components, such as a heat sink, may be coupled to the microelectronic assembly 100 based on specific needs. The conductive pillars 152 may be formed of any suitable conductive material, such as, for example, copper, silver, nickel, gold, aluminum, or other metals or alloys. The conductive pillars 152 may be formed using any suitable process, including, for example, lithographic or additive processes, such as cold spray or three-dimensional printing. In some embodiments, the conductive pillars 152 disclosed herein may have a pitch between 55 microns and 1000 microns. The conductive pillars 152 may have any suitable size and shape. In some embodiments, the conductive pillars 152 may have a cross-section that is circular, rectangular, or other shape.

[0071] The microelectronic assembly 100 may further include one or more top dies 114-3, 114-4, 114-5, 114-6 electrically coupled to the top surface of the core 103 by interconnects 150. In particular, conductive contacts 122 on the bottom surfaces of the dies 114-3, 114-4, 114-5, 114-6 may be electrically and mechanically coupled to conductive contacts 174 on the top surface of the core 103 by interconnects 150. The interconnects 150 may enable electrical coupling between the die 114-1, die 114-2, and dies 114-3, 114-4, 114-5, 114-6 through the TGV 110 and conductive paths 196 in the RDL 148. The interconnects 150 disclosed herein may take any suitable form. In some embodiments, a set of interconnects 150 may include solder 132 (e.g., solder bumps or balls that undergo thermal reflow to form interconnects 150). Interconnects 150 that include solder may include any suitable solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, a set of interconnects 150 may include an anisotropic conductive material, such as an anisotropic conductive film or an anisotropic conductive paste. The anisotropic conductive material may include a conductive material dispersed within a non-conductive material. In some embodiments, the anisotropic conductive material may include minute conductive particles embedded in a binder or a thermosetting adhesive film (e.g., a thermosetting biphenyl-type epoxy resin or an acrylic-based material). In some embodiments, the conductive particles may include a polymer and / or one or more metals (e.g., nickel or gold). For example, the conductive particles may include nickel-coated gold or silver-coated copper, which are in turn coated with a polymer. In another example, the conductive particles may include nickel. When an anisotropic conductive material is not compressed, there may not be a conductive path from one side of the material to the other.However, if the anisotropic conductive material is sufficiently compressed (e.g., by conductive contacts on either side of the anisotropic conductive material), conductive material near the area of ​​compression may contact each other to form a conductive path from one side of the film to the other within the area of ​​compression. In some embodiments, the interconnects 150 disclosed herein may have a pitch between about 18 microns and 75 microns. In some embodiments, the interconnects within the microelectronic assembly 100 may be metal-to-metal interconnects (e.g., copper-to-copper interconnects or plated interconnects). In such embodiments, the conductive contacts on either side of the interconnect may be joined together (e.g., under high pressure and / or temperature) without the use of an intervening solder or anisotropic conductive material.

[0072] The die 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and multiple conductive paths formed through the insulating material. In some embodiments, the insulating material of the die 114 may include a dielectric material such as silicon dioxide, silicon nitride, oxynitride, polyimide material, glass-reinforced epoxy matrix material, or a low- or ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, a photoimageable dielectric, and / or a benzocyclobutene-based polymer). In some embodiments, the insulating material of the die 114 may include a semiconductor material such as silicon, germanium, or a III-V material (e.g., gallium nitride), and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive paths within the die 114 may include conductive traces and / or conductive vias, and may connect any of the conductive contacts within the die 114 in any suitable manner (e.g., connecting multiple conductive contacts on the same or different surfaces of the die 114). The conductive paths within the die 114 may be bounded by a liner material, such as an adhesive liner and / or a barrier liner, as appropriate. In some embodiments, the die 114 is a wafer. In some embodiments, the die 114 is a monolithic silicon, fan-out or fan-in packaged die or die stack (e.g., stacked wafers, stacked dies, or stacked multi-layer dies).In various embodiments, die 114 may include or be a portion of one or more of: a power supply circuit, a III-V or III-N device such as a III-N or III-N amplifier (e.g., a GaN amplifier), a peripheral component interconnect express (PCIe) circuit, a double data rate (DDR) transfer circuit, or other electronic components known in the art; a central processing unit (CPU); a graphics processing unit (GPU); a memory device (e.g., a high-bandwidth memory device); logic circuitry; input / output circuitry; a transceiver such as a field programmable gate array transceiver; gate array logic such as field programmable gate array logic;

[0073] 1A may also include an underfill material 127. In some embodiments, the underfill material 127 may extend between the top surfaces of the dies 114-1, 114-2 around the associated interconnects 120 and the RDLs 148, and / or between the top surface of the core 103 around the associated interconnects 150 and the bottom surfaces of the upper dies 114-3, 114-4, 114-5, 114-6. The underfill material 127 may be an insulating material, such as a suitable epoxy material. In some embodiments, the underfill material 127 may include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, underfill material 127 may comprise an epoxy flux that aids in soldering dies 114-1, 114-2 to RDL 148 when forming interconnect 120, or dies 114-3, 114-4, 114-5, 114-6 to core 103 when forming interconnect 150, and then polymerizes and seals interconnects 120, 150, respectively. The underfill process may involve dispensing the underfill material in liquid form, allowing the material to flow and fill the interstitial spaces around interconnects 120, 150, and subjecting the assembly to a curing process, such as baking, to solidify the material. In some embodiments, underfill material 127 may be omitted. 1A shows separate portions of underfill material 127 under dies 114-3, 114-4, 114-5, and 114-6, underfill material 127 may be a single underfill material 127 under dies 114-3, 114-4, 114-5, and 114-6. Underfill material 127 may be selected to have a coefficient of thermal expansion (CTE) that may reduce or minimize stresses between die 114 and RDL 148, insulating material 133, and / or core 103 resulting from non-uniform thermal expansion within microelectronic assembly 100. In some embodiments, the CTE of underfill material 127 may have a value intermediate the CTE of RDL 148, insulating material 133, and / or core 103 (e.g., the CTE of the dielectric material of RDL 148) and the CTE of the insulating material of die 114.

[0074] The top dies 114-3, 114-4, 114-5, 114-6 may be electrically coupled to the respective die 114-1, 114-2 by the TGVs 110 and conductive paths 196 in the RDLs 148. The top dies 114-3, 114-4, 114-5, 114-6 may be electrically coupled to the package substrate 102 by the TGVs 110, conductive paths 196 in the RDLs 148, and conductive pillars in the insulating material 133, which may enable power, ground, and signal connections between the top dies 114-3, 114-4, 114-5, 114-6 and the package substrate 102.

[0075] The microelectronic assembly 100 of FIG. 1A may further include a package substrate 102. The package substrate 102 may be electrically coupled to the interposer 104 by interconnects 190. In particular, the conductive contacts 172 on the bottom surface of the interposer 104 may be electrically coupled to the conductive contacts 146 on the top surface of the package substrate 102 by the interconnects 190. The interconnects 190 disclosed herein may take any suitable form, including solder balls, as described above with reference to the interconnects 120, 150. As shown in FIG. 1A, in some embodiments, a set of the interconnects 190 may include solder 136 (e.g., solder bumps or balls that undergo thermal reflow to form the interconnects 190). In some embodiments, the interconnects 190 disclosed herein may have a pitch between approximately 20 microns and 300 microns. In some embodiments, an underfill material 127 may extend between the interposer 104 and the package substrate 102 around the associated interconnects 190.

[0076] 1A may further include a circuit board (not shown). The circuit board 131 may be, for example, a motherboard and may have other components mounted thereon. As is known in the art, the circuit board may include conductive paths and other conductive contacts for transferring power, ground, and signals throughout the circuit board.

[0077] In some embodiments, one or more levels of solder resist (e.g., liquid epoxy, liquid photoimageable polymer, dry film photoimageable polymer, acrylic, solvent) may be provided within the IC packages described herein and may not be labeled or shown to avoid cluttering the drawings. The solder resist may be a liquid or dry film material including a photoimageable polymer. In some embodiments, the solder resist may be non-photoimageable.

[0078] Note that in FIG. 1A and subsequent figures, interconnects (e.g., interconnects 120, 150, 190, 106) are shown as aligned at their respective interfaces solely for ease of illustration; in reality, some or all of them may be misaligned. Additionally, there may be other components not shown in the figures to avoid complexity, such as bond pads, landing pads, metallization, etc., present in the assembly. Note that FIG. 1A is intended to illustrate the relative placement of components in the assembly, and that, in general, such assemblies may include other components not shown (e.g., various interface layers or various other components related to optical functionality, electrical connections, or thermal mitigation). For example, in some further embodiments, the assemblies shown in FIGS. 1A and 1B may include more dies along with other electrical components. Additionally, while some components of the assemblies are shown in FIG. 1A as being flat rectangular or cuboid-shaped, this is for ease of illustration only, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and in some cases unavoidable due to, the manufacturing processes used to produce the various components.

[0079] FIG. 1B is a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of FIG. 1A, except for the differences described further. The configuration of the microelectronic assembly 100 described herein includes a first insulating material 133-1 surrounding the dies 114-1 and 114-2, and a first RDL 148-1 having a first conductive path 196-1 through the dielectric material, with the dies 114-1 and 114-2 electrically coupled to the first conductive path 196-1 in the first RDL 133-1 by an interconnect 106. An example of the interconnect 106 in some embodiments is a hybrid junction including a metal-metal junction and a dielectric-dielectric junction. In a general sense, the interconnect 106 may include a metal-metal junction and a dielectric-dielectric junction formed between layers on each side of the interconnect, which include bond pads in the dielectric material. The bond pads may also be referred to herein as conductive contacts or metal contacts. The metal-metal bond material may include copper-copper. Dielectric materials within the layers surrounding the bond pads may bond to each other. The dielectric materials may include inorganic dielectrics (e.g., silicon and oxygen in the form of silicon oxide) or organic dielectrics (e.g., polyimide). The bonded metal and dielectric materials form the interconnect 106, which provides electrical and mechanical coupling, including hybrid bonding. In various embodiments, the interconnects 106 may have a pitch of less than 10 microns between adjacent interconnects. In some embodiments, the interconnects 106 may have a pitch of between 2 microns and 70 microns (e.g., between 2 microns and 10 microns, between 10 microns and 45 microns, or between 45 microns and 70 microns). 1B further includes a second RDL 148-2 having a second conductive path 196-2 through a dielectric material on the top surface of the core 103 and a second insulating material 133-2 surrounding the dies 114-3, 114-4, 114-5, and 114-6. The top dies 114-3, 114-4, 114-5, and 114-6 can be electrically coupled to the second conductive path 196-2 in the second RDL 148-2 by interconnects 150.The dielectric material in the first RDL 148-1 may be the same dielectric material as the dielectric material in the second RDL 148-2 or may be a different dielectric material than the dielectric material in the second RDL 148-2. The first insulating material 133-1 may be the same material as the second insulating material 133-2 or may be a different material than the second insulating material 133-2.

[0080] FIG. 2 is a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of FIG. 1A , except for differences that will be further described. The configuration of the microelectronic assembly 100 described herein further includes a cavity 108 through the RDL 148, with the die 114-1 residing in the cavity 108 and electrically coupled to the TGV 110 in the core 103 by the interconnect 106. In some embodiments, an insulating material 133 may fill within and around the die 114-1 in the cavity 108. The microelectronic assembly 100 of FIG. 2 further includes top dies 114-3, 114-4, 114-5, 114-6 electrically coupled to the TGV 110 in the core 103 by the interconnect 106.

[0081] Figure 3 is a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of Figure 2, except for differences that will be further described. The configuration of microelectronic assembly 100 described herein further includes a cavity 109 through RDL 148 and through core 103, with die 114-1 residing within cavity 109 and electrically coupled to top dies 114-3, 114-4 by interconnects 106. Although Figure 3 shows dies 114-1, 114-3, 114-4 electrically coupled by interconnects 106, any suitable interconnects may be used, such as interconnects 150 in Figures 1A and 1B.

[0082] FIG. 4 is a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of FIG. 2, except for differences that will be further described. The configuration of the microelectronic assembly 100 described herein does not include a core 103. Instead, the microelectronic assembly 100 includes an RDL 148 having a cavity 108, an insulating material 133 surrounding dies 114-1 and 114-2, with die 114-1 residing within cavity 108 and electrically coupled to top dies 114-3 and 114-4 by interconnects 150. While FIG. 4 shows die 114 electrically coupled by interconnects 150, any suitable interconnects, such as interconnects 106 in FIG. 3, may be used.

[0083] Although the microelectronic assembly 100 shown in Figures 1A and 1B through 4 has a particular number of dies 114 in a particular arrangement, the microelectronic assembly 100 may have any suitable number and arrangement of dies 114. [Exemplary Method]

[0084] Any suitable technique may be used to fabricate the microelectronic assembly 100 disclosed herein. For example, FIGS. 5A through 5G are side cross-sectional views of various stages in an exemplary process for fabricating the microelectronic assembly 100 of FIG. 1A, according to various embodiments. Although the operations described below with reference to FIGS. 5A through 5G (and other of the accompanying figures depicting the fabrication process) are shown in a particular order, these operations may be performed in any suitable order. Moreover, additional operations not shown may be performed without departing from the scope of the present disclosure. Also, various of the operations described herein with respect to FIGS. 5A through 5G may be modified in accordance with the present disclosure to fabricate other of the microelectronic assemblies 100 disclosed herein.

[0085] FIG. 5A illustrates a core 103 including a first surface 170-1 and a second surface 170-2. The core 103 may include a TGV 110 extending therethrough. The TGV 110 may include any suitable conductive material, for example, a metal such as copper. The assembly of FIG. 5A may be fabricated by forming a via in an opening in the core 103 and plating copper into the via opening. The via opening may be formed using any suitable process, including lithography, laser-assisted wet etching, laser drilling (e.g., laser ablation using an excimer laser), or plasma etching. The via opening may have any suitable shape. For example, the via opening may have substantially vertical sidewalls to form a rectangular or cylindrical via, or angled sidewalls to form a conical via. The shape of the via opening may depend on the process used to form the via opening (e.g., a lithography process for a rectangular via and a laser drilling process for a conical via). In some embodiments, the top surface 170-2 of the core 103 may be attached to a carrier (not shown), which may comprise any suitable material to provide mechanical stability during manufacturing operations, such as glass.

[0086] 5B shows the assembly after forming the RDL 148 on the first surface 170-1 (e.g., the bottom surface) of the core 103. The RDL 148 may include conductive paths 196 through the dielectric material. The RDL 148 may be fabricated using any suitable technique, such as PCB or redistribution layer techniques.

[0087] FIG. 5C shows the assembly after forming conductive pillars 152 on the bottom surface of the RDL 148. The conductive pillars 152 may take the form of any of the embodiments disclosed herein and may be formed using any suitable technique, including lithographic or additive processes such as cold spray or three-dimensional printing. For example, the conductive pillars 152 may be formed by depositing, exposing, and growing a photoresist layer on the bottom surface of the RDL 148. The photoresist layer may be patterned to form cavities in the shape of the conductive pillars. To form the conductive pillars 152, a conductive material such as copper may be deposited into the openings in the patterned photoresist layer. The conductive material may be deposited using any suitable process, such as electroplating, sputtering, or electroless plating. The photoresist may be removed to expose the conductive pillars 152. In another example, a photoimageable dielectric may be used to form the conductive pillars 152. The conductive pillars may have any suitable dimensions. For example, in some embodiments, the individual conductive pillars may have an aspect ratio (height:diameter) of between 1:1 and 4:1 (e.g., between 1:1 and 3:1). The conductive pillars 152 may have any suitable cross-sectional shape, such as square, triangular, and elliptical, among others.

[0088] 5D shows the assembly after positioning the dies 114-1, 114-2, forming the interconnects 120, and depositing underfill material 127 around the interconnects 120. Any suitable method, such as automated pick-and-place, may be used to position the dies 114-1, 114-2. In some embodiments, the interconnects 120 may include solder. In such embodiments, the assembly of FIG. 5D may undergo a solder reflow process, during which the solder components of the interconnects 120 melt and bond to mechanically and electrically couple the dies 114-1, 114-2 to the bottom surface of the RDL 148.

[0089] 5E shows the assembly after depositing insulating material 133 over and around dies 114-1, 114-2 and conductive pillars 152. Insulating material 133 may be any suitable material described above with reference to FIG. 1A and may be formed using any suitable process, including lamination or slit coating and curing.

[0090] 5F shows the assembly after the bottom of insulating material 133 and conductive pillars 152 have been removed to expose the conductive contacts on the bottom surface of die 114-1. Insulating material 133 and the material of conductive pillars 152 may be removed using any suitable technique, including grinding, planarizing, or etching such as wet etching, dry etching (e.g., plasma etching), wet blasting, or laser ablation (e.g., with an excimer laser). In some embodiments, the thickness of insulating material 133 may be minimized to reduce the required etching time.

[0091] FIG. 5G shows the assembly of FIG. 5F after forming conductive contacts 172, 174 on the bottom and top surfaces of the assembly, placing dies 114-3, 114-4, 114-5, and 114-6 on the top surface of the assembly, forming interconnects 150, and depositing underfill material 127 around the interconnects 150. The conductive contacts 172, 174 may be formed using any suitable process, including semi-additive processes. For example, a lithography process may include applying and patterning photoresist to the top and bottom surfaces of the assembly of FIG. 5F, depositing a conductive material in the openings, and removing the photoresist. The conductive material may be deposited using any suitable process, including electroplating. Any suitable method, such as automated pick-and-place, may be used to place the dies 114-3, 114-4, 114-5, and 114-6. In some embodiments, the interconnects 150 may comprise solder. In such embodiments, the assembly of FIG. 5G may undergo a solder reflow process, during which the solder components of the interconnects 150 melt and bond, mechanically and electrically coupling the dies 114-3, 114-4, 114-5, 114-6 to the top surface of the core 103. In some embodiments, the underfill material 127 around the interconnects 150 may be omitted. Other finishing operations may be performed on the assembly of FIG. 5G, such as depositing a solder resist (not shown) and depositing solder 136 on the bottom surface. When multiple assemblies are fabricated together, the assemblies may be singulated. As shown, the assembly of FIG. 5G may itself be the microelectronic assembly 100. Further manufacturing operations may be performed on the microelectronic assembly 100 of FIG. 5G to form other microelectronic assemblies 100; for example, solder 136 may be used to couple the microelectronic assembly 100 of FIG. 5G to the package substrate 102 via interconnects 190, similar to the microelectronic assembly 100 of FIG. 1A, and / or, as shown in FIG. 1B, an insulating material 133 (e.g., the second insulating material 133-2 in FIG. 1B) may be deposited on and around 114-3, 114-4, 114-5, 114-6.

[0092] 6A-6C are side cross-sectional views of various stages in an exemplary process for fabricating a microelectronic assembly 100 similar to FIG. 1B, according to various embodiments. FIG. 6A shows the assembly of FIG. 5F, which may be fabricated using any suitable technique, including the processes described above with reference to FIGS. 5A-5F. FIG. 6A includes dies 114-1, 114-2 electrically coupled by interconnect 120 shown in FIG. 1A, instead of interconnect 106 shown in FIG. 1B.

[0093] 6B shows the assembly after forming RDL 148-2 on the second surface 170-2 (e.g., the top surface) of core 103. RDL 148-2 may include conductive paths 196-2 through the dielectric material. RDL 148-2 may be fabricated using any suitable technique, such as PCB or redistribution layer techniques.

[0094] FIG. 6C shows the assembly of FIG. 6B after forming conductive contacts 172, 174 on the bottom and top surfaces, placing dies 114-3, 114-4, 114-5, and 114-6 on the top surface of the assembly, forming interconnects 150, and depositing underfill material 127 around interconnects 150. Any suitable method, such as automated pick-and-place, may be used to place dies 114-3, 114-4, 114-5, and 114-6. In some embodiments, interconnects 150 may include solder. In such embodiments, the assembly of FIG. 6C may undergo a solder reflow process, during which the solder components of interconnects 150 melt and bond, mechanically and electrically coupling dies 114-3, 114-4, 114-5, and 114-6 to the top surface of the assembly of FIG. 6B. In some embodiments, underfill material 127 around interconnects 150 may be omitted. Other finishing operations may be performed on the assembly of FIG. 6C , such as depositing a solder resist (not shown) and depositing solder 136 on the bottom surface. When multiple assemblies are fabricated together, the assemblies may be singulated. As shown, the assembly of FIG. 6C may itself be the microelectronic assembly 100. Additional manufacturing operations may be performed on the microelectronic assembly 100 of FIG. 6C to form other microelectronic assemblies 100; for example, solder 136 may be used to bond the microelectronic assembly 100 of FIG. 6C to the package substrate 102 via interconnects 190, similar to the microelectronic assembly 100 of FIG. 1B , and / or insulating material 133 (e.g., second insulating material 133-2 in FIG. 1B ) may be deposited on and around 114-3, 114-4, 114-5, 114-6.

[0095] 7A through 7D are cross-sectional side views of various stages in an exemplary process for fabricating the microelectronic assembly 100 of FIG. 2, according to various embodiments. FIG. 7A shows an assembly including a core 103 having a first surface 170-1 and a second surface 170-2 and a TGV 110, and an RDL 148 having a conductive path 196 through a dielectric material at the first surface 170-1 (e.g., a bottom surface) of the core 103. The assembly of FIG. 7A can be fabricated using any suitable technique, including the techniques described above with reference to FIGS. 5A and 5B.

[0096] 7B shows the assembly after forming conductive pillars 152 on the bottom surface of RDL 148 and forming cavities 108 in the dielectric material of RDL 148. Cavities 108 may be formed using any suitable technique, including, for example, laser patterning techniques. Cavities 108 may have any suitable dimensions such that die 114-1 may be mounted therein. Conductive pillars 152 may take the form of any of the embodiments disclosed herein and may be formed using any suitable process, including that described above with reference to FIG. 5C.

[0097] 7C shows the assembly after placing die 114-1, forming interconnect 106, placing die 114-2, forming interconnect 120, depositing underfill material 127 around interconnect 120, depositing insulating material 133 over and around dies 114-1, 114-2 and conductive pillars 152, and planarizing insulating material 133 and conductive pillars 152 as needed, exposing conductive contacts on the bottom surface of die 114-1. Any suitable method, such as automated pick-and-place, may be used to place dies 114-1, 114-2. In some embodiments, interconnect 120 may not include solder and may instead be interconnect 106. Insulating material 133 may be any suitable material described above with reference to FIG. 1A and may be formed and planarized using any suitable process described above with reference to FIGS. 5E and 5F.

[0098] FIG. 7D shows the assembly of FIG. 7C after forming conductive contacts 172 on the bottom surface thereof, placing dies 114-3, 114-4, 114-5, and 114-6 on the top surface thereof, and forming interconnects 106. In some embodiments, a bonding layer (e.g., bond pads in a dielectric material) may be formed on the top surface of the assembly of FIG. 7C before forming the interconnects 106. Any suitable method, such as automated pick-and-place, may be used to place dies 114-3, 114-4, 114-5, and 114-6. Other finishing operations may be performed on the assembly of FIG. 7D, such as depositing solder resist (not shown) and depositing solder 136 on the bottom surface. When multiple assemblies are fabricated together, the assemblies may be singulated. As shown, the assembly of FIG. 7D itself may be the microelectronic assembly 100. Further manufacturing operations may be performed on the microelectronic assembly 100 of FIG. 7D to form other microelectronic assemblies 100; for example, solder 136 may be used to couple the microelectronic assembly 100 of FIG. 7D to the package substrate 102 via interconnects 190, similar to the microelectronic assembly 100 of FIG. 2, an insulating material 133 (e.g., the second insulating material 133-2 in FIG. 1B) may be deposited on and around dies 114-3, 114-4, 114-5, 114-6, and / or an RDL 148 (e.g., the second RDL 148-2 shown in FIG. 1B) may be formed on the top surface of the core 103 before electrically coupling the dies 114-3, 114-4, 114-5, 114-6.

[0099] 8A through 8D are cross-sectional side views of various stages in an exemplary process for fabricating the microelectronic assembly 100 of FIG. 3, according to various embodiments. FIG. 8A shows an assembly including a core 103 having a first surface 170-1 and a second surface 170-2 and a TGV 110, an RDL 148 having a conductive path 196 through a dielectric material at the first surface 170-1 (e.g., bottom surface) of the core 103, and a conductive pillar 152 on the bottom surface of the RDL 148. The assembly of FIG. 8A can be fabricated using any suitable technique, including the techniques described above with reference to FIGS. 5A through 5C.

[0100] 8B shows the assembly after forming cavity 109 in the dielectric material of RDL 148 and core 103. Cavity 109 may be formed using any suitable technique, including, for example, laser patterning techniques. Cavity 109 may have any suitable dimensions such that die 114-1 may be mounted therein.

[0101] 8C shows the assembly after positioning die 114-1, positioning die 114-2, forming interconnects 120, depositing underfill material 127 around interconnects 120, depositing insulating material 133 over and around dies 114-1, 114-2 and conductive pillars 152, and planarizing insulating material 133 and conductive pillars 152 as needed to expose conductive contacts on the bottom surface of die 114-1. Any suitable method, such as automated pick-and-place, may be used to position dies 114-1, 114-2. In some embodiments, interconnects 120 may not include solder and may instead be interconnects 106. Insulating material 133 may be any suitable material described above with reference to FIG. 1A and may be formed and planarized using any suitable process described above with reference to FIGS. 5E and 5F.

[0102] FIG. 8D shows the assembly of FIG. 8C after forming conductive contacts 172 on the bottom surface thereof, placing dies 114-3, 114-4, 114-5, and 114-6 on the top surface thereof, and forming interconnects 106. In some embodiments, a bonding layer (e.g., bond pads in a dielectric material) may be formed on the top surface of the assembly of FIG. 8C before forming the interconnects 106. Any suitable method, such as automated pick-and-place, may be used to place dies 114-3, 114-4, 114-5, and 114-6. Other finishing operations may be performed on the assembly of FIG. 8D, such as depositing solder resist (not shown) and depositing solder 136 on the bottom surface. When multiple assemblies are fabricated together, the assemblies may be singulated. As shown, the assembly of FIG. 8D itself may be the microelectronic assembly 100. Further manufacturing operations may be performed on the microelectronic assembly 100 of FIG. 8D to form other microelectronic assemblies 100; for example, solder 136 may be used to couple the microelectronic assembly 100 of FIG. 8D to the package substrate 102 via interconnects 190, similar to the microelectronic assembly 100 of FIG. 3, an insulating material 133 (e.g., the second insulating material 133-2 in FIG. 1B) may be deposited on and around dies 114-3, 114-4, 114-5, 114-6, and / or an RDL 148 (e.g., the second RDL 148-2 shown in FIG. 1B) may be formed on the top surface of the core 103 before electrically coupling the dies 114-3, 114-4, 114-5, 114-6.

[0103] 9A through 9E are cross-sectional side views of various stages in an exemplary process for fabricating the microelectronic assembly 100 of FIG. 4, according to various embodiments. FIG. 9A shows the assembly after forming RDLs 148 having conductive paths through a dielectric material on the carrier 101. The carrier 101 may comprise any suitable material for providing mechanical stability during manufacturing operations, such as glass. In some embodiments, a surface layer material (not shown), such as a solder resist material, may be deposited on the carrier prior to forming the RDLs 148.

[0104] 9B shows the assembly after forming conductive pillars 152 on the top surface of RDL 148 and forming cavities 108 in the dielectric material of RDL 148. Cavities 108 may be formed using any suitable technique, including, for example, laser patterning techniques. Cavities 108 may have any suitable dimensions such that die 114-1 may be mounted therein. Conductive pillars 152 may take the form of any of the embodiments disclosed herein and may be formed using any suitable process, including those described above with reference to FIG. 5C.

[0105] 9C shows the assembly after positioning die 114-1, positioning die 114-2, forming interconnects 120, depositing underfill material 127 around interconnects 120, depositing insulating material 133 over and around dies 114-1, 114-2 and conductive pillars 152, and planarizing insulating material 133 and conductive pillars 152 as needed to expose conductive contacts on the top surface of die 114-1. Die 114-1 may be attached to carrier 101 using any suitable technique, such as a die attach film (DAF) 154. Any suitable method, for example, automated pick-and-place, may be used to position dies 114-1, 114-2. In some embodiments, interconnects 120 may not include solder and may instead be interconnects 106. Insulating material 133 may be any suitable material as described above with reference to FIG. 1A and may be formed and planarized using any suitable process as described above with reference to FIGS. 5E and 5F.

[0106] FIG. 9D shows the assembly of FIG. 9C after inverting the assembly and removing carrier 101. DAF 154 may be removed from die 114-1 such that die 114-1 may have a recess 199 formed from the top surface 970-2 of the assembly of FIG. 9D. Recess 199 may have a thickness (e.g., z dimension) between 1 micron and 20 microns. As shown in FIG. 9D, conductive contacts 174 may be flush with top surface 970-2 of the assembly of FIG. 9D.

[0107] FIG. 9E shows the assembly of FIG. 9D after forming conductive contacts 172 on the bottom surface, placing dies 114-3, 114-4, 114-5, and 114-6 on the top surface of the assembly, forming interconnects 150, and depositing underfill material 127 around interconnects 150. Conductive contacts 172 may be formed using any suitable process, including semi-additive processes. Any suitable method, such as automated pick-and-place, may be used to place dies 114-3, 114-4, 114-5, and 114-6. In some embodiments, interconnects 150 may include solder. In such embodiments, the assembly of FIG. 9E may undergo a solder reflow process, during which solder components of interconnects 150 melt and bond to mechanically and electrically couple dies 114-3, 114-4, 114-5, and 114-6 to the top surface of RDL 148. In some embodiments, the underfill material 127 around the interconnects 150 may be omitted. Other finishing operations may be performed on the assembly of FIG. 9E , such as depositing a solder resist (not shown) and depositing solder 136 on the bottom surface. When multiple assemblies are fabricated together, the assemblies may be singulated. As shown, the assembly of FIG. 9E may itself be the microelectronic assembly 100. Additional manufacturing operations may be performed on the microelectronic assembly 100 of FIG. 9E to form other microelectronic assemblies 100; for example, solder 136 may be used to bond the microelectronic assembly 100 of FIG. 9E to the package substrate 102 via the interconnects 190, similar to the microelectronic assembly 100 of FIG. 4, and / or, as shown in FIG. 1B , an insulating material 133 (e.g., the second insulating material 133-2 in FIG. 1B ) may be deposited on and around 114-3, 114-4, 114-5, and 114-6.

[0108] The packages disclosed herein, such as any of these microelectronic assemblies 100, or any further embodiments described herein, can be included in any suitable electronic component. Figures 10 through 12 show various examples of packages, assemblies, and devices that can be used with or include any of the IC packages disclosed herein.

[0109] 10 is a side cross-sectional view of an exemplary IC package 2200 that may include a microelectronic assembly according to any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a system-in-package (SiP).

[0110] 10, package support 2252 may be formed of an insulator (e.g., ceramic, build-up film, epoxy film with filler particles therein, etc.) and may have conductive paths extending through the insulator between first surface 2272 and second surface 2274, or between different locations on first surface 2272 and / or different locations on second surface 2274. These conductive paths may take the form of any of the interconnect structures, including lines and / or vias, described above with reference to, for example, FIGS. 1A and 1B.

[0111] The package support 2252 may include conductive contacts 2263 coupled to conductive paths 2262 through the package support 2252, thereby allowing circuitry within the die 2256 and / or interposer 2257 to be electrically coupled to various of the conductive contacts 2264 (or to other devices contained within the package support 2252, not shown).

[0112] IC package 2200 may include an interposer 2257 coupled to a package support 2252 via conductive contacts 2261 of the interposer 2257, a first level interconnect (FLI) 2265, and conductive contacts 2263 of the package support 2252. The FLI 2265 shown in Figure 10 is a solder bump, although any suitable FLI 2265 may be used, such as a solder bump, solder post, or bond wire.

[0113] IC package 2200 may include one or more die 2256 coupled to interposer 2257 via conductive contacts 2254 of die 2256, FLI 2258, and conductive contacts 2260 of interposer 2257. In various embodiments, interposer 2257 may include core 103 including a glass as described herein. Conductive contacts 2260 may be coupled to conductive paths (not shown) through interposer 2257, allowing circuitry within die 2256 to be electrically coupled to various of conductive contacts 2261 (or to other devices (not shown) included in interposer 2257). While FLI 2258 shown in FIG. 10 is a solder bump, any suitable FLI 2258 may be used, such as a solder bump, solder post, or bond wire. As used herein, a "conductive contact" may refer to a portion of a conductive material (e.g., a metal) that acts as an interface between different components; a conductive contact may be recessed into, flush with, or extend away from the surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

[0114] In some embodiments, underfill material 2266 may be disposed between package support 2252 and interposer 2257 around FLI 2265, and mold 2268 may be disposed around die 2256 and interposer 2257 and in contact with package support 2252. In some embodiments, underfill material 2266 may be the same as mold 2268. An exemplary material that may be used for underfill material 2266 and mold 2268 is optionally epoxy. Second level interconnects (SLIs) 2270 may be coupled to conductive contacts 2264. The SLIs 2270 shown in FIG. 10 are solder balls (e.g., for a ball grid array (BGA) arrangement), but any suitable SLIs 2270 (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement) may be used. The SLI 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package as known in the art and described below with reference to FIG. 12.

[0115] In embodiments in which IC package 2200 includes multiple dies 2256, IC package 2200 may be referred to as a multi-chip package (MCP). Dies 2256 may include circuitry for performing any desired function. For example, in addition to one or more of dies 2256 including components of die 114 described herein, one or more of dies 2256 may be logic dies (e.g., silicon-based dies), one or more of dies 2256 may be memory dies (e.g., high-bandwidth memory), etc. In some embodiments, at least some of dies 2256 may not include components of die 114 described herein.

[0116] Although the IC package 2200 shown in FIG. 10 is a flip-chip package, other package architectures can be used. For example, the IC package 2200 can be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 can be a wafer-level chip-scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are shown in the IC package 2200, the IC package 2200 can include any desired number of dies 2256. The IC package 2200 can include additional passive components, such as surface-mount resistors, capacitors, and inductors, located on the first side 2272 or the second side 2274 of the package support 2252 or on either side of the interposer 2257. More generally, the IC package 2200 can include any other active or passive components known in the art.

[0117] 11 is a side cross-sectional view of an IC device assembly 2300 that may include components having one or more microelectronic assemblies 100 according to any of the embodiments disclosed herein. The IC device assembly 2300 includes multiple components disposed above a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components disposed above a first side 2340 of the circuit board 2302 and an opposing second side 2342 of the circuit board 2302; generally, components may be disposed above one or both of the sides 2340 and 2342. In particular, any suitable components of the IC device assembly 2300 may include any of one or more microelectronic assemblies 100 according to any of the embodiments disclosed herein; for example, any of the IC packages described below with reference to the IC device assembly 2300 may take the form of any of the embodiments of the IC package 2200 described above with reference to FIG. 10.

[0118] In some embodiments, circuit board 2302 may be a PCB including multiple metal layers separated from each other by layers of insulation and interconnected by conductive vias, any one or more of which may be formed in a desired circuit pattern to transfer electrical signals (optionally in conjunction with other metal layers) between components coupled to circuit board 2302. In other embodiments, circuit board 2302 may be a non-PCB package support.

[0119] 11 shows that, in some embodiments, IC device assembly 2300 may include package-on-interposer structure 2336 coupled to first surface 2340 of circuit board 2302 by bonding components 2316. Although not shown to avoid cluttering the drawing, in some embodiments, package-on-interposer structure 2336 may include a core 103, such as a glass layer. In other embodiments, package-on-interposer structure 2336 may not include a core. Bonding components 2316 may electrically and mechanically couple package-on-interposer structure 2336 to circuit board 2302 and may include solder balls (as shown), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical bonding structure.

[0120] Package-on-interposer structure 2336 may include an IC package 2320 coupled to interposer 2304 by bonding component 2318. In some embodiments, IC package 2320 may include microelectronic assembly 100 and other components described herein that are not shown to avoid cluttering the drawing. Bonding component 2318 may take any suitable form depending on the desired functionality, such as those described above with reference to bonding component 2316. In some embodiments, IC package 2320 may be or include IC package 2200, for example, as described above with reference to FIG. 10 .

[0121] 11 , multiple IC packages may be coupled to the interposer 2304, and in fact, additional interposers may be coupled to the interposer 2304. The interposer 2304 may provide intervening package support used to bridge the circuit board 2302 and the IC package 2320. In general, the interposer 2304 may redistribute connections to a wider pitch or reroute certain connections to different connections. For example, the interposer 2304 may couple the IC package 2320 to a BGA of the mating component 2316 for coupling to the circuit board 2302.

[0122] 11, IC package 2320 and circuit board 2302 are mounted on opposite sides of interposer 2304. In other embodiments, IC package 2320 and circuit board 2302 may be mounted on the same side of interposer 2304. In some embodiments, three or more components may be interconnected by interposer 2304.

[0123] The interposer 2304 may be formed of a polymer material such as epoxy, fiberglass-reinforced epoxy, ceramic material, or polyimide. In some implementations, the interposer 2304 may be formed of alternative rigid or flexible materials. These materials may include the same materials used for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including TSVs 2306. The interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on the interposer 2304. The package-on-interposer structure 2336 may take the form of any package-on-interposer structure known in the art.

[0124] In some embodiments, IC device assembly 2300 may include an IC package 2324 coupled to first surface 2340 of circuit board 2302 by coupling component 2322. Coupling component 2322 may take the form of any of the embodiments described above with reference to coupling component 2316, and IC package 2324 may take the form of any of the embodiments described above with reference to IC package 2320.

[0125] In some embodiments, IC device assembly 2300 may include a package-on-package structure 2334 coupled to second surface 2342 of circuit board 2302 by coupling component 2328. Package-on-package structure 2334 may include IC package 2326 and IC package 2332 coupled together by coupling component 2330 such that IC package 2326 is disposed between circuit board 2302 and IC package 2332. Coupling components 2328 and 2330 may take the form of any of the embodiments of coupling component 2316 described above, and IC package 2326 and / or 2332 may take the form of any of the embodiments of IC package 2320 described above. Package-on-package structure 2334 may be configured according to any of the package-on-package structures known in the art.

[0126] 12 is a block diagram of an exemplary computing device 2400 that may include one or more components having one or more IC packages according to any of the embodiments disclosed herein. For example, any suitable one of the components of computing device 2400 may include microelectronic assembly 100 including glass according to any of the embodiments disclosed herein. In another example, any one or more of the components of computing device 2400 may include any embodiment of IC package 2200 (e.g., shown in FIG. 10). In yet another example, any one or more of the components of computing device 2400 may include IC device assembly 2300 (e.g., shown in FIG. 11).

[0127] 12 as being included in computing device 2400, any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in computing device 2400 may be mounted on one or more motherboards. In some embodiments, some or all of these components are fabricated on a single SOC die.

[0128] 12 , but the computing device 2400 may include interface circuitry for coupling to one or more components. For example, the computing device 2400 may not include a display device 2406, but may include display device interface circuitry (e.g., connectors and driver circuits) to which the display device 2406 may be coupled. In another set of examples, the computing device 2400 may not include an audio input device 2418 or an audio output device 2408, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuits) to which the audio input device 2418 or the audio output device 2408 may be coupled.

[0129] Computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the terms “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that may be stored in registers and / or memory. Processing device 2402 may include one or more digital signal processors (DSPs), ASICs, CPUs, GPUs, cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. Computing device 2400 may include memory 2404, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, memory 2404 may include memory that shares a die with processing device 2402. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0130] In some embodiments, computing device 2400 may include a communications chip 2412 (e.g., one or more communications chips); note that the terms “chip,” “die,” and “IC die” are used interchangeably herein. For example, communications chip 2412 may be configured to manage multiple wireless communications for data transfer to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data through the use of modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated devices do not include any wires, although in some embodiments this may not be the case.

[0131] The communications chip 2412 may implement any of a number of wireless standards or protocols, including Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi® (IEEE 802.11 family), the IEEE 802.16 standard (e.g., the IEEE 802.16-2005 amendment), the Long Term Evolution (LTE) project with any amendments, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also referred to as "3GPP®2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are commonly referred to as WiMAX® networks, and the acronym stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed IEEE 802.16 standard compliance and interoperability testing. The communications chip 2412 may operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA or LTE network). The communications chip 2412 may operate according to GSM Evolution High Speed ​​Data Transmission (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communications chip 2412 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and beyond. In other embodiments, the communications chip 2412 may operate according to multiple other wireless protocols. The computing device 2400 may include an antenna 2422 for facilitating wireless communication and / or for receiving other wireless communications (such as AM or FM radio transmissions).

[0132] In some embodiments, the communications chip 2412 may manage wired communications, such as electrical, optical, or any other suitable communications protocol (e.g., Ethernet). As noted above, the communications chip 2412 may include multiple communications chips. For example, a first communications chip 2412 may be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communications chip 2412 may be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communications chip 2412 may be dedicated to wireless communications, and the second communications chip 2412 may be dedicated to wired communications.

[0133] Computing device 2400 may include battery / power circuitry 2414. Battery / power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 2400 to an energy source (e.g., AC line power) separate from computing device 2400.

[0134] The computing device 2400 may include a display device 2406 (or corresponding interface circuitry as described above). The display device 2406 may include any visual indicator, such as, for example, a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0135] The computing device 2400 may include an audio output device 2408 (or corresponding interface circuitry as described above). The audio output device 2408 may include any device that generates an audible indicator, such as, for example, a speaker, a headset, or earbuds.

[0136] The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry as described above). The audio input device 2418 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a Musical Instrument Digital Interface (MIDI) output).

[0137] The computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry as described above), which may be in communication with a satellite-based system and may receive the location of the computing device 2400 in a manner known in the art.

[0138] The computing device 2400 may include other output devices 2410 (as described above or corresponding interface circuitry). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0139] The computing device 2400 may include other input devices 2420 (or corresponding interface circuits as described above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an imaging device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0140] Computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), desktop computing device, server device or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device. In some embodiments, computing device 2400 may be any other electronic device that processes data.

[0141] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. While specific implementations and examples of the disclosure are described herein for illustrative purposes, those skilled in the art will recognize that various equivalent modifications are possible within the scope of the present disclosure.

[0142] The following paragraphs provide various examples of the embodiments disclosed herein.

[0143] Example 1 is a microelectronic assembly comprising: a first layer, the first layer having a first material and a die surrounded by the first material; a second layer on the first layer, the second layer having a second material and a conductive pathway through the second material, where the conductive pathway includes a conductive trace and a conductive via, where the conductive via includes an inverted trapezoid shape; and a third layer on the second layer, the third layer having a glass layer and a conductive through-glass via (TGV), where the conductive TGV is electrically coupled to the conductive pathway, and the die is electrically coupled to the conductive TGV by the conductive pathway.

[0144] Example 2 may include the subject matter described in Example 1 and may further specify that the die is electrically coupled to the conductive pathways by an interconnect, the interconnect including solder.

[0145] Example 3 may include the subject matter of Example 1 or 2 and may further specify that the die further comprises through-substrate vias (TSVs).

[0146] Example 4 may include the subject matter of any of Examples 1-4 and may further specify that the die may be a first die, and the microelectronic assembly may further comprise a second die on the third layer at a surface opposite the second layer, the second die electrically coupled to the conductive TGV by an interconnect.

[0147] Example 5 may include the subject matter of Example 4 and may further specify that the interconnect comprises solder.

[0148] Example 6 may include the subject matter described in Example 4 and may further specify that the interconnect includes a metal-metal junction and a dielectric-dielectric junction.

[0149] Example 7 may include the subject matter of any of Examples 1 to 6 and may further specify that the first material includes a molding material, a resin material, an epoxy material, or an underfill material, and the second material includes a build-up film, a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, silicon and oxygen, or silicon, oxygen, and nitrogen.

[0150] Example 8 may include the subject matter of Example 7 and may further specify that the first material includes an organic polymer containing inorganic silicon oxide particles or aluminum oxide particles.

[0151] Example 9 may include the subject matter of any of Examples 1-8 and may further specify that the second layer has a first conductive pathway through the second material, and the microelectronic assembly may further comprise a fourth layer on the third layer, the fourth layer having the second material and a second conductive pathway through the second material, where the second conductive pathway is electrically coupled to the conductive TGV.

[0152] Example 10 may include the subject matter of Example 9 and may further specify that the die in the first layer may be a first die, and the microelectronic assembly may further include a second die on the fourth layer on a surface opposite the third layer, the second die being electrically coupled to the second conductive pathway.

[0153] Example 11 can include the subject matter of any of Examples 1-10, and can further include a conductive pillar in the first material in the first layer adjacent to the die.

[0154] Example 12 may include the subject matter of Example 11 and may further specify that the material of the conductive pillars includes one or more of copper, silver, nickel, gold, and aluminum.

[0155] Example 13 can include the subject matter of any of Examples 1-12, and can further include a package substrate electrically coupled to the first layer on a surface facing the second layer.

[0156] Example 14 is a microelectronic assembly comprising: a glass layer having a first surface and an opposing second surface; a first via and a second via extending through the glass layer, the first via and the second via comprising a conductive material; a first material at the first surface of the glass layer, the first material having a cavity and a conductive path electrically coupled to the first via in the glass layer at the first surface; and a die in the cavity of the first material, the die being electrically coupled to the second via in the glass layer by an interconnect at the first surface, wherein the die extends beyond the first material at a surface of the glass layer opposite the first surface, wherein the die is surrounded by a second material different from the first material.

[0157] Example 15 may include the subject matter of Example 14 and may further specify that the first material comprises a build-up film, a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, silicon and oxygen, or silicon, oxygen, and nitrogen, and the second material comprises a mold material, a resin material, an epoxy material, or an underfill material.

[0158] Example 16 may include the subject matter of Examples 14 or 15, and may further specify that the second material includes a molding material, a resin material, or an epoxy material.

[0159] Example 17 may include the subject matter of any of Examples 14-16, and may further specify that the die further comprises a through-substrate via (TSV).

[0160] Example 18 may include the subject matter of any of Examples 14 to 17, and may further specify that the die may be a first die, the interconnect may be a first interconnect, and the microelectronic assembly may further include a second die at the second surface of the glass layer, the second die electrically coupled to the first via and the second via in the glass layer by a second interconnect.

[0161] Example 19 may include the subject matter of Example 18 and may further specify that the first interconnect or the second interconnect includes solder.

[0162] Example 20 may include the subject matter of Example 18, and may further specify that the first interconnect and the second interconnect include a metal-metal junction and a dielectric-dielectric junction.

[0163] Example 21 can include the subject matter of any of Examples 14 to 20, and can further include a conductive pillar in the second material adjacent to the die, the conductive pillar electrically coupled to the conductive path in the first material.

[0164] Example 22 may include the subject matter of Example 21 and may further specify that the material of the conductive pillars includes one or more of copper, silver, nickel, gold, and aluminum.

[0165] Example 23 may include the subject matter described in Example 21 and may further specify that the die may further have through-substrate vias (TSVs), and the microelectronic assembly may further include a package substrate electrically coupled to the TSVs in the die and the conductive pillars in the second material.

[0166] Example 24 is a microelectronic assembly comprising: a first material layer having a first die including a through-substrate via (TSV) and a second die, wherein the first die and the second die are surrounded by the first material; a second material layer on the first material layer, wherein the second material has a cavity and a conductive path, wherein the first die is within the cavity; and a third die on the second material layer, wherein the third die is electrically coupled to the first die and to the conductive path by an interconnect.

[0167] Example 25 may include the subject matter of Example 24 and may further specify that the first material comprises a build-up film, a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, silicon and oxygen, or silicon, oxygen, and nitrogen, and the second material comprises a mold material, a resin material, an epoxy material, or an underfill material.

[0168] Example 26 may include the subject matter of Examples 24 or 25, and may further specify that the first material includes a molding material, a resin material, or an epoxy material.

[0169] Example 27 may include the subject matter of any of Examples 24-26 and may further specify that the interconnect comprises solder.

[0170] Example 28 may include the subject matter of any of Examples 24-26, and may further specify that the interconnect includes a metal-metal junction and a dielectric-dielectric junction.

[0171] Example 29 may include the subject matter of any of Examples 24 to 28, and may further specify that a top surface of the first die is recessed relative to a top surface of the second material layer.

[0172] Example 30 may include the subject matter of any of Examples 24-29, and may further specify that the first material layer further comprises a conductive pillar surrounded by the first material, the conductive pillar electrically coupled to the conductive path in the second material.

[0173] Example 31 can include the subject matter of Example 30, and can further include a package substrate electrically coupled to the first die and to the conductive pillars in the first material.

[0174] Example 32 may include the subject matter of any of Examples 24 to 31, and may further include a glass layer between the second material layer and the third die, wherein the glass layer has through-glass vias (TGVs) electrically coupled to the conductive paths in the second material layer, and the third die is electrically coupled to the TGVs, wherein the cavity in the second material layer further extends through the glass layer, and wherein the first die is in the cavity through the second material layer and the glass layer.

[0175] Example 33 may include the subject matter of Example 32 and may further specify that the first material layer further comprises a conductive pillar surrounded by the first material, the conductive pillar electrically coupled to the conductive path in the second material.

[0176] Example 34 may include the subject matter of Example 33 and may further specify that the material of the conductive pillars includes one or more of copper, silver, nickel, gold, and aluminum.

[0177] Example 35 can include the subject matter of Example 33, and can further include a package substrate electrically coupled to the first die and to the conductive pillars in the first material.

[0178] Example 36 can include the subject matter of any of Examples 24-35, and can further include a third material surrounding the third die.

[0179] [Other possible items] [Item 1] a first layer, the first layer having a first material and a die surrounded by the first material; a second layer on the first layer, the second layer having a second material and a conductive pathway through the second material, where the conductive pathway includes a conductive trace and a conductive via, where the conductive via includes an inverted trapezoid shape; and a third layer on the second layer, the third layer having a glass layer and a conductive through-glass via (TGV), wherein the conductive TGV is electrically coupled to the conductive pathway, and the die is electrically coupled to the conductive TGV by the conductive pathway; A microelectronic assembly comprising: [Item 2] Item 10. The microelectronic assembly of item 1, wherein the die is electrically coupled to the conductive pathways by interconnects, the interconnects comprising solder. [Item 3] Item 10. The microelectronic assembly of item 1, wherein the die further comprises through-substrate vias (TSVs). [Item 4] the die is a first die, and the microelectronic assembly comprises: a second die on the third layer at a surface opposite the second layer, the second die being electrically coupled to the conductive TGV by an interconnect; Item 1. The microelectronic assembly of item 1, further comprising: [Item 5] Item 10. The microelectronic assembly of item 1, wherein the first material comprises one or more of a molding material, a resin material, an epoxy material, or an underfill material, and the second material comprises a build-up film, a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, silicon and oxygen, or silicon, oxygen, and nitrogen. [Item 6] a conductive pillar adjacent to the die in the first material in the first layer; Item 1. The microelectronic assembly of item 1, further comprising: [Item 7] the second layer having a first conductive path through the second material, and the microelectronic assembly comprising: a fourth layer on the third layer, the fourth layer having the second material and a second conductive path through the second material, wherein the second conductive path is electrically coupled to the conductive TGV; Item 1. The microelectronic assembly of item 1, further comprising: [Item 8] the die in the first layer is a first die, and the microelectronic assembly comprises: a second die on the fourth layer at a surface opposite the third layer, the second die being electrically coupled to the second conductive path; Item 8. The microelectronic assembly of item 7, further comprising: [Item 9] a glass layer having a first surface and an opposing second surface; a first via and a second via extending through the glass layer, the first via and the second via having a conductive material; a first material at the first surface of the glass layer, the first material having a cavity and a conductive path electrically coupled to the first via in the glass layer at the first surface; and a die in the cavity of the first material, the die being electrically coupled at the first surface to the second via in the glass layer by an interconnect, the die extending beyond the first material at a surface of the glass layer opposite the first surface, and the die being surrounded by a second material different from the first material; A microelectronic assembly comprising: [Item 10] 10. The microelectronic assembly of claim 9, wherein the first material comprises a build-up film, a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, silicon and oxygen, or silicon, oxygen, and nitrogen, and the second material comprises a molding material, a resin material, an epoxy material, or an underfill material. [Item 11] 10. The microelectronic assembly of claim 9, wherein the die further comprises through-substrate vias (TSVs). [Item 12] the die is a first die, the interconnect is a first interconnect, and the microelectronic assembly comprises: a second die at the second surface of the glass layer, the second die being electrically coupled to the first via and the second via in the glass layer by a second interconnect; Item 10. The microelectronic assembly of item 9, further comprising: [Item 13] Item 13. The microelectronic assembly of item 12, wherein the first interconnect or the second interconnect comprises solder. [Item 14] Item 13. The microelectronic assembly of item 12, wherein the first interconnect and the second interconnect comprise a metal-metal bond and a dielectric-dielectric bond. [Item 15] The die further comprises a through-substrate via (TSV), and the microelectronic assembly further comprises: a conductive pillar in the second material adjacent to the die, the conductive pillar being electrically coupled to the conductive path in the first material; and a package substrate electrically coupled to the TSVs in the die and to the conductive pillars in the second material; Item 10. The microelectronic assembly of item 9, further comprising: [Item 16] a first material layer having a first die including a through-substrate via (TSV) and a second die, wherein the first die and the second die are surrounded by the first material; a second material layer on the first material layer, wherein the second material layer has a cavity and a conductive path, and wherein the first die is within the cavity; and a third die on the second material layer, wherein the third die is electrically coupled to the first die and to the conductive paths by interconnects; A microelectronic assembly comprising: [Item 17] Item 17. The microelectronic assembly of item 16, wherein the first material comprises a build-up film, a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, silicon and oxygen, or silicon, oxygen, and nitrogen, and the second material comprises a molding material, a resin material, an epoxy material, or an underfill material. [Item 18] Item 17. The microelectronic assembly of item 16, wherein the top surface of the first die is recessed compared to the top surface of the second material layer. [Item 19] a glass layer between the second material layer and the third die, wherein the glass layer has through-glass vias (TGVs) electrically coupled to the conductive paths in the second material layer, the third die being electrically coupled to the TGVs, wherein the cavity in the second material layer further extends through the glass layer, and wherein the first die is within the cavity through the second material layer and the glass layer. Item 17. The microelectronic assembly of item 16, further comprising: [Item 20] 20. The microelectronic assembly of claim 19, wherein the first material layer further comprises a conductive pillar surrounded by the first material, the conductive pillar being electrically coupled to the conductive path in the second material. (Item 21) a first layer, the first layer having a first material and a die surrounded by the first material; a second layer on the first layer, the second layer having a second material and a conductive pathway through the second material, where the conductive pathway includes a conductive trace and a conductive via, where the conductive via includes an inverted trapezoid shape; and a third layer on the second layer, the third layer having a glass layer and a conductive through-glass via (TGV), wherein the conductive TGV is electrically coupled to the conductive pathway, and the die is electrically coupled to the conductive TGV by the conductive pathway; A microelectronic assembly comprising: (Item 22) Item 22. The microelectronic assembly of item 21, wherein the die is electrically coupled to the conductive pathways by interconnects, the interconnects comprising solder. (Item 23) 23. The microelectronic assembly of claim 21 or 22, wherein the die further comprises through-substrate vias (TSVs). (Item 24) the die is a first die, and the microelectronic assembly comprises: a second die on the third layer at a surface opposite the second layer, the second die being electrically coupled to the conductive TGV by an interconnect; 24. The microelectronic assembly of any one of items 21 to 23, further comprising: (Item 25) Item 25. The microelectronic assembly of item 24, wherein the interconnects comprise solder. (Item 26) 25. The microelectronic assembly of claim 24, wherein the interconnects include metal-metal and dielectric-dielectric bonds. (Item 27) 27. The microelectronic assembly of any one of items 21 to 26, wherein the first material comprises a molding material, a resin material, an epoxy material, or an underfill material, and the second material comprises a build-up film, a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, silicon and oxygen, or silicon, oxygen, and nitrogen. (Item 28) 28. The microelectronic assembly of claim 27, wherein the first material comprises an organic polymer containing inorganic silicon oxide or aluminum oxide particles. (Item 29) the second layer having a first conductive path through the second material, and the microelectronic assembly comprising: a fourth layer on the third layer, the fourth layer having the second material and a second conductive path through the second material, wherein the second conductive path is electrically coupled to the conductive TGV; 29. The microelectronic assembly of any one of items 21 to 28, further comprising: (Item 30) the die in the first layer is a first die, and the microelectronic assembly comprises: a second die on the fourth layer at a surface opposite the third layer, the second die being electrically coupled to the second conductive path; Item 30. The microelectronic assembly of item 29, further comprising: (Item 31) a conductive pillar adjacent to the die in the first material in the first layer; 31. The microelectronic assembly of any one of items 21 to 30, further comprising: (Item 32) Item 32. The microelectronic assembly of item 31, wherein the material of the conductive pillars comprises one or more of copper, silver, nickel, gold and aluminum. (Item 33) a package substrate electrically coupled to the first layer on a surface opposite the second layer; 33. The microelectronic assembly of any one of items 21 to 32, further comprising: (Item 34) a glass layer having a first surface and an opposing second surface; a first via and a second via extending through the glass layer, the first via and the second via having a conductive material; a first material at the first surface of the glass layer, the first material having a cavity and a conductive path electrically coupled to the first via in the glass layer at the first surface; and a die in the cavity of the first material, the die being electrically coupled at the first surface to the second via in the glass layer by an interconnect, the die extending beyond the first material at a surface of the glass layer opposite the first surface, and the die being surrounded by a second material different from the first material; An integrated circuit (IC) package comprising: (Item 35) Item 35. The IC package of item 34, wherein the first material comprises a build-up film, a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, silicon and oxygen, or silicon, oxygen, and nitrogen, and the second material comprises a molding material, a resin material, an epoxy material, or an underfill material. (Item 36) Item 36. The IC package of item 34 or 35, wherein the second material includes a molding material, a resin material, or an epoxy material. (Item 37) the die is a first die, the interconnect is a first interconnect, and the IC package is a second die at the second surface of the glass layer, the second die being electrically coupled to the first via and the second via in the glass layer by a second interconnect; 37. The IC package of any one of items 34 to 36, further comprising: (Item 38) a conductive pillar in the second material adjacent to the die, the conductive pillar being electrically coupled to the conductive path in the first material; 38. The IC package of any one of items 34 to 37, further comprising: (Item 39) a layer of a first material having a first die including a through-substrate via (TSV) and a second die, wherein the first die and the second die are surrounded by the first material; a layer of a second material on the layer of first material, wherein the second material has a cavity and conductive paths, and wherein the first die is within the cavity; and a third die on the second layer of material, wherein the third die is electrically coupled to the first die and to the conductive paths by interconnects; 1. A computing device comprising: (Item 40) Item 40. The computing device of item 39, wherein the first material comprises a build-up film, a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, silicon and oxygen, or silicon, oxygen, and nitrogen, and the second material comprises a molding material, a resin material, an epoxy material, or an underfill material. (Item 41) 41. The computing device of claim 39 or 40, wherein the first material comprises a molding material, a resin material, or an epoxy material. (Item 42) 42. The computing device of any one of items 39 to 41, wherein a top surface of the first die is recessed compared to a top surface of the second layer of material. (Item 43) a glass layer between the layer of second material and the third die, wherein the glass layer has through-glass vias (TGVs) electrically coupled to the conductive paths in the layer of second material, the third die being electrically coupled to the TGVs, wherein the cavity in the layer of second material further extends through the glass layer, and wherein the first die is within the cavity through the layer of second material and the glass layer. 43. The computing device of any one of items 39 to 42, further comprising: (Item 44) Item 44. The computing device of item 43, wherein the layer of first material further comprises a conductive pillar surrounded by the first material, the conductive pillar electrically coupled to the conductive path in the second material. (Item 45) Item 45. The computing device of item 44, wherein the material of the conductive pillars includes one or more of copper, silver, nickel, gold, and aluminum.

Claims

1. a first layer, the first layer having a first material and a die surrounded by the first material; a second layer on the first layer, the second layer having a second material and a conductive pathway through the second material, where the conductive pathway includes a conductive trace and a conductive via, where the conductive via includes an inverted trapezoid shape; and a third layer on the second layer, the third layer having a glass layer and a conductive through-glass via (TGV), wherein the conductive TGV is electrically coupled to the conductive pathway, and the die is electrically coupled to the conductive TGV by the conductive pathway; A microelectronic assembly comprising:

2. The microelectronic assembly of claim 1 , wherein the die is electrically coupled to the conductive pathways by interconnects, the interconnects comprising solder.

3. The microelectronic assembly of claim 1 , wherein the die further comprises through-substrate vias (TSVs).

4. the die is a first die and the microelectronic assembly comprises: a second die on the third layer at a surface opposite the second layer, the second die being electrically coupled to the conductive TGV by an interconnect; The microelectronic assembly of claim 1 further comprising:

5. The microelectronic assembly of claim 4 , wherein the interconnects comprise solder.

6. The microelectronic assembly of claim 4, wherein the interconnects include metal-to-metal and dielectric-to-dielectric bonds.

7. 10. The microelectronic assembly of claim 1, wherein the first material comprises a molding material, a resin material, an epoxy material, or an underfill material, and the second material comprises a build-up film, a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, silicon and oxygen, or silicon, oxygen, and nitrogen.

8. The microelectronic assembly of claim 7 , wherein the first material comprises an organic polymer containing inorganic silicon oxide or aluminum oxide particles.

9. the second layer having a first conductive path through the second material, and the microelectronic assembly comprising: a fourth layer on the third layer, the fourth layer having the second material and a second conductive path through the second material, wherein the second conductive path is electrically coupled to the conductive TGV; The microelectronic assembly of claim 1 further comprising:

10. the die in the first layer is a first die, and the microelectronic assembly comprises: a second die on the fourth layer at a surface opposite the third layer, the second die being electrically coupled to the second conductive path; The microelectronic assembly of claim 9 further comprising:

11. a conductive pillar adjacent to the die in the first material in the first layer; The microelectronic assembly of claim 1 further comprising:

12. The microelectronic assembly of claim 11 , wherein the material of the conductive pillars comprises one or more of copper, silver, nickel, gold, and aluminum.

13. a package substrate electrically coupled to the first layer on a surface opposite the second layer; The microelectronic assembly of claim 1 , further comprising:

14. a glass layer having a first surface and an opposing second surface; a first via and a second via extending through the glass layer, the first via and the second via having a conductive material; a first material at the first surface of the glass layer, the first material having a cavity and a conductive path electrically coupled to the first via in the glass layer at the first surface; and a die in the cavity of the first material, the die being electrically coupled at the first surface to the second via in the glass layer by an interconnect, the die extending beyond the first material at a surface of the glass layer opposite the first surface, wherein the die is surrounded by a second material different from the first material.

1. An integrated circuit (IC) package comprising:

15. 15. The IC package of claim 14, wherein the first material comprises a build-up film, a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, silicon and oxygen, or silicon, oxygen, and nitrogen, and the second material comprises a molding material, a resin material, an epoxy material, or an underfill material.

16. The IC package of claim 14 , wherein the second material comprises a molding material, a resin material, or an epoxy material.

17. the die is a first die, the interconnect is a first interconnect, and the IC package is a second die on the second surface of the glass layer, the second die being electrically coupled to the first via and the second via in the glass layer by a second interconnect; 15. The IC package of claim 14, further comprising:

18. a conductive pillar in the second material adjacent to the die, the conductive pillar being electrically coupled to the conductive path in the first material; 18. The IC package of claim 14, further comprising:

19. a layer of a first material having a first die including a through-substrate via (TSV) and a second die, wherein the first die and the second die are surrounded by the first material; a layer of a second material on the layer of first material, wherein the second material has a cavity and conductive paths, and wherein the first die is within the cavity; and a third die on the second layer of material, wherein the third die is electrically coupled to the first die and to the conductive paths by interconnects; 1. A computing device comprising:

20. 20. The computing device of claim 19, wherein the first material comprises a build-up film, a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, silicon and oxygen, or silicon, oxygen, and nitrogen, and the second material comprises a molding material, a resin material, an epoxy material, or an underfill material.

21. 20. The computing device of claim 19, wherein the first material comprises a molding material, a resin material, or an epoxy material.

22. 20. The computing device of claim 19, wherein a top surface of the first die is recessed compared to a top surface of the second layer of material.

23. a glass layer between the layer of second material and the third die, wherein the glass layer has through-glass vias (TGVs) electrically coupled to the conductive paths in the layer of second material, the third die being electrically coupled to the TGVs, wherein the cavity in the layer of second material further extends through the glass layer, and wherein the first die is within the cavity through the layer of second material and the glass layer.

23. The computing device of claim 19, further comprising:

24. 24. The computing device of claim 23, wherein the layer of first material further comprises a conductive pillar surrounded by the first material, the conductive pillar electrically coupled to the conductive path in the second material.

25. 25. The computing device of claim 24, wherein the material of the conductive pillars comprises one or more of copper, silver, nickel, gold, and aluminum.

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