Substrate support body including plurality of radio frequency (RF) electrodes

Abstract

To provide a process device capable of promoting plasma uniformity.SOLUTION: The present disclosure relates to a plasma semiconductor process and a process device for the process. The process device includes a chamber and a substrate support body. The substrate support body is disposed within the chamber. The substrate support body includes a support surface configured to support a semiconductor substrate within the chamber. The substrate support body includes a plurality of radio frequency (RF) electrodes. A first RF electrode of the plurality of RF electrodes is disposed near a center of the support surface. A second RF electrode of the plurality of RF electrodes is disposed near a periphery of the support surface. The first RF electrode and the second RF electrode intersect, along a side surface, with an axis parallel to a radial direction of the support surface between the center and the periphery of the support surface.SELECTED DRAWING: Figure 2

Description

[Background technology]

[0001] Plasma processes are widespread in the semiconductor industry. Plasma semiconductor processes have long been used for material etching, material deposition, and the like. These plasma processes are known to improve the process quality or resulting properties of semiconductor substrates. For example, plasma-enhanced chemical vapor deposition (PECVD) is known to offer advantages over traditional chemical vapor deposition (CVD) processes, such as lower deposition temperatures, higher material purity, and improved step coverage. In plasma etching processes, plasma is typically generated within a process chamber and may be accelerated by a surface electric field to achieve directional etching. However, the introduction of plasma has presented various challenges. Summary of the Invention

[0002] A first embodiment described herein is a process apparatus for semiconductor processing. The process apparatus includes a chamber and a substrate support. The chamber has an internal volume therein. The substrate support is disposed within the internal volume of the chamber. The substrate support includes a support surface configured to support a semiconductor substrate within the internal volume of the chamber. The substrate support includes a plurality of radio frequency (RF) electrodes. Each lateral dimension of each RF electrode of the plurality of RF electrodes is 2% or less of a wavelength of an RF signal applied to the respective RF electrode. Each dimension lies in a plane parallel to the support surface. The plurality of RF electrodes are configured to at least partially control a plasma within the internal volume of the chamber.

[0003] A second embodiment is a process apparatus for semiconductor processing. The process apparatus includes a chamber and a substrate support. The chamber has an internal volume therein. The substrate support is disposed within the internal volume of the chamber. The substrate support includes a support surface configured to support a semiconductor substrate within the internal volume of the chamber. The substrate support includes a plurality of radio frequency (RF) electrodes configured to at least partially control a plasma within the internal volume of the chamber. A first RF electrode of the plurality of RF electrodes is disposed near a center of the support surface, and a second RF electrode of the plurality of RF electrodes is disposed near a periphery of the support surface. The first RF electrode and the second RF electrode laterally intersect an axis parallel to a radial direction of the support surface between the center and the periphery of the support surface.

[0004] A third embodiment is a process apparatus for semiconductor processing. The process apparatus includes a chamber and a substrate support. The chamber has an internal volume therein. The substrate support is disposed within the internal volume of the chamber. The substrate support includes a support surface configured to support a semiconductor substrate within the internal volume of the chamber. The substrate support includes a plurality of radio frequency (RF) electrodes configured to at least partially control a plasma within the internal volume of the chamber. Each RF electrode of the plurality of RF electrodes has a side dimension of 221.1 millimeters or less, and each dimension lies in a plane parallel to the support surface.

[0005] A fourth embodiment is a method for semiconductor processing. The method includes generating a plasma in a process volume of a chamber of a process apparatus. A substrate support is disposed in the chamber and supports a semiconductor substrate on a support surface. The semiconductor substrate is exposed to the plasma. The method further includes controlling the plasma, including applying respective radio frequency (RF) signals to a plurality of RF electrodes disposed on the substrate support.

[0006] A fifth embodiment is a method for semiconductor processing. The method includes performing a plasma semiconductor process having first process conditions on a first plurality of substrates using a process apparatus. The process apparatus includes a substrate support configured to support the substrates during the plasma semiconductor process. The substrate support includes a plurality of radio frequency (RF) electrodes configured to control, at least in part, a plasma of the plasma semiconductor process. The first process conditions correspond to amplitude and phase of an RF signal applied to the plurality of RF electrodes during the plasma semiconductor process. The method includes measuring a first characteristic of each of the first plurality of substrates corresponding to a first position of a first RF electrode of the plurality of RF electrodes during the plasma semiconductor process. The first characteristic is formed by the plasma semiconductor process. The method includes measuring a second characteristic of each of the first plurality of substrates corresponding to a second position of a second RF electrode of the plurality of RF electrodes during the plasma semiconductor process. The second characteristic is formed by the plasma semiconductor process. The second position is different from the first position. The method includes determining, by a processor-based system, second process conditions to be applied during the plasma semiconductor process on a second plurality of substrates based on the first characteristic and the second characteristic. The second process conditions correspond to amplitudes and phases of RF signals applied to the plurality of RF electrodes during the plasma semiconductor process. The method includes performing a plasma semiconductor process having the second process conditions on a second plurality of substrates using the process apparatus.

[0007] The foregoing summary has outlined, rather broadly, various features of embodiments of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of such embodiments are described below. The described examples may be readily utilized as a basis for modifying or designing other examples within the scope of the appended claims. [Brief explanation of the drawings]

[0008] For a more detailed understanding of the above features, reference is now made to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] [Figure 1] 1 is a schematic diagram of a process apparatus for semiconductor processing according to some embodiments.

[0010] [Figure 2] FIG. 1 is a layout diagram of a radio frequency (RF) electrode arrangement according to some embodiments. [Figure 3] FIG. 1 is a layout diagram of a radio frequency (RF) electrode arrangement according to some embodiments. [Figure 4] FIG. 1 is a layout diagram of a radio frequency (RF) electrode arrangement according to some embodiments. [Figure 5] FIG. 1 is a layout diagram of a radio frequency (RF) electrode arrangement according to some embodiments. [Figure 6] FIG. 1 is a layout diagram of a radio frequency (RF) electrode arrangement according to some embodiments.

[0011] [Figure 7A] FIG. 7 is a layout diagram of the various RF electrodes of FIGS. 2 through 6 according to some embodiments. [Figure 7B] FIG. 7 is a layout diagram of the various RF electrodes of FIGS. 2 through 6 according to some embodiments. [Figure 7C] FIG. 7 is a layout diagram of the various RF electrodes of FIGS. 2 through 6 according to some embodiments. [Figure 7D] FIG. 7 is a layout diagram of the various RF electrodes of FIGS. 2 through 6 according to some embodiments.

[0012] [Figure 8] 1 is a schematic diagram of a process apparatus for semiconductor processing according to some embodiments.

[0013] [Figure 9] 1 is a schematic diagram of a process apparatus for semiconductor processing according to some embodiments.

[0014] [Figure 10]FIG. 10 is a schematic diagram of an RF power system of the process device of FIGS. 1, 8, and 9 in accordance with some embodiments.

[0015] [Figure 11] FIG. 10 is a schematic diagram of an RF power system that may be implemented with the process devices of FIGS. 1, 8, and 9 according to some embodiments.

[0016] [Figure 12] 1 is a processor-based system according to some embodiments.

[0017] [Figure 13] 1 is a flowchart of a method of semiconductor processing according to some embodiments.

[0018] [Figure 14] 1 is a flowchart of a method of semiconductor processing according to some embodiments.

[0019] The drawings and accompanying detailed description are provided to provide an understanding of the features of various examples and are not intended to limit the scope of the appended claims. The examples illustrated in the drawings and described in the accompanying detailed description may be readily utilized as a basis for modifying or designing other examples within the scope of the appended claims. Wherever possible, the same reference numbers may be used to designate identical elements common to the drawings. The figures are drawn to clearly illustrate associated elements or features and are not necessarily drawn to scale. DETAILED DESCRIPTION OF THE INVENTION

[0020] Various features are described below with reference to the figures. An embodiment may not have all aspects or advantages shown. An aspect or advantage described in connection with a particular embodiment is not necessarily limited to that embodiment and may be implemented in any other embodiment, even if not shown or explicitly described as such. Furthermore, while methods herein may be described with a particular order of operations, other methods according to other embodiments may be implemented in various other orders with more or fewer operations (e.g., including different sequential or parallel performance of various operations).

[0021] The present disclosure relates to plasma semiconductor processes and process apparatus for plasma semiconductor processes. Some embodiments described herein include a substrate support of a process apparatus, wherein the substrate support includes a plurality of radio frequency (RF) electrodes configured to control a plasma within the process apparatus. Providing the substrate support with a plurality of RF electrodes can enable more precise and localized control of the plasma, thereby promoting plasma uniformity.

[0022] Plasma non-uniformity during semiconductor processing can result in defects in the integrated circuit (IC) die being fabricated. Plasma non-uniformity has been observed between the center of a semiconductor substrate (e.g., a wafer) and near the edge of the semiconductor substrate. Because a significant number of IC die are fabricated near the edge of the semiconductor substrate, plasma non-uniformity at the edge of the semiconductor substrate can result in significant yield loss.

[0023] Various factors may contribute to plasma non-uniformity between the center and edge of a semiconductor substrate. One factor is typically the physical structure of the process equipment. The physical structure of the process equipment can affect the flow of gases during semiconductor processing, and such flow can be non-uniform throughout the chamber of the process equipment. This can result in variations in the concentrations of reactants and / or byproducts in the plasma at different locations. The physical structure of the process equipment can at least partially determine the electromagnetic field used to generate the plasma. The structure between the electrodes where the plasma is generated can determine the electromagnetic field. At the center of the electrode, the electromagnetic field is modeled as emanating from an infinite plane, with little or no edge effect. Near the edge of the electrode, edge effects become more pronounced, which can reduce and / or change the directionality of the electromagnetic field. As a result, the plasma density can be different at the center of the substrate than at the edge of the semiconductor substrate. Furthermore, because the edge of the electrode is closer to the wall of the chamber of the process equipment, low-resistance electromagnetic loops can be created, which can result in differences in plasma density and ion energy between the center and the edge.

[0024] Another factor may be the frequency of the RF signal used to generate the plasma and the lateral size of the electrode. Lowering the frequency of the RF signal (e.g., increasing the wavelength) can reduce the electromagnetic field. On the other hand, increasing the frequency can result in finite-wavelength effects that can affect the uniformity of the RF magnetic field in the plasma. Nonuniformity problems can increase with increasing frequency and substrate size. For example, the difference in electromagnetic field strength over a 1% wavelength interval along the direction of electromagnetic wave propagation can be as much as 6.28%. Even in the smoothest part of the wave, to achieve magnetic field uniformity better than 1%, the lateral size of the RF electrode may be no more than 2% of the RF signal's wavelength. In a semiconductor process chamber, the upper frequency limit for an RF signal for a 300 mm wafer size may be approximately 60 MHz. However, at this frequency, significant nonuniformity of the RF electromagnetic field can be observed on the semiconductor substrate.

[0025] According to some embodiments described herein, the substrate support includes multiple RF electrodes. In some embodiments, each RF electrode has a lateral dimension that is 2% or less of the wavelength of the RF signal applied to the RF electrode. Different RF signals may be applied to the RF electrodes. By making the electromagnetic field for each of the RF electrodes approximately uniform, it may be possible to achieve overall uniformity of the electromagnetic field on the semiconductor substrate through appropriate adjustment of the RF signal applied to the RF electrodes. This may overcome finite wavelength effects in plasma processing equipment and allow for the use of higher frequency RF power to generate higher density plasma or reduce surface electric fields and associated surface erosion. By individually controlling the multiple RF electrodes, the characteristics of the electromagnetic field on the semiconductor substrate may be adjusted to compensate for non-uniformities caused by other process parameters.

[0026] In some embodiments, two or more of the RF electrodes are disposed between the center and periphery of the support surface and laterally intersect an axis parallel to the radial direction of the support surface. The substrate support includes a support surface configured to support a semiconductor substrate during plasma semiconductor processing. By aligning two or more of the RF electrodes in such an arrangement, different RF signals can be applied, for example, to the RF electrodes near the center and the RF electrodes near the edge. By applying such different RF signals, the plasma can be controlled differently at the edge and the center, thereby promoting plasma uniformity. Such applied different RF signals can address various other effects of the plasma semiconductor process that cause plasma nonuniformity.

[0027] In some embodiments, the different RF signals applied to each RF electrode may have the same amplitude and phase to obtain a uniform electromagnetic field across a substrate larger than the individual electrodes, while in some other embodiments, the different RF signals applied to each RF electrode may have different amplitudes and / or phases to achieve a desired effect (e.g., compensation for non-uniformities due to other process parameters such as edge effects).

[0028] In some embodiments, each lateral dimension of each RF electrode of the substrate support is 221.1 millimeters (mm) or less, which is approximately 2% of the wavelength of a 27.12 MHz signal. In some embodiments, each lateral dimension of each RF electrode of the substrate support is 199.9 mm or less, which is approximately 2% of the wavelength of a 30 MHz signal. In some embodiments, each lateral dimension of each RF electrode of the substrate support is 99.9 mm or less, which is approximately 2% of the wavelength of a 60 MHz signal. In some embodiments, each lateral dimension of each RF electrode of the substrate support is in the range of 50.0 mm to 221.1 mm, 50.0 mm to 199.9 mm, or 50.0 mm to 99.9 mm, where 50.0 mm is approximately 2% of the wavelength of a 120 MHz signal. Providing RF electrodes with such dimensions on the substrate support can reduce plasma non-uniformity caused by wavelength effects and reduce potential electromagnetic field oscillations. Other benefits or advantages may be realized using various aspects described herein.

[0029] For simplicity and convenience, similar components shown in the figures may be referred to individually or collectively by the same base reference number. In the figures, instances of such components are labeled with the base reference number with a respective instance identifier (in the form "-number") appended thereto. For example, a description may refer to X widgets ZZZ, in which case the instances in the figures would be numbered ZZZ-1, ZZZ-2, ... ZZZ-x, etc. Reference herein to a particular instance of a component includes reference to the base reference number and the corresponding instance identifier (e.g., an instance of widget ZZZ-2).

[0030] FIG. 1 is a schematic diagram of a process tool 100 for semiconductor processing according to some embodiments. FIG. 1 includes X, Y, and Z axes for simplified illustration of various directions, and such axes are reproduced according to the directions in other figures. The process tool 100 in FIG. 1 is depicted in a simplified manner so as not to obscure various aspects described herein. Those skilled in the art will readily appreciate other aspects of the process tool 100. In this embodiment, the process tool 100 is depicted as a capacitively coupled plasma (CCP) process tool. In other embodiments, the process tool 100 may be configured as an inductively coupled plasma (ICP) process tool, an electron cyclotron resonance (ECR) process tool, or another process tool. Those skilled in the art will readily appreciate that aspects described herein are applicable to such other process tools. The process tool 100 may be for performing plasma semiconductor processes such as sputtering, physical vapor deposition (PVD), modified double plasma (MDP), plasma enhanced chemical vapor deposition (PECVD), ion beam etching (IBE), reactive ion etching (RIE), and other processes. The substrate to be processed may be a semiconductor wafer, a solar panel, a display panel, and / or other material.

[0031] The process apparatus 100 includes a chamber 102. The chamber 102 has an interior volume 104 defined by the interior walls of the chamber 102. The process apparatus 100 includes a substrate support 106 disposed within the interior volume 104 of the chamber 102. The substrate support 106 includes an electrostatic chuck (ESC) 108, a heater 110, and a base plate 112. In the illustrated configuration, the heater 110 is disposed above and in contact with the base plate 112, and the ESC 108 is disposed above and in contact with the heater 110. The substrate support 106 is disposed on and supported by a pedestal 114. The base plate 112 is disposed above and in contact with the pedestal 114. The substrate support 106 has a support surface 116 configured to support a semiconductor substrate 120 during semiconductor processing. During semiconductor processing, the semiconductor substrate 120 is disposed on the support surface 116 of the substrate support 106. In the illustration of FIG. 1, the support surface 116 is in the xy plane.

[0032] The ESC 108 includes n RF electrodes 130. As described in more detail below, the RF electrodes 130 are configured to have an RF voltage signal applied thereto, and may also have a direct current (DC) voltage applied thereto. The ESC 108 may include a dielectric material covering the RF electrodes 130 to electrically insulate direct contact between the RF electrodes 130. The dielectric material may be or include aluminum oxide (Al2O3), yttrium oxide (YO3), silicon oxide (SiO2), or the like, or a combination thereof. The RF electrodes 130 may be or include any metal, such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), or a combination thereof. Various arrangements and configurations of the RF electrodes 130 are illustrated in the following figures.

[0033] The heater 110 includes one or more resistive heating elements 134 disposed in a dielectric, thermally conductive material. An electrical current can be passed through the one or more resistive heating elements 134, thereby generating thermal energy that is conducted to the semiconductor substrate 120.

[0034] The base plate 112 includes a bias electrode 136 and a fluid channel 138. In this embodiment, the base plate 112 includes a single bias electrode 136, but as will be described in detail in subsequent embodiments, the base plate 112 may also include multiple bias electrodes. The bias electrode 136 may have a dielectric material thereon to electrically insulate the bias electrode 136 from direct contact with other components. The fluid channel 138 is disposed embedded in the bias electrode 136. The fluid channel 138 is configured to allow a fluid (e.g., a liquid) to flow therethrough to remove and dissipate thermal energy from the semiconductor substrate 120. The fluid channel 138 may also be referred to as a cooler.

[0035] The process apparatus 100 further includes a gas distribution plate 140 and a gas showerhead 142 disposed within the interior volume 104 of the chamber 102. The gas distribution plate 140 has an opening therethrough, and the gas showerhead 142 also has an opening therethrough. The gas distribution plate 140 and the gas showerhead 142 are electrically connected to a ground node (e.g., electrically grounded). The chamber 102 has a gas inlet 144 fluidly connected to a gas supply system 146 and a gas outlet 148 fluidly connected to an exhaust system 150. The gas distribution plate 140 and the gas showerhead 142 are disposed within the interior volume 104 of the chamber 102 relative to the substrate support 106 such that, during semiconductor processing, gas flows from the gas supply system 146 through the gas inlet 144, through the openings through the gas distribution plate 140, and then through the openings through the gas showerhead 142 to a process volume 152 within the interior volume 104. The process volume 152 is located between the gas showerhead 142 and the substrate support 106 and is typically where a plasma is generated (using a flow of gas into the process volume 152) during semiconductor processing. A semiconductor substrate 120 disposed on the support surface 116 of the substrate support 106 is exposed to the plasma in the process volume 152 during semiconductor processing. The gases then flow through the gas outlet 148 to an exhaust system 150 where they can be exhausted from within the interior volume 104 of the chamber 102.

[0036] The process tool 100 includes a power system including an RF power supply system 160, n RF signal control circuits 164, a DC power supply 170, n isolation filters 172, and n analog summer / summing circuits 174. The RF power supply system 160 may include an RF generator and an RF matching network and is configured to generate and output an RF signal, which may be a continuous RF signal and / or a pulsed RF signal, at an output node of the RF power supply system 160. The output node of the RF power supply system 160 is electrically connected to an input node of the RF signal control circuits 164. As described in more detail below, each RF signal control circuit 164 is individually or independently controllable to generate a conditioned RF signal based on the RF signal received from the RF power supply system 160. The conditioned RF signal generated by the RF signal control circuits 164 may have an conditioned amplitude of the received RF signal (e.g., may have a magnitude greater than 1, less than 1, depending on the gain of the RF signal control circuit 164) and / or may have a phase offset from the received RF signal. The gain and / or phase offset may be selectable from a range of gains and / or phase offsets that each RF signal control circuit 164 is configured to implement. Each RF signal control circuit 164 has an output node electrically connected to a first input node of a corresponding analog summer / summing circuit 174. The DC power supply 170 is configured to generate and output a DC voltage at the output node of the DC power supply 170. The output node of the DC power supply 170 is electrically connected to a respective input node of the isolation filter 172, and the output node of the isolation filter 172 is electrically connected to a respective second input node of the analog summer / summing circuit 174. Each isolation filter 172 is configured to suppress time-varying signals, such as RF signals. Each isolation filter 172 may be, for example, a low-pass filter.Each analog summer / summing circuit 174 is configured to sum or add the conditioned RF signal from a respective RF signal control circuit 164 to a DC voltage from a respective isolation filter 172 and DC power supply 170, and output a resulting RF / DC signal at an output node of the respective analog summer / summing circuit 174. Each analog summer / summing circuit 174 is electrically connected to a respective RF electrode 130 of the ESC 108.

[0037] During operation, the RF / DC signal output by a given analog summer / summing circuit 174 is applied to the respective RF electrode 130 to which the analog summer / summing circuit 174 is electrically connected. The DC component of the RF / DC signal (generated by the DC power supply 170) can be used to chuck the semiconductor substrate 120 onto the support surface 116 of the substrate support 106. The RF component of the RF / DC signal (output by the corresponding RF signal control circuit 164) can be used to generate and / or control a plasma in the process volume 152. By providing multiple RF electrodes 130, each with a corresponding independently controllable RF signal control circuit 164 to generate the RF component of the RF / DC signal, the RF signal for generating and controlling the plasma can be different at different locations on the substrate support 106. By enabling different RF signals at different locations, the plasma can be locally controlled to facilitate improved uniformity, and therefore, improved uniformity of the resulting structures formed by the semiconductor process. For clarity, as used herein, an RF / DC signal may include a DC component without an RF component (and vice versa). However, in some embodiments, the RF / DC signal includes both an RF component and a DC component.

[0038] The process tool 100 includes an RF power system 180. The RF power system 180 may include an RF generator and an RF matching network and is configured to generate and output an RF signal, which may be a continuous RF signal and / or a pulsed RF signal, at an output node of the RF power system 180. The output node of the RF power system 180 is electrically connected to a bias electrode 136 of the base plate 112. The base plate 112 may be strongly capacitively coupled to the RF electrode 130 in the ESC 108 in this embodiment. Therefore, according to some embodiments, the base plate 112 is biased by the RF signal output by the RF power system 180 to improve the operability of the RF electrode 130 to generate plasma.

[0039] In some embodiments, the RF power system 180 can operate at the same frequency as the RF power system 160. During operation, the RF power system 180 outputs an RF signal having a target amplitude and a target phase offset relative to the RF component of the RF / DC signal applied to the RF electrode 130. In some embodiments, the RF signal output by the RF power system 180 has an amplitude that is the average amplitude of the RF component of the RF / DC signal applied to the RF electrode 130. Furthermore, in some embodiments, the RF signal output by the RF power system 180 has a phase offset that allows the RF signal to be in phase with the average RF component of the RF / DC signal. Applying such an RF signal to the bias electrode 136 of the base plate 112 can improve the operability of the RF electrode 130 for generating and controlling a plasma. In some embodiments, the RF power system 180 can operate at a different frequency than the frequency of the RF power system 160 to provide dual-frequency operation of the plasma process. For example, the RF power system 180 may operate at a lower frequency than the frequency of the RF power system 160. The power of the lower frequency RF field may couple more to the plasma sheath compared to the higher frequency RF. Such dual frequency operation allows for adjustment of the division of RF power delivered to the plasma sheath and the main plasma. This allows for relatively separate control of plasma density and ion energy at the substrate.

[0040] The process tool 100 includes a controller 190. The controller 190 may be or include any processor-based system that is or may be a hardened processor architecture, a soft processor (e.g., implemented on the programmable fabric of a Field Programmable Gate Array (FPGA)), or a combination thereof. For example, the controller 190 may be or include a computer, a server, a programmable logic controller (PLC), or the like, or a combination thereof. The controller 190 may control the operation of the process tool 100 and may be programmed to perform the operations of the process tool 100 as described herein. Among other things, the controller 190 is communicatively coupled to the RF signal control circuitry 164. The controller 190 may be programmed to implement various settings for controlling the RF signal control circuitry 164.

[0041] 1 as being implemented to generate a plasma in the chamber 102, the RF electrode 130 may also be a bias electrode on a substrate support in other process tools, such as an ICP process tool. The embodiments described herein may be applied to other tools and configurations for controlling a plasma.

[0042] 2, 3, 4, 5, and 6 are layout diagrams of arrangements 200, 300, 400, 500, and 600 of RF electrodes 230, 330, 430, 530, and 630, respectively, according to some embodiments. The RF electrodes 130 in the ESC 108 of FIG. 1 can have any of the arrangements 200, 300, 400, 500, and 600 shown in FIGS. 2, 3, 4, 5, and 6, or any other arrangement. The arrangements 200, 300, 400, 500, and 600 are shown in an xy plane parallel to the support surface 116 that supports the semiconductor substrate 120. The edges 202, 302, 402, 502, and 602 of each of the arrangements 200, 300, 400, 500, and 600 are circular and coincident with (e.g., vertically aligned with) the edges of the support surface 116 of the substrate support 106. Other shapes of the edges 202, 302, 402, 502, 602 may also be implemented. The centers 204, 304, 404, 504, 604 of the respective arrangements 200, 300, 400, 500, 600 are shown to be coincident with (e.g., vertically aligned with) the center of the support surface 116.

[0043] Referring to FIG. 2 , arrangement 200 includes RF electrodes 230. In some embodiments, arrangement 200 includes between 10 and 200 RF electrodes 230. Layout 200 is a linear grid of RF electrodes 230. In this embodiment, RF electrodes 230 are rectangular (e.g., square) except for the RF electrodes 230 that intersect edge 202. For example, RF electrodes 230-1 and 230-2 at edge 202 have one arc-shaped side and the other straight side. The other RF electrodes 230 (e.g., RF electrodes 230-3 through 230-8) are rectangular (e.g., have straight sides). RF electrodes 230-5, 230-6, 230-7, and 230-8 are shown near center 204 of arrangement 200. A dielectric material 240 is disposed between adjacent RF electrodes 230 to prevent direct electrical contact between the adjacent RF electrodes 230.

[0044] Referring to FIG. 3 , arrangement 300 includes RF electrodes 330. In some embodiments, arrangement 300 includes between 6 and 200 RF electrodes 330. Arrangement 300 is a segmented concentric ring of RF electrodes 330 surrounding a segmented inner circle of RF electrodes 330. In this embodiment, each RF electrode 330 is a segment of a circle or a segment of a concentric ring. For example, each of RF electrodes 330-5, 330-6 near center 304 is a segment of the inner circle (e.g., a semicircle), and each of RF electrodes 330-1, 330-2 at edge 302 is a segment of the outer concentric ring. As shown in FIG. 3 , five concentric rings of RF electrodes 330 surround the segmented inner circle of RF electrodes 330-5, 330-6, and in other embodiments, any number of concentric rings may be implemented. Each RF electrode 330 in a concentric ring is separated from an adjacent RF electrode in that concentric ring in a respective direction perpendicular to the radial direction from the center 304. Each RF electrode 330 in a concentric ring has an inner arcuate side, an outer arcuate side, and opposing straight sides (e.g., extending radially from the center 304). A dielectric material 340 is disposed between adjacent RF electrodes 330 to prevent direct electrical contact between the adjacent RF electrodes 330.

[0045] Referring to FIG. 4 , arrangement 400 includes RF electrodes 430. In some embodiments, arrangement 400 includes between 6 and 200 RF electrodes 430. The arrangement 400 is a series of radially aligned, concentric rings surrounding an inner circle divided into sectors of RF electrodes 430. In this embodiment, each RF electrode 430 is a sector of a circle or a segment of a concentric ring. The segments of the concentric rings are radially aligned with the segments of the inner circle of arrangement 400. In the illustrated embodiment of FIG. 4 , arrangement 400 has 12 sectors (e.g., each sector is 30°). The inner circle and each concentric ring of arrangement 400 has sectors or segments within each of the 12 sectors. Other numbers of sectors may be implemented in other embodiments. As an example, each of the RF electrodes 430-5, 430-6 near the center 404 is a sector of an inner circle, and each of the RF electrodes 430-1, 430-2 at the edge 402 is a segment of an outer concentric ring. In other arrangements, the inner circle of RF electrodes may be a complete circle of a single RF electrode, as opposed to a circle divided into sectors of multiple RF electrodes. Although five concentric rings of RF electrodes 430 (e.g., RF electrodes 430-5, 430-6) are shown in FIG. 4 centered around the inner circle of RF electrodes, any number of concentric rings may be implemented in other embodiments. Each RF electrode 430 is divided from adjacent RF electrodes in each inner circle or concentric ring in a respective direction perpendicular to the radial direction from the center 404. Each RF electrode 430 in the inner circle has straight sides (e.g., extending radially from the center 404) and outer arcuate sides. Each RF electrode 430 in the concentric ring has an inner arcuate side, an outer arcuate side, and opposing straight sides (e.g., extending radially from the center 404). A dielectric material 440 is disposed between adjacent RF electrodes 430 to prevent direct electrical contact between the adjacent RF electrodes 430.

[0046] Referring to FIG. 5 , an arrangement 500 includes RF electrodes 530. In some embodiments, the arrangement 500 includes between 5 and 200 RF electrodes 530. The arrangement 500 is a series of divided concentric rings surrounding a complete inner circle of RF electrodes 530. In this embodiment, the complete inner circle of RF electrodes 530-5 is at the center 504, and each of the other RF electrodes 530 is a divided portion of the concentric ring. Although two concentric rings of RF electrodes 530 are shown in FIG. 5 with the complete inner circle of RF electrodes 530-5 at the center, in other embodiments, any number of concentric rings may be implemented. Each RF electrode 530 in a concentric ring is divided from the adjacent RF electrode 530 in that concentric ring in a respective direction perpendicular to the radial direction from the center 504. The complete inner circle of RF electrodes 530-5 has an outer circumference. Each RF electrode 530 in the concentric ring has an inner arcuate side, an outer arcuate side, and opposing straight sides (e.g., extending radially from the center 504). A dielectric material 540 is disposed between adjacent RF electrodes 530 to prevent direct electrical contact between the adjacent RF electrodes 530.

[0047] 2, 3, 4, and 5, for a given radial direction, different RF electrodes are positioned across an axis parallel to the radial direction of support surface 116 from the center of support surface 116 to the periphery of support surface 116. Such an axis parallel to the radial direction of support surface 116 may be, for example, from center 204, 304, 404, 504 to edge 202, 302, 402, 502 in arrangements 200, 300, 400, 500. For example, with reference to FIG. 2, RF electrodes 230-1, 230-5 are positioned across an axis from center 204 to edge 202 along line 250. Similarly, with reference to FIG. 3, for example, RF electrodes 330-1, 330-6 are positioned across an axis from center 304 to edge 302 along line 350. 4, RF electrodes 430-1, 430-5 are positioned along line 450, intersecting an axis from center 404 to edge 402. Referring to Figure 5, RF electrodes 530-1, 530-5 are positioned along line 550, intersecting an axis from center 504 to edge 502. By positioning different RF electrodes at the center and periphery of support surface 116, different RF signals can be applied at the center and periphery to locally control the plasma and promote plasma uniformity.

[0048] Referring to FIG. 6 , arrangement 600 includes RF electrodes 630. Arrangement 600 is a circle divided into sectors of RF electrodes 630. In this embodiment, each RF electrode 630 is a sector of a circle. In the illustrated embodiment of FIG. 6 , arrangement 600 has 12 sectors (e.g., each sector is 30°). Other numbers of sectors may be implemented in other embodiments. Each RF electrode 630 extends from near a center 604 to an edge 602. Each RF electrode 630 is separated from adjacent RF electrodes in respective directions perpendicular to the radial direction from center 604. RF electrodes 630 have straight sides (e.g., extending radially from center 604) and outer arcuate sides. A dielectric material 640 is disposed between adjacent RF electrodes 630 to prevent direct electrical contact between them.

[0049] FIGS. 7A, 7B, 7C, and 7D are layout diagrams of various RF electrodes of FIGS. 2 through 6 according to some embodiments. The RF electrodes of FIGS. 7A through 7D are shown to illustrate various aspects. FIG. 7A is a layout diagram of RF electrode 730-1, which may be RF electrode 230 intersecting edge 202 of FIG. 2. RF electrode 730-1 has vertices A1, B1, C1, and D1. RF electrode 730-1 has arcuate sides A1-B1, straight sides B1-C1, straight sides C1-D1, and straight sides D1-A1. FIG. 7B is a layout diagram of RF electrode 730-2, which may be RF electrodes 330, 430, and 530, which are divided portions of concentric rings of FIGS. 3, 4, and 5. RF electrode 730-2 has vertices A2, B2, C2, and D2. RF electrode 730-2 has outer arcuate sides A2-B2, straight sides B2-C2, inner arcuate sides C2-D2, and straight sides D2-A2. FIG. 7C is a layout diagram of RF electrode 730-3, which may be RF electrodes 330-5 and 330-6, which are segments of the inner circle in FIG. 3. RF electrode 730-3 has vertices A3 and B3 and arc point C3. The RF electrode has straight sides A3-B3 and arcuate sides A3-C3-B3. FIG. 7D is a layout diagram of RF electrode 730-4, which may be RF electrodes 430 and 630, which are sectors of the circle in FIGS. 4 and 6. RF electrode 730-4 has vertices A4, B4, and C4. RF electrode 730-4 has arcuate sides A4-B4, straight sides B4-C4, and straight sides C4-A4.

[0050] In some embodiments, each lateral dimension of each RF electrode 230, 330, 430, 530, 630 in arrangements 200, 300, 400, 500, 600 is less than 2% of the smallest wavelength of the respective RF signal (and thus the electromagnetic field) applied to the respective RF electrode. In some embodiments, the RF signal may be a multi-frequency RF signal, and therefore the smallest wavelength may be the RF signal with the highest frequency in the multi-frequency RF signal.

[0051] In some embodiments, each lateral dimension of each RF electrode 230, 330, 430, 530, 630 in arrangements 200, 300, 400, 500, 600 is less than 221.1 mm, more particularly less than 199.9 mm, and even more particularly less than 99.9 mm. In some embodiments, each lateral dimension of each RF electrode 230, 330, 430, 530, 630 in arrangements 200, 300, 400, 500, 600 ranges from greater than 50.0 mm to less than 221.1 mm, more particularly from greater than 50.0 mm to less than 199.9 mm, and even more particularly from greater than 50.0 mm to less than 99.9 mm. Figures 7A through 7D show the sides of an exemplary RF electrode 730. Furthermore, the sides, if present, may include the circumferential sides of a fully circular RF electrode, such as RF electrode 530-5 in FIG. 5, and the linear sides of a rectangular RF electrode, such as RF electrode 330-5 in FIG. 3. Providing the sides with such dimensions may reduce plasma non-uniformity caused by wavelength effects and may also reduce electromagnetic field oscillations. For process materials other than semiconductor wafers, the size and shape of the substrate support and the frequency of the RF electromagnetic field may vary. The method of using multiple RF electrodes with dimensions of 2% or less of the RF wavelength to reduce wavelength-induced non-uniformity is still applicable.

[0052] Figure 8 is a schematic diagram of a process apparatus 800 for semiconductor processing in accordance with some embodiments. The process apparatus 800 of Figure 8 is a variation of the process apparatus 100 of Figure 1, and therefore like reference numerals in the figures refer to like components. A description of like components will not be provided here for the sake of brevity.

[0053] The base plate 112 of the substrate support 106 of the process apparatus 800 includes n bias electrodes 836. The arrangement of the bias electrodes 836 in the base plate 112 corresponds to the arrangement of the RF electrodes 130 in the ESC 108. For example, each bias electrode 836 may generally have the same shape as the corresponding RF electrode 130 and be aligned vertically (e.g., in the z-direction).

[0054] The process device 800 further includes n RF bias control circuits 888. Each RF bias control circuit 888 has an input node electrically connected to an output node of the RF power supply system 180. Similar to the RF signal control circuit 164, each RF bias control circuit 888 is individually or independently controllable to generate an conditioned RF signal based on the RF signal received from the RF power supply system 180. The conditioned RF signal generated by the RF bias control circuit 888 may have an conditioned amplitude of the received RF signal (e.g., may have a magnitude greater than, equal to, or less than 1, depending on the gain of the RF bias control circuit 888) and / or may have a phase offset from the received RF signal. The gain and / or phase offset may be selectable from a range of gains and / or phase offsets that the respective RF bias control circuit 888 is configured to implement. Each RF bias control circuit 888 has an output node electrically connected to a respective bias electrode 836.

[0055] During operation, RF power supply system 180 outputs an RF bias signal to RF bias control circuit 888. The RF bias signal may be generated based on the RF signal output by RF power supply system 180 and may be frequency, phase, and amplitude matched by an RF matching network of RF power supply system 180, for example, according to the RF signal output by RF power supply system 160. RF bias control circuit 888 adjusts the RF bias signal such that each adjusted RF bias signal has a target gain and a target phase offset. The adjusted RF bias signal is output by each RF bias control circuit 888 to each bias electrode 836. The adjusted RF bias signal output by each RF bias control circuit 888 may have an amplitude and phase offset corresponding to the RF signal output by the corresponding RF signal control circuit 164. For example, the adjusted RF bias signal output by RF bias control circuit 888-1 may have an amplitude and phase offset corresponding to the RF signal output by RF signal control circuit 164-1, and the adjusted RF bias signal output by RF bias control circuit 888-n may have an amplitude and phase offset corresponding to the RF signal output by RF signal control circuit 164-n.

[0056] By providing multiple bias electrodes 836, each with a corresponding independently controllable RF bias control circuit 888 for generating an adjusted RF bias signal, the RF bias signal for biasing the substrate support 106 can be different at different locations on the substrate support 106. By allowing for different RF bias signals at different locations, the steerability of the RF electrodes 130 can be more precise and enhanced to facilitate improved plasma uniformity, and therefore improved uniformity of the resulting structures formed by the semiconductor process.

[0057] Figure 9 is a schematic diagram of a process apparatus 900 for semiconductor processing in accordance with some embodiments. The process apparatus 900 of Figure 9 is a variation of the process apparatus 100 of Figure 1, and therefore like reference numerals in the figures refer to like components. A description of like components will not be provided here for the sake of brevity.

[0058] The substrate support 106 further includes an intermediate plate 902. In the illustrated configuration, the heater 110 is disposed above and in contact with the base plate 112, the intermediate plate 902 is disposed above and in contact with the heater 110, and the ESC 108 is disposed above and in contact with the intermediate plate 902. The ESC 108 includes a chuck electrode 904. The chuck electrode 904 is configured to have a DC voltage applied thereto for chucking. The ESC 108 may include a dielectric material covering the chuck electrode 904 to electrically insulate direct contact between the chuck electrodes 904. The intermediate plate 902 includes n RF electrodes 130. As described above, the RF electrodes 130 are configured to have an RF voltage signal applied thereto. The intermediate plate 902 may include a dielectric material covering the RF electrodes 130 to electrically insulate direct contact between the RF electrodes 130.

[0059] Output nodes (e.g., a positive output node and a negative output node) of the DC power supply 170 are electrically connected to input nodes of the isolation filter 172, and the output nodes of the isolation filter 172 are electrically connected to respective chucking electrodes 904. The isolation filter 172 may be, for example, a low-pass filter. The DC power supply 170 may be selectively turned on and off to chuck and release the semiconductor substrate 120.

[0060] Each RF signal control circuit 164 has an output node electrically connected to a corresponding RF electrode 130. In the process apparatus 900 of Figure 9, a respective RF signal may be applied to the RF electrode 130 (e.g., to generate and / or control a plasma), while a DC voltage may be applied to the chuck electrode 904 (e.g., to check a semiconductor substrate).

[0061] In some embodiments, the process apparatus may be similar to the process apparatus 900 of FIG. 9 except that it includes a base plate 112 that includes n bias electrodes 836, and an RF power system 180 and an RF bias control circuit 888 as described with respect to the process apparatus 800 of FIG. 8.

[0062] 10 is a schematic diagram of an RF power system 1000 of the process tool 100, 800, 900 according to some embodiments. The RF power system 1000 includes an RF power supply system 160, an RF signal control circuit 164, an analog summer / summing circuit 174, and an RF electrode 130. Each RF signal control circuit 164 includes a respective voltage / power control circuit 1002 and a respective phase control circuit 1004. For example, RF signal control circuit 164-1 includes a voltage / power control circuit 1002-1 and a phase control circuit 1004-1, and RF signal control circuit 164-n includes a voltage / power control circuit 1002-n and a phase control circuit 1004-n. Each voltage / power control circuit 1002 has an input node that is an input node of the respective RF signal control circuit 164 and is electrically connected to an output node of the RF power supply system 160. Each voltage / power control circuit 1002 has an output node that is electrically connected to the input node of the respective phase control circuit 1004. Each phase control circuit 1004 has an output node that is an output node of a respective RF signal control circuit 164 and is electrically connected to a first input node of a respective analog summer / summing circuit 174. The voltage / power control circuit 1002 and phase control circuit 1004 of each RF signal control circuit 164 are communicatively connected to, for example, a controller 190 that receives one or more set points for each RF signal control circuit 164. The set points are digital numbers or codes that selectively configure the gain of the voltage / power control circuit 1002 and the phase offset of the phase control circuit 1004.

[0063] In some embodiments, the voltage / power control circuit 1002 may include an amplifier and a selectively configurable impedance network configured to receive an RF signal and output an RF signal whose gain is adjusted relative to the received RF signal. The selectively configurable impedance network may include, for example, several switching resistors connected in parallel. For example, the switching resistor may include a resistor electrically connected in series with a channel of a transistor. A signal, which may be a bit of a set value or a bit obtained by decoding the set value, may be applied to the gate of the transistor to selectively make the channel of the transistor conductive or non-conductive, for example. By selectively electrically connecting and / or disconnecting resistors in parallel, the gain of the voltage / power control circuit 1002 may be selectively configured. Those skilled in the art will readily understand the configuration of the voltage / power control circuit 1002 and how such a voltage / power control circuit 1002 may be selectively configurable to achieve different gains (which may be by using any combination of impedance elements, such as resistors, capacitors, and / or inductors).

[0064] Similarly, in some embodiments, the phase control circuit 1004 may include an amplifier and a selectively configurable impedance network configured to receive an RF signal and output an RF signal with an adjusted phase offset relative to the received RF signal. The selectively configurable impedance network may include several parallel-connected switching impedance elements, including, for example, resistors, capacitors, and / or inductors. A signal, which may be a setpoint bit or a bit obtained by decoding the setpoint value, may be applied to a transistor gate, for example, to selectively turn the transistor channel on or off. Selectively electrically connecting and / or disconnecting the impedance elements in parallel may selectively configure the phase offset of the phase control circuit 1004. Those skilled in the art will readily understand the configuration of the phase control circuit 1004 and how such a phase control circuit 1004 may be selectively configurable to achieve different phase offsets.

[0065] FIG. 11 is a schematic diagram of an RF power system 1100 that may be implemented with process tools 100, 800, 900 according to some embodiments. The RF power system 1100 of FIG. 11 is a variation of the RF power system 1000 of FIG. 10. The RF power system 1100 is a multi-frequency RF power system. The RF power system 1100 includes p RF power supply systems, two of which (e.g., RF power supply systems 160-1 and 160-2) are shown. Each RF power supply system 160 is configured to generate an RF signal at a target frequency, and the target frequencies of each RF power supply system 160 may be different. For example, the target frequency of RF power supply system 160-1 may be 13.56 MHz, and the target frequency of RF power supply system 160-2 may be 60 MHz.

[0066] The RF power system 1100 includes n RF signal control circuits 164 for each RF power supply system 160. In total, the RF power system 1100 includes (n×p) RF signal control circuits 164. Each RF signal control circuit 164 is labeled with the symbol "-ij," where i designates which RF electrode 130 is associated with the given RF signal control circuit 164 and j designates which RF power supply system is associated with the given RF signal control circuit 164. Each RF signal control circuit 164 includes a voltage / power control circuit 1002 and a phase control circuit 1004, and is configured as described above with respect to FIG. 10.

[0067] For each RF power system 160, the output node of the respective RF power system 160 is electrically connected to input nodes of n RF signal control circuits 164 associated with that RF power system 160. Each RF signal control circuit 164 has an output node electrically connected to an input node of a respective RF isolation filter 1102 (labeled similarly to the RF signal control circuit 164). Each RF isolation filter 1102 is configured to pass an RF signal having a target frequency of the RF signal generated by the associated RF power system 160. Each RF isolation filter 1102 may reject or attenuate any signals other than those at the target frequency. For example, the RF isolation filter 1102 may be a bandpass filter primarily targeted at the frequency of the RF signal generated by the associated RF power system 160.

[0068] The RF power system 1100 includes n analog summer / summing circuits 1074. Each analog summer / summing circuit 1074 has (p+1) input nodes and is associated with a respective RF electrode 130. An output node of each RF isolation filter 1102 associated with a given RF electrode 130 is electrically connected to a respective input node of the analog summer / summing circuit 1074 associated with that given RF electrode 130. Furthermore, a respective input node of each analog summer / summing circuit 1074 is electrically connected to an output node of a DC power supply 170. Each analog summer / summing circuit 1074 is configured to sum the p RF signals received from the respective RF isolation filters 1102 and a DC voltage received from the DC power supply 170 to generate an RF / DC signal. Each analog summer / summing circuit 1074 has an output node electrically connected to the RF electrode 130 associated with that analog summer / summing circuit 1074. The RF / DC signal generated by the analog summer / summing circuit 1074 is output at an output node to the RF electrode 130. By providing multiple RF power systems 160 generating RF signals at different frequencies, the RF / DC signal can include multiple RF components that are applied to the RF electrode 130. Other aspects of the RF power system 1100 will be apparent to those skilled in the art in light of the foregoing description, including the description of the RF power system 1000 of FIG.

[0069] 12 illustrates a processor-based system 1200 according to some embodiments. The processor-based system 1200 may be or include a computer, a server, a programmable logic controller (PLC), or the like, or a combination thereof. The processor-based system 1200 may be implemented as the controller 190 or any other processor-based system that performs any of the operations described herein. The processor-based system 1200 includes one or more processors 1202, a memory system 1212, a communication bus 1222, one or more input / output (I / O) interfaces 1232, and a network interface 1242.

[0070] Each processor 1202 may include one or more processor cores 1204. Each processor 1202 and / or processor core 1204 may be, for example, a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP), an enhanced processor such as an application specific integrated circuit (ASIC), or a combination thereof, or a soft processor implemented in programmable logic such as a field programmable gate array (FPGA).

[0071] The memory system 1212 includes one or more memory controllers 1214 and memories 1216. The memory controller 1214 is configured to control read and / or write access to a particular memory 1216 or a subset of the memory 1216. The memory 1216 may include main memory, disk storage, or any suitable combination thereof. The memory 1216 may include any type of volatile or non-volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state storage, etc. The memory 1216 is a non-transitory machine-readable storage medium. Instructions 1218 are stored in the memory 1216. The instructions 1218 may be machine-executable code (e.g., machine code) and may include firmware, software, programs, applications, or other machine-executable code. The instructions 1218 may embody, for example, software modules 1220, which, when executed by the one or more processors 1202, perform various functions and operations described herein.

[0072] The one or more I / O interfaces 1232 are configured to be electrically and / or communicatively coupled to one or more I / O devices 1234. The I / O devices 1234 include the RF signal control circuit 164 and, if applicable, the RF bias control circuit 888. The RF signal control circuit 164 and the RF bias control circuit 888 can receive their respective settings via the I / O interface 1232. Other exemplary I / O devices 1234 include a keyboard, a mouse, a display device, a printer, etc. The one or more I / O interfaces 1232 can include connectors or coupling circuits such as an industrial application connection, a Universal Serial Bus (USB) connection, a High-Definition Multimedia Interface (HDMI) connection, a Bluetooth® circuit, etc.

[0073] Network interface 1242 is configured to be communicatively coupled to network 1244. Network interface 1242 can include circuitry for wired communication, such as an Ethernet connection, and / or can include circuitry for wireless communication, such as circuitry for Wi-Fi® communication. For example, one or more computers and / or servers communicatively coupled to network 1244 may communicate recipes, process conditions, etc. to processor-based system 1200 via network 1244 and network interface 1242.

[0074] The communication bus 1222 is communicatively coupled to one or more processors 1202, the memory system 1212, one or more I / O interfaces 1232, and the network interface 1242. The various components may communicate with one another via the communication bus 1222. The communication bus 1222 may control the flow of communication, such as by including an arbiter that arbitrates communications.

[0075] 13 is a flowchart of a method 1300 of semiconductor processing according to some embodiments. The method 1300 can be implemented using the process tools 100, 800, 900 described above. Operation of the method 1300 can be initiated and / or controlled by the controller 190 (e.g., by execution of instructions 1218 by one or more processors 1202). At block 1302, the semiconductor substrate 120 is transferred into the chamber 102 of the process tool 100, 800, 900 and placed on a substrate support 106 (e.g., the ESC 108) within the chamber 102. The substrate support 106 (e.g., the ESC 108 or the middle plate 902) includes n RF electrodes 130 as described above. The semiconductor substrate 120 may be secured to the substrate support 106 by applying a DC voltage to the RF electrode 130 in the process apparatus 100, 800 of Figures 1 or 8, or by applying a DC voltage to the chucking electrode 904 (e.g., to chuck the semiconductor substrate 120) in the process apparatus 900 of Figure 9. In the process apparatus 100, 800 of Figures 1 or 8, the DC voltage may be applied to the RF electrode 130 using a respective RF / DC signal, as described above, which may not include an RF component when the semiconductor substrate 120 is initially secured to the ESC 108.

[0076] At block 1304, a plasma semiconductor process is performed in the chamber 102 of the process tool 100, 800, 900. The plasma semiconductor process can be, for example, an etching process, a deposition process, or any other applicable process. Exemplary plasma semiconductor processes include sputtering, PVD, MDP, PECVD, IBE, and RIE. Block 1304 includes, at block 1306, generating a plasma in the process volume 152 of the chamber 102. The semiconductor substrate 120 can be exposed to the plasma in the process volume 152. The plasma can be generated by flowing gases into the chamber 102 (e.g., from the gas supply system 146 through the gas inlet 144, the gas distribution plate 140, and the gas showerhead 142) and applying respective RF / DC signals (each of which includes an RF component) or respective RF signals to the RF electrode 130. The plasma can be generated as a result of the RF component or RF signal when the RF electrode 130 and the gas showerhead 142 are grounded. Block 1304 further includes, in block 1308, controlling the plasma by adjusting the amplitude and / or phase of the RF signal applied to the RF electrode 130 of the substrate support 106. While described separately for ease of reference, blocks 1306 and 1308 can be implemented by the same operation. In some embodiments, controlling the plasma can control the plasma at the periphery of the semiconductor substrate 120 compared to the center of the semiconductor substrate 120. In some embodiments, the plasma can be controlled differently between the center and periphery of the semiconductor substrate 120 by applying RF / DC signals having different respective RF components or different respective RF signals to different RF electrodes 130 at and near the edge of the semiconductor substrate 120 and near the center of the semiconductor substrate 120. The different RF components or signals can be implemented by selectively configuring the RF signal control circuitry 164 to generate respective adjusted RF signals, which may have different amplitudes, phase offsets, or any permutation thereof.The RF signal control circuitry 164 may be selectively configured according to settings communicated to the RF signal control circuitry 164 from the controller 190. Additionally, biasing the bias electrodes 136, 836 may be performed during blocks 1306, 1308. The biasing may include applying an RF bias signal to a single bias electrode 136, such as in the process tool 100, or applying respective RF bias signals to multiple bias electrodes 836, such as in the process tool 800.

[0077] In block 1310, the plasma semiconductor process is terminated and the semiconductor substrate 120 is transferred from within the chamber 102 of the process tool 100, 800, 900 to an outside location. At the end of the plasma semiconductor process, the DC / RF signal or the RF component of the RF signal may be stopped from being applied to the RF electrode 130 (e.g., the RF power supply system 160 is turned off), and gas may be stopped from being supplied to the chamber 102 and may be evacuated from within the chamber 102 to an outside location. In addition, the RF bias signal may be stopped from being applied to the bias electrode 136, 836. The DC component of the RF / DC signal may also be stopped (e.g., by turning off the DC power supply 170) to release the semiconductor substrate 120 from the ESC 108. The semiconductor substrate 120 may then be transferred from within the chamber 102 to an outside location.

[0078] 14 is a flowchart of a method 1400 for semiconductor processing according to some embodiments. At block 1402, a plasma semiconductor process, such as that described with respect to FIG. 13, is performed on a first plurality of semiconductor substrates (e.g., one or more lots of semiconductor substrates) using the process tool 100, 800, 900. The plasma process is performed at first process conditions. The first process conditions include settings for the RF signal control circuit 164 and, if applicable, settings for the RF bias control circuit 888. Based on these settings, an RF / DC signal or an RF component of an RF signal is applied to each RF electrode 130 during the plasma semiconductor process, and an RF signal is applied to the bias electrode 136, 836 during the plasma semiconductor process.

[0079] At block 1404, a first characteristic of each of the first plurality of semiconductor substrates corresponding to a respective position of a first one or more RF electrodes 130 of the RF electrodes 130 during the plasma semiconductor process is measured, and at block 1406, a second characteristic of each of the first plurality of semiconductor substrates corresponding to a respective position of a second one or more RF electrodes 130 of the RF electrodes 130 during the plasma semiconductor process is measured. The positions of the first one or more RF electrodes 130 are different from the positions of the second one or more RF electrodes 130. In some embodiments, the first positions may be near a center of each of the first plurality of semiconductor substrates during the plasma semiconductor process, and the second positions may be near an edge of each of the first plurality of semiconductor substrates during the plasma semiconductor process. The first and second characteristics may be the same feature or component, and "first" and "second" are used for ease of reference. The measurements may be performed by a metrology device. In some embodiments, the first and second characteristics may be or include a profile angle of a recess etched by the plasma semiconductor process. In some embodiments, the first and second properties may be or include a depth of a recess etched by the plasma semiconductor process. In some embodiments, the first and second properties may be or include a thickness of a film deposited by the plasma semiconductor process. Other properties may be measured. Variation between the first property and the second property may indicate non-uniformity of the plasma during the plasma semiconductor process as the first plurality of substrates are processed.

[0080] At block 1408, one or more processor-based systems are used to determine second process conditions to be applied in the process tool while the plasma semiconductor process is performed on the second plurality of semiconductor substrates. The second process conditions are determined based on the first and second characteristics measured in blocks 1404 and 1406, such as a difference between the first and second characteristics. The second process conditions are of the same type as the first process conditions, but the values ​​or data of the first and second process conditions may be different. As an example, a processor-based system running an Advanced Process Control (APC) algorithm may determine the amplitude and phase offset of the RF component of the DC / RF signal or RF signal applied to each RF electrode 130, as well as the amplitude and phase offset of the RF bias signal applied to each bias electrode 136, 836. The processor-based system running the APC algorithm may then determine settings for the RF signal control circuit 164 and, if applicable, the RF bias control circuit 888.

[0081] At block 1410, second process conditions are applied to a process tool for a plasma semiconductor process. For example, a processor-based system running an APC algorithm may communicate the second process conditions to the controller 190 (e.g., via the network 1244). The controller 190 may reset a recipe for the plasma semiconductor process to have the second process conditions and communicate the second process conditions (e.g., set points) to the RF signal control circuitry 164 and, if applicable, the RF bias control circuitry 888, so that these circuits are selectively configured based on the second process conditions.

[0082] At block 1412, a plasma semiconductor process is performed on a second plurality of semiconductor substrates using the process tool 100, 800, 900. The plasma process is performed at second process conditions. Based on the setpoints of the second process conditions, an RF component of an RF / DC signal is applied to the RF electrode 130 during the plasma semiconductor process, and an RF bias signal is applied to the bias electrode 136, 836 during the plasma semiconductor process.

[0083] A first embodiment is a process apparatus for semiconductor processing. The process apparatus includes a chamber and a substrate support. The chamber has an internal volume therein. The substrate support is disposed within the internal volume of the chamber. The substrate support includes a support surface configured to support a semiconductor substrate within the internal volume of the chamber. The substrate support includes a plurality of radio frequency (RF) electrodes. Each RF electrode of the plurality of RF electrodes has a lateral dimension that is 2% or less of a wavelength of an RF signal applied to the respective RF electrode. Each dimension lies in a plane parallel to the support surface. The plurality of RF electrodes are configured to at least partially control a plasma within the internal volume of the chamber.

[0084] In the process apparatus of the first embodiment, each RF electrode of the plurality of RF electrodes may be configured to have a voltage applied thereto independent of each other voltage applied to each other RF electrode of the plurality of RF electrodes.

[0085] In the process apparatus of the first embodiment, the plurality of RF electrodes may be further configured to have a direct current (DC) voltage applied thereto to chuck the semiconductor substrate onto the support surface.

[0086] In the process apparatus of the first embodiment, the substrate support may include an electrostatic chuck. The electrostatic chuck may include multiple RF electrodes. The substrate support may further include a base plate below the electrostatic chuck, and the base plate may have a single bias electrode configured to apply a bias RF signal thereto.

[0087] In the process apparatus of the first embodiment, the substrate support may include an electrostatic chuck, and the electrostatic chuck may include a plurality of RF electrodes. The substrate support may further include a base plate below the electrostatic chuck, and the base plate may include a plurality of bias electrodes. Each bias electrode of the plurality of bias electrodes may be configured to have a respective bias signal applied thereto independently of other bias signals applied to other bias electrodes of the plurality of bias electrodes.

[0088] The process apparatus of the first embodiment may further include an RF power system and multiple RF signal control circuits. The RF power system may be configured to output an RF signal at an output node of the RF power system. Each RF signal control circuit of the multiple RF signal control circuits may have an input node electrically connected to the output node of the RF power system and may have an output node electrically connected to a respective one of the multiple RF electrodes. Each RF signal control circuit of the multiple RF signal control circuits may be controllable to adjust the amplitude and phase of an RF signal to output a corresponding adjusted RF signal at the output node of the respective RF signal control circuit. In addition, the process apparatus may include a controller. The controller may include one or more processors and non-transitory memory. The non-transitory memory may include stored instructions that, when executed by the one or more processors, cause the one or more processors to control the multiple RF signal control circuits to adjust their respective amplitudes and respective phases.

[0089] In the process apparatus of the first embodiment, the plurality of RF electrodes may be arranged in a linear grid.

[0090] In the process apparatus of the first embodiment, the multiple RF electrodes may be arranged in divided concentric rings surrounding a divided inner circle.

[0091] In the process apparatus of the first embodiment, the plurality of RF electrodes may be arranged in radially aligned divided concentric rings surrounding an inner circle divided into sectors.

[0092] In the process apparatus of the first embodiment, the multiple RF electrodes may be arranged in divided concentric rings surrounding a complete inner circle.

[0093] In the process apparatus of the first embodiment, a plurality of RF electrodes may be arranged in a circle divided into sectors.

[0094] In the process apparatus of the first embodiment, each of the plurality of RF electrodes may have a side dimension of 221.1 millimeters or less, and each dimension may be in a plane parallel to the support surface.

[0095] In the process apparatus of the first embodiment, each of the plurality of RF electrodes may have a side dimension of 199.9 millimeters or less, and each dimension may be in a plane parallel to the support surface.

[0096] In the process apparatus of the first embodiment, each of the RF electrodes may have a side dimension ranging from 50.0 millimeters to 221.1 millimeters, and each dimension may be in a plane parallel to the support surface.

[0097] In the process apparatus of the first embodiment, each of the RF electrodes may have a side dimension ranging from 50.0 millimeters to 199.9 millimeters, and each dimension may be in a plane parallel to the support surface.

[0098] A second embodiment is a process apparatus for semiconductor processing. The process apparatus includes a chamber and a substrate support. The chamber has an internal volume therein. The substrate support is disposed within the internal volume of the chamber. The substrate support includes a support surface configured to support a semiconductor substrate within the internal volume of the chamber. The substrate support includes a plurality of radio frequency (RF) electrodes configured to at least partially control a plasma within the internal volume of the chamber. A first RF electrode of the plurality of RF electrodes is disposed near a center of the support surface, and a second RF electrode of the plurality of RF electrodes is disposed near a periphery of the support surface. The first RF electrode and the second RF electrode laterally intersect an axis parallel to a radial direction of the support surface between the center and the periphery of the support surface.

[0099] In the process apparatus of the second embodiment, each RF electrode of the plurality of RF electrodes may be configured to have a voltage applied thereto independent of each other voltage applied to each other RF electrode of the plurality of RF electrodes.

[0100] In the process apparatus of the second embodiment, the plurality of RF electrodes may be further configured to have a direct current (DC) voltage applied thereto to chuck the semiconductor substrate onto the support surface.

[0101] In the process apparatus of the second embodiment, the substrate support may include an electrostatic chuck, and the electrostatic chuck may include multiple RF electrodes. The substrate support may further include a base plate below the electrostatic chuck, and the base plate may have a single bias electrode configured to apply a bias RF signal thereto.

[0102] In the process apparatus of the second embodiment, the substrate support may include an electrostatic chuck, and the electrostatic chuck may include a plurality of RF electrodes. The substrate support may further include a base plate below the electrostatic chuck, and the base plate may include a plurality of bias electrodes. Each bias electrode of the plurality of bias electrodes may be configured to have a respective bias signal applied thereto independently of other bias signals applied to other bias electrodes of the plurality of bias electrodes.

[0103] The process apparatus of the second embodiment may further include an RF power system and multiple RF signal control circuits. The RF power system may be configured to output an RF signal at an output node of the RF power system. Each RF signal control circuit of the multiple RF signal control circuits may have an input node electrically connected to the output node of the RF power system and may have an output node electrically connected to a respective one of the multiple RF electrodes. Each RF signal control circuit of the multiple RF signal control circuits may be controllable to adjust the amplitude and phase of an RF signal to output a corresponding adjusted RF signal at the output node of the respective RF signal control circuit. In addition, the process apparatus may include a controller. The controller may include one or more processors and non-transitory memory. The non-transitory memory may include stored instructions that, when executed by the one or more processors, cause the one or more processors to control the multiple RF signal control circuits to adjust their respective amplitudes and respective phases.

[0104] In the process apparatus of the second embodiment, the plurality of RF electrodes may be arranged in a linear grid.

[0105] In the process apparatus of the second embodiment, the multiple RF electrodes may be arranged in divided concentric rings surrounding a divided inner circle.

[0106] In the process apparatus of the second embodiment, the plurality of RF electrodes may be arranged in radially aligned divided concentric rings surrounding an inner circle divided into sectors.

[0107] In the process apparatus of the second embodiment, the multiple RF electrodes may be arranged in divided concentric rings surrounding a complete inner circle.

[0108] In the process apparatus of the second embodiment, each of the RF electrodes may have a side dimension of 221.1 millimeters or less, and each dimension may be in a plane parallel to the support surface.

[0109] In the process apparatus of the second embodiment, each of the RF electrodes may have a side dimension of 199.9 millimeters or less, and each dimension may be in a plane parallel to the support surface.

[0110] In the process apparatus of the second embodiment, each of the plurality of RF electrodes may have a side dimension ranging from 50.0 millimeters to 221.1 millimeters, and each dimension may be in a plane parallel to the support surface.

[0111] In the process apparatus of the second embodiment, each of the RF electrodes may have a side dimension ranging from 50.0 millimeters to 199.9 millimeters, and each dimension may lie in a plane parallel to the support surface.

[0112] A third embodiment is a process apparatus for semiconductor processing. The process apparatus includes a chamber and a substrate support. The chamber has an internal volume therein. The substrate support is disposed within the internal volume of the chamber. The substrate support includes a support surface configured to support a semiconductor substrate within the internal volume of the chamber. The substrate support includes a plurality of radio frequency (RF) electrodes configured to at least partially control a plasma within the internal volume of the chamber. Each RF electrode of the plurality of RF electrodes has a side dimension of 221.1 millimeters or less, and each dimension lies in a plane parallel to the support surface.

[0113] In the process apparatus of the third embodiment, each RF electrode of the plurality of RF electrodes may be configured to have a voltage applied thereto independent of each other voltage applied to each other RF electrode of the plurality of RF electrodes.

[0114] In the process apparatus of the third embodiment, the plurality of RF electrodes may be further configured to have a direct current (DC) voltage applied thereto to chuck the semiconductor substrate onto the support surface.

[0115] In the process apparatus of the third embodiment, the substrate support may include an electrostatic chuck, and the electrostatic chuck may include multiple RF electrodes. The substrate support may further include a base plate below the electrostatic chuck, and the base plate may have a single bias electrode configured to apply a bias RF signal thereto.

[0116] In the process apparatus of the third embodiment, the substrate support may include an electrostatic chuck, and the electrostatic chuck may include a plurality of RF electrodes. The substrate support may further include a base plate below the electrostatic chuck, and the base plate may include a plurality of bias electrodes. Each bias electrode of the plurality of bias electrodes may be configured to have a respective bias signal applied thereto independently of other bias signals applied to other bias electrodes of the plurality of bias electrodes.

[0117] The process apparatus of the third embodiment may further include an RF power system and multiple RF signal control circuits. The RF power system may be configured to output an RF signal at an output node of the RF power system. Each RF signal control circuit of the multiple RF signal control circuits may have an input node electrically connected to the output node of the RF power system and may have an output node electrically connected to a respective one of the multiple RF electrodes. Each RF signal control circuit of the multiple RF signal control circuits may be controllable to adjust the amplitude and phase of an RF signal to output a corresponding adjusted RF signal at the output node of the respective RF signal control circuit. In addition, the process apparatus may include a controller. The controller may include one or more processors and non-transitory memory. The non-transitory memory may include stored instructions that, when executed by the one or more processors, cause the one or more processors to control the multiple RF signal control circuits to adjust their respective amplitudes and respective phases.

[0118] In the process apparatus of the third embodiment, the plurality of RF electrodes may be arranged in a linear grid.

[0119] In the process apparatus of the third embodiment, the multiple RF electrodes may be arranged in divided concentric rings surrounding a divided inner circle.

[0120] In the process apparatus of the third embodiment, the plurality of RF electrodes may be arranged in radially aligned divided concentric rings surrounding an inner circle divided into sectors.

[0121] In the process apparatus of the third embodiment, the multiple RF electrodes may be arranged in divided concentric rings surrounding a complete inner circle.

[0122] In the process apparatus of the third embodiment, a plurality of RF electrodes may be arranged in a circle divided into sectors.

[0123] In the process apparatus of the third embodiment, each of the plurality of RF electrodes may have a side dimension of greater than 50.0 millimeters, and each dimension may lie in a plane parallel to the support surface.

[0124] In the process apparatus of the third embodiment, each of the plurality of RF electrodes may have a side dimension of 199.9 millimeters or less, and each dimension may be in a plane parallel to the support surface.

[0125] In the process apparatus of the third embodiment, each of the plurality of RF electrodes may have a side dimension ranging from 50.0 millimeters to 199.9 millimeters, and each dimension may be in a plane parallel to the support surface.

[0126] A fourth embodiment is a method for semiconductor processing. The method includes generating a plasma in a process volume of a chamber of a process apparatus. A substrate support is disposed in the chamber and supports a semiconductor substrate on a support surface. The semiconductor substrate is exposed to the plasma. The method further includes controlling the plasma, including applying respective radio frequency (RF) signals to a plurality of RF electrodes disposed on the substrate support.

[0127] In the method of the fourth embodiment, each side dimension of each of the plurality of RF electrodes may be 2% or less of the wavelength of each RF signal applied to the respective RF electrode.

[0128] The method of the fourth embodiment may further include chucking the semiconductor substrate onto a substrate support, which includes applying a direct current (DC) voltage to the plurality of RF electrodes.

[0129] The method of the fourth embodiment may further include applying a bias RF signal to a bias electrode of the base plate. The substrate support may include an electrostatic chuck, and the electrostatic chuck may include multiple RF electrodes. The substrate support may further include a base plate disposed below the electrostatic chuck, and the base plate may have a single bias electrode.

[0130] The method of the fourth embodiment may further include applying a plurality of bias RF signals to respective bias electrodes of the base plate. The substrate support may include an electrostatic chuck, and the electrostatic chuck may include a plurality of RF electrodes. The substrate support may further include a base plate disposed below the electrostatic chuck, and the base plate may include the bias electrodes.

[0131] The method of the fourth embodiment may further include generating an initial RF signal by an RF power supply system, and adjusting, by each RF signal control circuit of the plurality of RF signal control circuits, an amplitude, a phase offset, or a combination thereof, of the initial RF signal to generate a respective RF signal of the RF signals applied to the plurality of RF electrodes.

[0132] In the method of the fourth embodiment, a first RF electrode of the plurality of RF electrodes may be disposed near a center of the semiconductor substrate, and a second RF electrode of the plurality of RF electrodes may be disposed near a periphery of the semiconductor substrate, and the first RF electrode and the second RF electrode may laterally intersect an axis parallel to a radial direction of the support surface between the center and the periphery of the support surface.

[0133] In the method of the fourth embodiment, the plurality of RF electrodes may be arranged in a linear grid.

[0134] In the method of the fourth embodiment, the multiple RF electrodes may be arranged in divided concentric rings surrounding a divided inner circle.

[0135] In the method of the fourth embodiment, the plurality of RF electrodes may be arranged in radially aligned divided concentric rings surrounding an inner circle divided into sectors.

[0136] In the method of the fourth embodiment, multiple RF electrodes may be arranged in divided concentric rings surrounding a complete inner circle.

[0137] In the method of the fourth embodiment, a plurality of RF electrodes may be arranged in a circle divided into sectors.

[0138] In the method of the fourth embodiment, each of the plurality of RF electrodes may have a lateral dimension of 221.1 millimeters or less, and each dimension may lie in a plane parallel to the support surface.

[0139] In the method of the fourth embodiment, each of the plurality of RF electrodes may have a lateral dimension of 199.9 millimeters or less, and each dimension may lie in a plane parallel to the support surface.

[0140] In the method of the fourth embodiment, each lateral dimension of each of the plurality of RF electrodes may be in the range of 50.0 millimeters to 221.1 millimeters, and each dimension may lie in a plane parallel to the support surface.

[0141] In the method of the fourth embodiment, each lateral dimension of each of the plurality of RF electrodes may be in the range of 50.0 millimeters to 199.9 millimeters, and each dimension may lie in a plane parallel to the support surface.

[0142] A fifth embodiment is a method for semiconductor processing. The method includes performing a plasma semiconductor process having first process conditions on a first plurality of substrates using a process apparatus. The process apparatus includes a substrate support configured to support the substrates during the plasma semiconductor process. The substrate support includes a plurality of radio frequency (RF) electrodes configured to control, at least in part, a plasma of the plasma semiconductor process. The first process conditions correspond to amplitude and phase of an RF signal applied to the plurality of RF electrodes during the plasma semiconductor process. The method includes measuring a first characteristic of each of the first plurality of substrates corresponding to a first position of a first RF electrode of the plurality of RF electrodes during the plasma semiconductor process. The first characteristic is formed by the plasma semiconductor process. The method includes measuring a second characteristic of each of the first plurality of substrates corresponding to a second position of a second RF electrode of the plurality of RF electrodes during the plasma semiconductor process. The second characteristic is formed by the plasma semiconductor process. The second position is different from the first position. The method includes determining, by a processor-based system, second process conditions to be applied during the plasma semiconductor process on a second plurality of substrates based on the first characteristic and the second characteristic. The second process conditions correspond to amplitudes and phases of RF signals applied to the plurality of RF electrodes during the plasma semiconductor process. The method includes performing a plasma semiconductor process having the second process conditions on a second plurality of substrates using the process apparatus.

[0143] In the method of the fifth embodiment, the first characteristic may include a first contour angle of a recess etched into each substrate of the first plurality of substrates corresponding to the first location, and the second characteristic may include a second contour angle of a recess etched into each substrate of the first plurality of substrates corresponding to the second location.

[0144] In the method of the fifth embodiment, the first characteristic may include a first depth of a recess to be etched into each substrate of the first plurality of substrates corresponding to the first location, and the second characteristic may include a second depth of a recess to be etched into each substrate of the first plurality of substrates corresponding to the second location.

[0145] In the method of the fifth embodiment, the first characteristic may include a first thickness of a film deposited on each substrate of the first plurality of substrates corresponding to a first position, and the second characteristic may include a second thickness of a film deposited on each substrate of the first plurality of substrates corresponding to a second position.

[0146] A sixth embodiment is a power system for semiconductor processing. The power system includes a first RF power supply system and a first plurality of RF signal control circuits. Each RF signal control circuit of the first plurality of RF signal control circuits has (i) an input node electrically connected to an output node of the first RF power supply system and (ii) an output node configured to be electrically connected to a respective RF electrode of an electrostatic chuck of a process tool. Each RF signal control circuit of the first plurality of RF signal control circuits is controllable to vary the amplitude and phase of an RF signal received at its respective input node and to output an output RF signal at its respective output node based on the RF signal received at its respective input node. Each RF signal control circuit of the first plurality of RF signal control circuits is controllable independently of each other RF signal control circuit of the first plurality of RF signal control circuits.

[0147] In a sixth embodiment, the power system may further include a plurality of analog summer / summer circuits. Each of the analog summer / summer circuits includes a first input node, a second input node, and an output node. The first input node of each of the analog summer / summer circuits is electrically connected to the output node of a respective RF signal control circuit of the first plurality of RF signal control circuits. The second input node of the analog summer / summer circuit is configured to be electrically connected to a DC power source. The output node of each of the analog summer / summer circuits is configured to be electrically connected to a respective RF electrode of the electrostatic chuck.

[0148] In a sixth embodiment, the power system may further include a second RF power supply system, a second plurality of RF signal control circuits, a first plurality of insulating filters, a second plurality of insulating filters, and a plurality of analog summers / summing circuits. Each RF signal control circuit of the second plurality of RF signal control circuits has (i) an input node electrically connected to the output node of the second RF power supply system and (ii) an output node configured to be electrically connected to a respective RF electrode of an electrostatic chuck of a process tool. Each RF signal control circuit of the second plurality of RF signal control circuits is controllable to vary the amplitude and phase of an RF signal received at its respective input node and output an output RF signal at its respective output node based on the RF signal received at its respective input node. Each RF signal control circuit of the second plurality of RF signal control circuits is controllable independently from each of the other RF signal control circuits of the second plurality of RF signal control circuits. Each insulating filter of the first plurality of insulating filters has an input node and an output node. The input node of each insulating filter of the first plurality of insulating filters is electrically connected to the output node of a respective one of the RF signal control circuits of the first plurality of RF signal control circuits. Each insulating filter of the second plurality of insulating filters has an input node and an output node. The input node of each insulating filter of the second plurality of insulating filters is electrically connected to the output node of a respective one of the RF signal control circuits of the second plurality of RF signal control circuits. Each analog adder / summer circuit of the plurality of analog adder / summer circuits includes a first input node, a second input node, and an output node. The first input node of each adder / summer circuit of the plurality of analog adder / summer circuits is electrically connected to the output node of a respective insulating filter of the first plurality of insulating filters. The second input node of each adder / summer circuit of the plurality of analog adder / summer circuits is electrically connected to the output node of a respective insulating filter of the second plurality of insulating filters. The output node of each analog adder / summer circuit of the plurality of analog adder / summer circuits is configured to be electrically connected to a respective RF electrode of the electrostatic chuck.

[0149] Although various examples have been described in detail, it should be understood that various changes, substitutions, and alterations can be made thereto without departing from the scope defined by the appended claims.

Claims

1. A process device for semiconductor processing, a chamber; a substrate support disposed within the chamber; the substrate support includes a support surface configured to support a semiconductor substrate in the chamber, the substrate support including a plurality of radio frequency (RF) electrodes configured to control a plasma in the chamber, a first RF electrode of the plurality of RF electrodes disposed near a center of the support surface and a second RF electrode of the plurality of RF electrodes disposed near a periphery of the support surface, the first RF electrode and the second RF electrode laterally intersecting an axis parallel to a radial direction of the support surface between the center and the periphery of the support surface; Process equipment.

2. 10. The process apparatus of claim 1, wherein each RF electrode of the plurality of RF electrodes is configured to have a voltage applied thereto independently.

3. 10. The process apparatus of claim 1, wherein the plurality of RF electrodes are further configured to have a direct current (DC) voltage applied thereto to chuck the semiconductor substrate onto the support surface.

4. 10. The process apparatus of claim 1, wherein the substrate support comprises an electrostatic chuck, the electrostatic chuck comprising the plurality of RF electrodes, and the substrate support further comprises a base plate below the electrostatic chuck, the base plate having a single bias electrode configured to have a bias RF signal applied thereto.

5. 2. The process apparatus of claim 1, wherein the substrate support comprises an electrostatic chuck, the electrostatic chuck comprising the plurality of RF electrodes, the substrate support further comprising a base plate below the electrostatic chuck, the base plate comprising a plurality of bias electrodes, each bias electrode of the plurality of bias electrodes independently configured to have a respective bias signal applied thereto.

6. an RF power system configured to output an RF signal at an output node of the RF power system; a plurality of RF signal control circuits; 2. The process apparatus of claim 1, wherein each RF signal control circuit of the plurality of RF signal control circuits has an input node electrically connected to the output node of the RF power system and an output node electrically connected to a respective one of the plurality of RF electrodes, and each RF signal control circuit of the plurality of RF signal control circuits is controllable to adjust the amplitude and phase of the RF signal to output a corresponding adjusted RF signal at the output node of the respective RF signal control circuit.

7. one or more processors; a non-transitory memory containing stored instructions; and a controller including:

7. The process apparatus of claim 6, wherein the instructions, when executed by the one or more processors, cause the one or more processors to control the plurality of RF signal control circuits to adjust the respective amplitudes and the respective phases.

8. The process apparatus of claim 1 , wherein the plurality of RF electrodes are arranged in a linear grid.

9. 10. The process apparatus of claim 1, wherein the plurality of RF electrodes are arranged in divided concentric rings surrounding a divided inner circle.

10. 10. The process apparatus of claim 1, wherein the plurality of RF electrodes are arranged in radially aligned divided concentric rings surrounding an inner circle divided into sectors.

11. 10. The process apparatus of claim 1, wherein the plurality of RF electrodes are arranged in divided concentric rings surrounding a complete inner circle.

12. 2. The process apparatus of claim 1, wherein each lateral dimension of each of said plurality of RF electrodes is less than or equal to 221.1 millimeters, said respective dimensions lying in a plane parallel to said support surface.

13. 2. The process apparatus of claim 1, wherein each side dimension of each of the plurality of RF electrodes is 199.9 millimeters or less, and said respective dimensions lie in a plane parallel to said support surface.

14. 2. The process apparatus of claim 1, wherein each lateral dimension of each of the plurality of RF electrodes ranges from 50.0 millimeters to 221.1 millimeters, the respective dimensions lying in a plane parallel to the support surface.

15. 2. The process apparatus of claim 1, wherein each lateral dimension of each of the plurality of RF electrodes ranges from 50.0 millimeters to 199.9 millimeters, the respective dimensions lying in a plane parallel to the support surface.

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