Switch device, load drive system and switch system

Abstract

To propose a switch device capable of appropriately realizing parallel drive.SOLUTION: In a switch device (10), a control circuit (11) turns on / off an output transistor (M1) provided between two terminals according to a control signal (Sin). The control circuit turns off the output transistor or limits a current value of the output transistor if abnormality is detected during an ON period of the output transistor, and switches a voltage level of a diagnostic terminal from a first level to a second level by switching a state of the diagnosis terminal from a first state to a second state. The control circuit turns off the output transistor if abnormality is not detected and the voltage level of the diagnostic terminal changes from the first level to the second level, during the ON period of the output transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a switch device, a load drive system, and a switch system. [Background technology]

[0002] 2. Description of the Related Art There is a switching device that turns on or off an output transistor provided between two terminals in response to an input control signal, thereby establishing or blocking conduction between the two terminals. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 065395

[0004] [overview] By preparing multiple switch devices and connecting multiple output transistors in the multiple switch devices in parallel, it is possible to reduce the overall on-resistance as much as necessary. However, current switch devices are not configured to enable proper parallel driving. Proposals for switch devices that can properly achieve parallel driving are anticipated.

[0005] a control circuit configured to control the output transistor to be turned on or off in response to a control signal supplied to the switch device; an abnormality detection circuit configured to detect an abnormality in the switch device; and a diagnostic output circuit configured to control the state of the diagnostic terminal; wherein the control circuit performs a first abnormality response operation when the abnormality is not detected after a reference period in which the output transistor is set to on in accordance with the control signal, and the first abnormality response operation switches the output transistor from on to off or limits a value of a current flowing through the output transistor to a limit value or less, and switches the state of the diagnostic terminal from a first state to a second state using the diagnostic output circuit, thereby switching a voltage level of the diagnostic terminal from a first level to a second level; and wherein the control circuit performs a second abnormality response operation when the abnormality is not detected after the reference period in which the output transistor is set to on in response to the control signal, and [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is an overall configuration diagram of a load driving system according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is an external perspective view of a switch device according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a schematic configuration diagram of a vehicle according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating a modified method of transmitting control signals between an MCU and a plurality of switch devices according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a diagram showing how an MCU and a plurality of switch devices are connected via a communication bus according to an embodiment of the present disclosure. [Figure 6]FIG. 6 is a diagram illustrating two flags stored in a memory in a control circuit according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is an overall configuration diagram of a load driving system according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram illustrating two flags stored in a memory in a control circuit according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a timing chart of the load driving system in the first case according to the embodiment of the present disclosure. [Figure 10] FIG. 10 is a timing chart of the load driving system in the first case according to the embodiment of the present disclosure. [Figure 11] FIG. 11 is a timing chart of the load driving system in the second case according to the embodiment of the present disclosure. [Figure 12] FIG. 12 is a timing chart of the load driving system in the second case according to the embodiment of the present disclosure. [Figure 13] FIG. 13 is an explanatory diagram of a reference configuration. [Figure 14] FIG. 14 is a configuration diagram relating to the detection of temperature abnormalities according to a second example belonging to an embodiment of the present disclosure. [Figure 15] FIG. 15 is a timing chart relating to the detection of a temperature abnormality in a second example belonging to an embodiment of the present disclosure. [Figure 16] FIG. 16 is a configuration diagram relating to the detection of temperature abnormalities according to a third example belonging to an embodiment of the present disclosure. [Figure 17] FIG. 17 is a timing chart relating to the detection of a temperature abnormality according to a third example belonging to an embodiment of the present disclosure.

[0007] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the referenced drawings, identical parts are designated by the same reference numerals, and redundant descriptions of identical parts will be omitted as a general rule. For the sake of simplicity, in this specification, symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs may be omitted or abbreviated. For example, the output wiring referred to by "W2" (see FIG. 1) described below may be written as output wiring W2 or abbreviated as wiring W2, but they all refer to the same thing.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having a reference potential of 0 V (zero volts), or refers to the 0 V potential itself. The reference conductor may be formed using a conductor such as metal. The 0 V potential may also be referred to as ground potential. Ground potential and ground voltage are synonymous. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a potential seen from ground.

[0009] A level refers to the level of potential, and for any given signal or voltage, a high level has a higher potential than a low level. For any given signal or voltage, a high level of the signal or voltage strictly means that the signal or voltage level is high, and a low level of the signal or voltage strictly means that the signal or voltage level is low. A level of a signal may be expressed as a signal level, and a level of a voltage may be expressed as a voltage level. For any given signal or voltage, a switch from a low level to a high level may be referred to as a rising edge, and a switch from a high level to a low level may be referred to as a falling edge.

[0010] For any signal having a high-level or low-level signal level, the period during which the level of the signal is the high level is referred to as the high-level period, and the period during which the level of the signal is the low level is referred to as the low-level period. The same applies to any voltage having a high-level or low-level voltage level.

[0011] For any transistor configured as a FET (field effect transistor) exemplified by a MOSFET, the on state refers to a state in which the drain and source of the transistor are conducting, and the off state refers to a state in which the drain and source of the transistor are non-conducting (blocked state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. MOSFET is an abbreviation of "metal-oxide-semiconductor field-effect transistor". Also, unless otherwise specified, in any MOSFET, the back gate may be considered to be short-circuited to the source.

[0012] Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection.

[0013] When any two voltages to be compared are voltage v1 and v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0014] FIG. 1 shows an overall configuration diagram of a load driving system SYS according to an embodiment of the present disclosure. The load driving system SYS mainly comprises a plurality of switch devices 10 and an MCU (Micro Controller Unit) 20. The plurality of switch devices 10 are identical to one another. The MCU 20 is an example of an external control device that controls the operation of each switch device 10. The load driving system SYS is also provided with a pull-up resistor Ra. A voltage source VS, a load LD, and an output capacitor Cout are connected to the load driving system SYS. Here, the load LD and the output capacitor Cout are considered to be external elements of the load driving system SYS, but the load LD and the output capacitor Cout may also be considered to be included as components of the load driving system SYS. Similarly, the voltage source VS may or may not be considered to be included as a component of the load driving system SYS.

[0015] Each switch device 10 includes a power supply terminal VBB, an output terminal OUT, a ground terminal GND, a control input terminal IN, and a diagnostic terminal ST. The power supply terminal VBB and the output terminal OUT may be referred to as a power input terminal and a power output terminal, respectively.

[0016] FIG. 2 is a perspective view of one switch device 10. The switch device 10 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing CS (package) that houses the semiconductor chip, and multiple external terminals exposed to the outside of the switch device 10 through the housing CS. The switch device 10 is formed by encapsulating the semiconductor chip in a housing CS made of resin. Note that the number of external terminals of the switch device 10 and the type of housing CS of the switch device 10 shown in FIG. 2 are merely examples and can be designed as desired. FIG. 1 shows five external terminals of the multiple external terminals provided on the switch device 10: a power supply terminal VBB, an output terminal OUT, a ground terminal GND, a control input terminal IN, and a diagnostic terminal ST. However, other external terminals may also be provided on the switch device 10. Note that the power supply terminal VBB may be composed of two or more external terminals. The same applies to the output terminal OUT or the ground terminal GND.

[0017] A voltage source VS is connected to ground and input wiring W1, and outputs a power supply voltage Vbb, which is a positive DC voltage with respect to ground. The power supply voltage Vbb is applied to the input wiring W1. The input wiring W1 is a wiring provided outside each switch device 10, and is a wiring connected to the voltage source VS and a power supply terminal VBB of each switch device 10. The power supply terminal VBB of each switch device 10 is commonly connected to the input wiring W1, and a common power supply voltage Vbb is applied to the power supply terminal VBB of each switch device 10.

[0018] The output terminal OUT of each switch device 10 is commonly connected to an output wiring W2, and is connected to a load LD through the output wiring W2. An output capacitor Cout is connected in parallel to the load LD. The voltage at the output terminal OUT is referred to as the output voltage Vout. Therefore, the output voltage Vout is applied to the output wiring W2. The output wiring W2 is a wiring provided outside the switch device 10, and is a wiring connected to the output terminal OUT of each switch device 10 and the load LD (more specifically, a wiring connecting the output terminal OUT of each switch device 10 and a parallel circuit of the load LD and the output capacitor Cout). A first end of the load LD is connected to the output wiring W2, and a second end of the load LD is connected to ground. A first end of the output capacitor Cout is connected to the output wiring W2, and a second end of the output capacitor Cout is connected to ground. The load LD is any load that is driven using the output voltage Vout as a power supply voltage.

[0019] The ground terminal GND of each switch device 10 is connected to ground. The control input terminal IN of each switch device 10 is connected to control wiring W3. The diagnostic terminal ST of each switch device 10 is connected to diagnostic wiring W4.

[0020] The MCU 20 is provided outside the switch device 10. The MCU 20 is supplied with a power supply voltage VCC having a predetermined positive DC voltage value and is connected to ground, and is driven based on the power supply voltage VCC. The control wiring W3 and the diagnostic wiring W4 are also connected to the MCU 20. A first end of the pull-up resistor Ra is connected to an application terminal 51 of the power supply voltage VCC (a node to which the power supply voltage VCC is applied), and a second end of the pull-up resistor Ra is connected to the diagnostic wiring W4.

[0021] Referring to Figure 3, in this embodiment, it is assumed that the load drive system SYS is mounted on a vehicle VHCL such as an automobile. In this case, the voltage source VS may be a battery installed in the vehicle VHCL. The vehicle VHCL is equipped with an electrical block BLK consisting of various electrical components, and the components of the electrical block BLK include the load drive system SYS, a load LD, and an output capacitor Cout, as well as various wirings including wirings W1 to W4. The load LD includes an ECU (Electronic Control Unit), as well as actuators such as motors, lighting devices, and air conditioners that are driven and controlled by the ECU.

[0022] The MCU 20 supplies a control signal Sin to each switch device 10 through a control wiring W3. The control signal Sin from the MCU 20 is received at the control input terminal IN of each switch device 10. In this embodiment, it is assumed that the MCU 20 supplies a common control signal Sin to the control input terminals IN of all switch devices 10 through a single control wiring W3. Therefore, the control signal Sin received at the control input terminals IN of all switch devices 10 is the same. However, as a modification, as shown in FIG. 4, the MCU 20 and multiple switch devices 10 may be connected by individual control wirings, and the MCU 20 may supply the control signal Sin individually to the multiple switch devices 10.

[0023] The signal on the diagnostic wiring W4 is referred to as the diagnostic signal Sst. The MCU 20 has an input terminal 21 connected to the diagnostic wiring W4 and receives the diagnostic signal Sst at the input terminal 21. The input impedance of the input terminal 21 as seen from the diagnostic wiring W4 is sufficiently high, and the current passing through the input terminal 21 can be considered to be zero.

[0024] Although omitted in FIG. 1 to avoid complication of the illustration, the MCU 20 and each switch device 10 may be connected to each other via a communication bus 30 consisting of a plurality of wires. In this case, the MCU 20 and each switch device 10 can perform bidirectional communication via the communication bus 30. Although the communication between each switch device 10 and the MCU 20 may be parallel communication, in this embodiment, the communication between each switch device 10 and the MCU 20 is assumed to be serial communication, and an SPI (Serial Peripheral Interface) is used as the interface for serial communication. However, the interface for serial communication between each switch device 10 and the MCU 20 is not limited to SPI, and therefore, for example, an I 2 An interface based on C (Inter-Integrated Circuit) or Microwire may also be used. The MCU 20 can send various command signals to each switch device 10 via the communication bus 30. Each switch device 10 can perform the operation and setting specified by the received command signal.

[0025] Each switch device 10 includes a group of circuits made of semiconductors, and in each switch device 10, the group of circuits is housed in a housing CS. In each switch device 10, the group of circuits made of semiconductors includes an output transistor M1, a control circuit 11, a memory 12, a charge pump circuit 13, an abnormality detection circuit 14, a diagnostic output circuit 15, an internal power supply circuit 16, and Schmitt buffers (Schmitt triggers) SM1 and SM2. The memory 12 is built into the control circuit 11. However, it may also be understood that the memory 12 is provided outside the control circuit 11.

[0026] Since the internal configuration of the plurality of switch devices 10 is the same, the internal configuration of one switch device 10 will be described.

[0027] The output transistor M1 is configured by an N-channel MOSFET. The drain of the output transistor M1 is connected to the power supply terminal VBB, and the source of the output transistor M1 is connected to the output terminal OUT. The drain current of the output transistor M1 is referred to as the output current Iout. An active clamper (not shown) may be provided between the drain and gate of the output transistor M1 to protect the output transistor M1 from a back electromotive force generated by an inductive load.

[0028] A control signal Sin is supplied from the MCU 20 to the control input terminal IN. The control signal Sin is a binary signal having a high or low signal level. The high level of the control signal Sin is an active level (on command level), and the high level control signal Sin is a signal with which the MCU 20 commands the switch device 10 and the control circuit 11 to set the output transistor M1 to an on state. The low level of the control signal Sin is a non-active level (off command level), and the low level control signal Sin is a signal with which the MCU 20 commands the switch device 10 and the control circuit 11 to set the output transistor M1 to an off state. The control signal Sin supplied to the control input terminal IN is input to the Schmitt buffer SM1. The Schmitt buffer SM1 shapes the waveform of the control signal Sin input thereto and outputs the waveform-shaped control signal Sin to the control circuit 11.

[0029] The control circuit 11 is connected to the gate and source of the output transistor M1, and controls the gate voltage of the output transistor M1 based on the waveform-shaped control signal Sin (in other words, by controlling the gate-source voltage of the output transistor M1), thereby controlling the state of the output transistor M1. The control signal Sin in the description of the operation mainly performed by the control circuit 11 is the control signal Sin after waveform shaping. However, there is no substantial difference in the level of the control signal Sin before and after waveform shaping.

[0030] As shown in Figure 6, flags Fa and Fb are stored and saved in memory 12. Memory 12 includes non-volatile memory and volatile memory classified as registers, etc. Flags Fa and Fb each have a value of "0" or "1." The control circuit 11 individually sets the values ​​of flags Fa and Fb to "0" or "1." Flag Fa is a self-detection flag, and flag Fb is a other-detection flag. The meaning and use of flags Fa and Fb will be described later.

[0031] On the assumption that flags Fa and Fb both have the value "0," the control circuit 11 controls and sets the output transistor M1 to the ON state by supplying an ON voltage Von to the gate of the output transistor M1 during a high-level period of the control signal Sin supplied to the control circuit 11. The control circuit 11 controls and sets the output transistor M1 to the OFF state by supplying an OFF voltage Voff to the gate of the output transistor M1 during a low-level period of the control signal Sin supplied to the control circuit 11.

[0032] The gate threshold voltage of the output transistor M1 is represented by the symbol "Vg_TH". The on-voltage Von is higher than the voltage that is higher than the source potential of the output transistor M1 by the gate threshold voltage Vg_TH. The on-voltage Von may be the drive voltage Vcp described below. The off-voltage Voff is lower than the voltage that is higher than the source potential of the output transistor M1 by the gate threshold voltage Vg_TH. The source voltage of the output transistor M1 may be used as the off-voltage Voff.

[0033] The charge pump circuit 13 is connected to the power supply terminal VBB, and under the control of the control circuit 11, boosts the power supply voltage Vbb to generate a drive voltage Vcp higher than the power supply voltage Vbb. The drive voltage Vcp is supplied to the control circuit 11. The difference between the drive voltage Vcp and the power supply voltage Vbb is greater than the gate threshold voltage Vg_TH of the output transistor M1. The control circuit 11 can use the drive voltage Vcp to turn on the output transistor M1. Note that the output transistor M1 can also be configured as a P-channel MOSFET, and if this modification is adopted, the charge pump circuit 13 will be unnecessary.

[0034] The abnormality detection circuit 14 detects multiple types of abnormalities that may occur in the switch device 10. The multiple types of abnormalities include an overcurrent abnormality in which the current flowing through the output transistor M1 becomes excessive, a temperature abnormality in which the temperature of the output transistor M1 becomes excessive, a low voltage abnormality in which the voltage supplied to the power supply terminal VBB becomes equal to or lower than the low voltage threshold, and an open abnormality in which the output terminal OUT becomes open. In order to detect an overcurrent abnormality, the abnormality detection circuit 14 has a built-in current sensor that detects the current flowing through the output transistor M1 (i.e., the output current Iout). The abnormality detection circuit 14 outputs a signal indicating whether or not an abnormality has been detected to the control circuit 11. The abnormality detection circuit 14 can output a signal indicating whether or not an abnormality has been detected to the control circuit 11 for each type of detectable abnormality.

[0035] The diagnostic output circuit 15 is a circuit for transmitting a signal indicating that an abnormality has been detected to the MCU 20 when any abnormality is detected by the abnormality detection circuit 14. Specifically, the diagnostic output circuit 15 has a diagnostic transistor 15a. The diagnostic transistor 15a is an N-channel MOSFET with an open-drain configuration. The drain of the diagnostic transistor 15a is connected to the diagnostic terminal ST, and the source of the diagnostic transistor 15a is connected to ground. The control circuit 11 is connected to the gate of the diagnostic transistor 15a and controls the gate voltage of the diagnostic transistor 15a to set the state of the diagnostic transistor 15a to on or off.

[0036] The internal power supply circuit 16 is connected to the power supply terminal VBB and generates the internal power supply voltage Vreg by stepping down the power supply voltage Vbb with respect to the ground voltage. The internal power supply voltage Vreg has a predetermined positive DC voltage value. Each circuit in the switch device 10 can be driven based on the internal power supply voltage Vreg with respect to the ground potential.

[0037] The input terminal of the Schmitt buffer SM2 is connected to the diagnostic terminal ST, and the output terminal of the Schmitt buffer SM2 is connected to the control circuit 11. The Schmitt buffer SM2 shapes the waveform of the diagnostic signal Sst at the diagnostic terminal ST and outputs the waveform-shaped diagnostic signal Sst to the control circuit 11. The input impedance of the Schmitt buffer SM2 as viewed from the diagnostic wiring W4 and the diagnostic terminal ST is sufficiently high, and the current between the diagnostic wiring W4 and the input terminal of the Schmitt buffer SM2 can be considered to be zero.

[0038] 7, when multiple switch devices 10 are to be distinguished from one another, the multiple switch devices 10 will be referred to as switch devices 10[1] to 10[n], where n is an integer equal to or greater than 2 and is equal to the total number of switch devices 10 provided in the load driving system SYS. Furthermore, the output transistor M1, control circuit 11, memory 12, charge pump circuit 13, abnormality detection circuit 14, diagnostic output circuit 15, internal power supply circuit 16, Schmitt buffer SM1, and Schmitt buffer SM2 in switch device 10[i] will be referred to as output transistor M1[i], control circuit 11[i], memory 12[i], charge pump circuit 13[i], abnormality detection circuit 14[i], diagnostic output circuit 15[i], internal power supply circuit 16[i], Schmitt buffer SM1[i], and Schmitt buffer SM2[i], respectively. Similarly, the diagnostic transistor 15a in the switch device 10[i] is specifically referred to as the diagnostic transistor 15a[i], and the output current Iout in the switch device 10[i] is specifically referred to as the output current Iout[i]. The power supply terminal VBB, output terminal OUT, ground terminal GND, control input terminal IN, and diagnostic terminal ST in the switch device 10[i] are specifically referred to as the power supply terminal VBB[i], output terminal OUT[i], ground terminal GND[i], control input terminal IN[i], and diagnostic terminal ST[i], respectively, where i represents any integer.

[0039] 8, the flag Fa in the memory 12[i] is specifically referred to as flag Fa[i], and the flag Fb in the memory 12[i] is specifically referred to as flag Fb[i]. In the following description, (Fa[i], Fb[i]) = (0,0) means that the flags Fa[i] and Fb[i] both have a value of "0." (Fa[i], Fb[i]) = (1,0) means that the flag Fa[i] has a value of "1" while the flag Fb[i] has a value of "0." (Fa[i], Fb[i]) = (0,1) means that the flag Fa[i] has a value of "0" while the flag Fb[i] has a value of "1." The control circuit 11[i] never sets both the flags Fa[i] and Fb[i] to "1."

[0040] Furthermore, the output signal of the Schmitt buffer SM1[i] is referred to as the control signal Sin[i] (see FIG. 7). The control signal Sin[i] is substantially the same signal as the control signal Sin at the control input terminal IN[i]. The Schmitt buffer SM1[i] is a buffer circuit with hysteresis characteristics, and at least the control signal Sin at the control input terminal IN[i] is a voltage (k H × VCC), it outputs a high-level control signal Sin[i], and when the control signal Sin at at least the control input terminal IN[i] has a voltage value of more than or equal to the voltage (k L × VCC), it outputs a low-level control signal Sin[i]. H and k L is "0 <k L <k H <1”, e.g., (k L ,k H)=(0.3, 0.7). Under the assumption that flags Fa and Fb in memory 12[i] both have the value "0," control circuit 11[i] controls and sets output transistor M1[i] to the on state by supplying an on voltage Von to the gate of output transistor M1[i] during a high-level period of control signal Sin[i]. Control circuit 11[i] controls and sets output transistor M1[i] to the off state by supplying an off voltage Voff to the gate of output transistor M1[i] during a low-level period of control signal Sin[i].

[0041] Furthermore, the output signal of the Schmitt buffer SM2[i] is referred to as the diagnostic signal Sst[i]. The diagnostic signal Sst[i] is substantially the same signal as the diagnostic signal Sst at the diagnostic terminal ST[i]. The Schmitt buffer SM2[i] is a buffer circuit with hysteresis characteristics, and at least the diagnostic signal Sst at the diagnostic terminal ST[i] is a voltage (k H ×VCC), a high-level diagnostic signal Sst[i] is output, and at least the diagnostic signal Sst at the diagnostic terminal ST[i] has a voltage value of more than or equal to the voltage (k L When the voltage value of the Schmitt buffer SM2[i] is equal to or less than VCC × VCC, the Schmitt buffer SM2[i] outputs a low-level diagnostic signal Sst[i]. The Schmitt buffer SM2[i] outputs the diagnostic signal Sst[i] to the control circuit 11[i]. The control circuit 11[i] can perform specific operations based on the diagnostic signal Sst[i] (details will be described later).

[0042] The power supply terminals VBB[1] to VBB[n] are all commonly connected to the input wiring W1, and the output terminals OUT[1] to OUT[n] are all commonly connected to the output wiring W2. That is, the output transistors M1[1] to M1[n] are connected in parallel to each other. Therefore, when the output transistors M1[1] to M1[n] are all set to the on state, the current flowing through the parallel circuit of the output transistors M1[1] to M1[n] (the sum of the output currents Iout[1] to Iout[n]) is supplied to the load LD.

[0043] Furthermore, since all of the diagnostic terminals ST[1] to ST[n] are commonly connected to the diagnostic wiring W4, the diagnostic transistors 15a[1] to 15a[n] ​​and the pull-up resistor Ra form a so-called wired OR circuit. Depending on the state of the diagnostic transistors 15a[1] to 15a[n], the diagnostic signal Sst of the diagnostic wiring W4 has a high level or a low level. The high level of the diagnostic signal Sst of the diagnostic wiring W4 substantially coincides with the level of the power supply voltage VCC, and is at least equal to the voltage (k H ×VCC). The low level of the diagnostic signal Sst on the diagnostic wiring W4 is substantially equal to the ground level, and is higher than at least the voltage (k L × VCC). Therefore, when the diagnostic signal Sst on the diagnostic wiring W4 has a high level, the diagnostic signals Sst[1] to Sst[n] all have a high level, and when the diagnostic signal Sst on the diagnostic wiring W4 has a low level, the diagnostic signals Sst[1] to Sst[n] all have a low level.

[0044] The diagnostic output circuit 15[i] controls or sets the state of the diagnostic terminal ST[i]. The state of the diagnostic terminal ST[i] is controlled to either a Hi-Z state or a Lo_Z state. When the diagnostic transistor 15a[i] is off, the state of the diagnostic terminal ST[i] is Hi-Z, and when the diagnostic transistor 15a[i] is on, the state of the diagnostic terminal ST[i] is Lo_Z. The input impedance of the diagnostic terminal ST[i] as seen from the diagnostic wiring W4 is much higher when the diagnostic terminal ST[i] is in the Hi-Z state than when the diagnostic terminal ST[i] is in the Lo-Z state.

[0045] When the diagnostic output circuit 15[i] sets the diagnostic terminal ST[i] to the Lo-Z state (i.e., when the diagnostic transistor 15a[i] is on), a current (hereinafter referred to as the diagnostic current) flows from the power supply voltage VCC application terminal 51 to ground through the pull-up resistor Ra, the diagnostic wiring W4, the diagnostic terminal ST[i], and the diagnostic transistor 15a[i]. The input impedance of the diagnostic terminal ST[i] as seen from the diagnostic wiring W4 is much smaller than the value of the pull-down resistor Ra when the diagnostic terminal ST[i] is in the Lo-Z state. Therefore, during the period when a diagnostic current is generated in any one or more of the switch devices 10[1] through 10[n] (i.e., during the period when one or more of the diagnostic transistors 15a[1] through 15a[n] ​​is on), the diagnostic signal Sst of the diagnostic wiring W4 and the voltage level of each diagnostic terminal ST are low (substantially at ground voltage).

[0046] During periods when no diagnostic current is generated in any of the switch devices 10[1]-10[n] (i.e., periods when all of the diagnostic transistors 15a[1]-15a[n] ​​are off), the diagnostic signal Sst on the diagnostic wiring W4 and the voltage level of each diagnostic terminal ST are high (substantially at the level of the power supply voltage VCC). Focusing on one switch device 10[i], when the diagnostic output circuit 15[i] sets the state of the diagnostic terminal ST[i] to the Hi-Z state (i.e., when the diagnostic transistor 15a[i] is off), the diagnostic current through the diagnostic output circuit 15[i] is cut off, and the diagnostic output circuit 15[i] stops setting the diagnostic signal Sst on the diagnostic wiring W4 and the voltage level of each diagnostic terminal ST to low. However, the voltage level of each diagnostic terminal ST can be set to low by other diagnostic output circuits 15.

[0047] When no abnormality is detected by the abnormality detection circuit 14[i], the control circuit 11[i] sets the diagnostic transistor 15a[i] to the off state, and when any abnormality is detected by the abnormality detection circuit 14[i], the control circuit 11[i] sets the diagnostic transistor 15a[i] to the on state.

[0048] For convenience of explanation, the operation of the load driving system SYS will be described below assuming that "n=2" unless otherwise specified.

[0049] [Case 1] 9 and 10 are timing charts of the load driving system SYS in Case 1. In Case 1, of the abnormality detection circuits 14[1] and 14[2], some abnormality is detected only in the abnormality detection circuit 14[1].

[0050] When the supply of the power supply voltage Vbb starts in each switch device 10, the control circuit 11 executes an initial sequence operation, and the switch device 10 enters an initial state. In the initial state of the switch device 10, the output transistor M1 and the diagnostic transistor 15a are off, and the values ​​of the flags Fa and Fb are both "0." At time t A1 Before time t, the MCU 20 keeps the control signal Sin that it outputs low. A1 In this case, the MCU 20 generates a rising edge (that is, a switch from low level to high level) in the control signal Sin that it outputs, which causes rising edges to occur in the control signals Sin[1] and Sin[2].

[0051] time t A1 At time t, (Fa[1], Fb[1])=(0,0), so the control circuit 11[1] switches the output transistor M1[1] from the off state to the on state in response to the rising edge of the control signal Sin[1]. A1 Since (Fa[2], Fb[2])=(0, 0) in this case, the control circuit 11[2] switches the output transistor M1[2] from the off state to the on state in response to the rising edge of the control signal Sin[2].

[0052] time t A1 From the time t A2 No abnormality is detected by the abnormality detection circuits 14[1] and 14[2] until time t A2A small amount of time has passed since the time t A3 In this example, the abnormality detection circuit 14[1] detects an abnormality in the switch device 10[1], and an abnormality detection signal indicating that an abnormality has been detected in the switch device 10[1] is transmitted from the abnormality detection circuit 14[1] to the control circuit 11[1]. In response to receiving the abnormality detection signal from the abnormality detection circuit 14[1], the control circuit 11[1] sets the self-detection flag flag Fa[1] to "1" (i.e., switches the value of the flag Fa[1] from "0" to "1"). At this time, the control circuit 11[1] maintains the value of the other-detection flag flag Fb[1] at "0". "Fa[1]=1" indicates that an abnormality was first detected in the switch device 10[1] of the switch devices 10[1] and 10[2].

[0053] The control circuit 11[1] executes the first anomaly response process during the period when "Fa[1]=1", that is, during the period when the flag Fa[1] has the value "1".

[0054] In the first anomaly response process according to the first case, the control circuit 11[1] can perform off-latch control. The off-latch control by the control circuit 11[1] switches the output transistor M1[1] from an on state to an off state and maintains the output transistor M1[1] in the off state regardless of the control signal Sin[1] (even if the control signal Sin[1] is at a high level).

[0055] Alternatively, in the first anomaly response process according to the first case, the control circuit 11[1] can perform intermittent on / off control assuming that the control signal Sin[1] is high. When intermittent on / off control is performed in the first anomaly response process according to the first case, the control circuit 11[1] first switches the output transistor M1[1] from an on state to an off state, and then, depending on the type and circumstances of the detected anomaly, maintains the output transistor M1[1] in an off state, returns the output transistor M1[1] to an on state, or alternately turns the output transistor M1[1] on and off. In any case, like the off latch control, the intermittent on / off control by the control circuit 11[1] also includes switching the output transistor M1[1] off.

[0056] Alternatively, in the first anomaly handling process according to the first case, the control circuit 11[1] can perform current limiting control on the assumption that the control signal Sin[1] is at a high level. The current limiting control by the control circuit 11[1] keeps the output transistor M1[1] in an on state until the value of the output current Iout[1] reaches a predetermined limit value I LIM It is limited to the following:

[0057] Alternatively, in the first anomaly handling process according to the first case, the control circuit 11[1] sets the diagnostic transistor 15a[1] to the ON state. A3 (strictly speaking, at time t A3 After a short time has elapsed since the start of the first anomaly detection, a fall edge (i.e., a switch from high level to low level) occurs in the diagnostic signal Sst and the diagnostic signals Sst[1] and Sst[2] on the signal wiring W4. That is, in the first anomaly response process for the first case, the control circuit 11[1] switches the state of the diagnostic terminal ST[1] from the Hi-Z state to the Lo-Z state using the diagnostic output circuit 15[1], thereby switching the voltage level of the diagnostic terminal ST[1] from the high level (the level of the power supply voltage VCC) to the low level (the level of the ground).

[0058] In the first case, in response to the occurrence of a fall edge in the diagnostic signal Sst[2], the control circuit 11[2] sets the other detection flag, flag Fb[2], to "1" (i.e., switches the value of flag Fb[2] from "0" to "1"). At this time, the control circuit 11[2] maintains the value of flag Fa[2], which is the self-detection flag, at "0". "Fb[2]=1" indicates that an abnormality was detected in another switch device 10 (here, switch device 10[1]) before the abnormality was detected in the switch device 10[2].

[0059] The control circuit 11[2] executes the second abnormality response process during the period when "Fb[2]=1", that is, during the period when the flag Fb[2] has the value "1". In the second abnormality response process for the first case, the control circuit 11[2] performs off-latch control. The off-latch control by the control circuit 11[2] switches the output transistor M1[2] from the on state to the off state and maintains the output transistor M1[2] in the off state regardless of the control signal Sin[2] (thus, even if the control signal Sin[2] is at a high level).

[0060] The control circuit 11[2] according to the first case switches the output transistor M1[2] to the off state by the second anomaly response process, and then maintains the output transistor M1[2] in the off state until a predetermined error release condition is met. That is, the off latch control by the control circuit 11[2] is stopped when the error release condition is met. The error release condition for the control circuit 11[2] is met when the level of the control signal Sin[2] changes from a high level (on command level) to a low level (off command level). In the first case, at time t A3 later time t A4 10, a fall edge occurs in the control signal Sin output from the MCU 20, and therefore the error release condition is met.

[0061] The control circuit 11 [2] according to the first case is configured to: A4When the error release condition is met at time t, the second anomaly response process is terminated (therefore, the off latch control that maintains the output transistor M1[2] in the off state is stopped) and the value of the flag Fb[2] is changed from "1" to "0" (see FIG. 10). A4 later time t A5 In this example, if a rising edge occurs in the control signal Sin output by the MCU 20, causing a rising edge in the control signal Sin[2] (i.e., if the level of the control signal Sin is set to high level), the control circuit 11[2] switches the output transistor M1[2] from the off state back to the on state in response to the rising edge of the control signal Sin[2]. Note that the control circuit 11[2] always keeps the diagnostic transistor 15a[2] in the off state when the control signal Sin[2] is at low level.

[0062] On the other hand, the control circuit 11[1] according to the first case is A3 After that, the first anomaly handling process is continued until a predetermined error release condition is met. The error release condition for the control circuit 11[1] is met when the level of the control signal Sin[1] changes from a high level (ON command level) to a low level (OFF command level). In the first case, at time t A3 later time t A4 At time t (see FIG. 10), a fall edge occurs in the control signal Sin output from the MCU 20, and the error release condition is met. A4 In the first case, when the level of the control signal Sin[1] becomes low, the control circuit 11[1] ends the first anomaly response process and keeps the output transistor M1[1] in the off state or switches the output transistor M1[1] from the on state to the off state. Also, the control circuit 11[1] according to the first case, after the start of the first anomaly response process, A4 When the error release condition is met at time t, the value of flag Fa[1] is changed from "1" to "0". A5In this example, if a rising edge occurs in the level of the control signal Sin output by the MCU 20, causing a rising edge in the control signal Sin[1] (i.e., if the level of the control signal Sin is set to a high level), the control circuit 11[1] switches the output transistor M1[1] from the off state back to the on state in response to the rising edge of the control signal Sin[1]. Note that the control circuit 11[1] always keeps the diagnostic transistor 15a[1] in the off state when the control signal Sin[1] is at a low level.

[0063] [Case 2] 11 and 12 are timing charts of the load driving system SYS in Case 2. In Case 2, of the abnormality detection circuits 14[2] and 14[1], some abnormality is detected only in the abnormality detection circuit 14[2].

[0064] When the supply of the power supply voltage Vbb starts in each switch device 10, the control circuit 11 executes an initial sequence operation, and the switch device 10 enters an initial state. In the initial state of the switch device 10, the output transistor M1 and the diagnostic transistor 15a are off, and the values ​​of the flags Fa and Fb are both "0." At time t shown in FIG. B1 Before time t, the MCU 20 keeps the control signal Sin that it outputs low. B1 In this case, the MCU 20 generates a rising edge in the control signal Sin that it outputs, which causes rising edges to also occur in the control signals Sin[1] and Sin[2].

[0065] time t B1 At time t, (Fa[1], Fb[1])=(0,0), so the control circuit 11[1] switches the output transistor M1[1] from the off state to the on state in response to the rising edge of the control signal Sin[1]. B1 Since (Fa[2], Fb[2])=(0, 0) in this case, the control circuit 11[2] switches the output transistor M1[2] from the off state to the on state in response to the rising edge of the control signal Sin[2].

[0066] time t B1 From the time t B2 No abnormality is detected by the abnormality detection circuits 14[1] and 14[2] until time t B2 A small amount of time has passed since the time t B3 In this example, the abnormality detection circuit 14[2] detects an abnormality in the switch device 10[2], and an abnormality detection signal indicating that an abnormality has been detected in the switch device 10[2] is transmitted from the abnormality detection circuit 14[2] to the control circuit 11[2]. In response to receiving the abnormality detection signal from the abnormality detection circuit 14[2], the control circuit 11[2] sets the self-detection flag flag Fa[2] to "1" (i.e., switches the value of flag Fa[2] from "0" to "1"). At this time, the control circuit 11[2] maintains the value of the other-detection flag flag Fb[2] at "0". "Fa[2]=1" indicates that an abnormality was first detected in the switch device 10[2] of the switch devices 10[1] and 10[2].

[0067] The control circuit 11[2] executes the first anomaly response process during the period when "Fa[2]=1", that is, during the period when the flag Fa[2] has the value "1".

[0068] In the first anomaly response process according to the second case, the control circuit 11[2] can perform off-latch control. The off-latch control by the control circuit 11[2] switches the output transistor M1[2] from an on state to an off state and maintains the output transistor M1[2] in the off state regardless of the control signal Sin[2] (even if the control signal Sin[2] is at a high level).

[0069] Alternatively, in the first anomaly response process according to the second case, the control circuit 11[2] can perform intermittent on / off control assuming that the control signal Sin[2] is high. When intermittent on / off control is performed in the first anomaly response process according to the second case, the control circuit 11[2] first switches the output transistor M1[2] from an on state to an off state, and then, depending on the type and circumstances of the detected anomaly, maintains the output transistor M1[2] in an off state, returns the output transistor M1[2] to an on state, or alternately turns the output transistor M1[2] on and off. In any case, like the off latch control, the intermittent on / off control by the control circuit 11[2] also includes switching the output transistor M1[2] off.

[0070] Alternatively, in the first anomaly response process according to the second case, the control circuit 11[2] can perform current limiting control on the assumption that the control signal Sin[2] is at a high level. The current limiting control by the control circuit 11[2] keeps the output transistor M1[2] in an on state and prevents the value of the output current Iout[2] from exceeding a predetermined limit value I LIM It is limited to the following:

[0071] In the first anomaly handling process for the second case, the control circuit 11[2] sets the diagnostic transistor 15a[2] to the ON state. B3 (strictly speaking, at time t B3 After a short time has elapsed since the start of the first anomaly detection, a fall edge occurs in the diagnostic signal Sst and the diagnostic signals Sst[1] and Sst[2] on the signal wiring W4. That is, in the first anomaly response process for the second case, the control circuit 11[2] switches the state of the diagnostic terminal ST[2] from the Hi-Z state to the Lo-Z state using the diagnostic output circuit 15[2], thereby switching the voltage level of the diagnostic terminal ST[2] from the high level (the level of the power supply voltage VCC) to the low level (the level of the ground).

[0072] In the second case, in response to the occurrence of a fall edge in the diagnostic signal Sst[1], the control circuit 11[1] sets the other detection flag, flag Fb[1], to "1" (i.e., switches the value of flag Fb[1] from "0" to "1"). At this time, the control circuit 11[1] maintains the value of flag Fa[1], which is the self-detection flag, at "0". "Fb[1]=1" indicates that an abnormality was detected in another switch device 10 (here, switch device 10[2]) before the abnormality was detected in the switch device 10[1].

[0073] The control circuit 11[1] executes the second abnormality response process during the period when "Fb[1]=1", that is, during the period when the flag Fb[1] has the value "1". In the second abnormality response process for the second case, the control circuit 11[1] performs off-latch control. The off-latch control by the control circuit 11[1] switches the output transistor M1[1] from the on state to the off state and maintains the output transistor M1[1] in the off state regardless of the control signal Sin[1] (thus, even if the control signal Sin[1] is at a high level).

[0074] The control circuit 11[1] according to the second case switches the output transistor M1[1] to the off state by the second anomaly response process, and then maintains the output transistor M1[1] in the off state until a predetermined error release condition is met. That is, the off latch control by the control circuit 11[1] is stopped when the error release condition is met. The error release condition for the control circuit 11[1] is met when the level of the control signal Sin[1] changes from a high level (on command level) to a low level (off command level). In the second case, at time t B3 later time t B4 12, a fall edge occurs in the control signal Sin output from the MCU 20, and therefore the error release condition is met.

[0075] The control circuit 11[1] according to the second case is configured to: B4When the error release condition is met at time t, the second anomaly response process is terminated (therefore, the off latch control that maintains the output transistor M1[1] in the off state is stopped) and the value of the flag Fb[1] is changed from "1" to "0" (see FIG. 12). B4 later time t B5 In this example, if a rising edge occurs in the control signal Sin output by the MCU 20, causing a rising edge in the control signal Sin[1] (i.e., if the level of the control signal Sin is set to high level), the control circuit 11[1] switches the output transistor M1[1] from the off state back to the on state in response to the rising edge of the control signal Sin[1]. Note that the control circuit 11[1] always keeps the diagnostic transistor 15a[1] in the off state when the control signal Sin[1] is at low level.

[0076] On the other hand, the control circuit 11[2] according to the second case is B3 After that, the first abnormality handling process is continued until a predetermined error release condition is met. The error release condition for the control circuit 11[2] is met when the level of the control signal Sin[2] changes from a high level (ON command level) to a low level (OFF command level). In the second case, at time t B3 later time t B4 At time t (see FIG. 12), a fall edge occurs in the control signal Sin output from the MCU 20, and the error release condition is met. B4 In the second case, when the level of the control signal Sin[2] becomes low, the control circuit 11[2] ends the first anomaly response process and keeps the output transistor M1[2] in the off state or switches the output transistor M1[2] from the on state to the off state. Also, the control circuit 11[2] according to the second case, after the start of the first anomaly response process, B4 When the error release condition is met at time t, the value of flag Fa[2] is changed from "1" to "0". B5In this example, if a rising edge occurs in the level of the control signal Sin output by the MCU 20, causing a rising edge in the control signal Sin[2] (i.e., if the level of the control signal Sin is set to high level), the control circuit 11[2] switches the output transistor M1[2] from the off state back to the on state in response to the rising edge of the control signal Sin[2]. Note that the control circuit 11[2] always keeps the diagnostic transistor 15a[2] in the off state when the control signal Sin[2] is at low level.

[0077] [Discussion including explanation of reference configuration] When supplying / cutting power to a load using a semiconductor switching element (corresponding to output transistor M1), it is necessary to minimize the on-resistance of the switching element. If power could be supplied to the load through a parallel circuit of multiple switching elements, the total on-resistance could be reduced. However, using switch devices having switching elements in parallel is usually difficult or not recommended (the switch device described here is a switch device different from switch device 10, and will be referred to as a reference switch device hereinafter). This is because there is a risk of malfunction due to differences in thresholds for overcurrent protection, overheat protection, etc. among multiple reference switch devices.

[0078] For example, when two reference switch devices are connected in parallel, differences in thresholds for overcurrent protection or overheat protection, etc., can cause one reference switch device to detect an abnormality and perform protective operation, while the other reference switch device continues normal operation without detecting an abnormality. In this case, a current higher than normal flows through the reference switch device that continues normal operation, and it is highly likely that an abnormality (such as an overcurrent abnormality) will be detected after a while. However, the abnormality detection and protective operation in the two reference switch devices are performed independently. Therefore, in a reference configuration such as that shown in FIG. 13 in which two reference switch devices, i.e., switch devices 910, separately supply diagnostic signals Sst' to the MCU 920, it is difficult for the MCU 920 to accurately grasp the load-side situation, making system design complicated.

[0079] For this reason, in systems that require a fairly low on-resistance, it is common to prepare multiple switching elements as discrete components, prepare a separate controller to drive and control each discrete component (switching element), and adopt a circuit configuration in which multiple discrete components are connected in parallel. However, this type of circuit configuration increases the number of components, which is disadvantageous in terms of cost. It also increases the difficulty of designing the board layout.

[0080] In contrast, in the load driving system SYS according to this embodiment, the switch device 10 that first detects an abnormality among the multiple switch devices 10 primarily transmits an error signal (a low-level diagnostic signal Sst on the diagnostic wiring W4) to the MCU 20. Therefore, by referring to the diagnostic signal Sst transmitted through the diagnostic wiring W4, the MCU 20 can accurately and simply recognize the state of the group of switch devices (10[1] to 10[n]) that drive the load LD. Since a sufficiently low on-resistance can be achieved using the switch device 10, which is an electronic component incorporating the output transistor M1, the number of components and costs can be reduced compared to a circuit configuration using discrete components, and the design of the board layout can also be expected to be simplified.

[0081] Because the load driving system SYS is designed to drive the load LD using a switch device group consisting of n switch devices 10, a state in which an abnormality is detected in a specific switch device 10 corresponds to a state in which an abnormality has occurred in the switch device group. When an abnormality has occurred in the switch device group (i.e., when the load LD is not being driven as designed), it is undesirable for the other switch devices 10 to continue operating independently of the abnormality in the specific switch device 10, as this may lead to unexpected problems (the overall behavior of the switch device group becomes unpredictable, resulting in a lack of operational stability). Taking this into consideration, in the configuration of this embodiment, when an abnormality is detected in a specific switch device 10, this information is transmitted to the other switch devices 10 via the respective diagnostic terminals ST, and the output transistors M1 of the other switch devices 10 are latched off. This eliminates the above-mentioned concerns.

[0082] Unlike the first and second cases, in the third case where abnormalities are detected simultaneously by the abnormality detection circuits 14[1] and 14[2], the control circuit 11[1] sets the flag Fa[1] to "1", and independently the control circuit 11[2] sets the flag Fa[2] to "1". Therefore, after the abnormality detection circuits 14[1] and 14[2] simultaneously detect abnormalities, the control circuit 11[1] performs the first abnormality response operation, and independently the control circuit 11[2] also performs the first abnormality response operation. In the third case, a single error signal is also supplied to the MCU 20, so no particular problems arise.

[0083] Below, several specific operation examples, application techniques, modified techniques, etc. related to the load drive system SYS or the switch device 10 will be described in multiple embodiments. The matters described above in this embodiment are applied to each of the following embodiments unless otherwise specified and unless there is a contradiction. If there are any matters in each embodiment that contradict the matters described above, the description in that embodiment may take precedence. Furthermore, unless there is a contradiction, the matters described in any of the multiple embodiments shown below can also be applied to any of the other embodiments (i.e., any two or more of the multiple embodiments can be combined).

[0084] <<First Example>> A first embodiment will be described. An overcurrent abnormality is included in the multiple types of abnormalities that can be detected by the abnormality detection circuit 14. In the first embodiment, it is assumed that the abnormality that can be detected by the abnormality detection circuit 14 is an overcurrent abnormality.

[0085] As described above, the abnormality detection circuit 14 incorporates a current sensor that detects the current (i.e., the output current Iout) flowing through the output transistor M1. In each switch device 10, the abnormality detection circuit 14 compares the value of the output current Iout detected using the current sensor with a predetermined overcurrent threshold I TH The presence or absence of an overcurrent abnormality is determined by comparing it with the

[0086] In each switch device 10, the abnormality detection circuit 14 detects whether the value of the output current Iout is greater than or equal to the overcurrent threshold I TH If the overcurrent threshold I is exceeded, it is determined that an overcurrent abnormality has occurred. TH The above value of the output current Iout[1] is A3 When an overcurrent is detected, the abnormality detection circuit 14[2] determines that an overcurrent abnormality exists and outputs an abnormality detection signal indicating that an overcurrent abnormality has been detected to the control circuit 11[1]. Similarly, the abnormality detection circuit 14[2] according to the second case (see FIG. 11) detects an overcurrent threshold I TH The above value of the output current Iout[2] is B3 When an overcurrent abnormality is detected, the control circuit 11 determines that an overcurrent abnormality exists and outputs an abnormality detection signal indicating that an overcurrent abnormality has been detected to the control circuit 11[2].

[0087] Alternatively, the abnormality detection circuit 14 in each switch device 10 detects whether the value of the output current Iout is greater than or equal to the overcurrent threshold I TH If the above condition continues for a predetermined time Δt1, it may be determined that an overcurrent abnormality has occurred. A3 The output current Iout[1] is equal to the overcurrent threshold I TH This is the point in time when the above state continues for a predetermined time Δt1 (see FIG. 9).A3 In the second case, the control circuit 11 may determine that an overcurrent abnormality has occurred at time t B3 The output current Iout[2] is equal to the overcurrent threshold I TH This is the point in time when the above state continues for a predetermined time Δt1 (see FIG. 11). B3 and outputs an abnormality detection signal indicating that an overcurrent abnormality has been detected to the control circuit 11[2].

[0088] The control circuit 11[1] in the first case executes a first abnormality response operation when the abnormality detection circuit 14[1] detects an overcurrent abnormality. The control circuit 11[2] in the second case executes a first abnormality response operation when the abnormality detection circuit 14[2] detects an overcurrent abnormality. As already mentioned, the first abnormality response operation can perform off-latch control, intermittent on / off control, or current limiting control.

[0089] When the off-latch control is performed in the first abnormality response operation according to the first case, the control circuit 11 [1] A3 and t A4 During this period, the output transistor M1[1] is maintained in the off state regardless of the control signal Sin[1] (even if the control signal Sin[1] is at a high level).

[0090] When intermittent on / off control is performed in the first abnormality response operation according to the first case, the control circuit 11[1] A3 After switching the output transistor M1[1] from on to off, the output transistor M1[1] is kept off for a predetermined cool-down time Δt2, and then the output transistor M1[1] is turned back on. After the output transistor M1[1] is turned back on, the value of the output current Iout[1] reaches the overcurrent threshold I THIf the value is equal to or exceeds the overcurrent threshold I, the output transistor M1[1] is kept off for a predetermined cool-down time Δt2, and the above operation is repeated. After the intermittent on / off control is started, the value of the output current Iout[1] when the output transistor M1[1] is on is equal to or exceeds the overcurrent threshold I TH If the voltage Vin is kept below the threshold voltage Vin, the control circuit 11[1] may keep the output transistor M1[1] on, provided that the control signal Sin[1] has a high level.

[0091] When current limiting control is performed in the first abnormality response operation according to the first case, the control circuit 11[1] controls the output current Iout[1] to a predetermined limit value I while keeping the output transistor M1[1] in the on state. LIM The gate voltage of the output transistor M1[1] is adjusted using the detection result of the current sensor so that it is limited to the following:

[0092] When the off latch control is performed in the first abnormality response operation according to the second case, the control circuit 11 [2] B3 and t B4 During this period, the output transistor M1[2] is maintained in the off state regardless of the control signal Sin[2] (even if the control signal Sin[2] is at a high level).

[0093] When the intermittent on / off control is performed in the first abnormality response operation according to the second case, the control circuit 11 [2] B3 After switching the output transistor M1[2] from on to off, the output transistor M1[2] is kept off for a predetermined cool-down time Δt2, and then the output transistor M1[2] is turned back on. After the output transistor M1[2] is turned back on, the value of the output current Iout[2] reaches the overcurrent threshold I TH If the value is equal to or exceeds the overcurrent threshold I, the output transistor M1[2] is kept off for a predetermined cool-down time Δt2, and the above operation is repeated. After the intermittent on / off control is started, the value of the output current Iout[2] when the output transistor M1[2] is on is equal to or exceeds the overcurrent threshold I THIf the voltage Vin is kept below the threshold voltage Vin, the control circuit 11[2] may keep the output transistor M1[2] on, provided that the control signal Sin[2] has a high level.

[0094] When current limiting control is performed in the first abnormality response operation in the second case, the control circuit 11[2] keeps the output transistor M1[2] in the on state and prevents the value of the output current Iout[2] from exceeding a predetermined limit value I LIM The gate voltage of the output transistor M1[2] is adjusted using the detection result of the current sensor so that it is limited to the following:

[0095] <<Second Example>> A second embodiment will be described. Temperature abnormality is one of the multiple types of abnormality that can be detected by the abnormality detection circuit 14. In the second embodiment, it is assumed that the abnormality that can be detected by the abnormality detection circuit 14 is temperature abnormality.

[0096] In each switch device 10, the abnormality detection circuit 14 has a temperature protection circuit 14a that detects a temperature Tj (see FIG. 14). The temperature Tj is the temperature at a predetermined first temperature measurement location within the switch device 10, and the first temperature measurement location is the position of the output transistor M1 within the switch device 10. In other words, the temperature Tj is the temperature of the output transistor M1. More specifically, the temperature Tj is the temperature at a predetermined location of the semiconductor that constitutes the output transistor M1, and corresponds to the junction temperature of the output transistor M1. However, the temperature Tj may be the temperature of any predetermined location within the switch device 10 that is different from the temperature of the output transistor M1. The temperature protection circuit 14a outputs a signal S according to the detected temperature Tj. TSD The signal S TSD is a binary signal with a value of "0" or "1". TSD is supplied to the control circuit 11.

[0097] Figure 15 shows the relationship between temperature Tj and signal S TSD 1 is a timing chart showing the relationship between the temperature Tj and the signal S TSD has a value of "0". Signal S TSDStarting from the state where the value of Tj is "0", the temperature Tj increases and the value of Tj <T TSD _H” is established, and “Tj≧T TSD When the signal S TSD The value of changes from "0" to "1", and then the temperature Tj decreases, resulting in "Tj ≥ T TSD _L” is established, and “Tj <T TSD When the signal S_L” is asserted, TSD The value of changes from "1" to "0". Here, T TSD _H and T TSD _L represent the predetermined protection temperature (protection start temperature) and protection release temperature, respectively. Protection temperature T TSD _H is protection release temperature T TSD Higher than the protection temperature T TSD _H, protection release temperature T TSD _L are 175° C. and 155° C., respectively. In this way, the temperature protection circuit 14a detects when the temperature Tj rises and reaches the predetermined protection temperature T TSD When it reaches _H, the signal S TSD It is configured to switch the value from "0" to "1".

[0098] In each switch device 10, the abnormality detection circuit 14 detects the signal S TSD When the value of signal S changes from "0" to "1", it is determined that there is a temperature abnormality. TSD The temperature abnormality based on the value of is specifically referred to as the first temperature abnormality. Therefore, the abnormality detection circuit 14[1] according to the first case (see FIG. 9) detects the temperature abnormality at time t A3 The signal S in the abnormality detection circuit 14[1] TSD When the value of has changed from "0" to "1", it is determined that a first temperature abnormality has occurred, and a signal S of "1" is output as an abnormality detection signal indicating that a first temperature abnormality has been detected. TSD Similarly, the abnormality detection circuit 14[2] according to the second case (see FIG. 11) outputs the B3 The signal S in the abnormality detection circuit 14[2] TSD When the value of has changed from "0" to "1", it is determined that a first temperature abnormality has occurred, and a signal S of "1" is output as an abnormality detection signal indicating that a first temperature abnormality has been detected.TSD is output to the control circuit 11[2].

[0099] The control circuit 11[1] according to the first case executes a first abnormality response operation when the abnormality detection circuit 14[1] detects a first temperature abnormality. The control circuit 11[2] according to the second case executes a first abnormality response operation when the abnormality detection circuit 14[2] detects a first temperature abnormality. In the first abnormality response operation corresponding to the detection of the first temperature abnormality, off-latch control or intermittent on / off control is executed.

[0100] When the off-latch control is performed in the first abnormality response operation according to the first case, the control circuit 11 [1] A3 and t A4 The signal S in the abnormality detection circuit 14[1] is generated regardless of the control signal Sin[1] (even if the control signal Sin[1] is at a high level). TSD (hence, the signal S TSD (even if the value of GND returns to "0"), the output transistor M1[1] is kept in the off state.

[0101] When intermittent on / off control is performed in the first abnormality response operation according to the first case, the control circuit 11[1] A3 After the output transistor M1[1] is switched from on to off, the signal S supplied from the temperature protection circuit 14a in the abnormality detection circuit 14[1] TSD monitors the signal S TSD When the value of returns from "1" to "0", the output transistor M1[1] is switched from off to on, assuming that the control signal Sin[1] has a high level. TSD If the value of changes from "0" to "1", the control circuit 11[1] turns the output transistor M1[1] back off. After that, the same process is repeated.

[0102] When the off latch control is performed in the first abnormality response operation according to the second case, the control circuit 11 [2] B3 and t B4The signal S in the abnormality detection circuit 14[2] is generated regardless of the control signal S in [2] (even if the control signal S in [2] is at a high level). TSD (hence, the signal S TSD (even if the value of GND returns to "0"), the output transistor M1[2] is kept in the off state.

[0103] When the intermittent on / off control is performed in the first abnormality response operation according to the second case, the control circuit 11 [2] B3 After the output transistor M1[2] is switched from on to off, the signal S supplied from the temperature protection circuit 14a in the abnormality detection circuit 14[2] TSD monitors the signal S TSD When the value of returns from "1" to "0", the output transistor M1[2] is switched from off to on, assuming that the control signal Sin[2] has a high level. TSD If the value of changes from "0" to "1", the control circuit 11[2] turns off the output transistor M1[2] again. After that, the same process is repeated.

[0104] <<Third Example>> A third embodiment will now be described. As in the second embodiment, in the third embodiment, it is assumed that the abnormality that can be detected by the abnormality detection circuit 14 is a temperature abnormality.

[0105] In each switch device 10, the abnormality detection circuit 14 includes a temperature protection circuit 14b that detects the difference between temperatures Tj and Tcnt (see FIG. 16). Temperature Tj is as described in the second embodiment. Temperature Tcnt is the temperature at a predetermined second temperature measurement location within the switch device 10. The second temperature measurement location is a location away from the output transistor M1. For example, temperature Tcnt may be the temperature of the control circuit 11. In either case, the second temperature measurement location is different from the first temperature measurement location (the location where temperature Tj is measured) described in the second embodiment. The temperature difference between temperatures Tj and Tcnt is hereinafter referred to as the temperature difference ΔT. Note that the temperature difference ΔT represents the height of temperature Tj relative to temperature Tcnt, and therefore, the temperature difference ΔT is expressed as "ΔT = Tj - Tcnt." The temperature protection circuit 14b generates and outputs a signal S_ΔT corresponding to the detected temperature difference ΔT. The signal S_ΔT is a binary signal having a value of "0" or "1." The signal S_ΔT is supplied to the control circuit 11.

[0106] FIG. 17 is a timing chart showing the relationship between the temperature difference ΔT and the signal S_ΔT. When the temperature difference ΔT is sufficiently small, the signal S_ΔT has a value of "0." Starting from the state where the signal S_ΔT has a value of "0," as the temperature difference ΔT increases, the condition changes from "ΔT<ΔT_H" to "ΔT≧ΔT_H," and the value of the signal S_ΔT changes from "0" to "1." Then, as the temperature difference ΔT decreases, the condition changes from "ΔT≧ΔT_L" to "ΔT<ΔT_L," and the value of the signal S_ΔT changes from "1" to "0." Here, ΔT_H and ΔT_L represent the predetermined protection temperature difference (protection start temperature difference) and protection release temperature difference, respectively. The protection temperature difference ΔT_H is greater than the protection release temperature difference ΔT_L. For example, the protection temperature difference ΔT_H and the protection release temperature difference ΔT_L are 80° C. and 45° C., respectively. In this way, the temperature protection circuit 14b is configured to switch the value of the signal S_ΔT from “0” to “1” when the temperature difference ΔT increases and reaches the predetermined protection temperature difference ΔT_H.

[0107] In each switch device 10, the abnormality detection circuit 14 determines that there is a temperature abnormality when the value of the signal S_ΔT changes from "0" to "1." The temperature abnormality based on the value of the signal S_ΔT is specifically referred to as a second temperature abnormality. Therefore, the abnormality detection circuit 14[1] according to the first case (see FIG. 9) determines that there is a temperature abnormality at time t A3 In response to the change in value of the signal S_ΔT in the abnormality detection circuit 14[1] from "0" to "1", the circuit 11 determines that a second temperature abnormality has occurred and outputs a signal S_ΔT of "1" to the control circuit 11[1] as an abnormality detection signal indicating that a second temperature abnormality has been detected. Similarly, the abnormality detection circuit 14[2] for the second case (see FIG. 11) detects that a second temperature abnormality has occurred at time t B3 When the value of the signal S_ΔT in the abnormality detection circuit 14[2] switches from "0" to "1", it is determined that a second temperature abnormality has occurred, and the signal S_ΔT of "1" is output to the control circuit 11[2] as an abnormality detection signal indicating that the second temperature abnormality has been detected.

[0108] The control circuit 11[1] in the first case executes a first abnormality response operation when the abnormality detection circuit 14[1] detects a second temperature abnormality. The control circuit 11[2] in the second case executes a first abnormality response operation when the abnormality detection circuit 14[2] detects a second temperature abnormality. In the first abnormality response operation corresponding to the detection of the second temperature abnormality, off-latch control or intermittent on / off control is executed.

[0109] When the off-latch control is performed in the first abnormality response operation according to the first case, the control circuit 11 [1] A3 and t A4 During this period, the output transistor M1[1] is maintained in the off state regardless of the control signal Sin[1] (even if the control signal Sin[1] is at a high level) and regardless of the value of the signal S_ΔT in the abnormality detection circuit 14[1] (even if the value of the signal S_ΔT returns to "0").

[0110] When intermittent on / off control is performed in the first abnormality response operation according to the first case, the control circuit 11[1] A3After switching the output transistor M1[1] from on to off, the control circuit 11[1] monitors the signal S_ΔT supplied from the temperature protection circuit 14b in the abnormality detection circuit 14[1], and if the value of the signal S_ΔT returns from "1" to "0", it switches the output transistor M1[1] from off to on, assuming that the control signal Sin[1] is at a high level. After that, if the value of the signal S_ΔT changes from "0" to "1", the control circuit 11[1] switches the output transistor M1[1] back to off. Thereafter, the same process is repeated.

[0111] When the off latch control is performed in the first abnormality response operation according to the second case, the control circuit 11 [2] B3 and t B4 During this period, the output transistor M1[2] is maintained in the off state regardless of the control signal Sin[2] (even if the control signal Sin[2] is at a high level) and regardless of the value of the signal S_ΔT in the abnormality detection circuit 14[2] (even if the value of the signal S_ΔT returns to "0").

[0112] When the intermittent on / off control is performed in the first abnormality response operation according to the second case, the control circuit 11 [2] B3 After switching the output transistor M1[2] from on to off, the control circuit 11[2] monitors the signal S_ΔT supplied from the temperature protection circuit 14b in the abnormality detection circuit 14[2], and if the value of the signal S_ΔT returns from "1" to "0", it switches the output transistor M1[2] from off to on, assuming that the control signal Sin[2] is at a high level. After that, if the value of the signal S_ΔT changes from "0" to "1", the control circuit 11[2] switches the output transistor M1[2] back to off. Thereafter, the same process is repeated.

[0113] <<Fourth Example>> A fourth embodiment will be described. TH For example, the control circuit 11 may be configured to set multiple thresholds, such as an overcurrent threshold I THIn this case, the control circuit 11, which has received the command signal from the MCU 20, sets one of the plurality of thresholds as the overcurrent threshold I in accordance with the content specified by the command signal. TH Alternatively, an adjustment terminal may be provided in the switch device 10 as one of the external terminals, and the overcurrent threshold I TH The adjustment resistor may be connected between the adjustment terminal and the ground. In this case, the overcurrent threshold I TH The control circuit 11 should have a function to set and change the overcurrent threshold I. TH By configuring the switch device 10 to be adjustable, it is possible to operate the overcurrent protection at a current value appropriate for the load drive system SYS.

[0114] It is also possible to design, manufacture, and sell a plurality of types of switch devices 10 in which the on-resistance of the output transistor M1 differs from one another. TH Making the on-resistance adjustable is also effective in reducing the number of types of switch devices 10 (reducing the number of lineups of on-resistances that need to be prepared).

[0115] However, the switch device 10 has an overcurrent threshold I TH It is not essential to provide the switch device 10 with an adjustment function for the overcurrent threshold I TH If the adjustment function of the overcurrent threshold I is not provided, the communication function for transmitting and receiving the command signal can be omitted, and the adjustment terminal and adjustment resistor are also unnecessary. TH It is possible to set the overcurrent threshold I to a relatively high value. For example, suppose that in the steady state, a 10A current is supplied to the load LD according to the design. Then, in the steady state, a current of 5A flows through each of the output transistors M1[1] and M1[2]. In such a configuration, the overcurrent threshold I is set to a value higher than the current supplied to the load LD in the steady state. THIt is sufficient to use each switch device 10 with a current limiting control set to a predetermined value (e.g., 12 A). In this way, even if one switch device 10 detects an abnormality and latches the output transistor M1 of the other switch device 10 off, the other switch device 10 can continue to supply the necessary current (10 A) to the load LD by using current limiting control or the like. The MCU 20 receives the low-level diagnostic signal Sst and issues an alarm to the driver of the vehicle VHCL, allowing the driver to take appropriate action, such as stopping the vehicle VHCL on the shoulder of the road. Even in a system designed to supply current to the load LD through cooperation between two switch devices 10, it is unlikely that a problem will arise if the load LD is driven by only one of the switch devices 10 for a short period of time, such as when the vehicle VHCL is stopped on the shoulder of the road.

[0116] <<Fifth Example>> A fifth embodiment will now be described.

[0117] In consideration of the concreteness of the explanation, the operation of the load driving system SYS has been described mainly assuming that "n=2." n corresponds to the total number of switch devices 10 (total number of output transistors M1 connected in parallel) (see FIG. 7). However, "n≧3" may also be true. For example, when "n=3," in the first case described above (FIGS. 9 and 10), the operation of switch device 10[3] is the same as the operation of switch device 10[2], and in the second case described above (FIGS. 11 and 12), the operation of switch device 10[3] is the same as the operation of switch device 10[1].

[0118] The load driving system SYS includes a switch system, which is configured with switch devices 10[1] to 10[n].

[0119] In the configuration illustrated in FIG. 1 and elsewhere, the switch device 10 is used as a so-called high-side switch. However, the switch device 10 may also be used as a so-called low-side switch. That is, the load LD may be inserted in series with the input wiring W1. In this case, the terminal VBB of each switch device 10 functions as a load connection terminal, and the output terminal OUT is directly connected to ground via the output wiring W2 (or the ground terminal GND is used as the output terminal OUT). In addition, the power supply voltage VCC may be separately supplied to the switch terminal 10 as a power supply voltage for driving the switch device 10 (by adding an external terminal for receiving the power supply voltage VCC to each switch terminal 10). When each switch device 10 is used as a so-called low-side switch, the charge pump circuit 13 is unnecessary, and the internal power supply circuit 16 simply generates the internal power supply voltage Vreg from the power supply voltage VCC.

[0120] In the present embodiment, an example has been given in which the switch device 10 is applied to a vehicle VHCL, but the application of the switch device 10 is not limited to a vehicle VHCL and may be any. For example, the switch device 10 may be mounted on any industrial machine or any home appliance.

[0121] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0122] The channel types of the FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0123] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0124] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0125] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0126] A switch device (10) according to one aspect of the present disclosure includes an input terminal (VBB), an output terminal (OUT), a diagnostic terminal (ST), an output transistor (M1) provided between the input terminal and the output terminal, a control circuit (11) configured to control the output transistor to be on or off in response to a control signal (Sin) supplied to the switch device, an abnormality detection circuit (14) configured to detect an abnormality in the switch device, and a diagnostic output circuit (15) configured to control the state of the diagnostic terminal, and the control circuit is configured to set the output transistor to on during a reference period (time t A1 and t A2 The period between or time t B1 and t B2 When the abnormality is detected after a reference period (a period between the reference period and the reference time), a first abnormality response operation is performed, and in the first abnormality response operation, the output transistor is switched from on to off or the value of the current flowing through the output transistor is limited to a limit value or less, and the state of the diagnostic terminal is switched from a first state (Hi-Z state) to a second state (Lo-Z state) using the diagnostic output circuit, thereby switching the voltage level of the diagnostic terminal from a first level (high level) to a second level (low level). When the abnormality is not detected after the reference period and the voltage level of the diagnostic terminal has changed from the first level to the second level, the control circuit performs a second abnormality response operation, and in the second abnormality response operation, the output transistor is switched from on to off.

[0127] When a switch device group is formed from multiple switch devices whose diagnostic terminals are connected to each other, detecting an abnormality in a specific switch device corresponds to an abnormality occurring in the switch device group. In this case, it is undesirable for the other switch devices to continue operating independently of the abnormality occurring in a specific switch device, as this could lead to unexpected problems (the overall behavior of the switch device group would become unpredictable, resulting in a lack of stability in the operation of the switch device group). By forming a switch device group using the first configuration, when an abnormality is detected in a specific switch device, the abnormality can be communicated to the other switch devices through each diagnostic terminal, switching off the output transistors of the other switch devices. In other words, the other switch devices will not continue operating independently of the abnormality occurring in a specific switch device, thereby eliminating the above-mentioned concerns (the first configuration can achieve this effect). Furthermore, the level of the wiring connecting the diagnostic terminals can be provided to an external control device, and in this case, the status of the switch device group can be grasped collectively by simply monitoring the level of the wiring from the external control device.

[0128] In the switch device according to the first configuration, the control circuit may be configured to maintain the output transistor in an off state after switching the output transistor from on to off in the second abnormality response operation (second configuration).

[0129] In the switch device according to the first configuration (see FIG. 10 or 12), the control circuit may be configured (third configuration) such that, after switching the output transistor from on to off in the second abnormality response operation, the control circuit maintains the output transistor off until an error cancellation condition is satisfied, the error cancellation condition being satisfied when the level of the control signal changes from an on command level (high level) that commands the output transistor to be set on to an off command level (low level) that commands the output transistor to be set off, and the control circuit, after switching the output transistor from on to off in the second abnormality response operation, switches the output transistor from off to on in response to the level of the control signal being set to the on command level after the error cancellation condition is satisfied. Note that the on command level and the off command level may be different from each other, and the relationship between their high and low levels may be arbitrary.

[0130] In the switch device according to any of the first to third configurations, the diagnostic terminal may be configured to be connected to a diagnostic wiring (W4) outside the switch device, the input impedance of the diagnostic terminal as seen from the diagnostic wiring is higher in the first state (Hi-Z state) than in the second state (Lo-Z state), when the diagnostic output circuit sets the state of the diagnostic terminal to the second state, a diagnostic current is generated through the diagnostic terminal and the diagnostic wiring, causing the voltage level of the diagnostic terminal to have the second level, and when the diagnostic output circuit sets the state of the diagnostic terminal to the first state, the diagnostic current is cut off, and the action of the diagnostic output circuit to set the voltage level of the diagnostic terminal to the second level may be stopped (fourth configuration).

[0131] In a switch device according to any of the first to third configurations, the diagnostic terminal may be configured to be connected to a diagnostic wiring (W4) outside the switch device, the diagnostic wiring being connected to an application terminal (51) of the first level voltage via a pull-up resistor (Ra), the diagnostic output circuit including a diagnostic switching element (15a) provided between the diagnostic terminal and ground, the second state being a state in which the diagnostic switching element is set to on to generate a diagnostic current flowing from the application terminal through the pull-up resistor, the diagnostic terminal, and the diagnostic switching element, thereby setting the voltage level of the diagnostic terminal to the second level lower than the first level, the first state being a state in which the diagnostic switching element is set to off, and when the state of the diagnostic terminal is set to the first state by the diagnostic output circuit, the diagnostic current through the diagnostic output circuit is cut off and the action of the diagnostic output circuit to set the voltage level of the diagnostic terminal to the second level may be stopped (fifth configuration).

[0132] In the switch device according to any one of the first to fifth configurations, the abnormality includes an overcurrent abnormality, and the abnormality detection circuit detects a value of an output current (Iout) flowing through the output transistor as a predetermined overcurrent threshold (I TH ) to determine whether or not there is an overcurrent abnormality, and when the overcurrent abnormality is detected after the reference period, the control circuit executes the first abnormality response operation, and in the first abnormality response operation based on the detection of the overcurrent abnormality, the control circuit may switch the output transistor from on to off or limit the value of the current flowing through the output transistor to less than or equal to the limit value (sixth configuration).

[0133] In the switch device according to any one of the first to sixth configurations, the abnormality includes a temperature abnormality, and the abnormality detection circuit detects a temperature (Tj) of the output transistor at a predetermined protection temperature (T TSDThe control circuit may be configured to determine the presence or absence of the temperature abnormality by comparing the temperature difference (ΔT=Tj-Tcnt) between the temperature of the output transistor and another temperature in the switch device with a predetermined protection temperature difference (ΔT_H), and when the temperature abnormality is detected after the reference period, the control circuit executes the first abnormality response operation, and switches the output transistor from on to off in the first abnormality response operation based on the detection of the temperature abnormality (seventh configuration).

[0134] A load driving system (SYS) according to one aspect of the present disclosure is a load driving system including a plurality of switch devices (10) according to any of the first to seventh configurations above, and an external control device (20) configured to supply the control signal to each switch device, wherein the plurality of output transistors (M1[1] to M1[n]) in the plurality of switch devices are connected in parallel with each other, current is supplied to a load (LD) through the parallel circuit of the plurality of output transistors, and diagnostic wiring (W4) to which the plurality of diagnostic terminals (ST[1] to ST[n]) in the plurality of switch devices are commonly connected is connected to the external control device (eighth configuration).

[0135] The load drive system described above can be designed to drive a load using a group of switch devices consisting of multiple switch devices. In this case, a state in which an abnormality is detected in a specific switch device corresponds to a state in which an abnormality has occurred in the group of switch devices. When an abnormality occurs in the group of switch devices (i.e., when the load is not being driven as designed), it is undesirable for the other switch devices to continue operating independently of the abnormality in the specific switch device, as this could lead to unexpected problems (the overall behavior of the group of switch devices becomes unpredictable, resulting in a lack of stability in the operation of the group of switch devices). In the load drive system described above, when an abnormality is detected in a specific switch device, this is communicated to the other switch devices through the respective diagnostic terminals, and the output transistors of the other switch devices are switched off. In other words, the other switch devices do not continue operating independently of the abnormality in a specific switch device, eliminating the above-mentioned concerns. Furthermore, because the diagnostic wiring connecting the diagnostic terminals is connected to an external control device, the status of the group of switch devices can be grasped collectively by simply monitoring the level of the diagnostic wiring from the external control device.

[0136] In the load driving system according to the eighth configuration, the reference period is a period during which the abnormality is not detected in each of the plurality of switch devices and the output transistor is set to on in accordance with the control signal, and when the abnormality is detected in a specific switch device (e.g., 10[1]) included in the plurality of switch devices after the reference period, the first abnormality response operation is executed in the control circuit of the specific switch device, and the voltage level of the diagnostic wiring is switched from the first level to the second level using the diagnostic output circuit of the specific switch device, and in response to the switching, the second abnormality response operation is executed in a switch device (e.g., 10[2]) of the plurality of switch devices other than the specific switch device, which may be a configuration (ninth configuration).

[0137] A switch system according to one aspect of the present disclosure is a switch system including a plurality of switch devices (10) according to any of the first to seventh configurations, in which the plurality of output transistors (M1[1] to M1[n]) in the plurality of switch devices are connected in parallel with each other, and the plurality of diagnostic terminals (ST[1] to ST[n]) in the plurality of switch devices are commonly connected to diagnostic wiring (W4) (tenth configuration).

[0138] In the switch system according to the eighth configuration, the reference period is a period during which the abnormality is not detected in each of the plurality of switch devices and the output transistor is set to on in accordance with the control signal, and when the abnormality is detected in a specific switch device (e.g., 10[1]) included in the plurality of switch devices after the reference period, the first abnormality response operation is performed in the control circuit of the specific switch device, thereby switching the voltage level of the diagnostic terminal from the first level to the second level using the diagnostic output circuit of the specific switch device, and in response to the switching, the second abnormality response operation is performed in a switch device (e.g., 10[2]) of the plurality of switch devices other than the specific switch device (an eleventh configuration). [Explanation of symbols]

[0139] SYS Load drive system VS voltage source LD load Cout Output capacitor W1 input wiring W2 output wiring W3 Control wiring W4 Diagnostic Wiring 30 Communication Bus Iout Output current Vout Output voltage Vbb power supply voltage Sin control signal Sst diagnostic signal 10 Switching device 20 MCU Ra pull-up resistor VBB power supply terminal OUT output terminal GND Ground terminal IN Control input terminal ST diagnostic terminal CS chassis VHCL Vehicles BLK Electrical block M1 Output transistor 11 Control circuit 12 Memory 13 Charge pump circuit 14 Abnormality detection circuit 14a, 14b Temperature protection circuit 15 Diagnostic Output Circuit 15a Diagnostic transistor 16 Internal power circuit SM1, SM2 Schmitt buffer Vcp drive voltage Vreg Internal power supply voltage Fa, Fb flags

Claims

1. A switching device, a control circuit configured to control the output transistor to be turned on or off in response to a control signal supplied to the switch device; an abnormality detection circuit configured to detect an abnormality in the switch device; and a diagnostic output circuit configured to control the state of the diagnostic terminal; the control circuit, when the abnormality is detected after a reference period in which the abnormality is not detected and the output transistor is set to on in accordance with the control signal, executes a first abnormality response operation, in which the control circuit switches the output transistor from on to off or limits a value of a current flowing through the output transistor to a limit value or less, and switches a state of the diagnostic terminal from a first state to a second state using the diagnostic output circuit, thereby switching a voltage level of the diagnostic terminal from a first level to a second level; When the abnormality is not detected and the voltage level of the diagnostic terminal changes from the first level to the second level after the reference period, the control circuit executes a second abnormality response operation, and switches the output transistor from on to off in the second abnormality response operation. , switch device.

2. The control circuit switches the output transistor from on to off in the second abnormality response operation, and then maintains the output transistor off. The switch device according to claim 1 .

3. the control circuit, after switching the output transistor from on to off in the second abnormality response operation, maintains the output transistor in an off state until an error cancellation condition is satisfied; the error release condition is met when a level of the control signal changes from an ON command level instructing to set the output transistor ON to an OFF command level instructing to set the output transistor OFF, The control circuit switches the output transistor from on to off in the second abnormality response operation, and then switches the output transistor from off to on in response to the level of the control signal being set to the on command level after the error release condition is satisfied. The switch device according to claim 1 .

4. the diagnostic terminal is configured to be connected to diagnostic wiring outside the switch device; an input impedance of the diagnostic terminal seen from the diagnostic wiring is higher in the first state than in the second state; when the diagnostic output circuit sets the state of the diagnostic terminal to the second state, a diagnostic current is generated through the diagnostic terminal and the diagnostic wiring, causing a voltage level of the diagnostic terminal to have the second level; When the diagnostic output circuit sets the state of the diagnostic terminal to the first state, the diagnostic current is cut off and the diagnostic output circuit stops setting the voltage level of the diagnostic terminal to the second level. The switch device according to claim 1 .

5. the diagnostic terminal is configured to be connected to a diagnostic wiring outside the switch device, and the diagnostic wiring is connected to an application terminal of the first level voltage via a pull-up resistor; the diagnostic output circuit includes a diagnostic switching element provided between the diagnostic terminal and ground; the second state is a state in which the diagnostic switching element is turned on to generate a diagnostic current flowing from the application end through the pull-up resistor, the diagnostic terminal, and the diagnostic switching element, thereby setting the voltage level of the diagnostic terminal to the second level lower than the first level; The first state is a state in which the diagnostic switching element is set to OFF, and when the state of the diagnostic terminal is set to the first state by the diagnostic output circuit, the diagnostic current through the diagnostic output circuit is cut off and the diagnostic output circuit stops setting the voltage level of the diagnostic terminal to the second level. The switch device according to claim 1 .

6. the abnormality includes an overcurrent abnormality, and the abnormality detection circuit determines whether or not the overcurrent abnormality exists by comparing a value of the output current flowing through the output transistor with a predetermined overcurrent threshold; When the overcurrent abnormality is detected after the reference period, the control circuit executes the first abnormality response operation, and in the first abnormality response operation based on the detection of the overcurrent abnormality, switches the output transistor from on to off or limits the value of the current flowing through the output transistor to the limit value or less. The switch device according to claim 1 .

7. the abnormality includes a temperature abnormality, and the abnormality detection circuit determines whether or not there is a temperature abnormality by comparing the temperature of the output transistor with a predetermined protection temperature, or by comparing a temperature difference between the temperature of the output transistor and another temperature in the switch device with a predetermined protection temperature difference; When the temperature abnormality is detected after the reference period, the control circuit executes the first abnormality response operation, and switches the output transistor from on to off in the first abnormality response operation based on the detection of the temperature abnormality. The switch device according to claim 1 .

8. A load driving system comprising a plurality of switch devices according to any one of claims 1 to 7 and an external control device configured to supply the control signal to each switch device, a plurality of output transistors in the plurality of switch devices are connected in parallel to each other, and a current is supplied to a load through the parallel circuit of the plurality of output transistors; A diagnostic wiring, to which a plurality of diagnostic terminals of the plurality of switch devices are commonly connected, is connected to the external control device. , load driving system.

9. the reference period is a period during which the abnormality is not detected in each of the plurality of switch devices and the output transistor is set to on in accordance with the control signal, After the reference period, when the abnormality is detected in a specific switch device included in the plurality of switch devices, the first abnormality response operation is executed in the control circuit of the specific switch device, whereby the voltage level of the diagnostic wiring is switched from the first level to the second level using the diagnostic output circuit of the specific switch device, and in response to the switching, the second abnormality response operation is executed in switch devices of the plurality of switch devices other than the specific switch device.

9. The load driving system according to claim 8.

10. A switch system including a plurality of switch devices according to any one of claims 1 to 7, wherein the plurality of output transistors in the plurality of switch devices are connected in parallel with each other, and the plurality of diagnostic terminals in the plurality of switch devices are commonly connected to a diagnostic wiring. , Switch System

11. the reference period is a period during which the abnormality is not detected in each of the plurality of switch devices and the output transistor is set to on in accordance with the control signal, After the reference period, when the abnormality is detected in a specific switch device included in the plurality of switch devices, the first abnormality response operation is executed in the control circuit of the specific switch device, whereby the voltage level of the diagnostic terminal is switched from the first level to the second level using the diagnostic output circuit of the specific switch device, and in response to the switching, the second abnormality response operation is executed in switch devices of the plurality of switch devices other than the specific switch device.

11. The switch system of claim 10.

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