Switching device and load driving system

Abstract

To respond appropriately to overcurrent.SOLUTION: A switch device (10) includes an input terminal (VBB), an output terminal (OUT), an output transistor (M1) provided between the input terminal and the output terminal, and a control circuit (11, etc.) that controls the output transistor to turn on or off in response to a control signal (Sin). The control circuit is capable of performing a protection operation that switches the output transistor from on to off, regardless of the control signal, on the basis of an external temperature (Tmp) of the switch device and an output current (Iout) flowing through the output transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a switch device and a load drive system. [Background technology]

[0002] 2. Description of the Related Art There is a switching device that turns on or off an output transistor provided between two terminals in response to an input control signal, thereby establishing or blocking conduction between the two terminals. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 065395

[0004] [overview] In order to ensure the safety of the wiring connected in series to the output transistor outside the switch device, appropriate measures against overcurrent are also required.

[0005] A switch device according to one aspect of the present disclosure includes an input terminal, an output terminal, an output transistor provided between the input terminal and the output terminal, and a control circuit configured to control the output transistor to be turned on or off in response to a control signal supplied to the switch device, wherein the control circuit is configured to be capable of performing a protection operation of switching the output transistor from on to off independently of the control signal, based on an external temperature of the switch device and an output current flowing through the output transistor. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is an overall configuration diagram of a load driving system according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is an external perspective view of a switch device according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a schematic configuration diagram of a vehicle according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is an explanatory diagram of three areas related to wiring safety according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is an operation flowchart of the switch device according to the embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram illustrating the relationship between the protection current value and the protection activation time according to the embodiment of the present disclosure. [Figure 7] FIG. 7 is a diagram illustrating the relationship between the protection current value and the protection activation time according to the embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram showing how the relationship between the protection current value and the protection activation time changes depending on the external temperature according to the embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram showing the relationship between the protection current value, the protection activation time, and the external temperature according to the first example of the embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram showing how the output current changes in the first example belonging to the embodiment of the present disclosure. [Figure 11] FIG. 11 is a diagram showing the relationship between the protection current value, the protection activation time, and the external temperature according to a second example of the embodiment of the present disclosure. [Figure 12] FIG. 12 is a diagram showing how the output current changes in a second example belonging to an embodiment of the present disclosure. [Figure 13] FIG. 13 is a diagram showing six candidates for the overcurrent protection characteristic according to a third example of the embodiment of the present disclosure. [Figure 14] FIG. 14 is a diagram showing a modified overall configuration of a load driving system according to a fourth example belonging to an embodiment of the present disclosure. [Figure 15] FIG. 15 is an explanatory diagram of a configuration for detecting an output current according to a fifth example of the embodiment of the present disclosure. [Figure 16] FIG. 16 is an explanatory diagram of a configuration for detecting an output current according to a sixth example of the embodiment of the present disclosure.

[0007] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the referenced drawings, identical parts are designated by the same reference numerals, and redundant descriptions of identical parts will be omitted as a general rule. For the sake of simplicity, in this specification, symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs may be omitted or abbreviated. For example, the output wiring referred to by "W2" (see FIG. 1) described below may be written as output wiring W2 or abbreviated as wiring W2, but they all refer to the same thing.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having a reference potential of 0 V (zero volts), or refers to the 0 V potential itself. The reference conductor may be formed using a conductor such as metal. The 0 V potential may also be referred to as ground potential. Ground potential and ground voltage are synonymous. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a potential seen from ground.

[0009] A level refers to the level of potential, and for any given signal or voltage, a high level has a higher potential than a low level. For any given signal or voltage, when the signal or voltage is at a high level, strictly speaking, the signal or voltage level is at a high level, and when the signal or voltage is at a low level, strictly speaking, the signal or voltage level is at a low level. A level for a signal may be expressed as a signal level, and a level for a voltage may be expressed as a voltage level.

[0010] For any signal having a high or low signal level, the period during which the signal level is high is called a high-level period, and the period during which the signal level is low is called a low-level period. The same applies to any voltage having a high or low voltage level.

[0011] For any transistor configured as a FET (field effect transistor) exemplified by a MOSFET, the on-state refers to a state in which the drain and source of the transistor are conducting, and the off-state refers to a state in which the drain and source of the transistor are non-conducting (blocked state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-mode MOSFET. MOSFET is an abbreviation of "metal-oxide-semiconductor field-effect transistor". Also, unless otherwise specified, in any MOSFET, the back gate may be considered to be short-circuited to the source.

[0012] Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection.

[0013] When any two voltages to be compared are voltage v1 and voltage v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0014] FIG. 1 shows an overall configuration diagram of a load driving system SYS according to an embodiment of the present disclosure. The load driving system SYS mainly comprises a switch device 10, an MCU (Micro Controller Unit) 20, and a temperature detection circuit 30. The MCU 20 is an example of an external control device that controls the operation of the switch device 10. The load driving system SYS also includes resistors 41 and 42. A voltage source VS, a load LD, and an output capacitor Cout are connected to the load driving system SYS. Here, the load LD and the output capacitor Cout are considered to be external elements of the load driving system SYS, but the load LD and the output capacitor Cout may also be considered to be included as components of the load driving system SYS. Similarly, the voltage source VS may or may not be considered to be included as a component of the load driving system SYS.

[0015] The switch device 10 includes a power supply terminal VBB, an output terminal OUT, a ground terminal GND, a control input terminal IN, a current information output terminal SNS, a diagnostic terminal ST, and terminals CSB, SCLK, SI, and SO. The power supply terminal VBB and the output terminal OUT may be referred to as a power input terminal and a power output terminal, respectively.

[0016] FIG. 2 is an external perspective view of the switch device 10. The switch device 10 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing CS (package) that houses the semiconductor chip, and multiple external terminals exposed to the outside of the switch device 10 through the housing CS. The switch device 10 is formed by encapsulating the semiconductor chip in a housing CS made of resin. Note that the number of external terminals of the switch device 10 and the type of housing CS of the switch device 10 shown in FIG. 2 are merely examples and can be designed as desired. FIG. 1 shows a total of 10 external terminals of the multiple external terminals provided on the switch device 10, including a power supply terminal VBB, an output terminal OUT, a ground terminal GND, a control input terminal IN, a current information output terminal SNS, a diagnostic terminal ST, and terminals CSB, SCLK, SI, and SO. However, other external terminals may also be provided on the switch device 10. Note that the power supply terminal VBB may be composed of two or more external terminals. The same applies to the output terminal OUT or the ground terminal GND.

[0017] The voltage source VS is connected to the ground and the input wiring W1, and outputs a power supply voltage Vbb, which is a positive DC voltage with respect to the ground. The power supply voltage Vbb is applied to the input wiring W1. The input wiring W1 is a wiring provided outside the switch device 10 and is a wiring connected to the voltage source VS and the power supply terminal VBB. Therefore, the power supply voltage Vbb is applied to the power supply terminal VBB. The current supplied from the voltage source VS to the power supply terminal VBB via the input wiring W1 is called the input current Iin.

[0018] The output terminal OUT is connected to the load LD through the output wiring W2. An output capacitor Cout is connected in parallel to the load LD. The voltage at the output terminal OUT is called the output voltage Vout. Therefore, the output voltage Vout is applied to the output wiring W2. The output wiring W2 is a wiring provided outside the switch device 10 and is a wiring connected to the output terminal OUT and the load LD (more specifically, a wiring connecting the output terminal OUT and the parallel circuit of the load LD and the output capacitor Cout). The current supplied from the output terminal OUT to the load LD (more specifically, the parallel circuit of the load LD and the output capacitor Cout) via the output wiring W2 is called the output current Iout. In other words, the load driving system SYS supplies the output current Iout to the load LD. The output current Iout is the drain current of the output transistor M1, which will be described later. A first terminal of the load LD is connected to the output wiring W2, and a second terminal of the load LD is connected to ground. A first terminal of the output capacitor Cout is connected to the output wiring W2, and a second terminal of the output capacitor Cout is connected to ground. The load LD is any load that drives the output voltage Vout as a power supply voltage.

[0019] The ground terminal GND is connected to the ground. The control input terminal IN, the current information output terminal SNS, the diagnostic terminal ST, and the terminals CSB, SCLK, SI, and SO are connected to the MCU 20.

[0020] The MCU 20 and the temperature detection circuit 30 are provided outside the switch device 10. The MCU 20 is supplied with a power supply voltage VCC having a predetermined positive DC voltage value and is connected to the ground, and is driven based on the power supply voltage VCC.

[0021] The temperature detection circuit 30 generates a temperature detection signal Tsns by detecting a temperature Tmp around the switch device 10. The temperature detection signal Tsns is output from the temperature detection circuit 30 to the MCU 20. The temperature Tmp is the temperature in a target space outside the switch device 10 and around the switch device 10. Hereinafter, the temperature Tmp will be referred to as the external temperature Tmp. The target space is the space in which the input wiring W1 and the output wiring W2 are disposed. The target space may also be the space in which either the input wiring W1 or the output wiring W2 is disposed. The temperature detection circuit 30 has a temperature measuring element (such as a resistance temperature detector, linear resistor, or thermistor) disposed in the target space and can detect the external temperature Tmp using the temperature measuring element. Alternatively, the temperature detection circuit 30 may be a semiconductor temperature sensor. The semiconductor temperature sensor has a silicon diode disposed in the target space and detects the external temperature Tmp using the temperature characteristics of the diode's forward voltage. Instead of the diode's forward voltage, the external temperature Tmp may be detected using the base-emitter voltage of a bipolar transistor.

[0022] The temperature detection signal Tsns is a voltage signal representing the external temperature Tmp (a voltage signal indicating the detected value of the external temperature Tmp). The temperature detection signal Tsns may be an analog voltage signal or a digital voltage signal. In either case, the value of the temperature detection signal Tsns identifies the value of the external temperature Tmp.

[0023] Referring to FIG. 3, in this embodiment, it is assumed that the load drive system SYS is mounted on a vehicle VHCL such as an automobile. In this case, the voltage source VS may be a battery installed in the vehicle VHCL. The vehicle VHCL is equipped with an electrical block BLK consisting of various electrical components. The components of the electrical block BLK include the load drive system SYS, a load LD, and an output capacitor Cout, as well as various wirings including an input wiring W1 and an output wiring W2. Therefore, the target space is the space within the vehicle VHCL. The load LD includes an ECU (Electronic Control Unit), as well as actuators such as motors that are driven and controlled by the ECU, lighting devices, air conditioners, etc.

[0024] The switch device 10 includes a group of circuits made of semiconductors, and the group of circuits is housed in a housing CS. The group of circuits made of semiconductors in the switch device 10 includes an output transistor M1, a controller 11, a driver 12, a charge pump circuit 13, a current detection circuit 14, an abnormality detection circuit 15, an error output circuit 16, an internal power supply circuit 17, and Schmitt buffers (Schmitt triggers) SM1 to SM4.

[0025] The output transistor M1 is configured by an N-channel MOSFET. The drain of the output transistor M1 is connected to the power supply terminal VBB, and the source of the output transistor M1 is connected to the output terminal OUT. The drain current of the output transistor M1 is the output current Iout. An active clamper (not shown) may be provided between the drain and gate of the output transistor M1 to protect the output transistor M1 from a back electromotive force generated in an inductive load.

[0026] A control signal Sin is supplied from the MCU 20 to the control input terminal IN. The control signal Sin is a binary signal having a high or low signal level. The high level of the control signal Sin is an active level (on command level), and the high level control signal Sin is a signal with which the MCU 20 commands the switch device 10 and the controller 11 to set the output transistor M1 to an on state. The low level of the control signal Sin is a non-active level (off command level), and the low level control signal Sin is a signal with which the MCU 20 commands the switch device 10 and the controller 11 to set the output transistor M1 to an off state. The control signal Sin supplied to the control input terminal IN is input to the Schmitt buffer SM1. The Schmitt buffer SM1 shapes the waveform of the control signal Sin input thereto and outputs the waveform-shaped control signal Sin to the controller 11.

[0027] The controller 11 generates a drive control signal Sdrv based on the waveform-shaped control signal Sin and outputs it to the driver 12. The control signal Sin in the description of the operation mainly performed by the controller 11 is the control signal Sin after waveform shaping. However, there is no substantial difference in the level of the control signal Sin before and after waveform shaping. For this reason, hereinafter, whether or not the control signal Sin is waveform-shaped will not be taken into consideration. Like the control signal Sin, the drive control signal Sdrv is a binary signal having a high or low signal level. In principle, the controller 11 outputs a high-level drive control signal Sdrv during the high-level period of the control signal Sin supplied to it, and outputs a low-level drive control signal Sdrv during the low-level period of the control signal Sin supplied to it. The high level of the drive control signal Sdrv is the active level, and the high-level drive control signal Sdrv is a signal with which the controller 11 commands the driver 12 to set the output transistor M1 to the on state. The low level of the drive control signal Sdrv is a non-active level, and the low level drive control signal Sdrv is a signal that the controller 11 uses to instruct the driver 12 to set the output transistor M1 to the off state.

[0028] The driver 12 is connected to the gate and source of the output transistor M1. During a high-level period of the drive control signal Sdrv, the driver 12 supplies a drive voltage Vcp, supplied from the charge pump circuit 13, to the gate of the output transistor M1, thereby setting the output transistor M1 to an ON state. During a low-level period of the drive control signal Sdrv, the driver 12 supplies a voltage at the source of the output transistor M1 or a ground voltage to the gate of the output transistor M1, thereby setting the output transistor M1 to an OFF state.

[0029] The charge pump circuit 13 is connected to the power supply terminal VBB, and generates a drive voltage Vcp higher than the power supply voltage Vbb by boosting the power supply voltage Vbb under the control of the controller 11. The drive voltage Vcp is supplied to the driver 12. The difference between the drive voltage Vcp and the power supply voltage Vbb is greater than the gate threshold voltage of the output transistor M1. Note that the output transistor M1 can also be configured as a P-channel MOSFET, and when this modification is adopted, the charge pump circuit 13 becomes unnecessary.

[0030] The current detection circuit 14 detects the drain current of the output transistor M1, i.e., detects the output current Iout flowing through the output transistor M1. The current detection circuit 14 outputs a current detection signal Isns indicating the detection result of the output current Iout to the abnormality detection circuit 15. The current detection circuit 14 may output the current detection signal Isns to the controller 11 instead of or in addition to the abnormality detection circuit 15. The current detection signal Isns may be an analog voltage signal indicating the value of the output current Iout, or may be a digital signal indicating the value of the output current Iout as a digital value. In either case, the value of the output current Iout is represented by the current detection signal Isns. The current detection circuit 14 also outputs an analog voltage signal Isns2 indicating the detection result of the output current Iout to the MCU 20 via the current information output terminal SNS. A pull-down resistor 42 is connected between a wiring 44 connecting the MCU 20 and the current information output terminal SNS and ground, and the voltage signal Isns2 is transmitted to the MCU 20 via the wiring 44. The voltage signal Isns2 may be the same as the current detection signal Isns, or may be a different signal. In the switch device 10, the output function of the voltage signal Isns2 and the current information output terminal SNS may be omitted.

[0031] The abnormality detection circuit 15 detects multiple types of abnormalities that may occur in the switch device 10. These types of abnormalities include an overcurrent abnormality in which an excessive current flows through the output transistor M1; a temperature abnormality in which the temperature of the output transistor M1 or a specific location within the switch device 10 exceeds a predetermined protection temperature; a low voltage abnormality in which the voltage supplied to the power supply terminal VBB falls below a low voltage threshold; and an open abnormality in which the output terminal OUT is in an open state. An overcurrent abnormality is detected based on a current detection signal Isns supplied from the current detection circuit 14. The abnormality detection circuit 15 outputs a signal indicating whether or not an abnormality has been detected to the controller 11. The abnormality detection circuit 15 can output a signal indicating whether or not an abnormality has been detected to the controller 11 for each type of detectable abnormality. The signals output from the abnormality detection circuit 15 to the controller 11 include an overcurrent detection signal Sdet. If the abnormality detection circuit 15 detects an abnormality, the controller 11 performs an abnormality response operation. One type of abnormality response operation is a shutdown operation that maintains the drive control signal Sdrv at a low level to keep the output transistor M1 in an off state regardless of the control signal Sin (even if the control signal Sin has a high level).

[0032] The error output circuit 16 is a circuit for transmitting a signal indicating that an abnormality has been detected to the MCU 20 when the abnormality detection circuit 15 detects an abnormality. Specifically, the error output circuit 16 has a transistor 16a with an open-drain configuration. The transistor 16a is an N-channel MOSFET. The drain of the transistor 16a is connected to the diagnostic terminal ST, and the source of the transistor 16a is connected to ground. A pull-up resistor 41 is connected between a wiring 43 connecting the MCU 20 and the diagnostic terminal ST and a node to which a power supply voltage VCC is applied. The controller 11 controls the gate voltage of the transistor 16a to turn the transistor 16a on or off. The controller 11 turns the transistor 16a off when no abnormality is detected by the abnormality detection circuit 15, and turns the transistor 16a on when an abnormality is detected by the abnormality detection circuit 15. The voltage of the wiring 43 substantially matches the power supply voltage VCC when the transistor 16a is off, and substantially matches the ground voltage when the transistor 16a is on. Therefore, the MCU 20 can recognize, based on the voltage of the wiring 43, what abnormality has been detected in the switch device 10.

[0033] The internal power supply circuit 17 is connected to the power supply terminal VBB and generates the internal power supply voltage Vreg by stepping down the power supply voltage Vbb with respect to the ground voltage. The internal power supply voltage Vreg has a predetermined positive DC voltage value. Each circuit in the switch device 10 can be driven based on the internal power supply voltage Vreg with respect to the ground potential.

[0034] The controller 11 is connected to the MCU 20 via a communication terminal group CTG consisting of terminals CSB, SCLK, SI, and SO, and is capable of bidirectional communication with the MCU 20 using the communication terminal group CTG. Note that communication between the controller 11 and the MCU 20 and communication between the switch device 10 and the MCU 20 are synonymous. Although communication between the switch device 10 and the MCU 20 may be parallel communication, in this embodiment, communication between the switch device 10 and the MCU 20 is assumed to be serial communication, and an SPI (Serial Peripheral Interface) is used as the serial communication interface. The terminal CSB is a chip select terminal that receives a chip select signal from the MCU 20. The terminal SCLK is a clock input terminal that receives a clock signal from the MCU 20. The terminal SI is a data input terminal that receives an input data signal from the MCU 20. The terminal SO is a data output terminal for outputting an output data signal to the MCU 20. The switch device 10 is provided with a Schmitt buffer SM2 that performs waveform shaping of a chip select signal received at a terminal CSB, a Schmitt buffer SM3 that performs waveform shaping of a clock signal received at a terminal SCLK, and a Schmitt buffer SM4 that performs waveform shaping of an input data signal received at a terminal SI, and the chip select signal, clock signal, and input data signal after waveform shaping are input to the controller 11. The controller 11 supplies an output data signal to the MCU 20 via a terminal SO.

[0035] A communication interface (not shown) that transmits and receives signals according to the SPI is included in the controller 11. However, it may be considered that a communication interface is provided between the communication terminal group CTG and the controller 11. The interface for serial communication between the switch device 10 and the MCU 20 is not limited to SPI. Therefore, for example, 2 An interface using C (Inter-Integrated Circuit) or Microwire may also be used.

[0036] The MCU 20 recognizes the external temperature Tmp based on the temperature detection signal Tsns. The MCU 20 transmits an external temperature signal (external temperature information) representing the external temperature Tmp recognized by itself to the switch device 10. The external temperature signal is received by the controller 11 via the communication terminal group CTG. The MCU 20 can periodically transmit an external temperature signal representing the latest external temperature Tmp based on the latest temperature detection signal Tsns to the switch device 10. The external temperature Tmp represented by the latest external temperature signal received by the controller 11 is particularly referred to as the reference external temperature Tmp. If the delay between when the external temperature Tmp is detected by the temperature detection circuit 30 and when the external temperature signal indicating the detection result is received by the controller 11 is sufficiently short and can be ignored, the reference external temperature Tmp at any time is the same as the external temperature Tmp detected by the temperature detection circuit.

[0037] The MCU 20 can also transmit various command signals to the switch device 10. The command signals are received by the controller 11 via the communication terminal group CTG. The controller 11 can perform operations and settings specified by the command signals.

[0038] The wires W1 and W2 are electrical wiring components made of copper wire with an insulating coating. In the load drive system SYS, a relatively large current (e.g., several amperes) is expected to flow as the output current Iout in a steady state, and when the load drive system SYS starts up, an even larger current (e.g., several tens of amperes) than in the steady state is expected to flow as the output current Iout for a short period of time as a rush current. For this reason, it is necessary to design and prepare wires W1 and W2 with a diameter large enough to be used safely. While making the diameter of wires W1 and W2 sufficiently large can eliminate safety concerns to a sufficient extent, increasing the diameter increases cost and size. It is necessary to make the diameter of wires W1 and W2 as small as possible while still ensuring safety.

[0039] For ease of explanation, the input wiring W1 or the output wiring W2 will be referred to as the target wiring below. The target wiring may be considered to refer to both the input wiring W1 and the output wiring W2. The output current Iout flows through the target wiring. The switch device 10 has the function of protecting the target wiring from excessive heat generation due to excessive current. This function corresponds to that of a so-called electronic fuse.

[0040] The characteristics of the target wiring will be described with reference to FIG. 4. FIG. 4 shows the characteristics of the target wiring as well as the operating region of the output transistor M1 determined in relation to the target wiring. The time during which the output transistor M1 is continuously maintained in the on state (the length of time during which the output transistor M1 is continuously maintained in the on state) is called the continuous on-time ton. The operating region of the output transistor M1 in relation to the characteristics of the target wiring is divided into three regions 610, 620, and 630. In FIG. 4, the regions 610 and 630 are represented by a first hatched region and a second hatched region (the same applies to FIG. 6, etc., described later). In FIG. 4, the region 620 is represented by a dotted region. The current value I shown in FIG. 4 A1 ~I A3 is "0 A1 A2 A3 ” are three predetermined current values ​​that satisfy the time t A1 ~t A3 is "0 <t A1 <t A2 <t A3 " are three predetermined times (lengths of time) that satisfy the following condition.

[0041] ​​​Region 610 is the normal operation region. Region 620 is the recommended protection region. Region 630 is the prohibited use region. On a graph with the output current Iout on the horizontal axis and the continuous on-time ton on the vertical axis, the recommended protection region 620 is located between the normal operation region 610 and the prohibited use region 630. The normal operation region 610 is a region in which the target wiring can be used safely. Unless some kind of failure occurs, the load driving system SYS drives the output transistor M1 within the normal operation region 610. The prohibited use region 630 is a region in which the target wiring cannot be used safely. Using the target wiring in the prohibited use region 630 (in other words, using the output transistor M1 in the prohibited use region 630) is prohibited for safety reasons. Therefore, if the output transistor M1 operates within the recommended protection region 620 for some reason, it is necessary to shut down the output transistor M1 before it reaches the prohibited use region 630. Shutting down the output transistor M1 means switching the output transistor M1 from an on state to an off state and maintaining it in the off state.

[0042] The output current Iout reaches the specified current value I A1 The region where the value of the output current Iout is less than the current value I A1 If the ON time t is less than t, the target wiring can be used safely even if the ON time t is sufficiently long. After the output transistor M1 is switched from OFF to ON, in the steady state, the value of the output current Iout will be equal to or greater than the current value I A1 The load drive system SYS and the load LD are designed so that

[0043] The output current Iout is the current value I A1 and current value I A2 The part of the region where the current value I A2 For example, the current value I A1Immediately after the output transistor M1 is switched from off to on, before the steady state is reached, an output current Iout larger than that in the steady state flows transiently as a rush current due to the charging of the output capacitor Cout, etc. The load driving system SYS and the load LD are designed so that the rush current falls within the normal operating region 610.

[0044] The output current Iout is the current value I A1 and the continuous on-time ton is equal to the predetermined time t A2 The region where the output current Iout is equal to or less than the current value I A1 When the continuous on-time ton is equal to the predetermined time t A2 The target wiring can be used safely if:

[0045] The output current Iout is the current value I A3 and the continuous on-time ton is equal to the predetermined time t A2 The region where the value of the output current Iout is equal to or greater than the current value I A3 When the continuous on-time ton is equal to the predetermined time t A2 The output transistor M1 is shut down before the value of the output current Iout reaches the current value I A3 and the continuous on-time ton is equal to the predetermined time t A2 The area below belongs to the protection recommendation area 620.

[0046] The output current Iout is the current value I A2 and the continuous on-time ton is equal to the predetermined time t A1 The region where the value of the output current Iout is equal to or less than the current value I A2 and the continuous on-time ton is equal to the predetermined time t A3 The region where the value of the output current Iout is equal to or greater than the current value I A2 coincides with "t A1 <ton<t A3 ” belongs to the protection recommended region 620.

[0047] For the sake of clarity, three current values ​​I A1 ~I A3 and three times t A1 ~t A3 The normal operation region 610, the recommended protection region 620, and the prohibited use region 630 have been described with a focus on the current Iout. A1 and current value I A2 When the output current Iout increases, the on-time t on belonging to the normal operation region 610 decreases continuously. Similarly, the on-time t on belonging to the prohibited use region 630 decreases continuously as the output current Iout increases. In either case, it is essential to shut down the output transistor M1 within the recommended protection region 620.

[0048] The controller 11 can cooperate with the current detection circuit 14 and the abnormality detection circuit 15 to perform an overcurrent protection operation α that contributes to ensuring the safety of the target wiring. The execution of the overcurrent protection operation α is determined when the output transistor M1 is set to the ON state, and therefore the output transistor M1 is in the ON state immediately before the execution of the overcurrent protection operation α. ​​The overcurrent protection operation α is a shutdown operation that switches the output transistor M1 from the ON state to the OFF state regardless of the control signal Sin (even if the control signal Sin is at a high level), and thereafter keeps the output transistor M1 in the OFF state. Note that the overcurrent protection operation α also serves to protect the switch device 10 itself from excessive heat generation.

[0049] The abnormality detection circuit 15 continuously monitors whether the overcurrent condition is met based on the current detection signal Isns, and outputs an overcurrent detection signal Sdet based on whether the overcurrent condition is met to the controller 11. The overcurrent detection signal Sdet is a binary signal having a value of "1" or "0", and in principle has a value of "0". The abnormality detection circuit 15 outputs the overcurrent detection signal Sdet of "1" to the controller 11 when the overcurrent condition is met. When the overcurrent detection signal Sdet has a value of "0", the controller 11 does not execute the overcurrent protection operation α. ​​The controller 11 executes the overcurrent protection operation α in response to the value of the overcurrent detection signal Sdet switching from "0" to "1".

[0050] FIG. 5 shows an operation flowchart of the switch device 10. For ease of explanation, it is assumed here that no abnormalities other than the overcurrent abnormality related to the overcurrent protection operation α occur. When the switch device 10 is started, the switch device 10 enters its initial state in step S11. In the initial state of the switch device 10, the overcurrent detection signal Sdet has a value of "0," and the drive control signal Sdrv is set to a low level, so that the output transistor M1 is off. In step S12 following step S11, the controller 11 checks whether the level of the control signal Sin is high, and only if the level of the control signal Sin is high (Y in step S12), does the controller 11 transition to step S13. In step S13, the controller 11 switches the level of the drive control signal Sdrv from a low level to a high level, thereby switching the output transistor M1 from an off state to an on state. Then, the process proceeds to step S14.

[0051] In step S14, the abnormality detection circuit 15 performs an overcurrent determination process. In the overcurrent determination process, the abnormality detection circuit 15 determines whether the overcurrent condition is met based on the current detection signal Isns. In step S15 following step S14, the determination result of whether the overcurrent condition is met is confirmed. If the overcurrent condition is met (Y in step S15), the process proceeds to step S21, and if the overcurrent condition is not met (N in step S15), the process proceeds to step S16.

[0052] In step S16, the abnormality detection circuit 15 maintains the value of the overcurrent detection signal Sdet at "0". Then, the process proceeds to step S17. In step S17, the controller 11 checks whether the control signal Sin has a low level. If the control signal Sin has a low level (Y in step S17), the process proceeds to step S18, and if the control signal Sin has a high level (N in step S17), the process returns to step S14. In step S18, the controller 11 switches the level of the drive control signal Sdrv from a high level to a low level, thereby switching the output transistor M1 from an on state to an off state. Then, the process returns to step S12.

[0053] In step S21, the abnormality detection circuit 15 switches the value of the overcurrent detection signal Sdet from "0" to "1." After step S21, the process proceeds to step S22. In step S22, the controller 11 receives the overcurrent detection signal Sdet of "1" and executes the overcurrent protection operation α. ​​This switches the output transistor M1 from an ON state to an OFF state, and the output transistor M1 is maintained in the OFF state thereafter until returning to step S13. After step S22, the process proceeds to step S23. In step S23, the controller 11 transmits an error signal to the MCU 20 using the error output circuit 16. The transmission of the error signal corresponds to switching the level of the wiring 43 from high to low by switching the transistor 16a from OFF to ON. Note that in step S23, error flag data indicating that an overcurrent abnormality due to the establishment of an overcurrent condition has been detected is stored in the controller 11. Having received the error signal, the MCU 20 can recognize that an overcurrent abnormality due to the establishment of an overcurrent condition has been detected by reading the error flag data using SPI communication.

[0054] After step S23, the process proceeds to step S24. In step S24, the controller 11 checks whether the control signal Sin has a low level. If the control signal Sin has a low level (Y in step S24), the process proceeds to step S25. If the control signal Sin has a high level (N in step S24), the process of step S24 is repeated. In step S25, the controller 11 and the abnormality detection circuit 15 work together to initialize the value of the overcurrent detection signal Sdet to "0," and then the process returns to step S12.

[0055] 5, when an overcurrent condition is met and the output transistor M1 is switched from the on state to the off state by overcurrent protection operation α, the output transistor M1 is latched in the off state. The latching of the output transistor M1 in the off state is released by temporarily returning the control signal Sin to a low level, and then the output transistor M1 is switched from the off state to the on state by setting the control signal Sin to a high level again.

[0056] The overcurrent condition will be described with reference to FIG. 6. To avoid cluttering the illustration, the normal operation region 610 and the prohibited use region 630 are represented by shaded regions in FIG. 6, but the recommended protection region 620 is not dotted as shown in FIG. 4 (the same applies to FIG. 7, etc., described later). The overcurrent condition is established when the output current Iout maintains a state where it has a protection current value Ip for the protection activation time tp. In the graph of FIG. 6, the point corresponding to the state where the output current Iout maintains a protection current value Ip for the protection activation time tp is within the recommended protection region 620. Although FIG. 6 shows the protection current value Ip as a single value and the protection activation time tp as a single time, in reality, the protection activation time tp is a function with the protection current value Ip as an independent variable. The broken line 640 in FIG. 6 represents the graph of this function (as in FIG. 7, described later). Therefore, the protection activation time tp varies with changes in the protection current value Ip. At this time, the protection activation time tp decreases as the protection current value Ip increases, and the protection activation time tp increases as the protection current value Ip decreases.

[0057] That is, as shown in FIG. 7, when the state where the output current Iout has the protection current value Ipa continues for the protection activation time tpa, the overcurrent condition is established, or when the state where the output current Iout has the protection current value Ipb continues for the protection activation time tpb, the overcurrent condition is established. Here, “Ipa < Ipb” and “tpa > tpb” are satisfied. The abnormality detection circuit 15 has a timer and determines whether the overcurrent condition is satisfied using the timer based on the current detection signal Isns. In the following, the symbol “Iout” may be used as a symbol indicating the value of the output current Iout, and the symbol “Iout” in any of the following expressions indicates the value of the output current Iout. Therefore, for example, “Iout = Ipa” means that the output current Iout has the protection current value Ipa (that is, the value of the output current Iout coincides with the protection current value Ipa), and “Iout > Ipa” means that the value of the output current Iout is greater than the protection current value Ipa.

[0058] Even when the state of “Iout = Ipa” continues for the time (tpa - Δt) and then the state of “Iout > Ipa” continues for the time Δt, the overcurrent condition is established. Similarly, even when the state of “Iout = Ipb” continues for the time (tpb - Δt) and then the state of “Iout > Ipb” continues for the time Δt, the overcurrent condition is established. The time (tpa - Δt) refers to a time that is shorter than the protection activation time tpa by the time Δt. The time (tpb - Δt) refers to a time that is shorter than the protection activation time tpb by the time Δt.

[0059] The relationship between the protection current value Ip and the protection activation time tp is referred to as the overcurrent protection characteristic. By using an appropriate overcurrent protection characteristic, the target wiring can be used safely and the target wiring can be protected from unexpected situations.

[0060] However, to properly protect the target wiring from excessive heat generation, consideration must also be given to the external temperature Tmp. Therefore, in the switch device 10, the relationship between the protection current value Ip and the protection activation time tp (overcurrent protection characteristics) is changed in response to the reference external temperature Tmp. Therefore, in the switch device 10, the protection activation time tp is a function that has not only the protection current value Ip as an independent variable but also the reference external temperature Tmp as an independent variable. As described above, the reference external temperature Tmp is the external temperature Tmp represented by the latest external temperature signal received by the controller 11. While the function for variably setting the overcurrent protection characteristics in response to the reference external temperature Tmp may be provided in the abnormality detection circuit 15, it is assumed here that this function is provided in the controller 11, and the overcurrent protection characteristics set by the controller 11 are used in the abnormality detection circuit 15.

[0061] The controller 11 decreases the protection activation time tp for a certain protection current value Ip as the reference external temperature Tmp increases, and increases the protection activation time tp for a certain protection current value Ip as the reference external temperature Tmp decreases.

[0062] In Figure 8, characteristic 650 MID is the reference external temperature Tmp at a predetermined intermediate temperature T MID The overcurrent protection characteristic is when the HIGH is the reference external temperature Tmp and the intermediate temperature T MID Higher than the specified high temperature T HIGH The overcurrent protection characteristic is when the LOW is the reference external temperature Tmp and the intermediate temperature T MID Lower than the predetermined low temperature T LOW The overcurrent protection characteristics are those when the reference external temperature Tmp coincides with the reference external temperature Tmp. An increase in the reference external temperature Tmp shifts the overcurrent protection characteristics in a direction that decreases the protection activation time tp (shifting them downward in the graph of FIG. 8). A decrease in the reference external temperature Tmp shifts the overcurrent protection characteristics in a direction that increases the protection activation time tp (shifting them upward in the graph of FIG. 8).

[0063] A first reference method has also been considered, in which the MCU 20 receives information about the output current Iout detected by the switch device 10 and the MCU 20 itself uses a timer to determine whether an overcurrent exists. In the first reference method, the MCU 20 sets overcurrent protection characteristics based on the diameter of the target wiring, measures the time during which the output current Iout remains excessive, and commands the switch device 10 to shut down the output transistor M1 as necessary. However, this first reference method increases the burden on the MCU 20 and requires signal exchange between the switch device 10 and the MCU 20, resulting in poor shutdown responsiveness. Furthermore, in the first reference method, if the MCU 20 controls the operation of multiple switch devices 10, the MCU 20 may lack communication terminals for receiving current information, or the processing load on the MCU 20 may become excessive, making it difficult to respond.

[0064] In this regard, the disadvantages associated with the first reference method can be eliminated by using a function (hereinafter referred to as the "self-protection function") in which the switch device 10 monitors the output current Iout and shuts down the output transistor M1 as necessary based on the overcurrent protection characteristics without relying on a command from the MCU 20. By appropriately setting the overcurrent protection characteristics according to the diameter of the target wiring, the diameter of the target wiring can be optimized while ensuring the safety of the target wiring. However, in the second reference method, which simply incorporates a self-protection function in the switch device, it is difficult to optimize the overcurrent protection characteristics because the external temperature Tmp is unknown, making it difficult to reduce the diameter of the target wiring.

[0065] Taking these factors into consideration, the load drive system SYS according to this embodiment transmits the external temperature Tmp to the switch device 10. The switch device 10 then dynamically sets the overcurrent protection characteristics in consideration of the external temperature Tmp. This allows the overcurrent protection characteristics to be optimized according to the external temperature Tmp. Optimizing the overcurrent protection characteristics leads to a reduction in the margin that must be secured in the design of the diameter of the target wiring, and therefore to a reduction in the diameter of the target wiring itself. A reduction in the diameter of the target wiring leads to a reduction in the weight of the vehicle VHCL, and ultimately to an increase in the cruising range of the vehicle VHCL.

[0066] Below, several specific operation examples, configuration examples, application techniques, modified techniques, etc. related to the load drive system SYS and the switch device 10 will be described in multiple embodiments. The matters described above in this embodiment are applied to each of the following embodiments unless otherwise specified and unless there is a contradiction. If there are any matters in each embodiment that contradict the matters described above, the description in that embodiment may take precedence. Furthermore, unless there is a contradiction, the matters described in any of the multiple embodiments shown below can also be applied to any of the other embodiments (i.e., any two or more of the multiple embodiments can be combined).

[0067] Note that the reference external temperature Tmp recognized by the switch device 10 is updated each time the switch device 10 receives the latest external temperature signal from the MCU 20, but in the following explanation, it is assumed that the reference external temperature Tmp remains unchanged or fixed during the period in which the success or failure of the overcurrent condition is being determined.

[0068] <<First Example>> A first embodiment will be described with reference to FIG. 9. In FIG. 9, characteristic 660 L is the overcurrent protection characteristic when the reference external temperature Tmp matches the specified low-side temperature T_L, and characteristic 660 H is the overcurrent protection characteristic when the reference external temperature Tmp coincides with a predetermined high-side temperature T_H. The high-side temperature T_H is higher than the low-side temperature T_L. The low-side temperature T_L and the high-side temperature T_H are respectively the above-mentioned intermediate temperature T MID and high temperature T HIGH In this case, the characteristic 660 L and 660 H are the characteristics 650 in Figure 8, respectively. MID and 650 HIGH Alternatively, the low-side temperature T_L and the high-side temperature T_H are the same as the low temperature T LOW and high temperature T HIGH In this case, the characteristic 660 L and 660 H are the characteristics 650 in Figure 8, respectively. LOW and 650 HIGHIt coincides. Alternatively, the low-side temperature T_L and the high-side temperature T_H may be the above-mentioned low temperature T LOW and the intermediate temperature T MID respectively, and in this case, the characteristics 660 L and 660 H respectively coincide with the characteristics 650 LOW and 650 MID in FIG. 8.

[0069] The current values Ip1 and Ip2 are two examples of the protection current value Ip (the first and second protection current values), and the current value Ip2 is larger than the current value Ip1. For example, the current values Ip1 and Ip2 are 20 A (amperes) and 40 A respectively. The times tp1 and tp3 are two examples of the protection activation time tp (the first and third activation protection times) when the reference external temperature Tmp coincides with the low-side temperature T_L. The times tp2 and tp4 are two examples of the protection activation time tp (the second and fourth activation protection times) when the reference external temperature Tmp coincides with the high-side temperature T_H. Here, "tp1 > tp2", "tp3 > tp4", "tp1 > tp3", and "tp2 > tp4" hold. In FIG. 9, "tp2 > tp3", but depending on the difference between the current values Ip1 and Ip2 and the difference between the temperatures T_L and T_H, any one of "tp2 > tp3", "tp2 = tp3", and "tp2 < tp3" holds.

[0070] When the reference external temperature Tmp coincides with the low-side temperature T_L, when the state where the output current Iout has the current value Ip1 continues for the time tp1, the abnormal detection circuit 15 determines that the overcurrent condition is established and outputs an overcurrent detection signal Sdet of "1" to the controller 11. When the reference external temperature Tmp coincides with the high-side temperature T_H, when the state where the output current Iout has the current value Ip1 continues for the time tp2, the abnormal detection circuit 15 determines that the overcurrent condition is established and outputs an overcurrent detection signal Sdet of "1" to the controller 11. Note that the state where the output current Iout has the current value Ip1 is a concept that includes not only the state where the value of the output current Iout exactly coincides with the current value Ip1 but also the state where the value of the output current Iout is slightly larger than the current value Ip1.

[0071] When the reference external temperature Tmp matches the low-side temperature T_L, and the state in which the output current Iout has the current value Ip2 continues for a time tp3, the abnormality detection circuit 15 determines that an overcurrent condition is established and outputs an overcurrent detection signal Sdet of "1" to the controller 11. When the reference external temperature Tmp matches the high-side temperature T_H, and the state in which the output current Iout has the current value Ip2 continues for a time tp4, the abnormality detection circuit 15 determines that an overcurrent condition is established and outputs an overcurrent detection signal Sdet of "1" to the controller 11. Note that the state in which the output current Iout has the current value Ip2 is a concept that includes not only a state in which the value of the output current Iout completely matches the current value Ip2, but also a state in which the value of the output current Iout is slightly larger than the current value Ip2.

[0072] In response to receiving the overcurrent detection signal Sdet of "1" from the abnormality detection circuit 15, the controller 11 performs the above-described overcurrent protection operation α.

[0073] In the comparison between the low-side temperature T_L and the high-side temperature T_H, "tp1>tp2" and "tp3>tp4" are established. Also, under the assumption that the reference external temperature Tmp is equal to the low-side temperature T_L, "Ip1<Ip2”であるから“tp1> Similarly, under the assumption that the reference external temperature Tmp is equal to the high-side temperature T_H,<Ip2”であるから“tp2> tp4” holds.

[0074] The output current Iout is the above-mentioned current value I A1 If the output current Iout fluctuates above this value (see FIG. 4), the abnormality detection circuit 15 may identify the maximum value of the output current Iout during the fluctuation period of the output current Iout, and determine whether the overcurrent condition is met by assuming that the output current Iout continues to have the maximum value during the fluctuation period. This ensures the safety of the target wiring. For example, as shown in FIG. 10, if the value of the output current Iout is greater than the current value I A1The current value Ip1 rapidly rises from below, and after the value of the output current Iout is maintained at the current value Ip1 for a time Δt1, it is assumed that the value of the output current Iout increases to the current value Ip2 and is maintained at the current value Ip2 for a time Δt2. In this case, since the maximum value of the output current Iout during the fluctuation period of the output current Iout is the current value Ip2, the abnormal detection circuit 15 may determine whether the overcurrent condition is satisfied by regarding the output current Iout as continuing to have the current value Ip2 during the fluctuation period. Then, if the current reference external temperature Tmp is the low-side temperature T_L, the overcurrent condition is satisfied when the sum of the time Δt1 and the time Δt2 reaches the time tp3 (assuming "Δt1 < tp3" here). If the current reference external temperature Tmp is the high-side temperature T_H, the overcurrent condition is satisfied when the sum of the time Δt1 and the time Δt2 reaches the time tp4 (assuming "Δt1 < tp4" here).

[0075] For the sake of specific explanation, the difference in the protection activation time when the reference external temperature Tmp is the low-side temperature T_L and the high-side temperature T_H has been described by focusing on two current values Ip1 and Ip2. However, the same applies when current values other than the current values Ip1 and Ip2 are the protection current values.

[0076] <<Second Embodiment>> The second embodiment will be described. Refer to FIG. 11. FIG. 11 is a figure obtained by simply adding two current ranges Rp1 and Rp2 to FIG. 9. The characteristics 660 L and 660 H are the same as those shown in the first embodiment (FIG. 9). The current values Ip1 and Ip2 and the times tp1 to tp4 shown in FIG. 11 are the same as those shown in the first embodiment (FIG. 9). Therefore, the magnitude relationship between the current values Ip1 and Ip2 and the magnitude relationship between the times tp1 to tp4 are also as shown in the first embodiment.

[0077] The current range Rp1 is a current range having a predetermined magnitude, and the current value Ip1 is a current value within the current range Rp1. The current range Rp2 is a current range having a predetermined magnitude, and the current value Ip2 is a current value within the current range Rp2. Here, the lower limit of the current range Rp2 is greater than the upper limit of the current range Rp1. In other words, the minimum current value of the current range Rp2 is greater than the maximum current value of the current range Rp1.

[0078] The abnormality detection circuit 15 according to the second embodiment sets a plurality of different current ranges and determines which of the plurality of current ranges the value of the output current Iout belongs to. When the current detection signal Isns is an analog voltage signal having a voltage value proportional to the magnitude of the output current Iout, the abnormality detection circuit 15 can determine which of the plurality of current ranges the value of the output current Iout belongs to using a plurality of comparators. The comparators may be window comparators. Two current ranges included in the plurality of current ranges are current ranges Rp1 and Rp2. The abnormality detection circuit 15 according to the second embodiment sets different protection activation times tp for the plurality of current ranges and further varies the protection activation time tp for each current range according to the reference external temperature Tmp.

[0079] Specifically, when the reference external temperature Tmp matches the low-side temperature T_L, and the state in which the output current Iout falls within the current range Rp1 continues for a time tp1, the abnormality detection circuit 15 determines that the overcurrent condition is met and outputs an overcurrent detection signal Sdet of "1" to the controller 11. When the reference external temperature Tmp matches the high-side temperature T_H, and the state in which the output current Iout falls within the current range Rp1 continues for a time tp2, the abnormality detection circuit 15 determines that the overcurrent condition is met and outputs an overcurrent detection signal Sdet of "1" to the controller 11.

[0080] When the reference external temperature Tmp matches the low-side temperature T_L, if the state in which the output current Iout falls within the current range Rp2 continues for a time tp3, the abnormality detection circuit 15 determines that the overcurrent condition is met and outputs an overcurrent detection signal Sdet of "1" to the controller 11. When the reference external temperature Tmp matches the high-side temperature T_H, if the state in which the output current Iout falls within the current range Rp2 continues for a time tp4, the abnormality detection circuit 15 determines that the overcurrent condition is met and outputs an overcurrent detection signal Sdet of "1" to the controller 11.

[0081] In response to receiving the overcurrent detection signal Sdet of "1" from the abnormality detection circuit 15, the controller 11 performs the above-described overcurrent protection operation α.

[0082] In the comparison between the low-side temperature T_L and the high-side temperature T_H, "tp1>tp2" and "tp3>tp4" are established. Also, under the assumption that the reference external temperature Tmp is equal to the low-side temperature T_L, "Ip1<Ip2”であるから“tp1> tp3” is established. Under the assumption that the reference external temperature Tmp is equal to the high-side temperature T_H, “Ip1<Ip2”であるから“tp2> tp4” holds.

[0083] The output current Iout is the above-mentioned current value I A1 If the output current Iout fluctuates above this value (see FIG. 4), the abnormality detection circuit 15 may identify the maximum value of the output current Iout during the fluctuation period of the output current Iout, and determine whether the overcurrent condition is met by assuming that the output current Iout continues to have the maximum value during the fluctuation period. This ensures the safety of the target wiring. For example, as shown in FIG. 12, if the value of the output current Iout is greater than the current value I A1The current rapidly rises from below to within the current range Rp1, and after the value of the output current Iout is maintained within the current range Rp1 for a time Δt1, the value of the output current Iout increases within the current range Rp2 and is maintained within the current range Rp2 for a time Δt2. In this case, since the maximum value of the output current Iout during the fluctuation period of the output current Iout is a value within the current range Rp2, the abnormal detection circuit 15 may determine whether the overcurrent condition is satisfied by regarding the output current Iout as continuing to have a value within the current range Rp2 during the fluctuation period. Then, if the current reference external temperature Tmp is the low-side temperature T_L, the overcurrent condition is satisfied when the sum of the time Δt1 and the time Δt2 reaches the time tp3 (assuming here that “Δt1 < tp3”). If the current reference external temperature Tmp is the high-side temperature T_H, the overcurrent condition is satisfied when the sum of the time Δt1 and the time Δt2 reaches the time tp4 (assuming here that “Δt1 < tp4”).

[0084] For the sake of specific description, the difference in the protection activation time when the reference external temperature Tmp is the low-side temperature T_L and the high-side temperature T_H has been described by focusing on the two current ranges Rp1 and Rp2, but the same applies to other current ranges.

[0085] <<Third Embodiment>> The third embodiment will be described. Fig. 13 shows characteristics 710 to 760, which are six candidates for overcurrent protection characteristics. However, characteristics 710 to 760 are candidates for overcurrent protection characteristics when the reference external temperature Tmp coincides with a predetermined standard temperature Tstd. The standard temperature Tstd is arbitrary. The standard outside air temperature (e.g., 25°C) may be set as the standard temperature Tstd, or the standard temperature of the space where the target wiring is arranged (e.g., 50°C) may be set as the standard temperature Tstd.

[0086] The MCU 20 can transmit to the switch device 10 (controller 11) a characteristic designation command signal that selects and designates the overcurrent protection characteristic from among the characteristics 710 to 760. The controller 11 stores characteristic designation data according to the characteristic designation command signal received from the MCU 20 in its own memory (not shown), and selects and adopts one of the characteristics 710 to 760 as the overcurrent protection characteristic at the standard temperature Tstd based on the characteristic designation data.

[0087] Here, when the switch device 10 receives a characteristic designation command signal that selects and designates characteristic 710 as the overcurrent protection characteristic, the controller 11 stores characteristic designation data having a value of "1" in the memory. When characteristic designation data having a value of "1" is stored in the memory, the controller 11 selects and adopts characteristic 710 as the overcurrent protection characteristic at standard temperature Tstd. Similarly, when the switch device 10 receives a characteristic designation command signal that selects and designates characteristic 720 as the overcurrent protection characteristic, the controller 11 stores characteristic designation data having a value of "2" in the memory. When characteristic designation data having a value of "2" is stored in the memory, the controller 11 selects and adopts characteristic 720 as the overcurrent protection characteristic at standard temperature Tstd. The same applies to characteristics 730 to 760. That is, when the switch device 10 receives a characteristic designation command signal that selects and designates the characteristics 730, 740, 750, and 760 as the overcurrent protection characteristics, the controller 11 stores characteristic designation data having the values ​​"3," "4," "5," and "6" in the memory. When the characteristic designation data having the values ​​"3," "4," "5," and "6" are stored in the memory, the controller 11 selects and adopts the characteristics 730, 740, 750, and 760 as the overcurrent protection characteristics at the standard temperature Tstd, respectively.

[0088] When the characteristic specification data has a value of "1", the relationship between the protection current value Ip and the protection activation time tp varies according to the reference external temperature Tmp based on characteristic 710. When the characteristic specification data has a value of "2", the relationship between the protection current value Ip and the protection activation time tp varies according to the reference external temperature Tmp based on characteristic 720. The same applies when the characteristic specification data has a value of "3", "4", "5", or "6".

[0089] Characteristics 710 to 760 are different from each other. In FIG. 13, a current value Ipa is shown as an example of the protection current value Ip. When the reference external temperature Tmp matches the standard temperature Tstd and the characteristic specification data has a value of "i", an overcurrent condition is established when the output current Iout has the current value Ipa for a duration of time tp[i]. The time tp[i] is the protection activation time tp when the current value Ipa corresponds to the protection current value Ip when the reference external temperature Tmp matches the standard temperature Tstd and the characteristic specification data has a value of "i". Here, i represents a natural number less than or equal to 6. "0 < tp[1] < tp[2] < tp[3] < tp[4] < tp[5] < tp[6]" holds.

[0090] When the reference external temperature Tmp is higher than the standard temperature Tstd when the characteristic specification data has a value of "i", an overcurrent condition is established when the output current Iout has the current value (Ipa - ΔI) for a duration of time tp[i]. The current value (Ipa - ΔI) is smaller than the current value Ipa by the current value ΔI. The current value ΔI varies according to the difference between the reference external temperature Tmp and the standard temperature Tstd (the controller 11 or the abnormality detection circuit 15 determines the current value ΔI according to the difference between the reference external temperature Tmp and the standard temperature Tstd).

[0091] In this way, the controller 11 switches the overcurrent protection characteristics (i.e., the relationship between the protection current value Ip and the protection activation time tp) between multiple stages when the reference external temperature Tmp is equal to the standard temperature Tstd, based on the characteristics specification data in accordance with the characteristics specification command signal from the MCU 20. This allows the designer and user of the load drive system SYS to select appropriate overcurrent protection characteristics, taking into account the necessary margin depending on the characteristics of the load LD, and by selecting appropriate overcurrent protection characteristics, it is possible to minimize the diameter of the target wiring. Note that while the example in Figure 13 has six stages, the total number of stages can be any number as long as it is two or more.

[0092] <<Fourth Example>> A fourth embodiment will now be described. As shown in Fig. 14, the temperature detection signal Tsns from the temperature detection circuit 30 may be input directly to the switch device 10 without going through the MCU 20. In this case, the temperature detection signal Tsns may be a digital signal, but here it is assumed that the temperature detection signal Tsns is an analog voltage signal representing the external temperature Tmp. In this case, the switch device 10 according to the fourth embodiment has a detection signal input terminal TT as one of its external terminals, and receives the temperature detection signal Tsns at the detection signal input terminal TT.

[0093] The temperature detection circuit 30 may generate the temperature detection signal Tsns by performing necessary signal processing (amplification, impedance conversion, etc.) on a signal generated internally according to the external temperature Tmp. A conversion circuit (not shown) that performs this signal processing may be considered to be inserted between the temperature detection circuit 30 and the detection signal input terminal TT.

[0094] The temperature detection signal Tsns input to the detection signal input terminal TT is input to the controller 11 through wiring within the switch terminal 10. The controller 11 converts the temperature detection signal Tsns into a digital signal and determines the external temperature Tmp based on the digital value of the obtained temperature detection signal Tsns. In the fourth embodiment, the determined external temperature Tmp is used as the reference external temperature Tmp.

[0095] <<Fifth Example>> A fifth embodiment will be described below: A method for detecting the output current Iout will be described with reference to FIG.

[0096] The switch device 10 according to the fifth embodiment includes a replica transistor M2 and a sense resistor Rsns. The replica transistor M2 is an N-channel MOSFET. The drain of the replica transistor M2 is connected to the drain of the output transistor M1, and the gate of the replica transistor M2 is connected to the gate of the output transistor M2. The source of the replica transistor M2 is connected to a first end of the sense resistor Rsns, and the second end of the sense resistor Rsns is connected to the output terminal OUT (and therefore the source of the output transistor M1). The replica transistor M2 has the same structure as the output transistor M1, and a current proportional to the output current Iout is the drain current I of the replica transistor M2. M2 However, the size of the replica transistor M2 is much smaller than the size of the output transistor M1, so the drain current I M2 is much smaller than the output current Iout.

[0097] The sense voltage Vsns is the voltage drop across the sense resistor Rsns. The value of the sense voltage Vsns is determined by the drain current I M2and the value of the sense resistor Rsns. Therefore, the sense voltage Vsns has a voltage value proportional to the output current Iout. The first and second terminals of the sense resistor Rsns are connected to the current detection circuit 14. The input impedance of the current detection circuit 14 seen from the sense resistor Rsns is sufficiently large, and the current flowing between the first and second terminals of the sense resistor Rsns and the current detection circuit 14 can be considered to be zero. The current detection circuit 14 generates a current detection signal Isns by performing necessary signal processing on the sense voltage Vsns. This signal processing includes, for example, an amplification process that amplifies the sense voltage Vsns and a noise reduction process that reduces noise in the sense voltage Vsns. If the current detection signal Isns is a digital signal, the signal processing also includes a process of digitizing the sense voltage Vsns. Here, for the sake of concrete explanation, the current detection signal Isns is generated by amplifying the sense voltage Vsns by a constant amplification factor k AMP Then, the equation "Isns=I M2 ×Rsns×k AMP " holds, and the drain current I M2 is the k of the output current Iout A If the equation is "Isns=Iout×k A ×Rsns×k AMP " holds (k A (For example, it is several hundredths to several thousandths.) The voltage signal Isns2 output to the MCU 20 may also be the same as the current detection signal Isns.

[0098] The abnormality detection circuit 15 recognizes the value of the output current Iout based on the current detection signal Isns. For example, when the current detection signal Isns has a signal value corresponding to the current value Ip1, the abnormality detection circuit 15 determines that the output current Iout has the current value Ip1, and when the current detection signal Isns has a signal value corresponding to the current value Ip2, the abnormality detection circuit 15 determines that the output current Iout has the current value Ip2 (see FIG. 9 or FIG. 11). Note that the fourth embodiment (see FIG. 14) may be applied to the fifth embodiment, and in the configuration of the fifth embodiment, the temperature detection signal Tsns from the temperature detection circuit 30 may be input directly to the switch device 10 without going through the MCU 20.

[0099] <<Sixth Example>> A sixth embodiment will be described. Another configuration related to the method for detecting the output current Iout will be described with reference to FIG. 16. Based on the configuration of the fifth embodiment, in the sixth embodiment, the sense resistor Rsns is provided outside the switch device 10. Except for the sense resistor Rsns being provided outside the switch device 10, the configuration of the load drive system SYS of the sixth embodiment is the same as that of the load drive system SYS of the fifth embodiment. Note that the fourth embodiment (see FIG. 14) may be applied to the sixth embodiment, and in the configuration of the sixth embodiment, the temperature detection signal Tsns from the temperature detection circuit 30 may be input directly to the switch device 10 without passing through the MCU 20.

[0100] In order to provide the sense resistor Rsns outside the switch device 10, a resistor connection terminal RT is provided as one of the external terminals of the switch device 10. In the sixth embodiment, a first end of the sense resistor Rsns is connected to the resistor connection terminal RT outside the switch device 10, and a second end of the sense resistor Rsns is connected to the output terminal OUT outside the switch device 10.

[0101] The replica transistor M2 according to the sixth embodiment has a drain connected to the drain of the output transistor M1, a gate connected to the gate of the output transistor M1, and a source connected to the resistor connection terminal RT. M2 flows through the sense resistor Rsns as a current proportional to the output current Iout, and as a result, a sense voltage Vsns similar to that in the fifth embodiment is generated across the sense resistor Rsns.

[0102] A first end of the sense resistor Rsns is connected to the current detection circuit 14 via a resistor connection terminal RT, and a second end of the sense resistor Rsns is connected to the current detection circuit 14 via an output terminal OUT. The input impedance of the current detection circuit 14 as seen from the sense resistor Rsns is sufficiently large, and the current flowing between the first and second ends of the sense resistor Rsns and the current detection circuit 14 can be considered to be zero. The method of generating the current detection signal Isns from the sense voltage Vsns in the current detection circuit 14 is the same as in the fifth embodiment.

[0103] The abnormality detection circuit 15 recognizes the value of the output current Iout based on the current detection signal Isns. For example, when the current detection signal Isns has a signal value corresponding to the current value Ip1, the abnormality detection circuit 15 determines that the output current Iout has the current value Ip1, and when the current detection signal Isns has a signal value corresponding to the current value Ip2, the abnormality detection circuit 15 determines that the output current Iout has the current value Ip2 (see FIG. 9 or FIG. 11).

[0104] Therefore, it is possible to adjust the overcurrent protection characteristics by adjusting the value of the sense resistor Rsns, which is an external resistor of the switch device 10. Changes in the value of the sense resistor Rsns cause the overcurrent protection characteristics to shift left or right on the graph in Figure 6.

[0105] In the fifth embodiment as well, the sense resistor Rsns built into the switch device 10 may be configured so that its value can be changed in multiple stages, and the controller 11 may adjust and change the value of the sense resistor Rsns in response to a command signal from the MCU 20. However, as in the sixth embodiment, a configuration in which the sense resistor Rsns is provided outside the switch device 10 makes it easier to adjust the value of the sense resistor Rsns with high precision.

[0106] <<Seventh Example>> A seventh embodiment will now be described.

[0107] The switch device 10 includes a control circuit that executes the above-described overcurrent protection operation α based on the external temperature Tmp and the output current Iout flowing through the output transistor M1. The control circuit is configured to include at least a controller 11. The controller 11 itself can be considered to correspond to the control circuit, or the driver 12, the current detection circuit 14, and the abnormality detection circuit 15, in addition to the controller 11, can also be considered to include all or part of the components of the control circuit.

[0108] In the configuration illustrated in FIG. 1 and elsewhere, the switch device 10 is used as a so-called high-side switch. However, the switch device 10 may also be used as a so-called low-side switch. That is, the load LD may be inserted in series with the input wiring W1. In this case, the terminal VBB functions as a load connection terminal, and the output terminal OUT is directly connected to ground via the output wiring W2 (or the ground terminal GND is used as the output terminal OUT). In addition, the power supply voltage VCC may be separately supplied to the switch terminal 10 as a power supply voltage for driving the switch device 10 (by adding an external terminal for receiving the power supply voltage VCC to the switch terminal 10). When the switch device 10 is used as a so-called low-side switch, the charge pump circuit 13 is not necessary, and the internal power supply circuit 17 may simply generate the internal power supply voltage Vreg from the power supply voltage VCC.

[0109] In the present embodiment, an example has been given in which the switch device 10 is applied to a vehicle VHCL, but the application of the switch device 10 is not limited to a vehicle VHCL and may be any. For example, the switch device 10 may be mounted on any industrial machine or any home appliance.

[0110] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0111] The channel types of the FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0112] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0113] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0114] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0115] A switch device (10) according to one aspect of the present disclosure includes an input terminal (VBB), an output terminal (OUT), an output transistor (M1) provided between the input terminal and the output terminal, and a control circuit (including at least a controller 11) configured to control the output transistor to be turned on or off in response to a control signal (Sin) supplied to the switch device, wherein the control circuit is configured (first configuration) to be able to perform a protection operation of switching the output transistor from on to off, regardless of the control signal, based on an external temperature (Tmp) of the switch device and an output current (Iout) flowing through the output transistor.

[0116] This makes it possible to properly ensure the safety of components (wiring, etc.) that are connected to the input terminal or output terminal and that are affected by external temperatures.

[0117] In the switch device according to the first configuration, the control circuit may be configured (second configuration) to execute the protection operation when the state in which the output current has a protection current value (Ip) continues for a protection activation time (tp), and the control circuit may be configured to decrease the protection activation time as the external temperature increases.

[0118] By decreasing the protection activation time as the external temperature increases, the safety of components (wiring, etc.) connected to the input terminal or output terminal and affected by the external temperature can be appropriately ensured.

[0119] In the switch device according to the second configuration (see FIG. 9), the control circuit may be configured (third configuration) to execute the protection operation when the state in which the output current has the protection current value (Ip1) continues for a first protection activation time (tp1) when the external temperature is a first temperature (T_L), and to execute the protection operation when the state in which the output current has the protection current value (Ip1) continues for a second protection activation time (tp2) shorter than the first protection activation time when the external temperature is a second temperature (T_H) higher than the first temperature.

[0120] In the switch device according to the second configuration (see FIG. 9), the control circuit executes the protection operation when the state in which the output current has the first protection current value (Ip1) continues for a first protection activation time (tp1) when the external temperature is a first temperature (T_L), and executes the protection operation when the state in which the output current has the first protection current value (Ip1) continues for a second protection activation time (tp2) shorter than the first protection activation time when the external temperature is a second temperature (T_H) higher than the first temperature, and executes the protection operation when the state in which the output current has the first protection current value (Ip1) continues for a second protection activation time (tp2) shorter than the first protection activation time when the external temperature is the first temperature (T_L). The protection operation may be performed when the state in which the output current has the second protection current value (Ip2) continues for a third protection activation time (tp3), and when the external temperature is the second temperature (T_H) and the state in which the output current has the second protection current value (Ip2) continues for a fourth protection activation time (tp4) that is shorter than the third protection activation time, the protection operation may be performed, and the second protection current value may be greater than the first protection current value, the third protection activation time may be shorter than the first protection activation time, and the fourth protection activation time may be shorter than the second protection activation time (fourth configuration).

[0121] In the switch device according to the second configuration (see FIG. 11), the control circuit may be configured (fifth configuration) to execute the protection operation when the state in which the output current falls within a specific current range (Rp1) that includes the protection current value (Ip1) continues for a first protection activation time (tp1) when the external temperature is a first temperature (T_L), and to execute the protection operation when the state in which the output current falls within the specific current range (Rp1) continues for a second protection activation time (tp2) that is shorter than the first protection activation time when the external temperature is a second temperature (T_H) that is higher than the first temperature.

[0122] In the switch device according to the second configuration, the control circuit executes the protection operation when the state in which the output current falls within a first specific current range (Rp1) including a first protection current value (Ip1) continues for a first protection activation time (tp1) when the external temperature is a first temperature (T_L), and executes the protection operation when the state in which the output current falls within the first specific current range continues for a second protection activation time (tp2) shorter than the first protection activation time when the external temperature is a second temperature (T_H) higher than the first temperature, and executes the protection operation when the output current falls within a The protection operation is executed when the state in which the output current falls within a second specific current range (Rp2) that includes a second protection current value (Ip2) continues for a third protection activation time (tp3), and the protection operation is executed when the state in which the output current falls within the second specific current range (Rp2) continues for a fourth protection activation time (tp4) that is shorter than the third protection activation time when the external temperature is the second temperature, and the lower limit of the second specific current range is greater than the upper limit of the first specific current range, the third protection activation time is shorter than the first protection activation time, and the fourth protection activation time is shorter than the second protection activation time (sixth configuration).

[0123] In the switch device according to any of the first to sixth configurations, the external temperature may be the temperature of the space in which an input wiring (W1) connected to the input terminal and provided outside the switch device or an output wiring (W2) connected to the output terminal and provided outside the switch device is located (seventh configuration).

[0124] This makes it possible to properly ensure the safety of the input wiring or output wiring that is affected by the external temperature.

[0125] In the switch device according to any of the above first to seventh configurations, the control circuit may be configured (eighth configuration) to switch the relationship between the protection current value and the protection activation time in a plurality of stages when the external temperature is equal to a predetermined temperature (Tstd).

[0126] In the switch device according to any one of the first to eighth configurations, the control circuit may be configured (ninth configuration) to receive a signal indicating the external temperature from an external control device (20) that supplies the control signal to the switch device.

[0127] In the switch device according to any one of the first to eighth configurations, the control circuit may be configured (tenth configuration) to receive a signal indicating the external temperature from an external circuit (30) different from an external control device (20) that supplies the control signal to the switch device, without going through the external control device (20).

[0128] A load driving system (SYS) according to one aspect of the present disclosure is a load driving system that includes a switch device (10) according to any of the first to eighth configurations described above, an external control device (20) configured to supply the control signal to the switch device, and a temperature detection circuit (30) configured to detect the external temperature, and supplies the output current to a load (LD), and is configured such that the detection result of the external temperature by the temperature detection circuit is transmitted to the switch device via the external control device or without via the external control device (eleventh configuration). [Explanation of symbols]

[0129] SYS Load drive system VS voltage source LD load Cout Output capacitor W1 input wiring W2 output wiring Iin Input current Iout Output current Vout Output voltage Vbb power supply voltage Sin control signal 10 Switching device 20 MCU 30 Temperature detection circuit 41 Pull-up resistor 42 Pull-down resistor VBB power supply terminal OUT output terminal GND Ground terminal IN Control input terminal SNS Current information output terminal ST diagnostic terminal CSB Chip select terminal SCLK Clock input terminal SI Data input terminal SO Data output terminal CTG communication terminal group CS chassis VHCL Vehicles BLK Electrical block M1 Output transistor 11 Controller 12 Drivers 13 Charge pump circuit 14 Current detection circuit 15 Abnormality detection circuit 16 Error output circuit 16a transistor 17 Internal power circuit SM1~SM4 Schmitt buffers Tsns Temperature detection signal Isns Current detection signal Isns2 voltage signal Sdrv drive control signal Sdet Overcurrent detection signal Vcp drive voltage Vreg Internal power supply voltage ton Continuous ON time Ip protection current value tp protection activation time 610 Safety protection area 620 Recommended Protection Areas 630 Prohibited area M2 replica transistor Rsns Sense resistor

Claims

1. A switch device comprising: an input terminal; an output terminal; an output transistor provided between the input terminal and the output terminal; and a control circuit configured to control the output transistor to be on or off in response to a control signal supplied to the switch device; The control circuit is configured to be able to perform a protection operation of switching the output transistor from on to off without relying on the control signal, based on an external temperature of the switch device and an output current flowing through the output transistor. , switch device.

2. the control circuit executes the protection operation when a state in which the output current has a protection current value continues for a protection activation time; The control circuit decreases the protection activation time as the external temperature increases. The switch device according to claim 1 .

3. The control circuit When the external temperature is a first temperature, and a state in which the output current has the protection current value continues for a first protection activation time, the protection operation is executed; When the external temperature is a second temperature higher than the first temperature, and a state in which the output current has the protection current value continues for a second protection activation time that is shorter than the first protection activation time, the protection operation is executed.

3. The switch device according to claim 2.

4. The control circuit When the external temperature is a first temperature, and a state in which the output current has a first protection current value continues for a first protection activation time, the protection operation is executed; When the external temperature is a second temperature higher than the first temperature, and a state in which the output current has the first protection current value continues for a second protection activation time that is shorter than the first protection activation time, the protection operation is executed; When the external temperature is the first temperature and a state in which the output current has a second protection current value continues for a third protection activation time, the protection operation is executed; When the external temperature is the second temperature, if a state in which the output current has the second protection current value continues for a fourth protection activation time that is shorter than the third protection activation time, the protective operation is executed. The second protection current value is greater than the first protection current value, the third protection activation time is shorter than the first protection activation time, and the fourth protection activation time is shorter than the second protection activation time.

3. The switch device according to claim 2.

5. The control circuit When the external temperature is a first temperature, and a state in which the output current falls within a specific current range including the protection current value continues for a first protection activation time, the protection operation is executed; When the external temperature is a second temperature higher than the first temperature, and the state in which the output current falls within the specific current range continues for a second protection activation time that is shorter than the first protection activation time, the protective operation is executed.

3. The switch device according to claim 2.

6. The control circuit When the external temperature is a first temperature, and a state in which the output current falls within a first specific current range that includes a first protection current value continues for a first protection activation time, the protective operation is executed; When the external temperature is a second temperature higher than the first temperature, and a state in which the output current falls within the first specific current range continues for a second protection activation time that is shorter than the first protection activation time, the protective operation is executed; When the external temperature is the first temperature, if a state in which the output current falls within a second specific current range including a second protection current value continues for a third protection activation time, the protective operation is executed; when the external temperature is the second temperature and a state in which the output current falls within a second specific current range continues for a fourth protection activation time that is shorter than the third protection activation time, the protective operation is executed; The lower limit of the second specific current range is greater than the upper limit of the first specific current range, the third protection activation time is shorter than the first protection activation time, and the fourth protection activation time is shorter than the second protection activation time.

3. The switch device according to claim 2.

7. The external temperature is the temperature of a space in which an input wiring connected to the input terminal and provided outside the switch device or an output wiring connected to the output terminal and provided outside the switch device is disposed.

7. The switch device according to claim 1.

8. The control circuit switches the relationship between the protection current value and the protection activation time in a plurality of stages when the external temperature is equal to a predetermined temperature.

7. The switch device according to claim 1.

9. The control circuit receives a signal indicating the external temperature from an external control device that supplies the control signal to the switch device.

7. The switch device according to claim 1.

10. The control circuit receives a signal indicating the external temperature from an external circuit different from an external control device that supplies the control signal to the switch device, without going through the external control device.

7. The switch device according to claim 1.

11. A switch device according to any one of claims 1 to 6; an external control device configured to provide the control signal to the switch device; a temperature detection circuit configured to detect the external temperature, and a load driving system configured to supply the output current to a load, The detection result of the external temperature by the temperature detection circuit is transmitted to the switch device via the external control device or without the external control device. , load driving system.

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