Method for manufacturing silicon wafer

Abstract

To prevent a deterioration in the surface roughness of a silicon wafer without depending on an epitaxial growth method.SOLUTION: Provided is a method for manufacturing a silicon wafer having a surface obtained by inclining the {110} surface of a silicon single crystal as a principal surface, the method including: a step of preparing a silicon wafer having an orientation of inclination angle at which the {110} surface is inclined relative to the principal surface within a range of 0-30° relative to the <100> orientation to the <110> orientation parallel to the {110} surface, and having an angle of inclination of 10° or less; and a heat treatment step of performing rapid temperature increase and decrease heat treatment of maintaining the silicon wafer at a highest attainment temperature of 1250-1400°C for 1-60 seconds, and subsequently cooling the silicon wafer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a silicon wafer. [Background technology]

[0002] (110) wafers have much faster hole mobility in certain directions than (100) wafers, which has led to improved processing speeds in devices, especially CMOS and advanced logic, and are attracting attention. However, (110) wafers have a problem in that their surface is more prone to roughening than (100) wafers, resulting in poorer surface quality, such as haze and surface roughness, compared to (100) wafers (even when epitaxial layers are stacked). Furthermore, when surface roughness deteriorates, carrier mobility decreases due to the effects of surface roughness scattering.

[0003] In Patent Document 1, the {110} plane is <100> The document discloses a silicon semiconductor substrate (hereinafter simply referred to as "substrate" or "silicon wafer") whose main surface is a surface tilted in the azimuth direction, and states that the tilt angle is preferably 0 to less than 8°. It also describes that the surface of the silicon semiconductor substrate can be deformed by batch heat treatment in a hydrogen gas or argon gas atmosphere for, for example, 1 hour. <110> It is described that steps parallel to the direction are formed, and carriers can flow directly under the terrace surface. In addition, Patent Document 2 describes that the tilt angle direction of the {110} plane is parallel to the {110} plane. <100> From the direction <110> It is described that the surface roughness can be improved in an epitaxial wafer having a tilt angle of 0 to 10 degrees in the range of 0 to 45 degrees relative to the orientation. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-265918 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-091891 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in silicon semiconductor substrates with a {110} plane as the principal surface, it is difficult to eliminate crystal defects such as COP and LPD on the substrate surface simply by optimizing the tilt angle and tilt direction. Furthermore, when a batch heat treatment is performed on a silicon semiconductor substrate with a {110} plane as the principal surface, even if the crystal defects on the substrate surface can be eliminated, the surface roughness may worsen, resulting in a risk of reduced carrier mobility.

[0006] In view of the above-mentioned problems, an object of the present invention is to provide a method for manufacturing a silicon wafer that eliminates crystal defects in the surface layer of a silicon wafer having a {110} plane as its main surface, while suppressing deterioration of the surface roughness of the silicon wafer. [Means for solving the problem]

[0007] In order to solve the above problems, the present invention provides a method for producing a silicon wafer having a main surface formed by tilting the {110} plane of a silicon single crystal, wherein the tilt angle direction of the {110} plane relative to the main surface is parallel to the {110} plane. <100> From the direction <110> The method includes a step of preparing a silicon wafer having a tilt angle of more than 0° and not more than 10° in the range of 0 to 30° with respect to the orientation, and a heat treatment step of subjecting the silicon wafer to a rapid temperature increase / decrease heat treatment in which the silicon wafer is held at a maximum temperature of 1250 to 1400°C for 1 to 60 seconds and then cooled.

[0008] When a silicon wafer having the tilt angle and tilt angle orientation under the above conditions is subjected to a rapid temperature increase / decrease heat treatment under the above conditions, it is possible to suppress deterioration of the surface roughness of the silicon wafer after the heat treatment.

[0009] The rapid temperature increase / decrease heat treatment can be carried out in a non-oxidizing atmosphere or in an atmosphere with an oxygen partial pressure of 1 to 100%.

[0010] Furthermore, the rapid temperature increase / decrease heat treatment is preferably carried out in a non-oxidizing atmosphere at a maximum temperature of 1250°C to 1400°C for a holding time of 5 seconds to 30 seconds, followed by cooling the wafer to 800°C or less, and then switching to an oxidizing atmosphere to carry out heat treatment to form a thermal oxide film of 1 nm or more on the wafer surface.

[0011] The wafer surface after rapid temperature increase / decrease heat treatment is very unstable, and it is not possible to completely prevent oxidation entrapment when exposed to the atmosphere. To prevent this, it is effective to form a thermal oxide film after the planarization process as a protective film. The thickness of the thermal oxide film must be 1 nm or more, and 5 nm or less is appropriate.

[0012] Furthermore, when the tilt angle is 0.01-0.5°, it is preferable to perform heat treatment with a maximum temperature of 1250-1300° C., and when the tilt angle is 7.0-9.0°, it is preferable to perform heat treatment with a maximum temperature of 1300-1400° C. Under these conditions, the effect of suppressing the deterioration of the surface roughness of the silicon wafer is significant.

[0013] Furthermore, when rapid heating and cooling heat treatment is performed in a non-oxidizing atmosphere during the heat treatment process, it is preferable to reduce the pressure in the chamber to 1 torr or less at 600°C or less from the start of the wafer heat treatment, and then treat the wafer at the maximum temperature. After that, the wafer is removed from the heat treatment furnace at a temperature between 300°C and 400°C. This method removes trace amounts of residual oxygen from the chamber before starting the rapid heating and cooling heat treatment in a non-oxidizing atmosphere. If the residual oxygen is not removed, the wafer surface will become rough after the rapid heating and cooling heat treatment. Furthermore, if the wafer removal temperature is too high, oxidation will occur immediately upon exposure to the atmosphere, causing the planarized surface to become rough. To prevent this, the removal temperature must be 400°C or less. [Effects of the Invention]

[0014] According to the present invention, it is possible to provide a method for manufacturing a silicon wafer that eliminates crystal defects in the surface layer of a silicon wafer having a {110} plane as its principal surface, while suppressing deterioration of the surface roughness of the silicon wafer. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a cross-sectional view showing an outline of an example of an RTP apparatus used in a silicon wafer manufacturing method according to an embodiment of the present invention. [Figure 2] FIG. 2 is a flowchart showing the steps of a method for manufacturing a silicon wafer according to an embodiment of the present invention. [Figure 3] FIG. 3 is a diagram illustrating the tilt angle and tilt angle orientation of a silicon wafer. [Figure 4] FIG. 4 is a diagram showing a sequence of heat treatment in the method for producing a silicon wafer according to the present invention. [Figure 5] FIG. 5 is a diagram showing another sequence of heat treatment in the method for producing a silicon wafer according to the present invention. [Figure 6] FIG. 6 is a graph showing the experimental results of the dependence of the surface roughness of a (110) wafer on the tilt angle and tilt angle orientation after rapid temperature increase / decrease heat treatment. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the embodiments described below. In addition, the same or corresponding elements in each drawing are appropriately designated by the same reference numerals. Furthermore, it should be noted that the drawings are schematic, and the dimensional relationships and ratios of each element may differ from those in reality. There may also be parts in which the dimensional relationships and ratios differ between the drawings.

[0017] FIG. 1 is a cross-sectional view showing an outline of an example of an RTP apparatus used in a silicon wafer manufacturing method according to an embodiment of the present invention.

[0018] As shown in FIG. 1, the RTP apparatus 10 includes a chamber (reaction tube) 20 having an atmospheric gas inlet 20a and an atmospheric gas outlet 20b, a plurality of lamps 30 spaced apart above the chamber 20, and a wafer support 40 that supports a wafer W in a reaction space 25 within the chamber 20.

[0019] The wafer support 40 includes an annular susceptor 40a that supports the outer periphery of the wafer W, and a stage 40b that supports the susceptor 40a. The wafer support 40 also includes a rotation means that rotates the wafer W around its central axis at a predetermined speed.

[0020] The chamber 20 is made of, for example, quartz. The lamp 30 is made of, for example, a halogen lamp. The susceptor 40a is made of, for example, silicon. The stage 40b is made of, for example, quartz.

[0021] 1, RTP is performed on a wafer W by introducing the wafer W into the reaction space 25 and supporting the wafer W on the susceptor 40a of the wafer support 40. Then, an atmospheric gas, which will be described later, is introduced through the atmospheric gas inlet 20a, and the surface of the wafer W is irradiated with light from the lamps 30 while the wafer W is being rotated.

[0022] The temperature in the reaction space 25 in this RTP device 10 is controlled by measuring the average temperature at multiple points on the wafer surface in the radial direction of the wafer below the wafer W using multiple radiation thermometers 50 embedded in the stage 40b of the wafer support part 40, and controlling the multiple halogen lamps 30 (such as individually controlling the ON / OFF of each lamp and controlling the intensity of the emitted light) based on the measured temperature.

[0023] Fig. 2 is a flowchart showing the steps of a method for manufacturing a silicon wafer according to an embodiment of the present invention. As shown in Fig. 2, the method for manufacturing a silicon wafer according to an embodiment of the present invention mainly comprises a silicon wafer preparation step S1, a heat treatment step S2, a final polishing step S3, and a final cleaning step S4. The preparation step S1 also comprises a single crystal pulling step S1a, a slicing step S1b, and a processing step S1c.

[0024] The single crystal pulling step S1a is a step of growing a silicon single crystal ingot by the Czochralski method. Growing a silicon single crystal ingot by the Czochralski method can be performed by a well-known method. Polycrystalline silicon filled in a quartz crucible is heated to form a silicon melt, and a seed crystal is brought into contact with the silicon melt from above the liquid surface. The seed crystal and the quartz crucible are rotated while being pulled up, and the diameter is expanded to a desired diameter to grow a straight body portion, thereby producing a silicon single crystal ingot.

[0025] The slicing step S1b is a step of slicing the silicon single crystal ingot to produce silicon wafers. In this step, the inclination angle direction of the {110} plane with respect to the main surface is parallel to the {110} plane. <100> From the direction <110> The silicon single crystal ingot is sliced ​​so that the tilt angle is 10° or less within a range of 0 to 30° relative to the orientation. It is assumed that the silicon single crystal ingot is grown in the single crystal pulling step S1a with a tilt angle of 0° and a tilt angle orientation of 0°, and then sliced ​​in the slicing step S1b to the desired tilt angle and tilt angle orientation. However, the seed crystal in the single crystal pulling step S1a may be processed to achieve the desired tilt angle and tilt angle orientation. By pulling a silicon single crystal with the desired tilt angle and tilt angle orientation, it is possible to slice it in the slicing step without adjusting the tilt angle and tilt angle orientation. The slicing step can be performed using a well-known method, such as a wire saw, an inner peripheral blade, or an outer peripheral blade.

[0026] Here, the tilt angle and tilt angle orientation of a silicon wafer will be explained. FIG. 3 is a diagram for explaining the tilt angle and tilt angle orientation of a silicon wafer. The tilt angle orientation that tilts the {110} plane with respect to the main surface is parallel to the {110} plane. <100> From the direction <110> The inclination angle of 10° or less in the range of 0 to 30° relative to the orientation is a description of the inclination angle and inclination angle orientation of a silicon wafer by expressing the crystal plane and crystal orientation of the unit cell of a silicon single crystal using Miller indices. Here, the inclination angle and inclination angle orientation of a silicon wafer will be explained with reference to Figure 3.

[0027] The method for manufacturing a silicon wafer according to an embodiment of the present invention is a method for manufacturing a silicon wafer whose main surface is a plane tilted from the {110} plane. Here, a {110} wafer basically refers to a wafer whose main surface coincides with the {110} plane, but silicon wafers according to an embodiment of the present invention also include those whose main surface is tilted with respect to the {110} plane. Therefore, silicon wafers according to an embodiment of the present invention also include those in which the normal to the {110} plane and the normal to the main surface do not coincide, as shown in FIG. 3(a). The angle α formed by the normal to the {110} plane and the normal to the main surface is the tilt angle.

[0028] Furthermore, the inclination of the {110} plane relative to the main surface of the silicon wafer has an orientation. As shown in Figure 3(a), the normal to the main surface does not coincide with the normal to the {110} plane, so the normal to the main surface can be projected onto the {110} plane. Then, the orientation of the projection of the normal to the main surface can be considered within the {110} plane. Here, the crystal orientation parallel to the {110} plane is <100> Orientation and <110> Considering the orientation, the orientation of the projection of the normal to the principal surface is <100> From the direction <110> The angle β is the tilt angle azimuth.

[0029] Here, since the unit cell of a silicon single crystal has symmetry, the crystal planes and crystal orientations include equivalent ones. <100> The directions include

[0001] [00-1], <110> The directions include [1-10] and [-110]. Therefore, <100> From the direction <110> The range of 0 to 30° relative to the orientation includes the range of 0 to 30° from the

[0001] orientation to the [1-10] orientation, the range of 0 to 30° from the

[0001] orientation to the [-110] orientation, the range of 0 to 30° from the [00-1] orientation to the [1-10] orientation, and the range of 0 to 30° from the [00-1] orientation to the [-110] orientation, as shown by the shaded area in Figure 3(b).

[0030] The processing step S1c is a step of chamfering the outer periphery, lapping, etching, polishing, etc.

[0031] The heat treatment step S2 is a step of performing a rapid temperature increase / decrease heat treatment. In the rapid temperature increase / decrease heat treatment, the tilt angle direction is parallel to the {110} plane. <100> From the direction <110> A silicon wafer having a main surface tilted from the {110} plane at an inclination angle of more than 0° but not exceeding 10° with respect to the orientation within a range of 0 to 30° is introduced into RTP apparatus 10, and a non-oxidizing atmosphere or an atmosphere with an oxygen partial pressure of 1 to 100% is created inside chamber 20 of RTP apparatus 10, and the wafer is held at a maximum temperature of 1250 to 1400°C for 1 to 60 seconds, and then cooled at a rate of 20 to 150°C / s. Note that the heat treatment step S2 may be a two-stage heat treatment in which rapid heating and cooling heat treatment is performed in a non-oxidizing atmosphere, followed by rapid heating and cooling heat treatment or batch heat treatment in an oxidizing atmosphere. In this case, it is desirable to perform a rapid temperature increase / decrease heat treatment in a non-oxidizing atmosphere at a maximum temperature of 1300°C or higher and 1350°C or lower for a holding time of 5 seconds or higher and 30 seconds or lower, then cool the wafer to 800°C or lower, and then switch to an oxidizing atmosphere and perform a rapid temperature increase / decrease heat treatment or a batch heat treatment to form a thermal oxide film of 1 nm or higher on the wafer surface.

[0032] FIG. 4 is a diagram showing the sequence of heat treatment in the method for producing a silicon wafer according to the present invention. In FIG. 4, the vertical axis represents temperature and the horizontal axis represents time. As shown in FIG. 4, in the heat treatment step S2, the temperature is rapidly increased from temperature T1 to temperature T2 at a rate of, for example, 30 to 120°C / s, maintained at that temperature for a period of time D1, and then rapidly cooled to temperature T3. The rate of temperature decrease for rapid cooling to temperature T3 is preferably 20 to 150°C / s. Temperature T2 is preferably 1250 to 1400°C, and time D1 is preferably 1 to 60 seconds. Temperature T3 is preferably 300 to 400°C. The atmosphere during the heat treatment can be a non-oxidizing atmosphere using, for example, argon or nitrogen as atmospheric gas, or an atmosphere with an oxygen partial pressure of 1 to 100%. When an atmosphere with an oxygen partial pressure of 1% or more but less than 100% is used, a mixed gas containing a non-oxidizing gas such as argon or nitrogen is preferably used.

[0033] FIG. 5 shows another heat treatment sequence in the silicon wafer manufacturing method according to the present invention. In FIG. 5, the vertical axis represents temperature and the horizontal axis represents time. As shown in FIG. 4, in the heat treatment step S2, the temperature is rapidly increased from T1 to T2, held at that temperature for D1, and then temporarily cooled to T3. The temperature is then increased again to T4, held at that temperature for D2, and then rapidly cooled to T5. Temperature T2 is preferably 1250 to 1350°C, and time D1 is preferably 1 second or more and 30 seconds or less. Temperature T4 and time D2 are appropriately set so as to form a thermal oxide film of 1 nm or more on the wafer surface. For example, temperature T4 is set to 1250 to 1300°C, and time D2 is set to 10 seconds or more and 60 seconds or less. However, batch heat treatment is also acceptable, in which case time D2 is set to, for example, 60 to 180 minutes. Temperature T5 is preferably 300 to 400°C. The atmosphere during the heat treatment at temperature T2 is a non-oxidizing atmosphere, and the atmosphere during the heat treatment at temperature T4 is an oxidizing atmosphere.

[0034] Returning to FIG. 2, the final polishing step S3 is a step of performing final polishing on the silicon wafer, and the final cleaning step S4 is a step of performing final cleaning on the silicon wafer. Note that although FIG. 2 shows that the final polishing step S3 is performed after the heat treatment step S2, it is also possible to perform the final polishing step S3 before the heat treatment step S2. In particular, in the case of the heat treatment step S2 in an argon gas atmosphere, it is preferable to perform the final polishing step S3 before the heat treatment step S2 and to perform only the final cleaning step S4 after the heat treatment step S2. This is because it is possible to prevent the roughness of the wafer surface from worsening due to polishing.

[0035] As mentioned above, the tilt angle direction is parallel to the {110} plane. <100> From the direction <110> By subjecting silicon wafers with an inclination angle of more than 0° and less than 10° with respect to the {110} plane in the range of 0 to 30° with respect to the orientation to a rapid temperature increase / decrease heat treatment with a maximum temperature of 1250°C to 1400°C and a holding time of 1 to 60 seconds, it is possible to obtain highly flat wafers with reduced surface roughness, even for {110} silicon wafers. This makes it possible to suppress a decrease in carrier mobility.

[0036] Furthermore, by further including an epitaxial growth step of growing a silicon single crystal thin film (also referred to as an "epitaxial layer") on the surface of the silicon wafer having high flatness by epitaxial growth, it is possible to manufacture an epitaxial wafer having a {110} main surface and an epitaxial layer on its surface that has high surface flatness and good crystallinity.

[0037] [Example] Next, an example will be described in which the effects of the above-described method for manufacturing a silicon wafer according to the present invention are verified.

[0038] Figure 6 is a graph showing the experimental results of the dependence of the surface roughness on the tilt angle and tilt angle orientation after rapid temperature increase / decrease heat treatment of a (110) wafer. The experiment shown in Figure 6 was carried out on a silicon single crystal with a {110} plane tilted relative to the main surface in a tilt angle orientation parallel to the {110} plane. <100> From the direction <110> (110) silicon wafers with tilt angles of 0-12° at 0, 15, 30, 40, 70, and 90° relative to the orientation were subjected to rapid heating and cooling heat treatment in an argon gas atmosphere, where the maximum temperature reached was 1300°C and held for 15 seconds, followed by cooling at a rate of 75°C / s. The surface roughness rms (nm) was then measured using AFM within a 3 μm range at the center of the wafer.

[0039] As can be seen from the graph shown in Figure 6, when the tilt angle azimuth is in the range of 0 to 30° and the tilt angle is 10° or less, the rms surface roughness is 0.8 nm or less, which is a significant effect in suppressing deterioration of surface roughness. Furthermore, even within the range of 0 to 30°, when the tilt angle is 0.01-0.5° and when the tilt angle is 7.0-9.0°, the rms surface roughness is 0.2 nm or less and 0.3 nm or less, respectively, which is a particularly significant effect in suppressing deterioration of surface roughness. As such, deterioration of surface roughness using rapid temperature increase / decrease heat treatment depends on the tilt angle and tilt angle azimuth, and the silicon wafer manufacturing method according to the present invention utilizes the dependence of the tilt angle and tilt angle azimuth to enhance the effect of suppressing deterioration of surface roughness.

[0040] Tables 1 and 2 below show the results of experiments verifying the effectiveness of combining the conditions of tilt angle and tilt angle orientation with the conditions of rapid heating and cooling heat treatment to suppress deterioration of surface roughness. The evaluation criteria for surface roughness are as follows. It was confirmed that crystal defects in the surface layer of silicon wafers after rapid heating and cooling heat treatment had disappeared. ○: Rms is less than 0.8 nm, and the surface roughness deteriorates by less than 0.48 nm due to RTP treatment △: Rms is less than 0.8 nm, and the surface roughness worsens by 0.48 nm or more due to RTP treatment ×: Rms is 0.8 nm or more, and the surface roughness deteriorates by 0.48 nm or more due to RTP treatment

[0041] [Table 1]

[0042] [Table 2]

[0043] As can be seen from Tables 1 and 2 above, when silicon wafers with a tilt angle orientation in the range of 0 to 30° and a tilt angle of 10° or less are subjected to rapid heating and cooling heat treatment, in which the maximum temperature is held at 1250 to 1400°C for 1 to 60 seconds and then cooled, the effect of sufficiently suppressing deterioration of surface roughness can be obtained in either a non-oxidizing atmosphere or an atmosphere with an oxygen partial pressure of 1 to 100%. On the other hand, as can be seen from Comparative Examples 1, 2, 6, and 7, if the holding time at the maximum temperature exceeds the range of 1 to 60 seconds, the effect of sufficiently suppressing deterioration of surface roughness cannot be obtained. Furthermore, as can be seen from Comparative Examples 3 and 8, if the tilt angle exceeds 10°, the effect of sufficiently suppressing deterioration of surface roughness cannot be obtained. Furthermore, as can be seen from Comparative Examples 4 and 9, if the tilt angle orientation exceeds the range of 0 to 30°, the effect of sufficiently suppressing deterioration of surface roughness cannot be obtained. Furthermore, as can be seen from Comparative Examples 5 and 10, the effect of sufficiently suppressing the deterioration of surface roughness cannot be obtained when the maximum temperature reached is below 1250° C. Thus, in order to obtain the effect of sufficiently suppressing the deterioration of surface roughness, it is necessary to perform rapid temperature increase / decrease heat treatment under appropriate conditions on silicon wafers having appropriate tilt angle orientations and tilt angles.

[0044] Although the present invention has been described above based on the embodiments, the present invention is not limited to the above embodiments. For example, the method for manufacturing a silicon wafer according to the embodiment of the present invention can be modified to further reduce surface roughness by modifying or adding manufacturing conditions to the above embodiments. [Explanation of symbols]

[0045] 10 RTP device 20 Chamber 20a Atmospheric gas inlet 20b Atmospheric gas outlet 25 Reaction Space 30 Lamp 40 wafer support

Claims

1. A method for producing a silicon wafer having a main surface tilted from the {110} plane, comprising the steps of: preparing a silicon wafer having a tilt angle orientation in the range of 0 to 30 degrees from a <100> orientation parallel to the {110} plane to the <110> orientation, and having a tilt angle relative to the {110} plane greater than 0 degrees and equal to or less than 10 degrees; a heat treatment process in which the silicon wafer is subjected to rapid temperature increase and decrease heat treatment, in which the maximum temperature is maintained at 1250 to 1400°C for 1 to 60 seconds and then cooled at a temperature decrease rate of 20 to 150°C / s; A method for producing a silicon wafer, comprising:

2. 2. The method for producing a silicon wafer according to claim 1, wherein the rapid temperature increase / decrease heat treatment is carried out in a non-oxidizing atmosphere.

3. 2. The method for producing a silicon wafer according to claim 1, wherein the rapid temperature increase / decrease heat treatment is carried out in an atmosphere with an oxygen partial pressure of 1 to 100%.

4. 2. The method for producing a silicon wafer according to claim 1, wherein the rapid temperature increase / decrease heat treatment is performed in a non-oxidizing atmosphere at a maximum temperature of 1250°C or higher and 1400°C or lower for a holding time of 5 seconds or higher and 30 seconds or lower, followed by cooling the wafer to 800°C or lower, and then switching the atmosphere to an oxidizing atmosphere to perform a heat treatment to form a thermal oxide film of 1 nm or higher on the wafer surface.

5. 2. The method for producing a silicon wafer according to claim 1, wherein when the tilt angle is 0.01-0.5°, heat treatment is performed so that the maximum temperature reaches 1250-1300°C, and when the tilt angle is 7.0-9.0°, heat treatment is performed so that the maximum temperature reaches 1300-1400°C.

6. 3. The method for producing a silicon wafer according to claim 2, wherein in the heat treatment step, the pressure in the chamber is reduced to 1 torr or less once at 600°C or less from the start of the heat treatment of the wafer, and the wafer is removed at a temperature of 300°C or more and 400°C or less.

7. 2. The method for producing a silicon wafer according to claim 1, further comprising an epitaxial growth step of growing a silicon single crystal thin film on the surface of the silicon wafer by epitaxial growth.

8. 2. The method for producing a silicon wafer according to claim 1, further comprising a final polishing step before the heat treatment step, and not polishing the silicon wafer after the heat treatment step.

9. 2. The method for manufacturing a silicon wafer according to claim 1, wherein the tilt angle is 0.01-0.5°, or 7.0-9.0°.

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