D / a converter
The D/A converter addresses errors and inefficiencies in existing designs by employing a common current source and internal switches with overlapping clocks, ensuring accurate and efficient analog output.
Patent Information
- Application Number
- JP2024052936
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-03-28
- Publication Date
- 2025-10-09
AI Technical Summary
Existing D/A converters face issues with offset, gain, and nonlinearity errors due to separate current sources in time-interleaved sub-DACs, leading to deviations in analog output voltage and inefficient power usage.
A D/A converter design with parallel-connected current source units, utilizing a common current source and four-phase overlapping clocks with 90° shifts, and internal switches synchronized with digital inputs to prevent errors and improve power efficiency through NRZ operation.
Prevents offset and gain errors, eliminates nonlinearity, and enhances power efficiency by using a common current source and internal switches, achieving faster conversion speeds.
Smart Images
Figure 2025151487000001_ABST
Abstract
Description
[Technical Field]
[0001] The present disclosure relates to a digital-to-analog converter. [Background technology]
[0002] Current-output D / A converters (hereafter abbreviated as DAC) are the fastest DACs in practical use. They convert the current of a current-source cell into an analog voltage by passing it through a resistor, which then outputs the analog voltage. Current-source cells are broadly divided into two types: a unary configuration with multiple current-source units with the same current value, and a binary configuration with multiple current-source units weighted by a current value ratio that is a power of two. In a unary configuration, the number of current-source units that output a current is controlled according to the digital input. In a binary configuration, the current-source unit that outputs a current is selected according to the digital input. This controls the current value of the current-source cell according to the digital input, and an analog voltage corresponding to the digital input is output.
[0003] Each bit of the digital input has a binary weight (a power of 2). The D / A converter outputs an analog voltage whose magnitude corresponds to that weight. In the case of 8 bits, the weight ratio from the least significant bit to the most significant bit is 1, 2, 4, ... 64, 128. In a binary configuration where this is directly set as the current amount for multiple current source units, the current amounts of the least significant to most significant current source cells are I0 = 1I, I1 = 2I, I2 = 4I, ... I7 = 128I, starting from the least significant bit. However, a problem occurs when switching digits, for example, from 127 (01111111) to 128 (10000000). At 127, a current of I0 + I1 + I2 + I3 + I4 + I5 + I6 flows, and at 128, a current of I7 flows. Since the current source units that pass current are completely swapped between 127 and 128, if there is an error in the current amount of each current source unit and this is biased toward the positive or negative side and superimposed, a large error (differential nonlinearity error) will occur.
[0004] On the other hand, in the unary configuration, a current of 127I flows at 127, and a current of 127I+1I flows at 128. Therefore, errors are not superimposed, and only the error of the added 1I remains, suppressing error. For this reason, the unary configuration is advantageous in terms of accuracy. However, a logic circuit must perform a decoding process (also known as binary-unary conversion or binary-thermometer conversion) to convert the binary code input to the unary current-source cell into a thermometer code. This binary-unary conversion requires multiple logic stages as the number of binary digits increases, resulting in longer processing times for the logic circuit. This delay also delays the switching of the switches within the current-source cell, slowing down the conversion speed. For this reason, considering the trade-off between accuracy and speed, a segment configuration is often used, with the upper half configured as a unary configuration and the lower half configured as a binary configuration.
[0005] A current source unit has a current source that supplies a constant current value and a switch that controls whether to output the current (see, for example, Non-Patent Document 1). The operation of a current source unit is broadly divided into single-ended operation and differential operation. In single-ended operation, two switches are used to switch whether the current of the current source cell is output or discarded as a dummy. In differential operation, two switches are used to switch whether the current of the current source cell is output as a positive output or a negative output.
[0006] A Quad Switching current source cell has also been proposed, in which two pairs of these two switches are connected to one current source (see, for example, Non-Patent Document 2). While one of the two pairs is operating, the other performs decoding processing of the next input data, alternately extracting output. This makes the delay of the logic circuit invisible, enabling faster conversion speeds.
[0007] After a digital signal is input to a sub-DAC, the output voltage gradually transitions and requires a certain amount of time to settle to its final value. To address this issue, it has been proposed to provide two sets of sub-DACs with quad-switching current-source cells, operate these sub-DACs alternately (time-interleaved operation), and selectively extract the output using a multiplexer (see, for example, Non-Patent Document 3). A total of four sets of switches are switched with a 90° phase difference. Each set does not output a voltage during the transition period in the first half of its operation, and instead extracts a voltage that has settled to its final value in the second half of its operation. This shortens the transition time of the output voltage of the sub-DAC, thereby enabling a conversion speed twice as fast as that of a single sub-DAC. [Prior art documents] [Non-patent literature]
[0008] [Non-Patent Document 1] A. van den Bosch, et al., "A 10-bit 1-GSample / s Nyquist current-steering CMOS D / A converter," IEEE JSSC, Mar. 2001. [Non-patent document 2] B. Schafferer, et al., "A 3V CMOS 400mW 14b 1.4GS / s DAC for Multi-Carrier Applications," IEEE ISSCC2004. [Non-patent document 3] E. Olieman, et al., "An Interleaved Full Nyquist High-Speed DAC Technique," IEEE JSSC, Mar. 2015. Summary of the Invention [Problem to be solved by the invention]
[0009] The Quad Switching DAC in Non-Patent Document 2 could only double its conversion speed. To further increase the speed, Non-Patent Document 3 uses a multiplexer to time-interleave two sets of sub-DACs. However, because the two sets of sub-DACs each use a separate current source, any errors in the current values of these current sources will cause an offset, causing the analog output voltage to deviate from the ideal value for the digital input. Furthermore, a gain error will occur, causing the output voltage range to deviate from the ideal value.
[0010] Furthermore, in Non-Patent Document 3, a multiplexer that selectively extracts the output of the sub-DAC is located outside the sub-DAC. Therefore, the magnitude of the current flowing through the multiplexer changes depending on the digital input. Because the drain voltage-current characteristics of a transistor are not linear, a nonlinear error occurs in which the voltage drop caused by the multiplexer's transistors does not linearly correspond to changes in the digital input. Therefore, the analog output voltage deviates from the ideal value for the digital input.
[0011] Furthermore, the DAC in Non-Patent Document 3 performs RZ (Return-to-Zero) operation, in which the output current of one of the two sub-DACs flows to Dummy. As a result, half of the current of the current source cell is wasted, which is disadvantageous in terms of power efficiency.
[0012] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to obtain a D / A converter that can prevent offset, gain error, and nonlinearity error and improve power efficiency. [Means for solving the problem]
[0013] A D / A converter according to the present disclosure includes a current source cell having a plurality of current source units connected in parallel to each other and outputting a current in response to a digital input, and a resistor for converting a total current of the plurality of current source units into an analog output voltage, wherein each current source unit receives first to fourth overlapping clocks whose phases are sequentially shifted by 90°, and first to fourth digital inputs which are portions of the digital input corresponding to each current source unit that are synchronized with the first to fourth overlapping clocks, and each current source unit has first to fourth switch sections connected in parallel to each other and current sources connected in series to the first to fourth switch sections, the second switch unit outputs the current of the current source in response to the second digital input during a period when the first and second overlapping clocks overlap, the second switch unit outputs the current of the current source in response to the second digital input during a period when the second and third overlapping clocks overlap, the third switch unit outputs the current of the current source in response to the third digital input during a period when the third and fourth overlapping clocks overlap, and the fourth switch unit outputs the current of the current source in response to the fourth digital input during a period when the fourth and first overlapping clocks overlap. [Effects of the Invention]
[0014] In the present disclosure, the first to fourth switch units use a common current source, which prevents offset and gain errors. Furthermore, the first to fourth switch units that switch operation are located within a current source unit, and the magnitude of the current flowing through the first to fourth switch units does not depend on the digital input, so no nonlinearity errors occur. Furthermore, NRZ operation is performed, which improves power efficiency. [Brief explanation of the drawings]
[0015] [Figure 1] 1 is a circuit diagram illustrating a D / A converter according to a first embodiment. [Figure 2] 1 is a circuit diagram showing a current source unit according to a first embodiment. [Figure 3] 4 is a timing chart showing the operation of the current source unit according to the first embodiment. [Figure 4] FIG. 10 is a circuit diagram showing a current source unit according to a second embodiment. [Figure 5] 10 is a timing chart showing the operation of the current source unit according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION
[0016] A D / A converter according to an embodiment will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.
[0017] Embodiment 1 1 is a circuit diagram showing a D / A converter according to a first embodiment. A logic circuit 1 receives digital inputs D0 to D n is processed and input to the current source cell 2. Four-phase overlap clocks Φ1 to Φ4, each phase shifted by 90°, are also input to the current source cell 2. Overlap clocks with adjacent numbers, for example, overlap clocks Φ1 and Φ2, are shifted in phase by 90° and overlap by 1 / 4 period. The overlap clocks Φ1 to Φ4 are generated by a four-phase clock generator disclosed in Japanese Patent No. 4152969, for example.
[0018] The current source cell 2 has multiple current source units 3 connected in parallel. Each of the multiple current source units 3 outputs a current according to a corresponding digital input. Resistors R+ and R- are connected between the current source cell 2 and the power supply. The resistor R+ divides the total current of the multiple current source units 3 into an analog output voltage V out The current source unit 3 operates differentially, and the resistor R- converts the total current of the inverted outputs of multiple current source units 3 into the analog output voltage V out -Convert to.
[0019] The current source unit 3 has switch sections SW1 to SW4 connected in parallel with each other and a current source I0 connected in series to the switch sections SW1 to SW4. n Upper side D k+1 ~D n The current source unit 3 corresponding to the digital inputs D0 to D n Lower side D0~D k It is a segment configuration in which the current source units 3 corresponding to the binary code D are configured. For example, in an 8-bit DAC, the unary configuration of the upper 5 bits is made up of 31 current source units 3 that flow the same current, and the binary configuration of the lower 3 bits is made up of current source units 3 including current sources I0 with current ratios of 1, 2, and 4. The current values of the current sources I0 of the multiple current source units 3 in the unary configuration are the same. The current values of the current sources I0 of the multiple current source units 3 in the binary configuration are weighted by current value ratios that are powers of 2. The logic circuit 1 is configured to convert the binary code D to be input to the current source units 3 in the unary configuration. k+1 ~D n A decoding process is performed to convert the signal into a thermometer code.
[0020] 2 is a circuit diagram showing a current source unit according to embodiment 1. The current source I0 is made up of two transistors controlled by voltages Vb and Vbcas, respectively, and passes a current of a constant value. The switch sections SW1 to SW4 are connected to the drain of the current source I0.
[0021] Digital Input D i1 ~D i4 is the digital input D corresponding to the i-th current source unit 3. i These are the parts that synchronize with the overlap clocks Φ1 to Φ4. Digital input D i1 ~D i4 are input to the current source unit 3 in sequence with a phase difference of 90 degrees. The logic circuit 1 outputs the digital input D i to digital input D i1 ~D i4 Generate.
[0022] The switch SW1 consists of transistors Q connected in series. 11 ~Q 13 and transistor Q connected in series with each other 11 ´~Q 13 ´ and transistor Q 11 ~Q 13 and transistor Q 11 ´~Q 13 Similarly, the switch SW2 has transistors Q 21 ~Q 23 and transistor Q connected in series with each other 21 ´~Q 23 The switch section SW3 has transistors Q 31 ~Q 33 and transistor Q connected in series with each other 31 ´~Q 33 The switch section SW4 has transistors Q 41 ~Q 43 and transistor Q connected in series with each other 41 ´~Q 43 ´ and.
[0023] Transistor Q 11 ~Q 13 are the overlap clock Φ1, overlap clock Φ2, and digital input D i1 It is controlled by the transistor Q 21 ~Q 23 are the overlap clock Φ2, overlap clock Φ3, and digital input D i2 It is controlled by the transistor Q 31 ~Q 33 are the overlap clock Φ3, overlap clock Φ4, and digital input D i3 It is controlled by the transistor Q 41 ~Q 43 are the overlap clock Φ4, overlap clock Φ1, and digital input D i4 is controlled by.
[0024] 3 is a timing chart showing the operation of the current source unit according to the first embodiment. i1 After the overlap clock Φ1 goes to "1", the transistor Q 11 Then, when the overlap clock Φ2 goes to "1", the transistor Q 12 When both overlap clocks Φ1 and Φ2 are at "1", the digital input D i1 Depending on the transistor Q 13 The current of the current source I0 is output by the digital input D i1 If is "1", then I out +, and if it is "0", it is I out -, that is, digital input D i1 The current from the current source I0 is I out + and I out -, and the timing at which the current flows is controlled by overlap clocks Φ1 and Φ2.
[0025] After that, when the overlap clock Φ1 becomes "0", the transistor Q 11 is turned off, and the current output from the switch SW1 stops. i2 becomes "1" and the same operation is performed by switch SW2, and D i3 becomes "1" and the same operation is performed by switch SW3, and D i4 becomes "1" and the same operation is performed by switch SW4.
[0026] Switch SW1 switches the digital input D during the overlapping period of the overlapping clocks Φ1 and Φ2. i1 The switch SW2 outputs the current of the current source I0 according to the period when the overlap clocks Φ2 and Φ3 overlap. i2 The switch SW3 outputs the current of the current source I0 according to the period when the overlap clocks Φ3 and Φ4 overlap. i3The switch SW4 outputs the current of the current source I0 according to the overlapping period of the overlapping clocks Φ4 and Φ1. i4 The current of the current source I0 is output according to the
[0027] In this way, the four-phase clock with a phase difference of 90° causes the switches SW1 to SW4 to perform time-interleaved operation within the current source unit 3. As a result, the current from the current source I0 is output by operating one of the switches SW1 to SW4, resulting in NRZ (Non-Return-to-Zero) operation.
[0028] As described above, in this embodiment, the switches SW1 to SW4 of the current source unit 3 use a common current source I0, so offset and gain errors can be prevented. Also, the switches SW1 to SW4 that switch operations are located inside the current source unit 3, and the magnitude of the current flowing through the switches SW1 to SW4 does not depend on the digital input, so no nonlinearity errors occur. Also, the current source unit 3 performs NRZ operation, so power efficiency can be improved.
[0029] The logic circuit 1 is realized by a processing circuit such as a CPU that executes a program stored in a memory, a system LSI, etc. Furthermore, a plurality of processing circuits may cooperate to execute the above functions.
[0030] Embodiment 2 4 is a circuit diagram showing a current source unit according to the second embodiment. The switch SW1 includes AND circuits A1 and A1′ and a transistor Q connected in series. 14 ,Q 15 and transistor Q connected in series with each other 14 ´,Q 15 The switch SW2 includes AND circuits A2 and A2' and a transistor Q 24 ,Q 25 and transistor Q connected in series with each other 24 ´,Q 25The switch SW3 includes AND circuits A3 and A3' and a transistor Q 34 ,Q 35 and transistor Q connected in series with each other 34 ´,Q 35 The switch SW4 includes AND circuits A4 and A4' and a transistor Q 44 ,Q 45 and transistor Q connected in series with each other 44 ´,Q 45 ´ and.
[0031] Overlap clock Φ1 and digital input D i1 are basically the same timing. Therefore, the AND circuit A1 uses the overlap clock Φ1 and the digital input D i1 The transistor Q1 performs an AND operation on the output D of the AND circuit A1. i1 Transistor Q 15 is controlled by the overlap clock Φ2. The AND circuit A1' is controlled by the overlap clock Φ1 and the digital input D i1 - is ANDed. Transistor Q1' is controlled by the output of AND circuit A1'. Transistor Q 15 ´ is controlled by the overlap clock Φ2.
[0032] AND circuit A2 is the overlap clock Φ2 and digital input D i2 AND operation. Transistor Q 24 is the output D of AND circuit A2 i2 Transistor Q 25 is controlled by the overlap clock Φ3. The AND circuit A2' is controlled by the overlap clock Φ2 and the digital input D i2 - AND operation. Transistor Q 24 ' is controlled by the output of AND circuit A2'. Transistor Q 25 ´ is controlled by the overlap clock Φ3.
[0033] AND circuit A3 is the overlap clock Φ3 and digital input Di3 AND operation. Transistor Q 34 is the output D of AND circuit A3 i3 Transistor Q 35 is controlled by the overlap clock Φ4. The AND circuit A3' is controlled by the overlap clock Φ3 and the digital input D i3 - AND operation. Transistor Q 34 ' is controlled by the output of AND circuit A3'. Transistor Q 35 ´ is controlled by the overlap clock Φ4.
[0034] AND circuit A4 is the overlap clock Φ4 and digital input D i4 AND operation. Transistor Q 44 is the output D of AND circuit A4 i4 Transistor Q 45 is controlled by the overlap clock Φ1. The AND circuit A4' is controlled by the overlap clock Φ4 and the digital input D i4 - AND operation. Transistor Q 44 The transistor Q' is controlled by the output of the AND circuit A4'. 45 ´ is controlled by the overlap clock Φ1.
[0035] 5 is a timing chart showing the operation of the current source unit according to the second embodiment. As in the first embodiment, the switches SW1 to SW4 in the current source unit 3 perform time-interleaved operation using four-phase clocks with a phase difference of 90°. That is, the switch SW1 switches the digital input D i1 The switch SW2 outputs the current of the current source I0 according to the period when the overlap clocks Φ2 and Φ3 overlap. i2 The switch SW3 outputs the current of the current source I0 according to the period when the overlap clocks Φ3 and Φ4 overlap. i3 The switch SW4 outputs the current of the current source I0 according to the overlapping period of the overlapping clocks Φ4 and Φ1.i4 The current of the current source I0 is output in accordance with the input signal, thereby achieving the same effect as in the first embodiment.
[0036] Furthermore, in this embodiment, by using AND circuits, the number of transistor stages in each of the switch sections SW1 to SW4 is reduced by one compared to Embodiment 1. This makes it possible to expand the output voltage range by one transistor stage.
[0037] The overlap clocks Φ1 and Φ2 are ANDed to generate the transistor Q 11 ,Q 12 It is also possible to reduce the number of transistor stages to one. In this case, the number of transistor stages is reduced by one. However, as the operating speed increases, the pulse width during the "1" period after the AND operation narrows, so the speed limit becomes lower than when the AND operation is not performed. [Explanation of symbols]
[0038] 1 Logic circuit, 2 Current source cell, 3 Current source unit, A1~A4 AND circuit, D0~D n ,D i1 ~D i4 Digital input, I0 current source, Q 11 ~Q 45 Transistor, R+, R- resistor, SW1 to SW4 switch section, Φ1 to Φ4 overlap clock
Claims
1. a current source cell having a plurality of current source units connected in parallel to each other and each outputting a current in response to a digital input; a resistor for converting a total current of the plurality of current source units into an analog output voltage; Each current source unit receives first to fourth overlap clocks whose phases are sequentially shifted by 90°, and first to fourth digital inputs which are portions of the digital inputs corresponding to each current source unit that are synchronized with the first to fourth overlap clocks, respectively; each current source unit includes first to fourth switch sections connected in parallel to one another and a current source connected in series to the first to fourth switch sections; the first switch unit outputs a current from the current source in response to the first digital input during a period in which the first and second overlapping clocks overlap; the second switch unit outputs a current from the current source in response to the second digital input during a period in which the second and third overlapping clocks overlap; the third switch unit outputs a current from the current source in response to the third digital input during a period in which the third and fourth overlapping clocks overlap; the fourth switch section outputs the current of the current source in response to the fourth digital input during a period in which the fourth and first overlapping clocks overlap.
2. 2. The D / A converter according to claim 1, further comprising a logic circuit that generates the first to fourth digital inputs from the digital inputs corresponding to each current source unit.
3. the first switch section has first to third transistors connected in series with each other, the first to third transistors being controlled by the first overlapping clock, the second overlapping clock, and the first digital input, respectively; the second switch section has fourth to sixth transistors connected in series with each other, the fourth to sixth transistors being controlled by the second overlapping clock, the third overlapping clock, and the second digital input, respectively; the third switch section has seventh to ninth transistors connected in series with each other, the seventh to ninth transistors being controlled by the third overlapping clock, the fourth overlapping clock, and the third digital input, respectively; 3. The D / A converter according to claim 1, wherein the fourth switch section has tenth to twelfth transistors connected in series with each other, and the tenth to twelfth transistors are controlled by the fourth overlapping clock, the first overlapping clock, and the fourth digital input, respectively.
4. the first switch unit has a first AND circuit and first and second transistors connected in series with each other, the first AND circuit performs an AND operation on the first overlapping clock and the first digital input, and the first and second transistors are controlled by the output of the first AND circuit and the second overlapping clock, respectively; the second switch unit has a second AND circuit and third and fourth transistors connected in series with each other, the second AND circuit performs an AND operation on the second overlapping clock and the second digital input, the third and fourth transistors are controlled by the output of the second AND circuit and the third overlapping clock, respectively; the third switch unit has a third AND circuit and fifth and sixth transistors connected in series with each other, the third AND circuit performs an AND operation on the third overlapping clock and the third digital input, the fifth and sixth transistors are controlled by the output of the third AND circuit and the fourth overlapping clock, respectively; 3. The D / A converter according to claim 1, wherein the fourth switch section has a fourth AND circuit and seventh and eighth transistors connected in series with each other, the fourth AND circuit performs an AND operation on the fourth overlap clock and the fourth digital input, and the seventh and eighth transistors are controlled by the output of the fourth AND circuit and the first overlap clock, respectively.
5. the current source cells have a segment configuration in which the current source units corresponding to the upper side of the digital inputs have a unary configuration and the current source units corresponding to the lower side of the digital inputs have a binary configuration; the current values of the current sources of the plurality of current source units in the unary configuration are the same; 3. The D / A converter according to claim 1, wherein the current values of the current sources of the plurality of current source units having the binary configuration are weighted by a current value ratio of a power of two.
6. 3. The D / A converter according to claim 1, wherein the current source unit operates differentially.