Head unit and liquid discharge device

Abstract

To provide a head unit capable of reducing the risk of distortion in the waveform of a drive signal.SOLUTION: In a head unit, a wiring board includes a first side, a second side positioned facing the first side, and a first supply point to which a first drive signal is supplied. When viewed along a second axis orthogonal to a first axis connecting the first and second sides, a first capacitor, in which a first reference voltage signal is supplied to a first electrode and a ground signal is supplied to a second electrode, is positioned between an output connector electrically connected to a first print head and the first supply point. The shortest distance between the output connector and the first electrode is shorter than the shortest distance between the output connector and the second electrode, and the shortest distance between the first supply point and the first electrode is longer than the shortest distance between the first supply point and the second electrode.SELECTED DRAWING: Figure 22

Description

[Technical Field]

[0001] The present invention relates to a head unit and a liquid ejection apparatus. [Background technology]

[0002] A known liquid ejection device uses piezoelectric elements to eject liquid to form documents or images on a medium. The piezoelectric elements are provided in correspondence with each of a plurality of ejection portions in a print head. When the piezoelectric elements are driven in accordance with a drive signal, an amount of liquid is ejected from the corresponding ejection portion in accordance with the drive of the piezoelectric element, forming dots on the medium.

[0003] For example, Patent Document 1 discloses a technique for reducing the risk of distortion occurring in the signal waveform of a drive signal by optimally arranging the propagation path of the drive signal that drives a piezoelectric element. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2023-063709 Summary of the Invention [Problem to be solved by the invention]

[0005] However, from the viewpoint of reducing the possibility of distortion occurring in the signal waveform of the drive signal, the technique described in Patent Document 1 alone is not sufficient, and there is room for further improvement. [Means for solving the problem]

[0006] One aspect of the head unit according to the present invention is a first print head including a first driving element having one end supplied with a first driving signal and the other end supplied with a first reference voltage signal having a constant voltage value, the first print head ejecting liquid in response to the driving of the first driving element; a driving unit that outputs the first driving signal and the first reference voltage signal to the first print head; Equipped with The drive unit is a first drive circuit that outputs the first drive signal; a first reference voltage signal output circuit that outputs the first reference voltage signal; an output connector electrically connected to the first print head; a first capacitor having a first electrode to which the first reference voltage signal is supplied and a second electrode to which a ground signal is supplied; a wiring board on which the output connector is provided and through which the first drive signal and the first reference voltage signal propagate; and the wiring substrate includes a first side, a second side facing the first side, and a first supply point to which the first driving signal is supplied; the first capacitor is located between the output connector and the first supply point when viewed along a second axis perpendicular to a first axis connecting the first side and the second side; the shortest distance between the output connector and the first electrode is shorter than the shortest distance between the output connector and the second electrode; The shortest distance between the first supply point and the first electrode is longer than the shortest distance between the first supply point and the second electrode.

[0007] One aspect of the liquid ejection device according to the present invention is a transport unit that transports the medium; a first print head including a first driving element having one end supplied with a first driving signal and the other end supplied with a first reference voltage signal having a constant voltage value, the first print head ejecting liquid onto the medium in response to the driving of the first driving element; a driving unit that outputs the first driving signal and the first reference voltage signal to the first print head; Equipped with The drive unit is a first drive circuit that outputs the first drive signal; a first reference voltage signal output circuit that outputs the first reference voltage signal; an output connector electrically connected to the first print head; a first capacitor having a first electrode to which the first reference voltage signal is supplied and a second electrode to which a ground signal is supplied; a wiring board on which the output connector is provided and through which the first drive signal and the first reference voltage signal propagate; and the wiring substrate includes a first side, a second side facing the first side, and a first supply point to which the first driving signal is supplied; the first capacitor is located between the output connector and the first supply point when viewed along a second axis perpendicular to a first axis connecting the first side and the second side; the shortest distance between the output connector and the first electrode is shorter than the shortest distance between the output connector and the second electrode; The shortest distance between the first supply point and the first electrode is longer than the shortest distance between the first supply point and the second electrode. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating a schematic configuration of a liquid ejection device. [Figure 2] FIG. 2 is a diagram illustrating a schematic configuration of a head unit. [Figure 3] 3A to 3C are diagrams showing examples of signal waveforms of drive signals COMA, COMB, and COMC. [Figure 4] FIG. 2 is a diagram illustrating a functional configuration of a drive signal selection circuit. [Figure 5] FIG. 10 is a diagram showing an example of the decoded content in the decoder. [Figure 6] FIG. 10 is a diagram showing an example of the configuration of a selection circuit corresponding to one ejection section. [Figure 7] 10A and 10B are diagrams for explaining the operation of a drive signal selection circuit. [Figure 8] FIG. 2 is a diagram illustrating an example of the configuration of a drive circuit. [Figure 9] FIG. 2 is a diagram illustrating an example of the configuration of a drive signal discharge circuit. [Figure 10]FIG. 2 is a diagram illustrating an example of the configuration of a reference voltage signal output circuit. [Figure 11] FIG. 2 is a diagram illustrating an example of the configuration of a VHV control signal output circuit. [Figure 12] FIG. 2 is a diagram illustrating a configuration of a state signal input / output circuit. [Figure 13] FIG. 2 is a diagram illustrating a configuration of an abnormality signal input / output circuit. [Figure 14] FIG. 2 is a diagram illustrating an example of the configuration of a step-down circuit. [Figure 15] FIG. 2 is a diagram illustrating an example of the configuration of a first step-down voltage circuit. [Figure 16] FIG. 2 is a diagram showing the structure of a discharge unit. [Figure 17] FIG. 1 is a diagram illustrating an example of the structure of a print head. [Figure 18] FIG. 2 is a diagram showing an example cross section of a print head. [Figure 19] FIG. 2 is a diagram showing the structure of a drive unit. [Figure 20] FIG. 2 is a diagram illustrating an example of the structure of a drive circuit module. [Figure 21] FIG. 2 is a diagram showing an example of a cross-sectional structure of a head substrate. [Figure 22] FIG. 4 is a diagram showing an example of the arrangement of a plurality of electronic components mounted on a head substrate. [Figure 23] FIG. 2 is a diagram showing an example of a wiring pattern formed on a head substrate for transmitting drive signals COMA1 to COMA6. [Figure 24] FIG. 2 is a diagram showing an example of a wiring pattern formed on a head substrate for propagating drive signals COMB1 to COMB6. [Figure 25] FIG. 2 is a diagram showing an example of a wiring pattern formed on a head substrate for transmitting drive signals COMC1 to COMC6 and reference voltage signals VBS1 to VBS3. [Figure 26] FIG. 10 is a diagram showing an example of a wiring pattern formed on a head substrate for propagating reference voltage signals VBS4 to VBS6. DETAILED DESCRIPTION OF THE INVENTION

[0009] Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings used are for the convenience of explanation. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0010] 1. Configuration of the liquid ejection device Fig. 1 is a diagram showing a schematic configuration of a liquid ejection device 1. As shown in Fig. 1, the liquid ejection device 1 is a so-called line-type inkjet printer that forms a desired image on a medium P by ejecting ink at a desired timing onto the medium P being transported by a transport unit 4. Here, in the following description, the direction in which the medium P is transported will sometimes be referred to as the transport direction, and the width direction of the transported medium P will sometimes be referred to as the main scanning direction.

[0011] As shown in FIG. 1, the liquid ejection device 1 includes a control unit 2, a liquid container 3, a transport unit 4, and a plurality of head units 5.

[0012] The control unit 2 includes an AC / DC converter, and receives a commercial AC voltage signal from outside the liquid ejection device 1. The AC / DC converter in the control unit 2 converts the input commercial AC voltage signal into a voltage signal VDC, which is a DC voltage signal with a predetermined voltage value, for example, 48 V, and supplies the voltage signal VDC to each element of the liquid ejection device 1. The control unit 2 also includes processing circuits such as a CPU (Central Processing Unit) and an FPGA (Field Programmable Gate Array), and a storage circuit such as a semiconductor memory. The processing circuit in the control unit 2 outputs control signals that control each element of the liquid ejection device 1 based on image data input from an external device, such as a host computer (not shown), that is provided outside the liquid ejection device 1.

[0013] The liquid container 3 stores ink as an example of a liquid to be supplied to the head unit 5. Specifically, the liquid container 3 stores ink of a plurality of colors to be ejected onto the medium P, such as black, cyan, magenta, yellow, red, gray, etc.

[0014] The transport unit 4 has a transport motor 41 and a transport roller 42. A transport control signal Ctrl-T output by the control unit 2 is input to the transport unit 4. The transport motor 41 is driven based on the input transport control signal Ctrl-T, and the drive of the transport motor 41 causes the transport roller 42 to rotate. The rotation of the transport roller 42 transports the medium P along the transport direction.

[0015] The multiple head units 5 are electrically connected to the control unit 2 via flexible cables such as flexible flat cables (FFCs). Such flexible cables such as FFCs that electrically connect the control unit 2 and the head units 5 may be 2 meters or longer. Each of the multiple head units 5 includes a drive unit 10 and a discharge unit 20. A voltage signal VDC and an image information signal IP output by the control unit 2 are input to the head unit 5 via the FFCs, and ink stored in a liquid container 3 is supplied to the head unit 5 via an ink tube (not shown). The head unit 5 operates using the voltage signal VDC as drive power. The drive unit 10 controls the operation of the discharge unit 20 based on the image information signal IP, and the discharge unit 20 discharges ink supplied from the liquid container 3 onto the medium P under the control of the drive unit 10.

[0016] In the liquid ejection device 1 of this embodiment, the ejection units 20 of each of the multiple head units 5 are arranged side by side along the main scanning direction so as to be equal to or greater than the width of the medium P. This enables the ejection units 20 to eject ink onto the entire widthwise area of ​​the medium P being transported. In other words, the liquid ejection device 1 of this embodiment constitutes a so-called line-type inkjet printer in which each of the multiple ejection units 20 arranged side by side so as to be equal to or greater than the width of the medium P ejects ink as the medium P is transported, thereby forming a desired image on the medium P. Note that the liquid ejection device 1 is not limited to a line-type inkjet printer, and may also be a so-called serial-type inkjet printer in which the ejection units 20 move back and forth along the width direction of the medium P, which is the main scanning direction, and eject ink onto the medium P being transported in synchronization with the reciprocating movement, thereby forming a desired image on the medium P.

[0017] 2. Functional configuration of the head unit 2.1 Functional configuration of the head unit Next, the schematic configuration of the head unit 5 will be described. Here, all of the multiple head units 5 that the liquid ejection device 1 has have the same configuration. Therefore, in the following explanation, only the configuration of one head unit 5 will be described. FIG. 2 is a diagram showing the schematic configuration of the head unit 5. As shown in FIG. 2, the head unit 5 has a drive unit 10 and a discharge unit 20. Furthermore, in the head unit 5, the drive unit 10 and the discharge unit 20 are electrically connected via a connection member 30.

[0018] The connection member 30 is a member for electrically connecting the drive unit 10 and the discharge unit 20, and may be a flexible printed circuit (FPC: Flexible Printed Circuits) or an FFC. Note that a BtoB (Board to Board) connector may be used as the connection member 30 instead of the FPC or FFC, or a configuration may be used in which the BtoB connector and the FPC or FFC are used together.

[0019] The drive unit 10 includes a control circuit 100, drive signal output circuits 50-1 to 50-6, a conversion circuit 120, a step-down circuit 130, and capacitors 110-1 to 110-6, 190-1 to 190-6.

[0020] The step-down circuit 130 receives step-down control signals VHVc1 to VHVc6 and a voltage signal VDC. That is, the drive unit 10 is supplied with the voltage signal VDC via a cable electrically connected to the control unit 2. The step-down circuit 130 steps down the input voltage signal VDC, which is a DC voltage with a voltage value of 48 V, to generate a plurality of DC voltage signals including a voltage signal VHV with a constant voltage value of 42 V and a voltage signal VDD with a constant voltage value of 5 V, and outputs these signals to the components of the head unit 5. At this time, the step-down circuit 130 operates based on the logic levels of the step-down control signals VHVc1 to VHVc6, thereby switching whether or not to output the voltage signal VHV obtained by stepping down the input voltage signal VDC. Specific examples of the configuration and operation of the step-down circuit 130 will be described later.

[0021] The control circuit 100 includes a processing circuit such as a CPU or FPGA, and a storage circuit such as a semiconductor memory. The control circuit 100 receives an image information signal IP output by the control unit 2. The control circuit 100 outputs signals that control each element of the head unit 5 based on the input image information signal IP.

[0022] The control circuit 100 generates a base data signal dDATA for controlling the operation of the discharge unit 20 based on the image information signal IP and outputs it to the conversion circuit 120. The conversion circuit 120 converts the base data signal dDATA into a differential signal such as LVDS (Low Voltage Differential Signaling) and outputs it to the discharge unit 20 as a data signal DATA. The conversion circuit 120 may convert the base data signal dDATA into a differential signal of a high-speed transfer method other than LVDS, such as LVPECL (Low Voltage Positive Emitter Coupled Logic) or CML (Current Mode Logic), and output it to the discharge unit 20 as a data signal DATA. The conversion circuit 120 may also convert a part or all of the input base data signal dDATA into a predetermined single-ended signal and output it to the discharge unit 20 as a data signal DATA.

[0023] The control circuit 100 also outputs base drive data signals dA1, dB1, and dC1 to the drive signal output circuit 50-1. Voltage signals VHV and VDD are also input to the drive signal output circuit 50-1. The drive signal output circuit 50-1 has drive circuits 52a, 52b, and 52c. The base drive data signal dA1 is input to the drive circuit 52a of the drive signal output circuit 50-1. The drive circuit 52a of the drive signal output circuit 50-1 operates based on the voltage signal VDD, performs digital-to-analog conversion on the input base drive data signal dA1, and then performs class D amplification on the converted signal based on the voltage signal VHV to generate the drive signal COMA1 and output it to the discharge unit 20. The base drive data signal dB1 is input to the drive circuit 52b of the drive signal output circuit 50-1. The drive circuit 52b included in the drive signal output circuit 50-1 operates based on the voltage signal VDD, performs digital-to-analog conversion on the input base drive data signal dB1, and then performs class-D amplification of the converted signal based on the voltage signal VHV to generate a drive signal COMB1, which is output to the discharge unit 20. The base drive data signal dC1 is input to the drive circuit 52c included in the drive signal output circuit 50-1. The drive circuit 52c included in the drive signal output circuit 50-1 operates based on the voltage signal VDD, performs digital-to-analog conversion on the input base drive data signal dC1, and then performs class-D amplification of the converted signal based on the voltage signal VHV to generate a drive signal COMC1, which is output to the discharge unit 20. In other words, the drive signal output circuit 50-1 generates drive signals COMA1, COMB1, and COMC1 having signal waveforms corresponding to the input base drive data signals dA1, dB1, and dC1, and outputs them to the discharge unit 20.

[0024] Furthermore, each of the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-1 generates a constant reference voltage signal VBS1 having a voltage value of 5.5V, 6V, or the like. The reference voltage signal VBS1 generated by each of the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-1 propagates through a common wiring and is output from the drive signal output circuit 50-1 to the discharge unit 20. Note that the drive signal output circuit 50-1 may output the reference voltage signal VBS1 output by any of the drive circuits 52a, 52b, and 52c to the discharge unit 20. The reference voltage signal VBS1 may also be generated by a power supply circuit (not shown) configured separately from the drive circuits 52a, 52b, and 52c.

[0025] The control circuit 100 also outputs basic drive data signals dAi, dBi, and dCi to the drive signal output circuit 50-i (where i is any one of 2 to 6). The drive signal output circuit 50-i also receives input of voltage signals VHV and VDD. The drive signal output circuit 50-i includes drive circuits 52a, 52b, and 52c. The basic drive data signal dAi is input to the drive circuit 52a included in the drive signal output circuit 50-i. The drive circuit 52a included in the drive signal output circuit 50-i operates based on the voltage signal VDD, performs digital-to-analog conversion on the input basic drive data signal dAi, and then performs class-D amplification on the converted signal based on the voltage signal VHV to generate the drive signal COMAi and output it to the discharge unit 20. The basic drive data signal dBi is input to the drive circuit 52b included in the drive signal output circuit 50-i. The drive circuit 52b included in the drive signal output circuit 50-i operates based on the voltage signal VDD, performs digital-to-analog conversion on the input base drive data signal dBi, and then performs class-D amplification on the converted signal based on the voltage signal VHV to generate the drive signal COMBi, which is output to the discharge unit 20. The base drive data signal dCi is input to the drive circuit 52c included in the drive signal output circuit 50-1. The drive circuit 52c included in the drive signal output circuit 50-i operates based on the voltage signal VDD, performs digital-to-analog conversion on the input base drive data signal dCi, and then performs class-D amplification on the converted signal based on the voltage signal VHV to generate the drive signal COMCi, which is output to the discharge unit 20. In other words, the drive signal output circuit 50-i generates drive signals COMAi, COMBi, and COMCi having signal waveforms corresponding to the input base drive data signals dAi, dBi, and dCi, and outputs them to the discharge unit 20.

[0026] Furthermore, each of the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-i generates a constant reference voltage signal VBSi having a voltage value of 5.5 V, 6 V, or the like. The reference voltage signal VBSi generated by each of the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-i propagates through common wiring and is output from the drive signal output circuit 50-i to the discharge unit 20. Note that the drive signal output circuit 50-i may output the reference voltage signal VBSi output by any of the drive circuits 52a, 52b, and 52c to the discharge unit 20. The reference voltage signal VBSi may also be generated by a power supply circuit (not shown) configured separately from the drive circuits 52a, 52b, and 52c.

[0027] The drive signal output circuit 50-1 also generates a step-down control signal VHVc1 and outputs it to the step-down circuit 130. The step-down control signal VHVc1 is generated by each of the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-1. The drive signal output circuit 50-1 then propagates the step-down control signals VHVc1 generated by each of the drive circuits 52a, 52b, and 52c via a common wiring and supplies them to the step-down circuit 130. Note that the drive signal output circuit 50-1 may output the step-down control signal VHVc1 generated by any of the drive circuits 52a, 52b, and 52c from the drive signal output circuit 50-1 and supply it to the step-down circuit 130. Similarly, the drive signal output circuit 50-i also generates a step-down control signal VHVci and outputs it to the step-down circuit 130. The step-down control signal VHVci is generated by each of the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-i. The drive signal output circuit 50-i propagates the step-down control signal VHVci generated by each of the drive circuits 52a, 52b, and 52c via a common wiring and supplies it to the step-down circuit 130. Note that the drive signal output circuit 50-i may output the step-down control signal VHVci generated by any of the drive circuits 52a, 52b, and 52c from the drive signal output circuit 50-1 and supply it to the step-down circuit 130.

[0028] Here, the drive signal output circuit 50-1 and the drive signal output circuits 50-2 to 50-6 have the same configuration, and when there is no need to distinguish them, they may be simply referred to as the drive signal output circuit 50. In this case, the drive signal output circuit 50 will be described as including drive circuits 52a, 52b, and 52c, with the drive circuit 52a outputting the drive signal COMA, the drive circuit 52b outputting the drive signal COMB, and the drive circuit 52c outputting the drive signal COMC. Furthermore, the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50 all have the same configuration, and when there is no need to distinguish them, they may be simply referred to as the drive circuit 52. In this case, the drive circuit 52 will be described as generating the drive signal COM based on the basic drive data signal do and outputting the generated drive signal COM to the discharge unit 20.

[0029] On the other hand, when describing the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-1 separately from the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-i, the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-1 may be referred to as drive circuits 52a1, 52b1, and 52c1, respectively, and the drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50-i may be referred to as drive circuits 52ai, 52bi, and 52ci, respectively. Specific examples of the configuration of the drive circuits 52 will be described later.

[0030] One end of capacitor 110-1 is electrically connected to the propagation path of the voltage signal VHV supplied to drive signal output circuit 50-1, and the other end is supplied with a ground signal at ground potential. One end of capacitor 110-i is electrically connected to the propagation path of the voltage signal VHV supplied to drive signal output circuit 50-i, and the other end is supplied with a ground signal. In other words, capacitors 110-1 to 110-6 function as stabilizing capacitors that stabilize the voltage values ​​of the voltage signals VHV supplied to the corresponding drive signal output circuits 50-1 to 50-6. These capacitors 110-1 to 110-6 are elements with large capacitance, and for example, electrolytic capacitors can be used. In the following description, capacitors 110-1 to 110-6 are assumed to be electrolytic capacitors, but capacitors 110-1 to 110-6 may be ceramic capacitors or film capacitors as long as they have a capacitance that stabilizes the voltage value of voltage signal VHV and is capable of supplying sufficient current to each of drive signal output circuits 50-1 to 50-6. Furthermore, the electrolytic capacitors used as capacitors 110-1 to 110-6 may be aluminum electrolytic capacitors or tantalum electrolytic capacitors.

[0031] One end of capacitor 190-1 is electrically connected to the propagation path of reference voltage signal VBS1 output by drive signal output circuit 50-1, and the other end is supplied with a ground signal. One end of capacitor 190-i is electrically connected to the propagation path of reference voltage signal VBSi output by drive signal output circuit 50-i, and the other end is supplied with a ground signal. In other words, capacitors 190-1 to 190-6 function as stabilizing capacitors that stabilize the voltage values ​​of reference voltage signals VBS1 to VBS6 output by the corresponding drive signal output circuits 50-1 to 50-6. These capacitors 190-1 to 190-6 are elements with large capacitance, and for example, electrolytic capacitors can be used. In the following description, the capacitors 190-1 to 190-6 are assumed to be electrolytic capacitors, but the capacitors 190-1 to 190-6 may be ceramic capacitors or film capacitors as long as they have a capacitance that stabilizes the voltage values ​​of the reference voltage signals VBS1 to VBS6 and is capable of supplying a sufficient current to the piezoelectric element 60 (described later) of the discharge unit 20. The electrolytic capacitors serving as the capacitors 190-1 to 190-6 may be aluminum electrolytic capacitors or tantalum electrolytic capacitors.

[0032] That is, the driving unit 10 includes a capacitor 190-1 having a positive terminal at one end supplied with a reference voltage signal VBS1 and a negative terminal at the other end supplied with a ground signal; a capacitor 190-2 having a positive terminal at one end supplied with a reference voltage signal VBS2 and a negative terminal at the other end supplied with a ground signal; a capacitor 190-3 having a positive terminal at one end supplied with a reference voltage signal VBS3 and a negative terminal at the other end supplied with a ground signal; and a capacitor 190-4 having a positive terminal at one end supplied with a reference voltage signal VBS4 and a negative terminal at the other end supplied with a ground signal. The capacitor 190-4 has one end, a negative pole, to which a ground signal is supplied; a capacitor 190-5 has one end, a positive pole, to which a reference voltage signal VBS5 is supplied and the other end, a negative pole, to which a ground signal is supplied; a capacitor 190-6 has one end, a positive pole, to which a reference voltage signal VBS6 is supplied and the other end, a negative pole, to which a ground signal is supplied; and capacitors 110-1 to 110-6 have one end, a positive pole, to which a voltage signal VHV is supplied and the other end, a negative pole, to which a ground signal is supplied.

[0033] The ejection unit 20 includes a restoration circuit 220 and print heads 23-1 to 23-6.

[0034] Data signal DATA is input to restoration circuit 220. Restoration circuit 220 restores the input data signal DATA, which is a differential signal, to a single-ended signal, converts the restored single-ended signal into a parallel signal corresponding to each of print heads 23-1 to 23-6, and outputs the parallel signals to the corresponding print heads 23-1 to 23-6.

[0035] Specifically, the restoration circuit 220 restores the data signal DATA and converts it into parallel signals to generate a clock signal SCK1, a print data signal SI1, and a latch signal LAT1, which it outputs to the print head 23-1. The restoration circuit 220 also restores the data signal DATA and converts it into parallel signals to generate a clock signal SCKi, a print data signal SIi, and a latch signal LATi, which it outputs to the print head 23-i. Note that any of the clock signals SCK1 to SCK6, print data signals SI1 to SI6, and latch signals LAT1 to LAT6 corresponding to the print heads 23-1 to 23-6 output by the restoration circuit 220 may be input in common to the print heads 23-1 to 23-6.

[0036] Here, considering that the restoration circuit 220 restores the data signal DATA and converts it into a parallel signal to generate the clock signals SCK1-SCK6, the print data signals SI1-SI6, and the latch signals LAT1-LAT6, the data signal DATA output by the conversion circuit 120 is a differential signal that serially includes signals corresponding to the clock signals SCK1-SCK6, the print data signals SI1-SI6, and the latch signals LAT1-LAT6. Therefore, the original data signal dDATA output by the control circuit 100 includes single-ended signals corresponding to the clock signals SCK1-SCK6, the print data signals SI1-SI6, and the latch signals LAT1-LAT6. In other words, the control circuit 100 outputs the original data signal dDATA as a signal to control the operation of the print heads 23-1-23-6 of the discharge unit 20.

[0037] The print head 23-1 has a drive signal selection circuit 200 and multiple ejection units 600. Each of the multiple ejection units 600 includes a piezoelectric element 60. That is, the print head 23-1 has the same number of piezoelectric elements 60 as the multiple ejection units 600. The print head 23-1 receives voltage signals VHV and VDD, drive signals COMA1, COMB1, and COMC1, a reference voltage signal VBS1, a clock signal SCK1, a print data signal SI1, and a latch signal LAT1. The voltage signals VHV and VDD, drive signals COMA1, COMB1, and COMC1, the clock signal SCK1, the print data signal SI1, and the latch signal LAT1 are input to the drive signal selection circuit 200 of the print head 23-1. The drive signal selection circuit 200 uses the voltage signal VDD as drive power and generates the drive signal VOUT by selecting or deselecting each of the drive signals COMA1, COMB1, and COMC1 based on the input voltage signal VHV, clock signal SCK1, print data signal SI1, and latch signal LAT1. The drive signal selection circuit 200 then supplies the generated drive signal VOUT to one end of the piezoelectric element 60 of the corresponding ejection unit 600. At this time, a reference voltage signal VBS1 is supplied to the other end of the piezoelectric element 60. The piezoelectric element 60 is driven by the potential difference between the drive signal VOUT supplied to one end and the reference voltage signal VBS1 supplied to the other end. Ink is ejected from the corresponding ejection unit 600 according to the drive amount of this piezoelectric element 60.

[0038] Similarly, print head 23-i has a drive signal selection circuit 200 and multiple ejection units 600. Each of the multiple ejection units 600 includes a piezoelectric element 60. That is, print head 23-i has the same number of piezoelectric elements 60 as the multiple ejection units 600. Voltage signals VHV, VDD, drive signals COMAi, COMBi, COMCi, reference voltage signal VBSi, clock signal SCKi, print data signal SIi, and latch signal LATi are input to print head 23-i. The voltage signals VHV, VDD, drive signals COMAi, COMBi, COMCi, clock signal SCKi, print data signal SIi, and latch signal LATi are input to the drive signal selection circuit 200 of print head 23-i. The drive signal selection circuit 200 uses the voltage signal VDD as drive power and generates the drive signal VOUT by selecting or deselecting each of the drive signals COMAi, COMBi, and COMCi based on the input voltage signal VHV, clock signal SCKi, print data signal SIi, and latch signal LATi. The drive signal selection circuit 200 then supplies the generated drive signal VOUT to one end of the piezoelectric element 60 of the corresponding ejection unit 600. At this time, a reference voltage signal VBSi is supplied to the other end of the piezoelectric element 60. The piezoelectric element 60 is driven by the potential difference between the drive signal VOUT supplied to one end and the reference voltage signal VBSi supplied to the other end. Ink is ejected from the corresponding ejection unit 600 according to the drive amount of this piezoelectric element 60.

[0039] As described above, the head unit 5 of the liquid ejection device 1 has the drive unit 10 and the ejection unit 20, and the drive unit 10 controls the operation of the ejection unit 20 based on the image information signal IP output by the control unit 2, and the ejection unit 20 ejects ink supplied from the liquid container 3 onto the medium P under the control of the drive unit 10. As a result, the head unit 5 ejects a predetermined amount of ink onto the medium P at a predetermined timing based on the image information signal IP. As a result, the liquid ejection device 1 forms a desired image on the medium P.

[0040] That is, the head unit 5 has a drive unit 10 that receives an external voltage signal VDC and outputs drive signals COMA1 to COMA6, COMB1 to COMB6, COMC1 to COMC6, and reference voltage signals VBS1 to VBS6, and an ejection unit 20 that ejects ink in accordance with the drive signals COMA1 to COMA6, COMB1 to COMB6, and COMC1 to COMC6. In other words, the drive unit 10 outputs the drive signals COMA1 to COMA6, COMB1 to COMB6, COMC1 to COMC6, and reference voltage signals VBS1 to VBS6 to the corresponding print heads 23-1 to 23-6.

[0041] Here, the print heads 23-1 to 23-6 of the discharge unit 20 have the same configuration and only differ in the signals they receive. Therefore, in the following description, when there is no need to distinguish between the print heads 23-1 to 23-6, they may be simply referred to as print heads 23. In this case, the drive signals COMA1 to COMA6 input to the print heads 23 may be referred to as drive signals COMA, the drive signals COMB1 to COMB6 may be referred to as drive signals COMB, the drive signals COMC1 to COMC6 may be referred to as drive signals COMC, the clock signals SCK1 to SCK6 may be referred to as clock signals SCK, the print data signals SI1 to SI6 may be referred to as print data signals SI, and the latch signals LAT1 to LAT6 may be referred to as latch signals LAT.

[0042] 2.2 Configuration and operation of the drive signal selection circuit Next, we will explain the configuration and operation of the drive signal selection circuit 200 of the print head 23. Before explaining the configuration and operation of the drive signal selection circuit 200 of the print head 23, we will first explain an example of the signal waveforms included in the drive signals COMA, COMB, and COMC input to the drive signal selection circuit 200.

[0043] 3 is a diagram showing an example of the signal waveforms of the drive signals COMA, COMB, and COMC. As shown in Fig. 3, the drive signal COMA includes a trapezoidal waveform Adp arranged in a period T from when the latch signal LAT rises to when the next latch signal LAT rises. The trapezoidal waveform Adp is a signal waveform that, when supplied to one end of the piezoelectric element 60, drives the piezoelectric element 60 so that a predetermined amount of ink is ejected from the corresponding ejection portion 600.

[0044] The drive signal COMB includes a trapezoidal waveform Bdp arranged at a period T. The trapezoidal waveform Bdp is a signal waveform having a smaller voltage amplitude than the trapezoidal waveform Adp, and when the trapezoidal waveform Bdp is supplied to one end of the piezoelectric element 60, it causes the ejection section 600 corresponding to that piezoelectric element 60 to eject a smaller amount of ink than a predetermined amount. In other words, when the trapezoidal waveform Bdp is supplied to one end of the piezoelectric element 60, it is a signal waveform that drives the piezoelectric element 60 so that the corresponding ejection section 600 ejects a smaller amount of ink than a predetermined amount.

[0045] Here, the amount of ink ejected from the ejection section 600 when the drive signal COMA is supplied to the piezoelectric element 60 is greater than the amount of ink ejected from the ejection section 600 when the drive signal COMB is supplied to the piezoelectric element 60. Therefore, the drive amount of the piezoelectric element 60 when the drive signal COMA is supplied to the piezoelectric element 60 is greater than the drive amount of the piezoelectric element 60 when the drive signal COMB is supplied to the piezoelectric element 60. In other words, the amount of ink ejected from the ejection section 600 corresponding to the piezoelectric element 60 when the drive signal COMA is supplied to the piezoelectric element 60 is different from the amount of ink ejected from the ejection section 600 corresponding to the piezoelectric element 60 when the drive signal COMB is supplied to the piezoelectric element 60; the amount of ink ejected from the ejection section 600 corresponding to the piezoelectric element 60 when the drive signal COMA is supplied to the piezoelectric element 60 is greater than the amount of ink ejected from the ejection section 600 corresponding to the piezoelectric element 60 when the drive signal COMB is supplied to the piezoelectric element 60; therefore, the amount of current generated by the propagation of the drive signal COMA is greater than the amount of current generated by the propagation of the drive signal COMB.

[0046] The drive signal COMC also includes a trapezoidal waveform Cdp arranged at a period T. The trapezoidal waveform Cdp is a signal waveform whose voltage amplitude is smaller than those of the trapezoidal waveforms Adp and Bdp, and when the trapezoidal waveform Cdp is supplied to one end of the piezoelectric element 60, it vibrates the ink near the nozzle opening to an extent that ink is not ejected from the ejection section 600 corresponding to that piezoelectric element 60. In other words, when the trapezoidal waveform Cdp is supplied to one end of the piezoelectric element 60, it drives the piezoelectric element 60 to an extent that ink is not ejected from the corresponding ejection section 600. This trapezoidal waveform Cdp vibrates the ink near the nozzle opening of the ejection section 600 including the piezoelectric element 60. As a result, the risk of an increase in ink viscosity near the corresponding nozzle opening is reduced.

[0047] As described above, the drive signals COMA and COMB drive the corresponding piezoelectric elements 60 so that ink is ejected from the ejection portions 600, and the drive signal COMC drives the corresponding piezoelectric elements 60 so that ink is not ejected from the ejection portions 600. In other words, the drive amount of the piezoelectric elements 60 when the drive signals COMA and COMB are supplied to the piezoelectric elements 60 is greater than the drive amount of the piezoelectric elements 60 when the drive signal COMC is supplied to the piezoelectric elements 60. Therefore, the voltage amplitude of the drive signals COMA and COMB is greater than the voltage amplitude of the drive signal COMC, and the amount of current generated in conjunction with the propagation of the drive signals COMA and COMB is greater than the amount of current generated in conjunction with the propagation of the drive signal COMC.

[0048] Furthermore, at the start and end timings of each of the trapezoidal waveforms Adp, Bdp, and Cdp, the voltage value of each of the trapezoidal waveforms Adp, Bdp, and Cdp is a common voltage Vc. That is, the trapezoidal waveforms Adp, Bdp, and Cdp are signal waveforms that each start and end at voltage Vc.

[0049] In the following description, the amount of ink ejected from the ejection section 600 corresponding to a piezoelectric element 60 when the trapezoidal waveform Adp is supplied to one end of the piezoelectric element 60 may be referred to as a large amount, and the amount of ink ejected from the ejection section 600 corresponding to the piezoelectric element 60 when the trapezoidal waveform Bdp is supplied to one end of the piezoelectric element 60 may be referred to as a small amount, which is different from the large amount. Also, the operation of vibrating the ink near the nozzle opening to such an extent that ink is not ejected from the ejection section 600 corresponding to the piezoelectric element 60 when the trapezoidal waveform Cdp is supplied to one end of the piezoelectric element 60 may be referred to as micro-vibration BSD.

[0050] That is, in the liquid ejection device 1 of this embodiment, the drive circuit 52a outputs a drive signal COMA that drives the piezoelectric element 60 so that the ejection section 600 of the print head 23 ejects a predetermined amount of ink, which is a large amount; the drive circuit 52b outputs a drive signal COMB that drives the piezoelectric element 60 so that the ejection section 600 of the print head 23 ejects a small amount of ink, which is less than the predetermined amount; and the drive circuit 52c outputs a drive signal COMC that drives the piezoelectric element 60 so that the ejection section 600 of the print head 23 does not eject ink.

[0051] 3, various signal waveforms may be used depending on the type of ink ejected from the ejection unit 600, the number of piezoelectric elements 60 driven by the drive signals COMA, COMB, COMC, the length of the wiring through which the drive signals COMA, COMB, COMC are transmitted, and the like. Therefore, the drive signals COMA1 to COMA6 may each have a signal waveform of a different shape, and the amount of ink ejected from the corresponding ejection unit 600 by the drive signal COMA1 may be different from the amount of ink ejected from the corresponding ejection unit 600 by the drive signal COMAi. Similarly, the drive signals COMB1 to COMB6 may each have a signal waveform of a different shape, and the amount of ink ejected from the corresponding ejection unit 600 by the drive signal COMB1 may be different from the amount of ink ejected from the corresponding ejection unit 600 by the drive signal COMBi. Similarly, the drive signals COMC1 to COMC6 may have signal waveforms with different shapes, and the amount of displacement of the piezoelectric element 60 caused by the drive signal COMC1 may differ from the amount of displacement of the piezoelectric element 60 caused by the drive signal COMCi.

[0052] Next, the configuration and operation of the drive signal selection circuit 200 that outputs the drive signal VOUT by selecting or deselecting each of the drive signals COMA, COMB, and COMC will be described. Fig. 4 is a diagram showing the functional configuration of the drive signal selection circuit 200. As shown in Fig. 4, the drive signal selection circuit 200 includes a selection control circuit 210 and a plurality of selection circuits 230.

[0053] A print data signal SI, a latch signal LAT, and a clock signal SCK are input to the selection control circuit 210. The selection control circuit 210 also has n sets of shift registers (S / R) 212, latch circuits 214, and decoders 216, each corresponding to one of the n ejection units 600. That is, the drive signal selection circuit 200 includes n shift registers 212, n latch circuits 214, and n decoders 216, the same number as the n ejection units 600.

[0054] The print data signal SI is a signal synchronized with the clock signal SCK, and includes 2-bit print data [SIH, SIL] for specifying the dot size formed by ink ejected from each of the n ejection units 600 as one of "large dot LD," "small dot SD," "non-ejection ND," and "slight vibration BSD." This print data signal SI is held in the shift register 212 corresponding to the ejection unit 600 for each 2-bit print data [SIH, SIL].

[0055] Specifically, the n shift registers 212 corresponding to the ejection units 600 are cascaded together. The 2-bit print data [SIH, SIL] included in the print data signal SI is sequentially transferred to the subsequent stages of the cascaded shift registers 212 in accordance with the clock signal SCK. When the supply of the clock signal SCK stops, the n shift registers 212 hold the 2-bit print data [SIH, SIL] corresponding to the ejection unit 600 corresponding to that shift register 212. Note that in FIG. 4, in order to distinguish the n cascaded shift registers 212, they are illustrated as 1st stage, 2nd stage, ..., nth stage from the upstream side where the print data signal SI is input to the downstream side.

[0056] Each of the n latch circuits 214 simultaneously latches the 2-bit print data [SIH, SIL] held in the corresponding shift register 212 at the rising edge of the latch signal LAT.

[0057] The 2-bit print data [SIH, SIL] latched by the latch circuit 214 is input to the corresponding decoder 216. Each of the n decoders 216 decodes the input 2-bit print data [SIH, SIL] and outputs selection signals S1, S2, and S3 at logic levels corresponding to the decoded data every period T. FIG. 5 shows an example of the decoded data in the decoder 216. The decoder 216 generates signals with logic levels determined by the input 2-bit print data [SIH, SIL] and the decoded data shown in FIG. 5, and outputs the generated selection signals S1, S2, and S3 by level-shifting the logic levels of the generated signals to high-amplitude logic levels according to the voltage value of the voltage signal VHV. For example, if the 2-bit print data [SIH, SIL] input to the decoder 216 is [1, 0], the decoder 216 sets the logic levels of the selection signals S1, S2, and S3 to L, H, and L levels, respectively, during period T.

[0058] Returning to FIG. 4 , a selection circuit 230 is provided corresponding to each of the n discharge units 600. That is, the drive signal selection circuit 200 has n selection circuits 230. The selection circuits 230 receive selection signals S1, S2, S3 and drive signals COMA, COMB, COMC output by the decoder 216 corresponding to the same discharge unit 600. The selection circuits 230 select or deselect each of the drive signals COMA, COMB, COMC based on the selection signals S1, S2, S3 to generate a drive signal VOUT and output it to the corresponding discharge unit 600.

[0059] Fig. 6 is a diagram showing an example of the configuration of the selection circuit 230 corresponding to one discharge section 600. As shown in Fig. 6, the selection circuit 230 has inverters 232a, 232b, and 232c, and transfer gates 234a, 234b, and 234c.

[0060] The selection signal S1 is input to the positive control terminal (not marked with a circle) of the transfer gate 234a, and is also logically inverted by the inverter 232a and input to the negative control terminal (marked with a circle) of the transfer gate 234a. The drive signal COMA is input to the input terminal of the transfer gate 234a. When the input selection signal S1 is at H level, the transfer gate 234a establishes conduction between the input terminal and the output terminal, and when the input selection signal S1 is at L level, the transfer gate 234a establishes non-conduction between the input terminal and the output terminal. In other words, when the selection signal S1 is at H level, the transfer gate 234a outputs the drive signal COMA to the output terminal, and when the selection signal S1 is at L level, the transfer gate 234a does not output the drive signal COMA to the output terminal.

[0061] The selection signal S2 is input to a positive control terminal (not marked with a circle) of the transfer gate 234b, and is also logically inverted by the inverter 232b and input to a negative control terminal (marked with a circle) of the transfer gate 234b. The drive signal COMB is input to the input terminal of the transfer gate 234b. When the input selection signal S2 is at a high level, the transfer gate 234b establishes electrical continuity between its input terminal and output terminal, and when the input selection signal S2 is at a low level, the transfer gate 234b establishes electrical continuity between its input terminal and output terminal. That is, when the selection signal S2 is at a high level, the transfer gate 234b outputs the drive signal COMB to the output terminal, and when the selection signal S2 is at a low level, the transfer gate 234b does not output the drive signal COMB to the output terminal.

[0062] The selection signal S3 is input to the positive control terminal (not marked with a circle) of the transfer gate 234c, and is also logically inverted by the inverter 232c and input to the negative control terminal (marked with a circle) of the transfer gate 234c. The drive signal COMC is input to the input terminal of the transfer gate 234c. When the input selection signal S3 is at H level, the transfer gate 234c establishes conduction between the input terminal and the output terminal, and when the input selection signal S3 is at L level, the transfer gate 234c establishes non-conduction between the input terminal and the output terminal. In other words, when the selection signal S3 is at H level, the transfer gate 234c outputs the drive signal COMC to the output terminal, and when the selection signal S3 is at L level, the transfer gate 234c does not output the drive signal COMC to the output terminal.

[0063] In the selection circuit 230, the output terminals of the transfer gates 234a, 234b, and 234c are commonly connected. That is, the drive signals COMA, COMB, and COMC selected or not selected by the selection signals S1, S2, and S3 are output from the output terminals of the commonly connected transfer gates 234a, 234b, and 234c. The drive signal selection circuit 200 then supplies the signals from the output terminals of the transfer gates 234a, 234b, and 234c as drive signals VOUT to the piezoelectric elements 60 of the corresponding ejection units 600.

[0064] The operation of the drive signal selection circuit 200 configured as described above will now be described. FIG. 7 is a diagram illustrating the operation of the drive signal selection circuit 200. The print data signal SI is a signal that includes 2-bit print data [SIH, SIL] serially, and is input to the drive signal selection circuit 200 in synchronization with the clock signal SCK. The 2-bit print data [SIH, SIL] included in the print data signal SI is then sequentially transferred to the subsequent shift register 212 in synchronization with the clock signal SCK. Thereafter, when the input of the clock signal SCK stops, the 2-bit print data [SIH, SIL] corresponding to each of the ejection units 600 is held in the shift register 212 corresponding to the same ejection unit 600.

[0065] Thereafter, when the latch signal LAT rises, the latch circuit 214 simultaneously latches the 2-bit print data [SIH, SIL] held in the shift register 212. Note that in Fig. 7, the 2-bit print data [SIH, SIL] latched by the latch circuit 214 and corresponding to the 1st, 2nd, ..., nth stages of the shift register 212 are illustrated as LT1, LT2, ..., LTn.

[0066] The 2-bit print data [SIH, SIL] latched by the latch circuit 214 is input to the decoder 216. The decoder 216 outputs selection signals S1, S2, and S3 at logic levels corresponding to the dot size defined by the input 2-bit print data [SIH, SIL].

[0067] Specifically, when the input 2-bit print data [SIH, SIL] is [1, 1], the decoder 216 outputs the logic levels of the selection signals S1, S2, and S3 as H, L, and L levels to the selection circuit 230 during the period T. As a result, the selection circuit 230 selects the trapezoidal waveform Adp during the period T. This causes the drive signal selection circuit 200 to output the drive signal VOUT corresponding to the "large dot LD" shown in FIG.

[0068] Furthermore, when the input 2-bit print data [SIH, SIL] is [1, 0], the decoder 216 outputs the logic levels of the selection signals S1, S2, and S3 as L, H, and L levels to the selection circuit 230 during the period T. As a result, the selection circuit 230 selects the trapezoidal waveform Bdp during the period T. This causes the drive signal selection circuit 200 to output a drive signal VOUT corresponding to the "small dot SD" shown in FIG.

[0069] Furthermore, when the input 2-bit print data [SIH, SIL] is [0, 1], the decoder 216 outputs the logic levels of the selection signals S1, S2, and S3 as L, L, L levels to the selection circuit 230 during the period T. As a result, the selection circuit 230 does not select any of the trapezoidal waveforms Adp, Bdp, and Cdp during the period T. This causes the drive signal selection circuit 200 to output a drive signal VOUT corresponding to "non-ejection ND" shown in FIG.

[0070] Here, when the selection circuit 230 does not select any of the trapezoidal waveforms Adp, Bdp, and Cdp, the voltage Vc that was previously supplied to the corresponding piezoelectric element 60 is held at one end of the piezoelectric element 60 by the capacitive component of the piezoelectric element 60. In other words, when the drive signal selection circuit 200 outputs a constant drive signal VOUT at voltage Vc, this includes the case where the previous voltage Vc held by the capacitive component of the piezoelectric element 60 is supplied to the piezoelectric element 60 as the drive signal VOUT when none of the trapezoidal waveforms Adp, Bdp, and Cdp is selected as the drive signal VOUT.

[0071] Furthermore, when the input 2-bit print data [SIH, SIL] is [0, 0], the decoder 216 outputs the logic levels of the selection signals S1, S2, and S3 as L, L, and H levels to the selection circuit 230 during the period T. As a result, the selection circuit 230 selects the trapezoidal waveform Cdp during the period T. This causes the drive signal selection circuit 200 to output a drive signal VOUT corresponding to the "micro vibration BSD" shown in FIG.

[0072] As described above, the drive signal selection circuit 200 selects or deselects the drive signals COMA, COMB, and COMC based on the voltage signal VHV, the print data signal SI, the latch signal LAT, and the clock signal SCK, thereby generating drive signals VOUT corresponding to each of the multiple ejection units 600 and outputting them to the corresponding ejection units 600. This allows the amount of ink ejected from each of the multiple ejection units 600 to be individually controlled.

[0073] Furthermore, in the liquid ejection device 1 of this embodiment, when large dots are formed on the medium P, the drive signal selection circuit 200 supplies the drive signal COMA output by the drive circuit 52a to the ejection unit 600 as the drive signal VOUT. When small dots are formed on the medium P, the drive signal selection circuit 200 supplies the drive signal COMB output by the drive circuit 52b to the ejection unit 600 as the drive signal VOUT. That is, the drive signal selection circuit 200 selects either the drive signal COMA or COMB depending on the size of the dots to be formed on the medium P. Therefore, the waveform cycle of the drive signals COMA and COMB can be shortened compared to a configuration in which one drive signal includes multiple signal waveforms and the size of the dots to be formed on the medium P is determined by selecting the signal waveforms in a time-division manner. As a result, the image formation speed at which the liquid ejection device 1 forms a desired image on the medium P can be increased.

[0074] Furthermore, in the liquid ejection device 1 of this embodiment, in addition to the drive signals COMA and COMB, the drive signal COMC that drives the piezoelectric element 60 so as not to eject ink onto the medium P is included, thereby reducing the risk of ejection abnormalities occurring in the ejection section 600 due to increased ink viscosity, without reducing the image formation speed at which a desired image is formed on the medium P. That is, in the liquid ejection device 1 of this embodiment, by having the drive signal COMC in addition to the drive signals COMA and COMB, it is possible to increase the image formation speed at which a desired image is formed on the medium P without reducing the quality of the image formed on the medium P, and reduce the risk of a decrease in ink ejection accuracy.

[0075] Here, the drive signal VOUT supplied to the piezoelectric element 60 is generated by selecting a signal waveform included in each of the drive signals COMA, COMB, and COMC. That is, when the drive signal selection circuit 200 selects the drive signal COMA, the drive signal COMA is supplied as the drive signal VOUT to the corresponding piezoelectric element 60. When the drive signal selection circuit 200 selects the drive signal COMB, the drive signal COMB is supplied as the drive signal VOUT to the corresponding piezoelectric element 60. When the drive signal selection circuit 200 selects the drive signal COMC, the drive signal COMC is supplied as the drive signal VOUT to the corresponding piezoelectric element 60. That is, the drive circuit 52a outputs the drive signal COMA to be supplied to the piezoelectric element 60, the drive circuit 52b outputs the drive signal COMB to be supplied to the piezoelectric element 60, and the drive circuit 52c outputs the drive signal COMC to be supplied to the piezoelectric element 60.

[0076] 2.3 Drive circuit configuration and operation Next, a description will be given of the configuration and operation of the drive circuit 52 that generates and outputs the drive signal COM. Fig. 8 is a diagram showing an example of the configuration of the drive circuit 52. The drive circuit 52 includes an integrated circuit 500, an amplifier circuit 550, a demodulation circuit 560, and a feedback circuit 570.

[0077] The integrated circuit 500 includes an amplification control signal generation circuit 502, an internal voltage generation circuit 400, an oscillation circuit 410, a clock selection circuit 411, an abnormality detection circuit 430, a register control circuit 440, a drive signal discharge circuit 450, a reference voltage signal output circuit 460, a VHV control signal output circuit 470, a status signal input / output circuit 480, and an abnormality signal input / output circuit 490.

[0078] A voltage signal VDD is supplied to the internal voltage generation circuit 400. The internal voltage generation circuit 400 generates a voltage signal GVDD having a voltage value of, for example, DC 7.5 V by boosting or lowering the input voltage signal VDD. This voltage signal GVDD is input to various components of the integrated circuit 500, including a gate driver 540, which will be described later. Note that the integrated circuit 500 may use the input voltage signal VDD at its original voltage value without boosting or lowering it.

[0079] A master drive data signal dO is input to the amplification control signal generation circuit 502 via a terminal dO_i. The amplification control signal generation circuit 502 generates amplification control signals Hgd and Lgd based on the input master drive data signal dO. The amplification control signal generation circuit 502 includes a DAC interface (DAC_I / F: Digital to Analog Converter Interface) 510, a DAC unit 520, a modulation unit 530, and a gate driver 540.

[0080] The DAC interface 510 receives a master drive data signal dO via a terminal dO_i and a clock signal MCK via a terminal MCK-i. The clock signal MCK may be generated by an oscillator circuit (not shown) included in the drive unit 10 or the control unit 2. The DAC interface 510 integrates the master drive data signal dO based on the clock signal MCK to generate, for example, 10-bit drive waveform data dW that defines the waveform of the drive signal COM. The drive waveform data dW is input to the DAC section 520. The DAC section 520 converts the input drive waveform data dW into an analog drive waveform signal aW. This drive waveform signal aW is a target signal for the drive signal COM before amplification. The drive waveform signal aW is input to the modulation section 530. The modulation section 530 generates and outputs a modulated signal Ms by pulse-width modulating the drive waveform signal aW. In other words, the modulation unit 530 outputs a modulation signal Ms obtained by modulating the drive waveform signal aW. The gate driver 540 receives the voltage signals VHV and GVDD and the modulation signal Ms. The gate driver 540 amplifies the input modulation signal Ms based on the voltage signal GVDD, and generates an amplification control signal Hgd level-shifted to a high-amplitude logic level based on the voltage signal VHV, and an amplification control signal Lgd inverted from the input modulation signal Ms and amplified based on the voltage signal GVDD. That is, the logic levels of the amplification control signal Hgd and the amplification control signal Lgd are exclusively H level.

[0081] Here, the logic levels being exclusively H level means that the logic levels of the amplification control signal Hgd and the amplification control signal Lgd are not H level at the same time, and does not include the case where the logic levels of the amplification control signal Hgd and the amplification control signal Lgd are L level at the same time. Therefore, the gate driver 540 may include a timing control circuit or the like that controls the timing so that the logic levels of the amplification control signal Hgd and the amplification control signal Lgd are not H level at the same time.

[0082] The amplification control signal Hgd is output from the integrated circuit 500 via the terminal Hg_o and input to the amplifier circuit 550. The amplification control signal Lgd is output from the integrated circuit 500 via the terminal Lg_o and input to the amplifier circuit 550. Here, the amplification control signal Hgd is a signal obtained by level-shifting the logical level of the modulation signal Ms, and the amplification control signal Lgd is a signal obtained by inverting the logical level of the modulation signal Ms. Therefore, in a broad sense, the amplification control signals Hgd and Lgd can also be considered as modulation signals generated by the modulation section 530.

[0083] The amplifier circuit 550 operates based on the amplification control signals Hgd and Lgd to output the amplified modulated signal AMs. In other words, the amplifier circuit 550 amplifies the modulated signal Ms and outputs the amplified modulated signal AMs.

[0084] Specifically, the amplifier circuit 550 includes transistors 551 and 552. Each of the transistors 551 and 552 is, for example, an N-channel field effect transistor (FET). A voltage signal VHV is supplied to the drain terminal of the transistor 551. An amplification control signal Hgd is supplied to the gate terminal of the transistor 551 via a terminal Hg_o. A source terminal of the transistor 551 is electrically connected to a drain terminal of the transistor 552. An amplification control signal Lgd is supplied to the gate terminal of the transistor 552 via a terminal Lg_o. A ground signal is supplied to the source terminal of the transistor 552. In the amplifier circuit 550 configured as described above, the transistor 551 operates in response to the amplification control signal Hgd, and the transistor 552 operates in response to the amplification control signal Lgd. At this time, the transistors 551 and 552 are turned on exclusively. Then, by driving the transistors 551 and 552, an amplified modulation signal AMs obtained by amplifying the modulation signal Ms based on the voltage signal VHV is generated at a connection point where the source terminal of the transistor 551 and the drain terminal of the transistor 552 are connected. The amplifier circuit 550 outputs the generated amplified modulation signal AMs to the connection point.

[0085] The amplified modulated signal AMs output by the amplifier circuit 550 is input to the demodulation circuit 560. The demodulation circuit 560 includes a coil 561 and a capacitor 562. One end of the coil 561 is electrically connected to the source terminal of the transistor 551 and the drain terminal of the transistor 552. The other end of the coil 561 is electrically connected to one end of the capacitor 562. A ground signal is supplied to the other end of the capacitor 562. In other words, the coil 561 and the capacitor 562 form a low-pass filter. The demodulation circuit 560 smoothes and demodulates the amplified modulated signal AMs supplied by the low-pass filter to generate the drive signal COM. The drive signal COM generated by the demodulation circuit 560 is output from the drive circuit 52 via the terminal COM-Out. In other words, the amplifier circuit 550 and the demodulation circuit 560 operate under the control of the integrated circuit 500 to output the drive signal COM corresponding to the voltage signal VHV.

[0086] The drive signal COM output from the demodulation circuit 560 is fed back to the modulation unit 530 via a feedback circuit 570. The feedback circuit 570 includes resistors 571 and 572. One end of the resistor 571 is electrically connected to the other end of the coil 561, and the other end of the resistor 571 is electrically connected to one end of the resistor 572. A voltage signal VHV is supplied to the other end of the resistor 572. The other end of the resistor 571 and one end of the resistor 572 are electrically connected to the modulation unit 530 via terminals Com-Dis. That is, a signal based on the drive signal COM is fed back to the modulation unit 530. This improves the waveform accuracy of the signal waveform of the drive signal COM output from the demodulation circuit 560. Note that the feedback circuit 570 may have a feedback path that extracts a specific frequency component from the drive signal COM and feeds the extracted signal back to the modulation unit 530, in addition to the configuration including the resistors 571 and 572 described above.

[0087] As described above, the amplified control signal generating circuit 502, amplifier circuit 550, demodulation circuit 560, and feedback circuit 570 generate and output the drive signal COM that drives the piezoelectric element 60 based on the basic drive data signal dO. In the following description, the amplified control signal generating circuit 502, amplifier circuit 550, demodulation circuit 560, and feedback circuit 570 that output the drive signal COM that drives the piezoelectric element 60 based on the basic drive data signal dO may be referred to as the drive signal generating circuit 501. The drive signal COM generated by the drive signal generating circuit 501 is supplied to the piezoelectric element 60 via the terminal COM-Out. The drive signal generating circuit 501 configured as described above can output a drive signal COM whose voltage value changes, such as the trapezoidal waveforms Adp, Bdp, and Cdp shown in FIG. 3, as well as a signal whose voltage value is constant when the basic drive data signal dO corresponding to a constant voltage value is supplied.

[0088] That is, the drive circuit 52 has an amplifier circuit 550 and a demodulation circuit 560 that receive a voltage signal VHV and output a drive signal COM corresponding to the voltage signal VHV, and an integrated circuit 500 that receives a voltage signal VDD and controls the driving of the amplifier circuit 550 in accordance with the voltage signal VDD. The drive circuit 52 outputs the drive signal COM by amplifying, based on the voltage signal VHV, a drive waveform signal aW that corresponds to a basic drive data signal dO on which the drive signal COM is based.

[0089] The oscillation circuit 410 generates and outputs a clock signal LCK that defines the operation timing of the integrated circuit 500. The clock signal LCK is input to a clock selection circuit 411 and an abnormality detection circuit 430.

[0090] The clock selection circuit 411 receives the clock signals MCK, LCK, and a clock selection signal CSW. Based on the logic level of the clock selection signal CSW, the clock selection circuit 411 switches between outputting the clock signal MCK as the clock signal RCK to the register control circuit 440 or outputting the clock signal LCK as the clock signal RCK to the register control circuit 440. For example, when the input clock selection signal CSW is at an H level, the clock selection circuit 411 outputs the clock signal MCK as the clock signal RCK to the register control circuit 440, and when the input clock selection signal CSW is at an L level, the clock selection circuit 411 outputs the clock signal LCK as the clock signal RCK to the register control circuit 440.

[0091] The abnormality detection circuit 430 includes an oscillation abnormality detection unit 431 , an operation abnormality detection unit 432 , and a power supply voltage abnormality detection unit 433 .

[0092] The clock signal LCK output by the oscillation circuit 410 is input to the oscillation abnormality detection unit 431. The oscillation abnormality detection unit 431 acquires the frequency, voltage value, etc. of the input clock signal LCK and detects whether the clock signal LCK is normal from the acquired information. If the oscillation abnormality detection unit 431 detects an abnormality in the input clock signal LCK, it generates a clock selection signal CSW indicating the abnormality and outputs it to the clock selection circuit 411, and also generates an error signal NES indicating the abnormality and outputs it to the register control circuit 440. If the oscillation abnormality detection unit 431 does not detect an abnormality in the input clock signal LCK, it generates a clock selection signal CSW indicating normality and outputs it to the clock selection circuit 411, and also generates an error signal NES indicating normality and outputs it to the register control circuit 440.

[0093] An operation status signal ASS indicating the operation status of the various components included in the drive circuit 52 is input to the operation abnormality detection unit 432. Based on the input operation status signal ASS, the operation abnormality detection unit 432 detects whether the various components of the drive circuit 52 are operating normally. When an operation status signal ASS indicating that an abnormality has occurred in any of the various components of the drive circuit 52 is input, the operation abnormality detection unit 432 generates an error signal NES indicating the abnormality and outputs it to the register control circuit 440.

[0094] The voltage signal VHV is input to the power supply voltage abnormality detection unit 433. The power supply voltage abnormality detection unit 433 detects whether the voltage value of the input voltage signal VHV is normal. If the detected voltage value of the voltage signal VHV is abnormal, the power supply voltage abnormality detection unit 433 generates an error signal FES indicating the abnormality and outputs it to the register control circuit 440.

[0095] The register control circuit 440 includes a sequence register 441, a status register 442, and a register control unit 443. The sequence register 441 and the status register 442 hold operation information and the like that is input as a master drive data signal dO in synchronization with the clock signal MCK. The register control unit 443 generates control signals CNT1 to CNT5 based on the information held in the sequence register 441 and the status register 442 in synchronization with the clock signal RCK. Then, the register control circuit 440 outputs the control signals CNT1 to CNT5 generated by the register control unit 443 to the corresponding components.

[0096] The control signal CNT1 output by the register control circuit 440 is input to the drive signal discharge circuit 450. The drive signal discharge circuit 450 is electrically connected to the terminal COM-Out via the terminal Com-Dis and the feedback circuit 570. This drive signal discharge circuit 450 controls the release of residual charge accumulated in the propagation path of the drive signal COM.

[0097] FIG. 9 is a diagram illustrating an example of the configuration of a drive signal discharge circuit 450. The drive signal discharge circuit 450 includes a resistor 451, a transistor 452, and an inverter 453. Note that the description will be given assuming that the transistor 452 is an NMOS transistor. One end of the resistor 451 is electrically connected to a terminal Com-Dis. The other end of the resistor 451 is electrically connected to a drain terminal of the transistor 452. A ground signal is supplied to the source terminal of the transistor 452. A control signal CNT1 is input to the gate terminal of the transistor 452 via an inverter 453. The drive signal discharge circuit 450 configured as described above discharges residual charge accumulated in the propagation path of the drive signal COM when an L-level control signal CNT1 is input. Specifically, when an L-level control signal CNT1 is input to the drive signal discharge circuit 450, the transistor 452 is controlled to be on. As a result, the terminal Com-Out is electrically connected to the propagation path through which the ground signal propagates via the resistor 571, the terminal Com-Dis, the resistor 451, and the transistor 542. As a result, residual charge accumulated in the propagation path of the drive signal COM, including the terminal COM-Out, is released.

[0098] The control signal CNT2 output by the register control circuit 440 is input to a reference voltage signal output circuit 460. The reference voltage signal output circuit 460 is electrically connected to the piezoelectric element 60 via a terminal VBS_o and a terminal VBS-Out. The reference voltage signal output circuit 460 generates and outputs a reference voltage signal VBS to be supplied to the piezoelectric element 60 in response to the control signal CNT2.

[0099] FIG. 10 is a diagram illustrating an example of the configuration of a reference voltage signal output circuit 460. The reference voltage signal output circuit 460 includes a comparator 461, transistors 462 and 463, resistors 464, 465, and 466, and an inverter 467. Note that the transistor 462 is a PMOS transistor, and the transistor 463 is an NMOS transistor. A reference voltage Vref is supplied to the negative input terminal of the comparator 461. The reference voltage Vref may be, for example, a bandgap reference voltage of the integrated circuit 500. The positive input terminal of the comparator 461 is electrically connected to one end of the resistor 464 and one end of the resistor 465. The output terminal of the comparator 461 is electrically connected to the gate terminal of the transistor 462. A voltage signal GVDD is supplied to the source terminal of the transistor 462. The drain terminal of the transistor 462 is electrically connected to the other end of the resistor 464, one end of the resistor 466, and a terminal VBS_o from which a reference voltage signal VBS is output. The other end of the resistor 466 is electrically connected to the drain terminal of the transistor 463. A control signal CNT2 is input to the gate terminal of the transistor 463 via an inverter 467. A ground signal is supplied to the source terminal of the transistor 463 and the other end of the resistor 465.

[0100] In the reference voltage signal output circuit 460 configured as described above, when the voltage value supplied to the positive input terminal of the comparator 461 is greater than the voltage value of the reference voltage Vref supplied to the negative input terminal of the comparator 461, the comparator 461 outputs an H-level signal. This controls the transistor 462 to be OFF, and the voltage signal GVDD is not supplied to the terminal VBS_o. On the other hand, when the voltage value supplied to the positive input terminal of the comparator 461 is smaller than the voltage value of the reference voltage Vref supplied to the negative input terminal of the comparator 461, the comparator 461 outputs an L-level signal. This controls the transistor 462 to be ON, and the voltage signal GVDD is supplied to the terminal VBS_o. That is, in the reference voltage signal output circuit 460, the comparator 461 controls the conduction state of the transistor 462 so that the voltage value obtained by dividing the voltage value of the terminal VBS_o by the resistors 464 and 465 becomes equal to the voltage value of the reference voltage Vref. As a result, the reference voltage signal output circuit 460 generates a signal with a constant voltage value based on the voltage signal GVDD. This signal with a constant voltage value generated by the reference voltage signal output circuit 460 is output as the reference voltage signal VBS. The reference voltage signal VBS output by the reference voltage signal output circuit 460 is then supplied to the piezoelectric element 60 via terminals VBS_o and VBS_Out.

[0101] Furthermore, a control signal CNT2 is input to the reference voltage signal output circuit 460. When the control signal CNT2 of H level is input to the reference voltage signal output circuit 460, the transistor 463 is controlled to be turned off. As a result, a high impedance is established between the terminal VBS_o and the propagation path through which the ground signal is propagated. Therefore, the reference voltage signal VBS generated by the reference voltage signal output circuit 460 is output via the terminal VBS_o. On the other hand, when the control signal CNT2 of L level is input to the reference voltage signal output circuit 460, the transistor 463 is controlled to be turned on. As a result, the terminal VBS_o is electrically connected to the propagation path through which the ground signal is propagated via the resistor 576 and the transistor 463. Therefore, the reference voltage signal VBS generated by the reference voltage signal output circuit 460 is not output, and the potential of the terminal VBS_o becomes the ground signal. That is, when an L-level control signal CNT2 is input to the reference voltage signal output circuit 460, the reference voltage signal output circuit 460 stops outputting the reference voltage signal VBS to the piezoelectric element 60 and releases the charge stored in the terminal VBS_o.

[0102] The control signal CNT3 output by the register control circuit 440 is input to a VHV control signal output circuit 470. The VHV control signal output circuit 470 is electrically connected to the step-down circuit 130 via a terminal VHVc_o and a terminal VHVc-Out. The VHV control signal output circuit 470 controls the operation of the step-down circuit 130 by outputting to the step-down circuit 130 a step-down control signal VHVc whose logic level changes in response to the control signal CNT3.

[0103] FIG. 11 is a diagram illustrating an example of the configuration of a VHV control signal output circuit 470. The VHV control signal output circuit 470 includes a transistor 471 and a resistor 472. Note that the following description will be given assuming that the transistor 471 is a PMOS transistor. A voltage signal GVDD is supplied to the source terminal of the transistor 471. A drain terminal of the transistor 471 is electrically connected to one end of the resistor 472 and the terminal VHVc_o. A control signal CNT3 is input to the gate terminal of the transistor 471. A ground signal is supplied to the other end of the resistor 472. When an L-level control signal CNT3 is input to the VHV control signal output circuit 470 configured as described above, the VHV control signal output circuit 470 supplies a voltage signal GVDD to the terminal VHVc_o. In other words, the VHV control signal output circuit 470 outputs a step-down control signal VHVc of the voltage signal GVDD. Furthermore, when an H-level control signal CNT3 is input to the VHV control signal output circuit 470, the VHV control signal output circuit 470 supplies a ground signal to the terminal VHVc_o. In other words, the VHV control signal output circuit 470 outputs a step-down control signal VHVc that is a ground signal. That is, the VHV control signal output circuit 470 generates a step-down control signal VHVc whose H-level is the voltage value of the voltage signal GVDD and whose L-level is the ground signal in accordance with the logical level of the control signal CNT3, and outputs the step-down control signal VHVc to the step-down circuit 130.

[0104] The control signal CNT4 output by the register control circuit 440 is input to a status signal input / output circuit 480. The status signal input / output circuit 480 is electrically connected to other components via a terminal BUSY_io. This status signal input / output circuit 480 outputs a status signal BUSY whose logic level changes in response to the control signal CNT4, thereby notifying the other components of the operating state of the drive circuit 52 and acquiring the status signal BUSY output by the other components. Here, the other components may be, for example, any of the drive signal output circuits 50-1 to 52-6 included in the liquid ejection device 1, or may be the control circuit 100.

[0105] FIG. 12 is a diagram showing the configuration of the status signal input / output circuit 480. The status signal input / output circuit 480 includes a transistor 481, an inverter 482, and a resistor 483. Note that the description will be given assuming that the transistor 481 is a PMOS transistor. The inverter 482 functions as a CMOS input terminal of the integrated circuit 500. That is, the status signal input / output circuit 480 generates a status signal BUSY based on the control signal CNT4 output from the register control circuit 440 and outputs it to other components via a terminal BUSY_io, while outputting a signal input via a terminal BUSY-io to the register control circuit 440. Note that in FIG. 12, the control signal CNT4 output from the register control circuit 440 is illustrated as a control signal CNT4-out, and the control signal CNT4 output to the register control circuit 440 is illustrated as a control signal CNT4-in.

[0106] A voltage signal GVDD is supplied to the source terminal of the transistor 481. The drain terminal of the transistor 481 is electrically connected to the input terminal of the inverter 482, one terminal of the resistor 483, and the terminal BUSY_io. A control signal CNT4-out output from the register control circuit 440 is input to the gate terminal of the transistor 481. A control signal CNT4-in is output from the output terminal of the inverter 482 to the register control circuit 440. A ground signal is supplied to the other terminal of the resistor 483. When an L-level control signal CNT4 is input to the status signal input / output circuit 480 configured as described above, the status signal input / output circuit 480 supplies a voltage signal GVDD to the terminal BUSY_io. In other words, the status signal input / output circuit 480 outputs a status signal BUSY of the voltage signal GVDD. On the other hand, when an H-level control signal CNT4 is input to the status signal input / output circuit 480, the status signal input / output circuit 480 supplies a ground signal to the terminal BUSY_io. In other words, the status signal input / output circuit 480 outputs the status signal BUSY, which is a ground signal. That is, the status signal input / output circuit 480 generates the status signal BUSY, whose H level is the voltage value of the voltage signal GVDD and whose L level is the ground signal, in accordance with the logic level of the control signal CNT4, and outputs it to other components.

[0107] The control signal CNT5 output by the register control circuit 440 is input to the abnormality signal input / output circuit 490. The abnormality signal input / output circuit 490 is electrically connected to other components via a terminal ERR_io. This abnormality signal input / output circuit 490 outputs an abnormality signal ERR whose logic level changes in response to the control signal CNT5, thereby notifying the other components whether or not an abnormality has occurred in the drive circuit 52, and also acquiring the abnormality signal ERR output from the other components. Here, the other components may be, for example, any of the drive signal output circuits 50-1 to 50-6 included in the liquid ejection device 1, or may be the control circuit 100.

[0108] FIG. 13 is a diagram illustrating the configuration of the abnormality signal input / output circuit 490. The abnormality signal input / output circuit 490 includes a transistor 491, an inverter 492, and a resistor 493. In the following description, the transistor 491 will be described as a PMOS transistor. The inverter 492 functions as a CMOS input terminal of the integrated circuit 500. That is, the abnormality signal input / output circuit 490 generates an abnormality signal ERR based on the control signal CNT5 output from the register control circuit 440 and outputs it via the terminal ERR-io. It also outputs a signal input via the terminal ERR_io to the register control circuit 440. In FIG. 13, the control signal CNT5 output from the register control circuit 440 is illustrated as the control signal CNT5-out, and the control signal CNT5 output to the register control circuit 440 is illustrated as the control signal CNT5-in.

[0109] A voltage signal GVDD is supplied to the source terminal of the transistor 491. The drain terminal of the transistor 491 is electrically connected to the input terminal of the inverter 492, one terminal of the resistor 493, and the terminal ERR-io. A control signal CNT5-out output from the register control circuit 440 is input to the gate terminal of the transistor 491. A control signal CNT5-in is output from the output terminal of the inverter 492 to the register control circuit 440. A ground signal is supplied to the other terminal of the resistor 493. When a low-level control signal CNT5 is input to the abnormality signal input / output circuit 490 configured as described above, the abnormality signal input / output circuit 490 supplies a voltage signal GVDD to the terminal ERR-io. In other words, the abnormality signal input / output circuit 490 outputs an abnormality signal ERR of the voltage signal GVDD. On the other hand, when a high-level control signal CNT5 is input to the abnormality signal input / output circuit 490, the abnormality signal input / output circuit 490 supplies a ground signal to the terminal ERR_io. In other words, the abnormality signal input / output circuit 490 outputs the abnormality signal ERR of the ground signal. That is, the abnormality signal input / output circuit 490 generates the abnormality signal ERR whose H level is the voltage value of the voltage signal GVDD and whose L level is the ground signal in accordance with the logic level of the control signal CNT5, and outputs it to other components.

[0110] As described above, the drive unit 10 of this embodiment has the drive circuit 52 that outputs the drive signal COM, and the reference voltage signal output circuit 460 that outputs the reference voltage signal VBS. Specifically, the drive circuit 52 of this embodiment has a drive signal generation circuit 501 that generates a drive signal COM that drives the piezoelectric element 60 based on the basic drive data signal dO, a drive signal discharge circuit 450 that discharges residual charge remaining in the propagation path of the drive signal COM, a reference voltage signal output circuit 460 that outputs a reference voltage signal VBS and discharges residual charge remaining in the propagation path of the reference voltage signal VBS, a VHV control signal output circuit 470 that controls the operation of the step-down circuit 130, a status signal input / output circuit 480 and an abnormality signal input / output circuit 490 that propagate status and the presence or absence of an abnormality between other components, and a register control circuit 440 that controls the operation of the drive signal discharge circuit 450, the reference voltage signal output circuit 460, the VHV control signal output circuit 470, the status signal input / output circuit 480, and the abnormality signal input / output circuit 490 by switching the logical levels of the control signals CNT1 to CN5.

[0111] In the drive circuit 52 of this embodiment, the register control circuit 440 controls the operation of the drive signal discharge circuit 450, the reference voltage signal output circuit 460, and the VHV control signal output circuit 470 using the control signals CNT1 to CN3, thereby controlling the supply of the voltage signal VHV, the drive signal COM, and the reference voltage signal VBS to the print head 23 without going through the control circuit 100. This reduces the processing load on the control circuit 100, and because the control circuit 100 is not used, the supply of the voltage signal VHV, the drive signal COM, and the reference voltage signal VBS to the print head 23 can be controlled at appropriate timing and in a short time.

[0112] For example, when the liquid ejector 1 is in a standby mode or sleep mode in which it stops operating without ejecting ink onto the medium P, the register control circuit 440 controls the logic levels of the control signals CNT1 to CNT3 so that the drive signal discharge circuit 450 discharges residual charge accumulated in the propagation path of the drive signal COM, including the terminal COM-Out, the reference voltage signal output circuit 460 stops outputting the reference voltage signal VBS to the piezoelectric element 60, discharges charge accumulated in the terminal VBS_o, and the VHV control signal output circuit 470 stops outputting the voltage signal VHV from the step-down circuit 130. This discharges charge across both ends of the piezoelectric element 60 in the print head 23. Therefore, even if the standby mode or sleep mode in which the liquid ejector 1 stops operating extends for a long period of time, the risk of an unintended voltage being applied to the piezoelectric element 60 in the print head 23 and an unintended continuous displacement being applied to the piezoelectric element 60 in the print head 23 is reduced. As a result, the risk of the driving characteristics of the piezoelectric element 60 changing is reduced, the risk of the ejection accuracy of the ink ejected by driving the piezoelectric element 60 being reduced, and the risk of abnormalities occurring in the piezoelectric element 60 due to unintended displacement applied to the piezoelectric element 60 is also reduced.

[0113] Furthermore, at the timing when the operating mode of the liquid ejector 1 transitions from the above-described standby mode or sleep mode to a drive mode in which ink is ejected onto the medium P, the register control circuit 440 sequentially switches the logic levels of the control signals CNT1 to CNT3 in accordance with a predetermined operating sequence. This allows the operating mode of the liquid ejector 1 to transition smoothly, and also reduces the risk of an unintended voltage being applied to the piezoelectric element 60 of the print head 23, even during a transition of the operating mode.

[0114] Furthermore, in the drive circuit 52 of this embodiment, the register control circuit 440 controls the operation of the status signal input / output circuit 480 and the abnormality signal input / output circuit 490 using the control signals CNT4 to CN5, thereby allowing the operating status and the presence or absence of an abnormality to be shared among the multiple drive circuits 52 included in the liquid ejection device 1 and the head unit 5. As a result, in the drive circuit 52 of this embodiment, when the liquid ejection device 1 and the head unit 5 include multiple drive circuits 52, if an abnormality occurs in one of the multiple drive circuits 52, information about the abnormality can be obtained without going through the control circuit 100. As a result, in the drive circuit 52 of this embodiment, it is possible to execute the stop process of the drive circuit 52 at an appropriate timing and in a short time.

[0115] 2.4 Step-down circuit configuration and operation Next, a description will be given of the configuration and operation of the step-down circuit 130. Fig. 14 is a diagram showing an example of the configuration of the step-down circuit 130. As shown in Fig. 14, the step-down circuit 130 has a VHV supply switching circuit 140, a first step-down circuit 150a, and a second step-down circuit 150b.

[0116] The VHV supply switching circuit 140 receives step-down control signals VHVc1-VHVc6 output by the drive signal output circuits 50-1-50-6, respectively. If all of the step-down control signals VHVc1-VHVc6 input from the drive signal output circuits 50-1-50-6 contain information requesting the output of the voltage signal VHV, the VHV supply switching circuit 140 outputs an enable signal ENvh that enables the output of the voltage signal VHV. If at least one of the step-down control signals VHVc1-VHVc6 input from the drive signal output circuits 50-1-50-6 contains information not requesting the output of the voltage signal VHV, the VHV supply switching circuit 140 outputs an enable signal ENvh that does not enable the output of the voltage signal VHV. Such a VHV supply switching circuit 140 can be configured using a combination of logic circuits such as AND circuits and OR circuits.

[0117] The first step-down circuit 150a receives the voltage signal VDC output by the control unit 2 and the enable signal ENvh output by the VHV supply switching circuit 140. When the enable signal ENvh enabling the output of the voltage signal VHV is input, the first step-down circuit 150a generates a voltage signal VHV obtained by stepping down the voltage value of the voltage signal VDC, and when the enable signal ENvh disabling the output of the voltage signal VHV is input, the first step-down circuit 150a stops generating the voltage signal VHV. That is, the integrated circuit 500 included in the drive circuit 52 outputs a step-down control signal VHVc to control whether or not to output the voltage signal VHV from the first step-down circuit 150a.

[0118] The second step-down circuit 150b receives as input a voltage signal VDC and an enable signal ENvd output by the control unit 2. The enable signal ENvd is a signal that switches whether or not to enable the output of the voltage signal VDD from the second step-down circuit 150b, and is input, for example, from the control unit 2. When the enable signal ENvd that enables the output of the voltage signal VDD is input, the second step-down circuit 150b generates a voltage signal VDD that is a step-down voltage of the voltage signal VDC, and when the enable signal ENvd that disables the output of the voltage signal VDD is input, the second step-down circuit 150b stops generating the voltage signal VDD.

[0119] That is, the step-down circuit 130 of the drive unit 10 has a first step-down circuit 150a that steps down the voltage signal VDC and outputs a voltage signal VHV, and a second step-down circuit 150b that steps down the voltage signal VDC and outputs a voltage signal VDD.

[0120] As described above, the voltage signal VHV is used as a power supply voltage for amplification when the drive circuit 52 generates the drive signal COM, and as a voltage for level-shifting the selection signals S1, S2, and S3 output by the decoder 216 of the drive signal selection circuit 200 to a high-amplitude logic. That is, the voltage signal VHV is mainly used to drive the piezoelectric element 60 when the operating mode of the liquid ejector 1 is a drive mode in which ink is ejected onto the medium P. Whether or not the first step-down voltage circuit 150a outputs such a voltage signal VHV is controlled by the enable signal ENvh corresponding to the step-down control signals VHVc1 to VHVc6 output by the drive signal output circuits 50-1 to 50-6, respectively. This allows the first step-down voltage circuit 150a to output the voltage signal VHV only during the period in which the voltage signal VHV is used, for example, when the operating mode of the liquid ejector 1 is the drive mode. This reduces the power consumption associated with the generation of the voltage signal VHV, reduces the risk of an unintended voltage being applied to the piezoelectric element 60 due to leakage current or the like that may occur with the propagation of the voltage signal VHV, and also reduces the risk of an unintended continuous displacement being applied to the piezoelectric element 60 of the print head 23. As a result, the risk of the drive characteristics of the piezoelectric element 60 changing is reduced, reducing the risk of a decrease in the ejection accuracy of ink ejected by driving the piezoelectric element 60, and also reducing the risk of an abnormality occurring in the piezoelectric element 60 due to an unintended displacement being applied to the piezoelectric element 60.

[0121] On the other hand, the voltage signal VDD, which is a DC voltage signal with a smaller voltage value than the voltage signal VHV, is mainly used as a power supply voltage for the integrated circuit 500 and drive signal selection circuit 200 included in the control circuit 100 and drive circuit 52. The control circuit 100, integrated circuit 500, and drive signal selection circuit 200 must operate regardless of the operating mode of the liquid ejection device 1. Therefore, the second step-down voltage circuit 150b outputs the voltage signal VDD regardless of the operating mode of the liquid ejection device 1. In the step-down circuit 130 of this embodiment, an enable signal ENvd, which is independent of the enable signal ENvh, is input to the second step-down voltage circuit 150b. This allows the second step-down voltage circuit 150b to continuously output the voltage signal VDD regardless of the operating status of the first step-down voltage circuit 150a. The enable signal ENvd input to the second step-down circuit 150b is not limited to being input from the control unit 2, but may be, for example, a signal fixed to a predetermined logic level that enables the output of the voltage signal VDD in the second step-down circuit 150b.

[0122] Here, an example of the configuration of the first step-down voltage circuit 150a and the second step-down voltage circuit 150b will be described. The first step-down voltage circuit 150a and the second step-down voltage circuit 150b have the same configuration, except for the voltage value of the signal they output. Therefore, in the following explanation, only an example of the configuration of the first step-down voltage circuit 150a will be explained, and an explanation of an example of the configuration of the second step-down voltage circuit 150b will be simplified or omitted.

[0123] Fig. 15 is a diagram showing an example of the configuration of the first step-down voltage circuit 150a. Fig. 15 illustrates a step-down switching regulator as an example of the first step-down voltage circuit 150a. As shown in Fig. 15, the first step-down voltage circuit 150a includes an integrated circuit 160a, a coil 152a, capacitors 153a and 156a, and resistors 154a and 155a.

[0124] The integrated circuit 160a has terminals tvdd, tvbt, tvsw, tvfb, tvss, tgnd, and ten that are electrically connected to various circuits included in the first step-down voltage circuit 150a. The integrated circuit 160a operates using a voltage signal VDC input via the terminal tvdd as drive power. When an enable signal ENvh that enables the operation of the first step-down voltage circuit 150a is input to the integrated circuit 160a via the terminal ten, the integrated circuit 160a generates a switching signal VSW and outputs it from the terminal tvsw. The integrated circuit 160a also has a drive circuit 161, a switching circuit 164, and a transistor 167.

[0125] The drive circuit 161 includes a drive control circuit 162 and a level shift circuit 163. An enable signal ENvh and a feedback voltage signal VFB are input to the drive control circuit 162. The drive control circuit 162 outputs a master drive signal BDS whose logic level is inverted according to the voltage value of the input feedback voltage signal VFB during a period when the enable signal ENvh that enables the output of the voltage signal VHV is input. The master drive signal BDS output by the drive control circuit 162 is input to a level shift circuit 163. A boot voltage signal VBT and a switching signal VSW are input to the level shift circuit 163. The level shift circuit 163 shifts the H-level voltage value of the input master drive signal BDS to the voltage value of the boot voltage signal VBT, and also generates and outputs a drive signal HDRV by shifting the L-level voltage value of the input master drive signal BDS to the voltage value of the switching signal VSW. Furthermore, during the period when an enable signal ENvh that enables the output of the voltage signal VHV is input, the drive control circuit 162 outputs a drive signal LDRV whose logic level is inverted according to the voltage value of the input feedback voltage signal VFB.

[0126] The drive signals HDRV and LDRV output by the drive circuit 161 are input to a switching circuit 164. The switching circuit 164 includes transistors 165 and 166, which are n-channel FETs (Field Effect Transistors). The drive signal HDRV output by the drive circuit 161 is supplied to a gate terminal of the transistor 165. The drain terminal of the transistor 165 is electrically connected to the terminal tvdd, and the source terminal is electrically connected to the terminal tvsw. The drive signal LDRV output by the drive circuit 161 is supplied to a gate terminal of the transistor 166. The drain terminal of the transistor 165 is electrically connected to the terminal tvsw, and the source terminal is electrically connected to the terminal tvss. A ground signal is supplied to the terminal tvss.

[0127] As described above, the source terminal of transistor 165 and the drain terminal of transistor 166 are connected to each other, and the connection point between the source terminal of transistor 165 and the drain terminal of transistor 166 is electrically connected to terminal tvsw of integrated circuit 160a. When an H-level drive signal HDRV is supplied to switching circuit 164, the drain terminal and source terminal of transistor 165 become conductive, and when an H-level drive signal LDRV is supplied to switching circuit 164, the drain terminal and source terminal of transistor 166 become conductive. Therefore, when an H-level drive signal HDRV is input to switching circuit 164, switching circuit 164 outputs the voltage signal VDC as the switching signal VSW from terminal tvsw, and when an H-level drive signal LDRV is input, switching circuit 164 outputs the switching signal VSW, which is a ground signal, from terminal tvsw.

[0128] That is, the switching circuit 164 controls the conduction states of the transistors 165 and 166 in accordance with the drive signals HDRV and LDRV output by the drive circuit 161, and outputs the switching signal VSW from a terminal tvsw, which is a connection point between the source terminal of the transistor 165 and the drain terminal of the transistor 166. Here, in the following description, a state in which the drain terminals and source terminals of the transistors 165 and 166 are controlled to be conductive will sometimes be referred to as "on," and a state in which the drain terminals and source terminals of the transistors 165 and 166 are controlled to be non-conductive will sometimes be referred to as "off."

[0129] The drive control circuit 162 also outputs a boost control signal BC whose logic level is inverted at a timing synchronized with at least one of the basic drive signal BDS and the drive signal LDRV. The boost control signal BC is supplied to the gate terminal of a transistor 167. The transistor 167 is a p-channel FET, with its source terminal electrically connected to the terminal tvdd and its drain terminal electrically connected to the terminal tvbt. When a low-level boost control signal BC is supplied to the gate terminal of the transistor 167, the source terminal and the drain terminal are electrically connected, and when a high-level boost control signal BC is supplied to the gate terminal of the transistor 167, the source terminal and the drain terminal are electrically disconnected. Therefore, when a low-level boost control signal BC is supplied to the gate terminal of the transistor 167, the transistor 167 supplies the voltage signal VDC to the terminal tvbt, and when a high-level boost control signal BC is supplied to the gate terminal of the transistor 167, the transistor 167 stops supplying the voltage signal VDC to the terminal tvbt. In the following description, the state in which the source terminal and drain terminal of transistor 167 are controlled to be conductive may be referred to as "on," and the state in which the drain terminal and source terminal of transistor 167 are controlled to be non-conductive may be referred to as "off."

[0130] One end of the coil 152a is electrically connected to the terminal tvsw, and the other end is electrically connected to one end of the capacitor 153a. A ground signal is supplied to the other end of the capacitor 153a. That is, the coil 152a and the capacitor 153a form a low-pass filter circuit. The switching signal VSW output via the terminal tvsw of the integrated circuit 160a is smoothed by the low-pass filter circuit formed by the coil 152a and the capacitor 153a. The first step-down circuit 150a outputs the signal smoothed by the low-pass filter circuit as the voltage signal VHV.

[0131] One end of the resistor 154a is electrically connected to the other end of the coil 152a, and the other end is electrically connected to one end of the resistor 155a. A ground signal is supplied to the other end of the resistor 155a. The connection point between the other end of the resistor 154a and the one end of the resistor 155a is electrically connected to the terminal tvfb of the integrated circuit 160a. That is, the resistors 154a and 155a divide the voltage value of the voltage signal VHV and feed the divided signal back to the integrated circuit 160a as the feedback voltage signal VFB.

[0132] The drive control circuit 162 controls at least one of the time when the base drive signal BDS is at a high level, the time when the base drive signal BDS is at a low level, the time when the drive signal LDRV is at a high level, and the time when the drive signal LDRV is at a low level so that the voltage value of the input feedback voltage signal VFB becomes a predetermined value.

[0133] Specifically, the drive control circuit 162 increases the on-duty of the output basic drive signal BDS when the voltage value of the input feedback voltage signal VFB is smaller than a predetermined voltage value, and increases the on-duty of the output drive signal LDRV when the voltage value of the input feedback voltage signal VFB is larger than the predetermined voltage value, thereby controlling the voltage value of the voltage signal VHV smoothed by the low-pass filter circuit formed by the coil 152a and capacitor 153a.

[0134] Here, the on-duty is the proportion of the time during which an H-level signal is output relative to the time from when the output signal changes from H level to when it changes from L level to H level again. For example, if the time from when the output signal changes from H level to when it changes from L level to H level again is 100 ms, and the time during which the signal is at H level is 30 ms, the on-duty is 30%. Increasing the on-duty means increasing the proportion of the time during which an H-level signal is output relative to the time during which the output signal changes from H level to when it changes from L level to H level again. For example, the time during which the output signal changes from H level to when it changes from L level to H level again may be fixed and the time during which the signal is at H level may be lengthened; the time during which the signal is at L level may be fixed and the time during which the signal is at H level may be lengthened during the period from when the output signal changes from H level to when it changes from L level to H level again; or the time during which the signal is at H level may be fixed and the time during which the signal is at H level during the period from when the output signal changes from H level to when it changes from L level to H level again.

[0135] One end of the capacitor 156a is electrically connected to the terminal tvsw that outputs the switching signal VSW, and the other end is electrically connected to the terminal tvbt. A charge corresponding to the potential difference between the one end and the other end is accumulated in the capacitor 156a. The capacitor 156a generates a boot voltage signal VBT whose voltage value changes in response to changes in the voltage value of the switching signal VSW output from the terminal tvsw, and outputs the generated signal from the other end.

[0136] As described above, the first step-down circuit 150a in this embodiment includes the integrated circuit 160a, the coil 152a, and the capacitor 153a, and generates and outputs the voltage signal VHV obtained by stepping down the voltage value of the voltage signal VDC in response to the enable signal ENvh based on the step-down control signals VHVc1 to VHVc6 input from the drive signal output circuits 50-1 to 50-6.

[0137] Furthermore, the first step-down voltage circuit 150a in this embodiment preferably has a so-called soft start function that gradually increases the voltage value of the output voltage signal VHV toward a predetermined voltage value when the input enable signal ENvh switches from a state in which the output of the voltage signal VHV is not enabled to a state in which the output of the voltage signal VHV is enabled. In other words, the first step-down voltage circuit 150a has a soft start function that gradually increases the voltage value of the voltage signal VHV when starting to output the voltage signal VHV.

[0138] Specifically, when the enable signal ENvh input to the first step-down voltage circuit 150a switches from a state in which the output of the voltage signal VHV is not enabled to a state in which the output of the voltage signal VHV is enabled, the drive control circuit 162 gradually increases the on-duty of the basic drive signal BDS to be output, regardless of the voltage value of the input feedback voltage signal VFB, thereby gradually increasing the voltage value of the voltage signal VHV output by the first step-down voltage circuit 150a.

[0139] When the voltage value of the voltage signal VHV output by the first step-down circuit 150a reaches a predetermined voltage value, for example, 42 V, the voltage value of the feedback voltage signal VFB input to the drive control circuit 162 reaches the predetermined voltage value. When the voltage value of the feedback voltage signal VFB input to the drive control circuit 162 reaches the predetermined value, the drive control circuit 162 switches control of the on-duty of the basic drive signal BDS to be output to control based on the voltage value of the feedback voltage signal VFB. As a result, the voltage value of the voltage signal VHV output by the first step-down circuit 150a is controlled to be constant at the predetermined voltage value.

[0140] As described above, immediately after the enable signal ENvh input to the first step-down circuit 150a switches from a state in which the output of the voltage signal VHV is not enabled to a state in which the output of the voltage signal VHV is enabled, the first step-down circuit 150a executes a soft start, thereby reducing the risk of an inrush current occurring immediately after the supply of the voltage signal VHV begins.

[0141] As described above, the second step-down voltage circuit 150b in this embodiment has the same configuration as the first step-down voltage circuit 150a. Therefore, in the following description, the second step-down voltage circuit 150b will be described as having an integrated circuit 160b corresponding to the integrated circuit 160a, a coil 152b corresponding to the coil 152a, and a capacitor 153b corresponding to the capacitor 153a, and generating and outputting a voltage signal VDD obtained by stepping down the voltage value of the voltage signal VDC.

[0142] 3. Head unit structure Next, the structure of the head unit 5 of this embodiment will be described. As described above, the head unit 5 has a drive unit 10 and a discharge unit 20, which are electrically connected via a connection member 30. Below, an example of the structure of the drive unit 10 and the structure of the discharge unit 20 will be described.

[0143] 3.1 Structure of the discharge unit First, an example of the structure of the discharge unit 20 of the head unit 5 will be described. FIG. 16 is a diagram showing the structure of the discharge unit 20. Here, in the following description, the X1 axis, Y1 axis, and Z1 axis, which are perpendicular to each other, will be used. Furthermore, in the following description, the tip side of an arrow along the illustrated X1 axis will be referred to as the +X1 side, and the starting side will be referred to as the -X1 side. The tip side of an arrow along the illustrated Y1 axis will be referred to as the +Y1 side, and the starting side will be referred to as the -Y1 side. The tip side of an arrow along the illustrated Z1 axis will be referred to as the +Z1 side, and the starting side will be referred to as the -Z1 side.

[0144] 16, the discharge unit 20 includes a housing 31, an assembly substrate 33, a flow path structure 34, a head substrate 35, distribution channels 37, a fixed plate 39, and print heads 23-1 to 23-6. In the discharge unit 20, the flow path structure 34, the head substrate 35, the distribution channels 37, and the fixed plate 39 are stacked in this order along the Z1 axis from the −Z1 side to the +Z1 side: fixed plate 39, distribution channels 37, head substrate 35, and flow path structure 34. The housing 31 is positioned around the flow path structure 34, the head substrate 35, the distribution channels 37, and the fixed plate 39 so as to support the flow path structure 34, the head substrate 35, the distribution channels 37, and the fixed plate 39. The assembly substrate 33 is held by the housing 31 and stands upright on the +Z1 side of the housing 31. The print heads 23-1 to 23-6 are positioned between the distribution channels 37 and the fixed plate 39 so as to be partially exposed to the outside of the discharge unit 20.

[0145] Before describing the structure of the discharge unit 20, the structure of the print head 23 provided in the discharge unit 20 will first be described. Fig. 17 is a diagram showing an example of the structure of the print head 23. Fig. 18 is a diagram showing an example of a cross section of the print head 23. Here, Fig. 18 is a cross section of the print head 23 taken along line Aa shown in Fig. 17. Note that line Aa shown in Fig. 17 is an imaginary line segment that passes through the introduction path 661 provided in the print head 23 and also passes through the nozzle N1 and nozzle N2.

[0146] 17 and 18, the print head 23 has a plurality of nozzles N1 arranged in a row and a plurality of nozzles N2 arranged in a row. The total number of nozzles N1 and nozzles N2 in the print head 23 is n, which is the same as the number of ejection portions 600 in the print head 23. Note that the following description will be given assuming that the number of nozzles N1 and the number of nozzles N2 in the print head 23 are the same. That is, the print head 23 has n / 2 nozzles N1 and n / 2 nozzles N2. In the following description, when there is no need to distinguish between nozzles N1 and nozzles N2, they may be simply referred to as nozzles N.

[0147] The print head 23 includes a wiring member 388 , a case 660 , a protective substrate 641 , a flow path forming substrate 642 , a communication plate 630 , a compliance substrate 620 , and a nozzle plate 623 .

[0148] In the flow path forming substrate 642, pressure chambers CB1, which are partitioned by a plurality of partition walls by anisotropic etching from one surface side, are arranged in a row corresponding to the nozzles N1, and pressure chambers CB2, which are partitioned by a plurality of partition walls by anisotropic etching from one surface side, are arranged in a row corresponding to the nozzles N2. Here, in the following description, when there is no need to distinguish between the pressure chambers CB1 and CB2, they may be simply referred to as pressure chambers CB.

[0149] The nozzle plate 623 is located on the -Z1 side of the flow path forming substrate 642. The nozzle plate 623 is provided with a nozzle row Ln1 formed by n / 2 nozzles N1 and a nozzle row Ln2 formed by n / 2 nozzles N2. Here, in the following description, the surface of the nozzle plate 623 on the -Z1 side where the nozzles N open may be referred to as the liquid ejection surface 623a.

[0150] A communication plate 630 is located on the -Z1 side of the flow path forming substrate 642 and on the +Z1 side of the nozzle plate 623. The communication plate 630 is provided with a nozzle communication passage RR1 that communicates between the pressure chamber CB1 and the nozzle N1, and a nozzle communication passage RR2 that communicates between the pressure chamber CB2 and the nozzle N2. The communication plate 630 is also provided with a pressure chamber communication passage RK1 that communicates between an end of the pressure chamber CB1 and the manifold MN1, and a pressure chamber communication passage RK2 that communicates between an end of the pressure chamber CB2 and the manifold MN2, which are independent and correspond to the pressure chambers CB1 and CB2, respectively.

[0151] Manifold MN1 includes a supply communication passage RA1 and a connection communication passage RX1. The supply communication passage RA1 penetrates the communication plate 630 along the Z1 axis, while the connection communication passage RX1 does not penetrate the communication plate 630 along the Z1 axis, but opens on the nozzle plate 623 side of the communication plate 630 and extends partway along the Z1 axis. Similarly, manifold MN2 includes a supply communication passage RA2 and a connection communication passage RX2. The supply communication passage RA2 penetrates the communication plate 630 along the Z1 axis, while the connection communication passage RX2 does not penetrate the communication plate 630 along the Z1 axis, but opens on the nozzle plate 623 side of the communication plate 630 and extends partway along the Z1 axis. The connection communication passage RX1 included in manifold MN1 communicates with the corresponding pressure chamber CB1 via a pressure chamber communication passage RK1, and the connection communication passage RX2 included in manifold MN2 communicates with the corresponding pressure chamber CB2 via a pressure chamber communication passage RK2.

[0152] In the following description, when there is no need to distinguish between the nozzle communication passage RR1 and the nozzle communication passage RR2, they may simply be referred to as the nozzle communication passage RR; when there is no need to distinguish between the manifold MN1 and the manifold MN2, they may simply be referred to as the manifold MN; when there is no need to distinguish between the supply communication passage RA1 and the supply communication passage RA2, they may simply be referred to as the supply communication passage RA; and when there is no need to distinguish between the connection communication passage RX1 and the connection communication passage RX2, they may simply be referred to as the connection communication passage RX.

[0153] A vibration plate 610 is located on the +Z1 side surface of the flow path forming substrate 642. Furthermore, n piezoelectric elements 60 corresponding to the nozzles N1 and N2 are formed in two rows on the +Z1 side surface of the vibration plate 610.

[0154] The piezoelectric element 60 has a piezoelectric body 601 and a pair of electrodes 602, 603 arranged to sandwich the piezoelectric body 601. The electrode 602 and the piezoelectric body 601 are formed for each pressure chamber CB on the +Z1 side surface of the vibration plate 610, and the electrode 603 is configured as a common electrode shared by the pressure chambers CB on the +Z1 side surface of the vibration plate 610. The piezoelectric element 60 is driven so that the piezoelectric body 601 is displaced in the up and down direction by supplying a drive signal VOUT from the drive signal selection circuit 200 to the electrode 602 and a reference voltage signal VBS to the electrode 603, which is the common electrode.

[0155] A protective substrate 641 is bonded to the surface on the +Z1 side of the flow path forming substrate 642. The protective substrate 641 forms a protective space 644 for protecting the piezoelectric element 60. The protective substrate 641 is also provided with a through hole 643 that penetrates along the Z1 axis. Lead electrodes 611 drawn from the electrodes 602, 603 of the piezoelectric element 60 are extended so that their ends are exposed inside the through hole 643. The wiring member 388 is electrically connected to the lead electrodes 611 exposed inside the through hole 643.

[0156] A case 660 is fixed to the protective substrate 641 and the communicating plate 630. The case 660 defines a portion of a manifold MN that communicates with the pressure chambers CB. The case 660 is bonded to the protective substrate 641 and also to the communicating plate 630. Specifically, the case 660 has a recess 665 on its -Z1 side that accommodates the flow path forming substrate 642 and the protective substrate 641. The recess 665 has an opening area larger than the surface where the protective substrate 641 is bonded to the flow path forming substrate 642. The flow path forming substrate 642 and the like are accommodated in the recess 665. The opening surface of the recess 665 on the -Z1 side is sealed by the communicating plate 630 with the flow path forming substrate 642 and the like accommodated in the recess 665. As a result, the case 660, the flow path forming substrate 642, and the protective substrate 641 define supply communication channels RB1 and RB2 on the outer periphery of the flow path forming substrate 642. Here, when there is no need to distinguish between the supply communication passage RB1 and the supply communication passage RB2, they may be simply referred to as the supply communication passage RB.

[0157] Furthermore, a compliance substrate 620 is provided on the surface of the communicating plate 630 where the supply communicating passages RA and the connection communicating passages RX open. The openings of the supply communicating passages RA and the connection communicating passages RX are sealed by this compliance substrate 620. Such a compliance substrate 620 has a sealing film 621 and a fixed substrate 622. The sealing film 621 is formed of a flexible thin film or the like, and the fixed substrate 622 is formed of a hard material, such as a metal, for example, stainless steel.

[0158] An introduction path 661 for supplying ink to the manifold MN is also provided in the case 660. Furthermore, the case 660 is provided with a connection port 662, which is an opening that communicates with the through-hole 643 of the protective substrate 641 and penetrates along the Z1 axis, and through which the wiring member 388 is inserted.

[0159] The wiring member 388 is a flexible member for electrically connecting the print head 23 and the head substrate 35, and for example, an FPC can be used. An integrated circuit 201 is mounted by COF (Chip On Film) on the wiring member 388. At least a part of the drive signal selection circuit 200 described above is mounted on this integrated circuit 201.

[0160] In the print head 23 configured as described above, the wiring member 388 propagates the voltage signal VHV, drive signals COMA, COMB, and COMC, the reference voltage signal VBS, the clock signal SCK, the print data signal SI, and the latch signal LAT. Of these, the voltage signal VHV, drive signals COMA, COMB, and COMC, the clock signal SCK, the print data signal SI, and the latch signal LAT are input to a drive signal selection circuit 200 including an integrated circuit 201 provided on the wiring member 388. The drive signal selection circuit 200 selects or deselects the drive signals COMA, COMB, and COMC based on the input voltage signal VHV, the clock signal SCK, the print data signal SI, and the latch signal LAT, thereby generating and outputting a drive signal VOUT. The drive signal VOUT output by the drive signal selection circuit 200 propagates through the wiring member 388 and is supplied to an electrode 602 via a lead electrode 611. Furthermore, the reference voltage signal VBS is propagated through the wiring member 388 and supplied to the electrode 603 via the lead electrode 611. As a result, the piezoelectric body 601 deforms in accordance with the potential difference between the drive signal VOUT supplied to the electrode 602 and the reference voltage signal VBS supplied to the electrode 603. In other words, the piezoelectric element 60 is driven. As the piezoelectric element 60 is driven, the diaphragm 610 on which the piezoelectric element 60 is provided is displaced in the vertical direction. As a result, the internal pressure of the corresponding pressure chamber CB changes, and ink stored inside the pressure chamber CB is ejected from the nozzle N in accordance with the change in the internal pressure of the pressure chamber CB.

[0161] In the print head 23 configured as above, the configuration including the nozzles N, nozzle communication paths RR, pressure chambers CB, piezoelectric elements 60, and vibration plate 610 corresponds to the above-mentioned ejection units 600. In other words, the print head 23 has a plurality of ejection units 600 that include piezoelectric elements 60 and eject ink in response to the driving of the piezoelectric elements 60.

[0162] That is, the ejection unit 20 includes a print head 23-1 which includes a piezoelectric element 60 to which a drive signal VOUT based on the drive signals COMA1, COMB1, and COMC1 is supplied at one end and a reference voltage signal VBS1 having a constant voltage value is supplied at the other end, and ejects ink in response to the driving of the piezoelectric element 60; a print head 23-2 which includes a piezoelectric element 60 to which a drive signal VOUT based on the drive signals COMA2, COMB2, and COMC2 is supplied at one end and a reference voltage signal VBS2 having a constant voltage value is supplied at the other end, and ejects ink in response to the driving of the piezoelectric element 60; and a print head 23-3 which includes a piezoelectric element 60 to which a drive signal VOUT based on the drive signals COMA3, COMB3, and COMC3 is supplied at one end and a reference voltage signal VBS3 having a constant voltage value is supplied at the other end, and ejects ink in response to the driving of the piezoelectric element 60. 3-3, a print head 23-4 including a piezoelectric element 60 to one end of which a drive signal VOUT based on the drive signals COMA4, COMB4, and COMC4 is supplied, and to the other end of which a reference voltage signal VBS4 with a constant voltage value is supplied, and which ejects ink in response to the driving of the piezoelectric element 60, a print head 23-5 including a piezoelectric element 60 to one end of which a drive signal VOUT based on the drive signals COMA5, COMB5, and COMC5 is supplied, and to the other end of which a reference voltage signal VBS5 with a constant voltage value is supplied, and which ejects ink in response to the driving of the piezoelectric element 60, and a print head 23-6 including a piezoelectric element 60 to one end of which a drive signal VOUT based on the drive signals COMA6, COMB6, and COMC6 is supplied, and to the other end of which a reference voltage signal VBS6 with a constant voltage value is supplied, and which ejects ink in response to the driving of the piezoelectric element 60.

[0163] Returning to FIG. 16 , the fixed plate 39 is located on the −Z1 side of the print heads 23-1 to 23-6. The print heads 23-1 to 23-6 are fixed to the fixed plate 39. Specifically, the fixed plate 39 has six openings 391 that penetrate the fixed plate 39 along the Z1 axis and correspond to the print heads 23-1 to 23-6, respectively. The print heads 23-1 to 23-6 are fixed to the fixed plate 39 so that the liquid ejection surfaces 623a are exposed from the six openings 391, respectively.

[0164] The distribution flow path 37 is located on the +Z1 side of the print heads 23-1 to 23-6. Four inlet ports 373 are provided on the +Z1 side surface of the distribution flow path 37. The four inlet ports 373 are flow path pipes that protrude from the +Z1 side surface of the distribution flow path 37 along the Z1 axis to the +Z1 side and communicate with flow path holes (not shown) formed on the -Z1 side surface of the flow path structure 34. In addition, flow path pipes (not shown) that communicate with the four inlet ports 373 are located on the -Z1 side surface of the distribution flow path 37. These flow path pipes (not shown) located on the -Z1 side surface of the distribution flow path 37 communicate with the inlet channels 661 of each of the print heads 23-1 to 23-6. In addition, the distribution flow path 37 has six openings 371 that penetrate along the Z1 axis. Wiring members 388 of each of the print heads 23-1 to 23-6 are inserted through these six openings 371.

[0165] The head substrate 35 is located on the +Z1 side of the distribution flow path 37. A wiring member FC is attached to the head substrate 35, which is electrically connected to the assembly substrate 33 (described later). The head substrate 35 also has four openings 351 and notches 352 and 353. The wiring members 388 of the print heads 23-2 to 23-5 pass through the four openings 351 and are electrically connected to the head substrate 35 by solder or the like. The wiring member 388 of the print head 23-1 passes through the notch 352, and the wiring member 388 of the print head 23-6 passes through the notch 353. The wiring members 388 of the print heads 23-1 and 23-6 that pass through the notches 352 and 353, respectively, are electrically connected to the head substrate 35 by solder or the like.

[0166] Furthermore, four notches 355 are formed at the four corners of the head substrate 35. Introduction portions 373 pass through the four notches 355. The four introduction portions 373 that pass through the notches 355 are connected to the flow path structure 34 located on the +Z1 side of the head substrate 35.

[0167] The flow path structure 34 includes a flow path plate Su1 and a flow path plate Su2. The flow path plate Su1 and the flow path plate Su2 are stacked along the Z1 axis with the flow path plate Su1 located on the +Z1 side and the flow path plate Su2 located on the -Z1 side, and are bonded to each other with an adhesive or the like. The flow path structure 34 also includes four inlet ports 341 on its +Z1 side surface that protrude toward the +Z1 side along the Z1 axis. The four inlet ports 341 communicate with flow path holes (not shown) formed on the -Z1 side surface of the flow path structure 34 via ink flow paths formed inside the flow path structure 34. The flow path holes (not shown) formed on the -Z1 side surface of the flow path structure 34 communicate with the four inlet ports 373. The flow path structure 34 also includes a through hole 343 that penetrates along the Z1 axis. A wiring member FC that electrically connects to the head substrate 35 is inserted through the through hole 343.

[0168] Here, in addition to an ink flow path that connects the introduction section 341 with a flow path hole (not shown) formed on the surface on the -Z1 side, the inside of the flow path structure 34 may also be provided with a capture filter or the like for capturing foreign matter contained in the ink flowing through the ink flow path.

[0169] The housing 31 is positioned so as to cover the periphery of the flow path structure 34, the head substrate 35, the distribution flow paths 37, and the fixed plate 39, and supports the flow path structure 34, the head substrate 35, the distribution flow paths 37, and the fixed plate 39. The housing 31 has four openings 311, an assembly substrate insertion portion 313, and a holding member 315.

[0170] Four introduction parts 341 of the flow path structure 34 are inserted into the four opening parts 311, respectively. Then, ink is supplied from the liquid container 3 to the four introduction parts 341 that have passed through the four opening parts 311 via tubes or the like (not shown).

[0171] The holding member 315 sandwiches the assembly substrate 33 between itself and the housing 31, with a portion of the assembly substrate 33 inserted through the assembly substrate insertion portion 313. The assembly substrate 33 is provided with a connection portion 330. The connection portion 330 is fitted with a connection member 30 that transmits various signals, such as the voltage signals VHV and VDD, the data signal DATA, the drive signals COMA, COMB, and COMC, the reference voltage signal VBS, and other power supply voltages, output by the drive unit 10. The wiring member FC of the head substrate 35 is electrically connected to the assembly substrate 33, thereby electrically connecting the assembly substrate 33 and the head substrate 35. The assembly substrate 33 may also be provided with a semiconductor device equivalent to the restoration circuit 220 described above. While FIG. 16 illustrates a case in which the assembly substrate 33 is provided with one connection portion 330, the assembly substrate 33 may have multiple connection portions 330.

[0172] In the ejection unit 20 configured as described above, the liquid container 3 and the introduction portion 341 communicate with each other via a tube (not shown) or the like, so that ink stored in the liquid container 3 is supplied to the ejection unit 20. The ink supplied to the ejection unit 20 is guided through ink channels formed inside the flow path structure 34 to flow path holes (not shown) formed on the -Z1 side surface of the flow path structure 34, and then supplied to the four introduction portions 373 of the distribution flow path 37. The ink supplied to the distribution flow path 37 is distributed to each of the print heads 23-1 to 23-6 in ink channels (not shown) formed inside the distribution flow path 37, and then supplied to the introduction paths 661 of the corresponding print heads 23-1 to 23-6. The ink supplied to the print heads 23-1 to 23-6 via the introduction paths 661 is then stored in the pressure chambers CB included in the ejection unit 600.

[0173] Furthermore, various signals output by the drive unit 10, including the voltage signals VHV and VDD, drive signals COMA1 to COMA6, COMB1 to COMB6, and COMC1 to COMC6, reference voltage signals VBS1 to VBS6, and data signal DATA, propagate through the connection member 30 and are input to the discharge unit 20 via the connection portion 330. The various signals input to the discharge unit 20, including the drive signals COMA1 to COMA6, COMB1 to COMB6, and COMC1 to COMC6, reference voltage signals VBS1 to VBS6, and data signal DATA, propagate through the assembly substrate 33 and head substrate 35. At this time, the restoration circuit 220 generates clock signals SCK1 to SCK6, print data signals SI1 to SI6, and latch signals LAT1 to LAT6 corresponding to the print heads 23-1 to 23-6, respectively, from the data signal DATA, and separates them corresponding to each of the print heads 23-1 to 23-6. The voltage signals VHV, VDD, drive signals COMA1-COMA6, COMB1-COMB6, COMC1-COMC6, reference voltage signals VBS1-VBS6, clock signals SCK1-SCK6, print data signals SI1-SI6, and latch signals LAT1-LAT6 are input to wiring members 388 of the corresponding print heads 23-1-23-6. The voltage signals VHV, VDD, drive signals COMA, COMB, COMC, reference voltage signal VBS, clock signal SCK, print data signal SI, and latch signal LAT supplied to wiring members 388 propagate through wiring members 388. At this time, an integrated circuit 201 including a drive signal selection circuit 200 provided on wiring members 388 generates drive signals VOUT corresponding to each of the n ejectors 600 and supplies them to electrodes 602 of the piezoelectric elements 60 included in the corresponding ejectors 600. As a result, the n piezoelectric elements 60 are individually driven in response to the drive signal VOUT, and as a result, ink stored in the pressure chambers CB corresponding to the piezoelectric elements 60 is ejected from the corresponding nozzles N.

[0174] 3.2 Drive unit structure Next, the structure of the drive unit 10 of the head unit 5 will be described. Here, Figures 19 and 20 show the X2, Y2, and Z2 axes, which are mutually perpendicular and independent of the X1, Y1, and Z1 axes described above. In the following description, the tip side of an arrow along the illustrated X2 axis will be referred to as the +X2 side, and the starting side as the -X2 side; the tip side of an arrow along the illustrated Y2 axis will be referred to as the +Y2 side, and the starting side as the -Y2 side; and the tip side of an arrow along the illustrated Z2 axis will be referred to as the +Z2 side, and the starting side as the -Z2 side.

[0175] Fig. 19 is a diagram showing the structure of the drive unit 10. As shown in Fig. 19, the drive unit 10 includes a base substrate B1, a conversion circuit substrate B2, and drive circuit modules DRV1 to DRV6.

[0176] The base substrate B1 includes a surface 801 and a surface 802 located on the back side of the surface 801 and facing the surface 801. The base substrate B1 is located such that the surfaces 801 and 802 extend along the Y2Z2 plane formed by the Y2 axis and the Z2 axis, with the surface 801 on the +X2 side and the surface 802 on the -X2 side. Details of the base substrate B1 will be described later.

[0177] The conversion circuit board B2 is located on the +X2 side of surface 801 of the base substrate B1, and its component mounting surface on which various electronic components are mounted extends along the Y2Z2 plane. The conversion circuit board B2 is electrically connected to the base substrate B1 via a BtoB connector on the -X2 side of the component mounting surface. The conversion circuit board B2 is also fixed to the base substrate B1 with one or more screws.

[0178] A connector CN1 and an integrated circuit IC1 are provided on the +X2 side of the component mounting surface of the conversion circuit board B2. The connector CN1 is located on the +Z2 side of the conversion circuit board B2. A cable such as an FFC that electrically connects the drive unit 10 and the control unit 2 is attached to the connector CN1. The integrated circuit IC1 is located on the +Z2 side of the connector CN1. At least a portion of the control circuit 100 and conversion circuit 120 described above is mounted on this integrated circuit IC2.

[0179] Various signals including the image information signal IP output by the control unit 2 are input to the drive unit 10 via the connector CN1. The various signals including the image information signal IP input to the drive unit 10 propagate through the conversion circuit board B2 and are input to the integrated circuit IC1. The integrated circuit IC1 generates various signals including the data signal DATA and the basic drive data signals dA1 to dA6, dB1 to dB6, and dC1 to dC6 based on the input image information signal IP. The data signal DATA generated by the integrated circuit IC1 and the various signals including the basic drive data signals dA1 to dA6, dB1 to dB6, and dC1 to dC6 then propagate through the conversion circuit board B2 and are output to the base board B1 via a BtoB connector electrically connected to the base board B1.

[0180] The drive circuit modules DRV1 to DRV6 are located on the surface 801 side of the base substrate B1 and on the -Z2 side of the conversion circuit substrate B2. Specifically, the drive circuit modules DRV1 to DRV3 are located on the surface 801 side of the base substrate B1 and on the -Z2 side of the conversion circuit substrate B2, extending from the +Y2 side to the -Y2 side along the Y2 axis, in the order of drive circuit module DRV1, drive circuit module DRV2, and drive circuit module DRV3, spaced apart from one another in an upright state relative to the base substrate B1. Furthermore, the drive circuit modules DRV4 to DRV6 are located on the surface 801 side of the base substrate B1 and on the -Z2 side of the drive circuit modules DRV1 to DRV3, extending from the +Y2 side to the -Y2 side along the Y2 axis, spaced apart from one another in the order of drive circuit module DRV4, drive circuit module DRV5, and drive circuit module DRV6. At this time, each of the drive circuit modules DRV1 to DRV6 is fixed to the base substrate B1 via a corresponding BtoB connector and electrically connected to the base substrate B1. Note that the drive circuit modules DRV1 to DRV6 may be fixed to the base substrate B1 using fixing members such as screws in addition to the BtoB connectors.

[0181] The drive circuit modules DRV1 to DRV6 positioned as above each include the drive signal output circuits 50-1 to 50-6. Specifically, the drive circuit module DRV1 includes the drive signal output circuit 50-1, the drive circuit module DRV2 includes the drive signal output circuit 50-2, the drive circuit module DRV3 includes the drive signal output circuit 50-3, the drive circuit module DRV4 includes the drive signal output circuit 50-4, the drive circuit module DRV5 includes the drive signal output circuit 50-5, and the drive circuit module DRV6 includes the drive signal output circuit 50-6. Then, the drive circuit module DRV1 outputs the drive signals COMA1, COMB1, COMC1 and the reference voltage signal VBS1 generated by the drive signal output circuit 50-1 to the base substrate B1 via the corresponding BtoB connectors, and similarly, the drive circuit module DRVi outputs the drive signals COMAi, COMBi, COMCi and the reference voltage signal VBSi generated by the drive signal output circuit 50-i to the base substrate B1 via the corresponding BtoB connectors.

[0182] Here, the drive circuit modules DRV1 to DRV6 all have the same configuration. Therefore, when there is no need to distinguish between the drive circuit modules DRV1 to DRV6, they may be simply referred to as drive circuit modules DRV. In this case, the drive circuit module DRV will be described as including a drive signal output circuit 50 as drive signal output circuits 50-1 to 50-6, and outputting drive signals COMA, COMB, COMC and a reference voltage signal VBS to the base substrate B1 via corresponding BtoB connectors.

[0183] Here, an example of the structure of the drive circuit module DRV will be described. Fig. 20 is a diagram showing an example of the structure of the drive circuit module DRV. As shown in Fig. 20, the drive circuit module DRV includes drive circuits 52a, 52b, and 52c included in the drive signal output circuit 50, a connector CN3a, and a drive circuit board DRB on which the drive circuits 52a, 52b, and 52c and the connector CN3a are mounted.

[0184] The drive circuit board DRB is a circuit board on which various electronic components are mounted, and is positioned so that the component mounting surface extends along the X2Z2 plane formed by the X2 axis and the Z2 axis.

[0185] The drive circuits 52a, 52b, and 52c are positioned side by side along the Z2 axis on the −Y2 side surface of the drive circuit board DRB.

[0186] Specifically, the drive circuit 52a has an integrated circuit 500, an amplifier circuit 550, and a coil 561 arranged in this order from the −X2 side to the +X2 side along the X2 axis, with the coil 561, amplifier circuit 550, and integrated circuit 500. At this time, the transistors 551 and 552 included in the amplifier circuit 550 of the drive circuit 52a are arranged in parallel along the Z2 axis. Meanwhile, the drive circuit 52b has an integrated circuit 500, amplifier circuit 550, and coil 561 included in the drive circuit 52b on the −Z2 side of the drive circuit 52a, and is arranged in this order from the −X2 side to the +X2 side along the X2 axis, with the coil 561, amplifier circuit 550, and integrated circuit 500. At this time, the transistors 551 and 552 included in the amplifier circuit 550 of the drive circuit 52b are arranged in parallel along the Z2 axis. Furthermore, the drive circuit 52c is on the -Z2 side of the drive circuit 52a and on the +Z2 side of the drive circuit 52b, and the integrated circuit 500, amplifier circuit 550, and coil 561 included in the drive circuit 52c are arranged in this order from the -X2 side to the +X2 side along the X2 axis. At this time, the transistors 551 and 552 included in the amplifier circuit 550 of the drive circuit 52c are arranged side by side along the Z2 axis. That is, the drive circuits 52a, 52b, and 52c are arranged in this order on the -Y2 side surface of the drive circuit substrate DRB, along the Z2 axis from the +Z2 side to the -Z2 side.

[0187] At this time, the integrated circuits 500 possessed by each of the drive circuits 52a, 52b, and 52c are arranged side by side along the Z2 axis, the amplifier circuits 550 possessed by each of the drive circuits 52a, 52b, and 52c are arranged side by side along the Z2 axis, and the coils 561 possessed by each of the drive circuits 52a, 52b, and 52c are arranged side by side along the Z2 axis.

[0188] As described above, the voltage amplitudes of the drive signals COMA and COMB are greater than that of the drive signal COMC. Therefore, the amount of current generated by the propagation of the drive signals COMA and COMB is greater than the amount of current generated by the propagation of the drive signal COMC. Therefore, the heat generated by the drive circuit 52a, which outputs the drive signal COMA, and the heat generated by the drive circuit 52b, which outputs the drive signal COMB, are greater than the heat generated by the drive circuit 52c, which outputs the drive signal COMC. By placing the drive circuit 52c, which generates less heat, between the drive circuits 52a and 52b, which generate more heat, the drive circuits 52a and 52b are spaced apart. This reduces the risk of the heat generated by the drive circuit 52a and the heat generated by the drive circuit 52b interfering with each other and causing localized heat concentration in the drive circuit module DRV.

[0189] The connector CN3a is located on the -Y2 side of the drive circuit board DRB, on the -X2 side of the drive circuits 52a, 52b, and 52c, along the edge of the drive circuit board DRB on the -X2 side. This connector CN3a mates with a connector CN3b (described later) provided on the base substrate B1, electrically connecting the drive circuit board DRB to the base substrate B1. In other words, the connectors CN3a and CN3b form a BtoB connector that electrically connects the drive circuit module DRV to the base substrate B1. As a result, the drive signals COMA, COMB, and COMC and the reference voltage signal VBS output by the drive circuits 52a, 52b, and 52c are input to the base substrate B1. In this case, the terminals through which the drive signals COMA, COMB, and COMC of the connector CN3a are transmitted and the terminals through which the drive signals COMA, COMB, and COMC of the connector CN3b are transmitted correspond to the above-mentioned terminals COM-Out, and the terminals through which the reference voltage signal VBS of the connector CN3a is transmitted and the terminals through which the reference voltage signal VBS of the connector CN3b is transmitted correspond to the above-mentioned terminals VBS-Out.

[0190] 20, the connector CN3a is located on the -X2 side of the drive circuits 52a, 52b, and 52c, along the edge of the drive circuit board DRB on the -X2 side, so that the shortest distance between the coil 561 of the drive circuit 52a and the connector CN3a is shorter than the shortest distance between the integrated circuit 500 of the drive circuit 52a and the connector CN3a, the shortest distance between the coil 561 of the drive circuit 52b and the connector CN3a is shorter than the shortest distance between the integrated circuit 500 of the drive circuit 52b and the connector CN3a, and the shortest distance between the coil 561 of the drive circuit 52c and the connector CN3a is shorter than the shortest distance between the integrated circuit 500 of the drive circuit 52c and the connector CN3a. This allows the wiring length of the wiring patterns on the drive circuit board DRB through which the drive signals COMA, COMB, and COMC and the reference voltage signal VBS output by the drive circuits 52a, 52b, and 52c propagate to be shortened. As a result, the waveform accuracy of the signal waveforms of the drive signals COMA, COMB, COMC and the reference voltage signal VBS output from the drive circuit module DRV is improved.

[0191] That is, the driving unit 10 has a driving circuit module DRV including a driving signal output circuit 50-1 including driving circuits 52a, 52b, and 52c, a reference voltage signal output circuit 460 included in the driving circuits 52a, 52b, and 52c, a connector CN3a electrically connected to the base substrate B1, and a driving circuit board DRB on which the driving signal output circuit 50 including the driving circuits 52a, 52b, and 52c and the connector CN3a are provided.

[0192] Returning to FIG. 19, a connector CN2 is provided on a surface 801 of the base substrate B1. The connector CN2 is located along the edge on the -Z2 side of the base substrate B1. One end of the connection member 30 is attached to this connector CN2. The other end of the connection member 30 is connected to the above-mentioned connection section 330. As a result, signals including the drive signals COMA1 to COMA6, COMB1 to COMB6, and COMC1 to COMC6 that have propagated through the base substrate B1 and the data signal DATA are supplied to the discharge unit 20.

[0193] That is, the drive unit 10 has a connector CN2 electrically connected to the ejection unit 20 having the print heads 23-1 to 23-6, and a base substrate B1 on which the connector CN2 is provided and through which the drive signals COMA1 to COMA6, COMB1 to COMB6, COMC1 to COMC6, and reference voltage signals VBS1 to VBS6 propagate.

[0194] In the drive unit 10 of this embodiment configured as described above, the drive circuit module DRV including the drive signal output circuit 50 is fixed upright to the base substrate B1 via a BtoB connector. This eliminates the need to mount the drive signal output circuits 50-1 to 50-6 on the base substrate B1, making it possible to reduce the size of the base substrate B1, and as a result, it is possible to reduce the size of the drive unit 10 including the base substrate B1, and the head unit 5 having the drive unit 10.

[0195] On the other hand, with this configuration, the base substrate B1 is smaller, and therefore the area on the base substrate B1 where wiring patterns through which various signals propagate is reduced. As a result, there is a risk that the various signals propagating through the base substrate B1 may interfere with each other. In particular, if distortion occurs in the signal waveforms of the drive signals COMA1 to COMA6, COMB1 to COMB6, and COMC1 to COMC6 propagating through the base substrate B1, the drive characteristics of the multiple piezoelectric elements 60 of the ejection unit 20 may change, increasing the risk that the accuracy of ink ejection from the ejection unit 20 may deteriorate.

[0196] Therefore, the following describes an example of an optimal arrangement of electronic components mounted on the base substrate B1, which is a configuration that can achieve both miniaturization of the base substrate B1 and a reduction in the risk of distortion occurring in the signal waveforms of the propagating drive signals COMA1 to COMA6, COMB1 to COMB6, and COMC1 to COMC6, and an example of an optimal wiring pattern formed on the base substrate B1, which is an example of an optimal wiring pattern for propagating the drive signals COMA1 to COMA6, COMB1 to COMB6, and COMC1 to COMC6 and the reference voltage signals VBS1 to VBS6 that propagate through the base substrate B1.

[0197] Before describing an example of an optimal arrangement of electronic components mounted on the base substrate B1 and an example of an optimal wiring pattern formed on the base substrate B1, the structure of the base substrate B1 will be described first. Fig. 21 is a diagram showing an example of the cross-sectional structure of the base substrate B1. As shown in Fig. 21, the base substrate B1 includes surface wiring layers 811 and 812 located between the above-mentioned surface 801 and surface 802, internal wiring layers 820-1 to 820-m, and a plurality of insulating layers 810.

[0198] The surface wiring layer 811 is a surface layer that forms a wiring pattern on the surface 801, and the surface wiring layer 812 is a surface layer that forms a wiring pattern on the surface 802. The internal wiring layers 820-1 to 820-m are located between the surface wiring layer 811 and the surface wiring layer 812 along the X2 axis and are internal layers that form wiring patterns inside the base substrate B1, and are stacked in the order of internal wiring layers 820-1, 820-2, ..., 820-(m-1), 820-m from the +X2 side to the -X2 side. Then, on each of the surface wiring layers 811, 812 and the internal wiring layers 820-1 to 820-m, wiring patterns through which various signals propagate are formed by etching copper foil or the like that has excellent electrical conductivity.

[0199] The multiple insulating layers 810 insulate the surface wiring layers 811 and 812 and the internal wiring layers 820-1 to 820-m from one another. Specifically, the multiple insulating layers 810 are located along the X2 axis between the surface wiring layer 811 and the internal wiring layer 820-1, between the internal wiring layer 820-1 and the internal wiring layer 820-2, between the internal wiring layer 820-j (j is any one of 1 to m-1) and the internal wiring layer 820-(j+1), and between the internal wiring layer 820-m and the surface wiring layer 812. The multiple insulating layers 810 are made of a material with excellent insulating properties, such as epoxy glass formed by impregnating glass fiber cloth with epoxy resin. Note that a solder resist (not shown) may be applied to the surfaces 801 and 802 to insulate the surface wiring layer 811 and the surface wiring layer 812.

[0200] As described above, the base substrate B1 of this embodiment includes a surface 801, a surface 802 located on the reverse side of the surface 801 and facing the surface 801, and a plurality of internal wiring layers 820 located between the surfaces 801 and 802. That is, the base substrate B1 is configured as a so-called multilayer substrate having a plurality of layers. A plurality of electronic components are mounted on at least one of the surfaces 801 and 802 of the base substrate B1, and the plurality of electronic components mounted on the surfaces 801 and 802 are electrically connected to each other via wiring patterns formed on the surface wiring layers 811 and 812 and the internal wiring layers 820-1 to 820-m. In this way, the base substrate B1 propagates various signals to desired configurations.

[0201] Next, an example of an optimal arrangement of electronic components mounted on the base substrate B1, which is a multilayer substrate, will be described. Fig. 22 is a diagram showing an example of an arrangement of multiple electronic components mounted on the base substrate B1. In Fig. 22, electronic components mounted on a surface 801 located on the +X2 side of the base substrate B1 are shown by solid lines, and electronic components mounted on a surface 802 located on the -X2 side of the base substrate B1 are shown by dashed lines.

[0202] As shown in Fig. 22, the base substrate B1 includes sides 821, 822, 823, and 824. Sides 821 and 822 are positioned opposite each other along the Z2 axis, with side 821 on the +Z2 side and side 822 on the -Z2 side. Sides 823 and 824 are longer than sides 821 and 822, and are positioned opposite each other along the Y2 axis, with side 823 on the +Y2 side and side 824 on the -Y2 side. In other words, the base substrate B1 has a substantially rectangular shape with sides 821 and 822 as short sides and sides 823 and 824 as long sides. The shape of the base substrate B1 is not limited to a rectangular shape.

[0203] On a surface 801 of the base substrate B1, the connector CN2, connectors CN3b-1 to CN3b-6 as the above-mentioned connector CN3b, and two connectors CN4b are mounted.

[0204] The connector CN2 is located at the end of the base substrate B1 on the -Z2 side. Specifically, the connector CN2 has a plurality of terminals through which signals including the drive signals COMA1 to COMA6, COMB1 to COMB6, and COMC1 to COMC6 and the data signal DATA are transmitted, and the plurality of terminals are mounted on the end of the base substrate B1 on the -Z2 side so that they are arranged in parallel along the side 822.

[0205] Connectors CN3b-4, CN3b-5, and CN3b-6 are positioned on the +Z2 side of connector CN2, aligned along the Y2 axis from the +Y2 side to the -Y2 side in the order connector CN3b-4, connector CN3b-5, and connector CN3b-6.

[0206] The connector CN3b-4 is connected to the connector CN3a of the drive circuit module DRV4. That is, the connector CN3b-4 has a plurality of terminals through which the drive signals COMA4, COMB4, and COMC4 output by the drive signal output circuit 50-4 and the reference voltage signal VBS4 are transmitted. The connector CN3b-5 is connected to the connector CN3a of the drive circuit module DRV5. That is, the connector CN3b-5 has a plurality of terminals through which the drive signals COMA5, COMB5, and COMC5 output by the drive signal output circuit 50-5 and the reference voltage signal VBS5 are transmitted. The connector CN3b-6 is connected to the connector CN3a of the drive circuit module DRV6. That is, the connector CN3b-6 has a plurality of terminals through which the drive signals COMA6, COMB6, and COMC6 output by the drive signal output circuit 50-6 and the reference voltage signal VBS6 are transmitted. The connectors CN3b-4, CN3b-5, and CN3b-6 are provided on the base substrate B1 so that the multiple terminals that each have are arranged in parallel along the Z2 axis.

[0207] Connectors CN3b-1, CN3b-2, and CN3b-3 are located on the +Z2 side of connectors CN3b-4, CN3b-5, and CN3b-6, along the Y2 axis, from the +Y2 side to the -Y2 side, in the order of connector CN3b-1, connector CN3b-2, and connector CN3b-3.

[0208] The connector CN3b-1 is connected to the connector CN3a of the drive circuit module DRV1. That is, the connector CN3b-1 has a plurality of terminals through which the drive signals COMA1, COMB1, and COMC1 output by the drive signal output circuit 50-1 and the reference voltage signal VBS1 are transmitted. The connector CN3b-2 is connected to the connector CN3a of the drive circuit module DRV2. That is, the connector CN3b-2 has a plurality of terminals through which the drive signals COMA2, COMB2, and COMC2 output by the drive signal output circuit 50-2 and the reference voltage signal VBS2 are transmitted. The connector CN3b-3 is connected to the connector CN3a of the drive circuit module DRV3. That is, the connector CN3b-3 has a plurality of terminals through which the drive signals COMA3, COMB3, and COMC3 output by the drive signal output circuit 50-3 and the reference voltage signal VBS3 are transmitted. The connectors CN3b-1, CN3b-2, and CN3b-3 are provided on the base substrate B1 so that the multiple terminals that each have are arranged in parallel along the Z2 axis.

[0209] As described above, on base substrate B1, connectors CN3b-1, CN3b-2, and CN3b-3 are located farther from connector CN2 than connectors CN3b-4, CN3b-5, and CN3b-6 are. In other words, on base substrate B1, the shortest distance between connectors CN3b-1, CN3b-2, and CN3b-3 and connector CN2 is longer than the shortest distance between connectors CN3b-4, CN3b-5, and CN3b-6 and connector CN2. Therefore, the drive signal output circuit 50-1 included in the drive circuit module DRV1 connected to the connector CN3b-1, the drive signal output circuit 50-2 included in the drive circuit module DRV2 connected to the connector CN3b-2, and the drive signal output circuit 50-3 included in the drive circuit module DRV3 connected to the connector CN3b-3 are located farther from the connector CN2 than the drive signal output circuit 50-4 included in the drive circuit module DRV4 connected to the connector CN3b-4, the drive signal output circuit 50-5 included in the drive circuit module DRV5 connected to the connector CN3b-5, and the drive signal output circuit 50-6 included in the drive circuit module DRV6 connected to the connector CN3b-6. In other words, the shortest distance between the drive signal output circuits 50-1, 50-2, 50-3 and the connector CN2, and the shortest distance between the reference voltage signal output circuit 460 included in each of the drive signal output circuits 50-1, 50-2, 50-3 and the connector CN2 is longer than the shortest distance between the drive signal output circuits 50-4, 50-5, 50-6 and the connector CN2, and the shortest distance between the reference voltage signal output circuit 460 included in each of the drive signal output circuits 50-4, 50-5, 50-6 and the connector CN2.

[0210] The two connectors CN4b are positioned side by side along the Y2 axis on the +Z2 side of the connectors CN3b-1, CN3b-2, and CN3b-3. The two connectors CN4b form a BtoB connector by mating with a connector (not shown) provided on the component mounting surface on the -X2 side of the conversion circuit board B2. This electrically connects the conversion circuit board B2 to the base board B1. That is, the two connectors CN4b have multiple terminals through which various signals, including the data signal DATA and the basic drive data signals dA1 to dA6, dB1 to dB6, and dC1 to dC6, are transmitted. The two connectors CN4b are mounted on the base board B1 so that their multiple terminals are arranged side by side along the Z2 axis.

[0211] As shown in FIG. 22, capacitors 110-1 to 110-6, 190-1 to 190-6, a first step-down voltage circuit 150a, and a second step-down voltage circuit 150b are provided on a surface 802 of the base substrate B1.

[0212] Capacitors 190-4 to 190-6 are positioned in the normal direction to surface 801 of base substrate B1, and when base substrate B1 is viewed along the X2 axis, between connector CN2, which is located at the end of base substrate B1 on the -Z2 side, and connectors CN3b-4, CN3b-5, and CN3b-6, which are positioned side by side along the Y2 axis, from the +Y2 side to the -Y2 side, in the order of capacitor 190-4, capacitor 190-5, and capacitor 190-6.

[0213] In this case, capacitor 190-4 is provided on base substrate B1 so that the shortest distance between capacitor 190-4 and connector CN3b-4 is shorter than the shortest distance between capacitor 190-5 and connector CN3b-4 and the shortest distance between capacitor 190-6 and connector CN3b-4, capacitor 190-5 is provided on base substrate B1 so that the shortest distance between capacitor 190-5 and connector CN3b-5 is shorter than the shortest distance between capacitor 190-4 and connector CN3b-5 and the shortest distance between capacitor 190-6 and connector CN3b-5, and capacitor 190-6 is provided on base substrate B1 so that the shortest distance between capacitor 190-6 and connector CN3b-6 is shorter than the shortest distance between capacitor 190-4 and connector CN3b-6 and the shortest distance between capacitor 190-5 and connector CN3b-6.

[0214] The capacitor 190-4 is mounted on the base substrate B1 so that one end to which the reference voltage signal VBS4 is supplied, the positive pole of the electrolytic capacitor serving as the capacitor 190-4, is on the -Z2 side, and the other end to which the ground signal is supplied, the negative pole of the electrolytic capacitor serving as the capacitor 190-4, is on the +Z2 side, and these one and other ends are positioned along the Z2 axis. That is, the capacitor 190-4 is mounted on the base substrate B1 so that one end to which the reference voltage signal VBS4 is supplied is on the connector CN2 side that outputs the reference voltage signal VBS4 to the discharge unit 20, and the other end to which the ground signal is supplied is on the connector CN3b-4 side to which the drive signals COMA4, COMB4, and COMC4 are supplied.

[0215] Similarly, the capacitor 190-5 is mounted on the base substrate B1 so that one end to which the reference voltage signal VBS5 is supplied, the positive pole of the electrolytic capacitor serving as the capacitor 190-5, is on the -Z2 side, and the other end to which the ground signal is supplied, the negative pole of the electrolytic capacitor serving as the capacitor 190-5, is on the +Z2 side, and these one and other ends are positioned along the Z2 axis. That is, the capacitor 190-5 is mounted on the base substrate B1 so that one end to which the reference voltage signal VBS5 is supplied is on the connector CN2 side that outputs the reference voltage signal VBS5 to the discharge unit 20, and the other end to which the ground signal is supplied is on the connector CN3b-5 side to which the drive signals COMA5, COMB5, and COMC5 are supplied.

[0216] Similarly, the capacitor 190-6 is mounted on the base substrate B1 so that one end to which the reference voltage signal VBS6 is supplied, the positive pole of the electrolytic capacitor serving as the capacitor 190-6, is on the -Z2 side, and the other end to which the ground signal is supplied, the negative pole of the electrolytic capacitor serving as the capacitor 190-6, is on the +Z2 side, and these one and other ends are positioned along the Z2 axis. That is, the capacitor 190-6 is mounted on the base substrate B1 so that one end to which the reference voltage signal VBS6 is supplied is on the connector CN2 side that outputs the reference voltage signal VBS6 to the discharge unit 20, and the other end to which the ground signal is supplied is on the connector CN3b-6 side to which the drive signals COMA6, COMB6, and COMC6 are supplied.

[0217] Capacitors 190-1 to 190-3 are positioned in the normal direction to surface 801 of base substrate B1, and when base substrate B1 is viewed along the X2 axis, between connectors CN3b-4, CN3b-5, and CN3b-6, which are positioned in a row along the Y2 axis, and connectors CN3b-1, CN3b-2, and CN3b-3, which are positioned in a row along the Y2 axis, from the +Y2 side to the -Y2 side, in the order of capacitor 190-1, capacitor 190-2, and capacitor 190-3.

[0218] In this case, capacitor 190-1 is provided on base substrate B1 so that the shortest distance between capacitor 190-1 and connector CN3b-1 is shorter than the shortest distance between capacitor 190-2 and connector CN3b-1 and the shortest distance between capacitor 190-3 and connector CN3b-1, capacitor 190-2 is provided on base substrate B1 so that the shortest distance between capacitor 190-2 and connector CN3b-2 is shorter than the shortest distance between capacitor 190-1 and connector CN3b-2 and the shortest distance between capacitor 190-3 and connector CN3b-2, and capacitor 190-3 is provided on base substrate B1 so that the shortest distance between capacitor 190-3 and connector CN3b-3 is shorter than the shortest distance between capacitor 190-1 and connector CN3b-3 and the shortest distance between capacitor 190-2 and connector CN3b-3.

[0219] The capacitor 190-1 is mounted on the base substrate B1 so that one end to which the reference voltage signal VBS1 is supplied, the positive pole of the electrolytic capacitor serving as the capacitor 190-1, is on the -Z2 side, and the other end to which the ground signal is supplied, the negative pole of the electrolytic capacitor serving as the capacitor 190-1, is on the +Z2 side, and these one and other ends are positioned along the Z2 axis. That is, the capacitor 190-1 is mounted on the base substrate B1 so that one end to which the reference voltage signal VBS1 is supplied is on the connector CN2 side that outputs the reference voltage signal VBS1 to the discharge unit 20, and the other end to which the ground signal is supplied is on the connector CN3b-1 side to which the drive signals COMA1, COMB1, and COMC1 are supplied.

[0220] Similarly, the capacitor 190-2 is mounted on the base substrate B1 so that one end to which the reference voltage signal VBS2 is supplied, the positive pole of the electrolytic capacitor serving as capacitor 190-2, is on the -Z2 side, and the other end to which the ground signal is supplied, the negative pole of the electrolytic capacitor serving as capacitor 190-2, is on the +Z2 side, and these one and other ends are positioned along the Z2 axis. That is, the capacitor 190-2 is mounted on the base substrate B1 so that one end to which the reference voltage signal VBS2 is supplied, is on the connector CN2 side that outputs the reference voltage signal VBS2 to the discharge unit 20, and the other end to which the ground signal is supplied, is on the connector CN3b-2 side to which the drive signals COMA2, COMB2, and COMC2 are supplied.

[0221] Similarly, the capacitor 190-3 is mounted on the base substrate B1 so that one end to which the reference voltage signal VBS3 is supplied, the positive pole of the electrolytic capacitor serving as the capacitor 190-3, is on the -Z2 side, and the other end to which the ground signal is supplied, the negative pole of the electrolytic capacitor serving as the capacitor 190-3, is on the +Z2 side, and the one and other ends are positioned along the Z2 axis. That is, the capacitor 190-3 is mounted on the base substrate B1 so that one end to which the reference voltage signal VBS3 is supplied is on the connector CN2 side that outputs the reference voltage signal VBS3 to the discharge unit 20, and the other end to which the ground signal is supplied is on the connector CN3b-3 side to which the drive signals COMA3, COMB3, and COMC3 are supplied.

[0222] That is, the shortest distance between the connector CN2 and the capacitors 190-1 to 190-3 is longer than the shortest distance between the connector CN2 and the capacitors 190-4 to 190-6.

[0223] Capacitors 110-4 to 110-6 are positioned in the normal direction to surface 801 of base substrate B1, and when base substrate B1 is viewed along the X2 axis, between connectors CN3b-4, CN3b-5, and CN3b-6, which are positioned in a row along the Y2 axis, and capacitors 190-1, 190-2, and 190-3, which are positioned in a row along the Y2 axis, from the +Y2 side to the -Y2 side, in the order of capacitor 110-4, capacitor 110-5, and capacitor 110-6.

[0224] In this case, capacitor 110-4 is provided on base substrate B1 so that the shortest distance between capacitor 110-4 and connector CN3b-4 is shorter than the shortest distance between capacitor 110-5 and connector CN3b-4 and the shortest distance between capacitor 110-6 and connector CN3b-4, capacitor 110-5 is provided on base substrate B1 so that the shortest distance between capacitor 110-5 and connector CN3b-5 is shorter than the shortest distance between capacitor 110-4 and connector CN3b-5 and the shortest distance between capacitor 110-6 and connector CN3b-5, and capacitor 110-6 is provided on base substrate B1 so that the shortest distance between capacitor 110-6 and connector CN3b-6 is shorter than the shortest distance between capacitor 110-4 and connector CN3b-6 and the shortest distance between capacitor 110-5 and connector CN3b-6.

[0225] Capacitor 110-4 is mounted on base substrate B1 so that one end to which voltage signal VHV is supplied, the positive pole of the electrolytic capacitor serving as capacitor 110-4, is on the -Z2 side, and the other end to which a ground signal is supplied, the negative pole of the electrolytic capacitor serving as capacitor 110-4, is on the +Z2 side, and the one end and the other end are positioned along the Z2 axis. Similarly, capacitor 110-5 is mounted on base substrate B1 so that one end to which voltage signal VHV is supplied, the positive pole of the electrolytic capacitor as capacitor 110-5, is on the -Z2 side, and the other end to which a ground signal is supplied, the negative pole of the electrolytic capacitor as capacitor 110-5, is on the +Z2 side, and that the one and other ends are positioned along the Z2 axis; capacitor 110-6 is mounted on base substrate B1 so that one end to which voltage signal VHV is supplied, the positive pole of the electrolytic capacitor as capacitor 110-6, is on the -Z2 side, and the other end to which a ground signal is supplied, the negative pole of the electrolytic capacitor as capacitor 110-6, is on the +Z2 side, and that the one and other ends are positioned along the Z2 axis.

[0226] Capacitors 110-1 to 110-3 are positioned in the normal direction to surface 801 of base substrate B1, and when base substrate B1 is viewed along the X2 axis, between connectors CN3b-1, CN3b-2, and CN3b-3, which are positioned in a row along the Y2 axis, and connector CN4b, which is positioned in a row along the Y2 axis, from the +Y2 side to the -Y2 side, in the order of capacitor 110-1, capacitor 110-2, and capacitor 110-3.

[0227] In this case, capacitor 110-1 is provided on base substrate B1 so that the shortest distance between capacitor 110-1 and connector CN3b-1 is shorter than the shortest distance between capacitor 110-2 and connector CN3b-1 and the shortest distance between capacitor 110-3 and connector CN3b-1, capacitor 110-2 is provided on base substrate B1 so that the shortest distance between capacitor 110-2 and connector CN3b-2 is shorter than the shortest distance between capacitor 110-1 and connector CN3b-2 and the shortest distance between capacitor 110-3 and connector CN3b-2, and capacitor 110-3 is provided on base substrate B1 so that the shortest distance between capacitor 110-3 and connector CN3b-3 is shorter than the shortest distance between capacitor 110-1 and connector CN3b-3 and the shortest distance between capacitor 110-2 and connector CN3b-3.

[0228] Capacitor 110-1 is mounted on base substrate B1 so that one end to which voltage signal VHV is supplied, the positive pole of the electrolytic capacitor serving as capacitor 110-1, is on the -Z2 side, and the other end to which a ground signal is supplied, the negative pole of the electrolytic capacitor serving as capacitor 110-1, is on the +Z2 side, and the one end and the other end are positioned along the Z2 axis. Similarly, capacitor 110-2 is mounted on base substrate B1 so that one end to which voltage signal VHV is supplied, the positive pole of the electrolytic capacitor as capacitor 110-2, is on the -Z2 side, and the other end to which a ground signal is supplied, the negative pole of the electrolytic capacitor as capacitor 110-2, is on the +Z2 side, and that the one and other ends are positioned along the Z2 axis; capacitor 110-3 is mounted on base substrate B1 so that one end to which voltage signal VHV is supplied, the positive pole of the electrolytic capacitor as capacitor 110-3, is on the -Z2 side, and that the other end to which a ground signal is supplied, the negative pole of the electrolytic capacitor as capacitor 110-3, is on the +Z2 side, and that the one and other ends are positioned along the Z2 axis.

[0229] The first step-down circuit 150a is located in the normal direction of the surface 801 of the base substrate B1, and is located between the capacitors 110-1, 110-2, and 110-3, which are located side by side along the Y2 axis, when the base substrate B1 is viewed along the X2 axis, and the connector CN4b, which is located side by side along the Y2 axis.

[0230] In addition, the second step-down circuit 150b is located on the +Z2 side of the connector CN4b, which is located next to it along the Y2 axis, in the normal direction of the surface 801 of the base substrate B1, when viewing the base substrate B1 along the X2 axis.

[0231] As described above, base substrate B1 includes side 821, side 822 located opposite side 821, side 823, and side 824 located opposite side 823. Connector CN2, connectors CN3b-1 to CN3b-6, and two connectors CN4b are provided on surface 801 of base substrate B1, and capacitors 110-1 to 110-6, 190-1 to 190-6, first step-down circuit 150a, and second step-down circuit 150b are provided on surface 802 of base substrate B1.

[0232] The connectors CN3a of each of the drive circuit modules DRV1 to DRV6 are fitted into the connectors CN3b-1 to CN3b-6 provided on the surface 801 of the base substrate B1. The connector CN3b-1 provided on the surface 801 of the base substrate B1 is fitted into the connector CN3a of the drive circuit module DRV1, thereby electrically connecting the drive circuit board DRB on which the drive signal output circuit 50-1 of the drive circuit module DRV1 is mounted to the base substrate B1, and the connector CN3b-i provided on the surface 801 of the base substrate B1 is fitted into the connector CN3a of the drive circuit module DRVi, thereby electrically connecting the drive circuit board DRB on which the drive signal output circuit 50-i of the drive circuit module DRVi is mounted to the base substrate B1.

[0233] In other words, the drive circuit board DRB on which the drive signal output circuit 50-1 of the drive circuit module DRV1 is mounted is electrically connected to the base substrate B1 via a BtoB connector consisting of connector CN3b-1 and connector CN3a, and the drive circuit board DRB on which the drive signal output circuit 50-i of the drive circuit module DRVi is mounted is electrically connected to the base substrate B1 via a BtoB connector consisting of connector CN3b-i and connector CN3a.

[0234] Therefore, the drive signal output circuits 50-1 to 50-6 that output the drive signals COMA1 to COMA6, COMB1 to COMB6, and COMOC1 to COMC6 and the reference voltage signals VBS1 to VBS6 are located on the surface 801 side of the base substrate B1. That is, the shortest distance between surface 801 and drive circuits 52a, 52b, 52c that each of drive signal output circuits 50-1 to 50-6 has is shorter than the shortest distance between surface 802 and drive circuits 52a, 52b, 52c that each of drive signal output circuits 50-1 to 50-6, and the shortest distance between surface 801 and reference voltage signal output circuits 460 that each of drive circuits 52a, 52b, 52c that each of drive signal output circuits 50-1 to 50-6 has is shorter than the shortest distance between surface 802 and reference voltage signal output circuits 460 that each of drive circuits 52a, 52b, 52c that each of drive signal output circuits 50-1 to 50-6 has. In other words, the base substrate B1 is located between the drive signal output circuits 50-1 to 50-6 and the capacitors 110-1 to 110-6, 190-1 to 190-6, the first step-down voltage circuit 150a, and the second step-down voltage circuit 150b.

[0235] Then, via a BtoB connector consisting of connector CN3b-1 and connector CN3a, the drive signals COMA1, COMB1, COMC1 output by the drive signal output circuit 50-1 of the drive circuit module DRV1 and the reference voltage signal VBS1 are supplied to the base substrate B1, and via a BtoB connector consisting of connector CN3b-i and connector CN3a, the drive signals COMAi, COMBi, COMCi output by the drive signal output circuit 50-i of the drive circuit module DRVi and the reference voltage signal VBSi are supplied to the base substrate B1. That is, the base substrate B1 has an electrode which is a connection point electrically connected to the connector CN3b-1 and to which the drive signals COMA1, COMB1, COMC1 and the reference voltage signal VBS1 are supplied, an electrode which is a connection point electrically connected to the connector CN3b-2 and to which the drive signals COMA2, COMB2, COMC2 and the reference voltage signal VBS2 are supplied, an electrode which is a connection point electrically connected to the connector CN3b-3 and to which the drive signals COMA3, COMB3, COMC3 and the reference voltage signal VBS3 are supplied, an electrode which is a connection point electrically connected to the connector CN3b-4 and to which the drive signals COMA4, COMB4, COMC4 and the reference voltage signal VBS4 are supplied, an electrode which is a connection point electrically connected to the connector CN3b-5 and to which the drive signals COMA5, COMB5, COMC5 and the reference voltage signal VBS5 are supplied, and an electrode which is a connection point electrically connected to the connector CN3b-6 and to which the drive signals COMA6, COMB6, COMC6 and the reference voltage signal VBS6 are supplied.

[0236] Furthermore, when viewed along the X2 axis, which is perpendicular to the Z2 axis connecting sides 821 and 822 of base substrate B1, capacitor 190-1 is located between connector CN2 and connector CN3b-1, between connector CN2 and the electrode whereby connector CN3b-1 is electrically connected to base substrate B1, capacitor 190-2 is located between connector CN2 and connector CN3b-2, between connector CN2 and the electrode whereby connector CN3b-2 is electrically connected to base substrate B1, and capacitor 190-3 is located between connector CN2 and connector CN3b-3, between connector CN2 and the electrode whereby connector CN3b-3 is electrically connected to base substrate B1.

[0237] At this time, the capacitor 190-1 is arranged on the base board B1 so that the shortest distance between the connector CN2 and the positive pole of one end of the capacitor 190-1 to which the reference voltage signal VBS1 is supplied is shorter than the shortest distance between the connector CN2 and the negative pole of the other end of the capacitor 190-1 to which the ground signal is supplied, and the shortest distance between the connector CN3b-1 and the positive pole of one end of the capacitor 190-1 to which the reference voltage signal VBS1 is supplied is longer than the shortest distance between the connector CN3b-1 and the negative pole of the other end of the capacitor 190-1 to which the ground signal is supplied. The capacitor 190-2 is arranged on the base board B1 so that the shortest distance between the connector CN2 and the positive pole of one end of the capacitor 190-2 to which the reference voltage signal VBS2 is supplied is shorter than the shortest distance between the connector CN2 and the negative pole of the other end of the capacitor 190-2 to which the ground signal is supplied, and The capacitor 190-3 is arranged on the base substrate B1 so that the shortest distance between the connector CN2 and the + pole of one end of the capacitor 190-2 to which the reference voltage signal VBS2 is supplied is longer than the shortest distance between the connector CN3b-2 and the - pole of the other end of the capacitor 190-2 to which the ground signal is supplied, and the capacitor 190-3 is arranged on the base substrate B1 so that the shortest distance between the connector CN2 and the + pole of one end of the capacitor 190-3 to which the reference voltage signal VBS3 is supplied is shorter than the shortest distance between the connector CN2 and the - pole of the other end of the capacitor 190-3 to which the ground signal is supplied, and the shortest distance between the connector CN3b-3 and the + pole of one end of the capacitor 190-3 to which the reference voltage signal VBS3 is supplied is longer than the shortest distance between the connector CN3b-3 and the - pole of the other end of the capacitor 190-3 to which the ground signal is supplied.

[0238] Similarly, when viewed along the X2 axis, which is perpendicular to the Z2 axis connecting sides 821 and 822 of base substrate B1, capacitor 190-4 is located between connector CN2 and connector CN3b-4, between connector CN2 and the electrode whereby connector CN3b-4 is electrically connected to base substrate B1, capacitor 190-5 is located between connector CN2 and connector CN3b-5, between connector CN2 and the electrode whereby connector CN3b-5 is electrically connected to base substrate B1, and capacitor 190-6 is located between connector CN2 and connector CN3b-6, between connector CN2 and the electrode whereby connector CN3b-6 is electrically connected to base substrate B1.

[0239] At this time, the capacitor 190-4 is arranged on the base board B1 so that the shortest distance between the connector CN2 and the positive pole of one end of the capacitor 190-4 to which the reference voltage signal VBS4 is supplied is shorter than the shortest distance between the connector CN2 and the negative pole of the other end of the capacitor 190-4 to which the ground signal is supplied, and the shortest distance between the connector CN3b-4 and the positive pole of one end of the capacitor 190-4 to which the reference voltage signal VBS4 is supplied is longer than the shortest distance between the connector CN3b-4 and the negative pole of the other end of the capacitor 190-4 to which the ground signal is supplied, and the capacitor 190-5 is arranged on the base board B1 so that the shortest distance between the connector CN2 and the positive pole of one end of the capacitor 190-5 to which the reference voltage signal VBS5 is supplied is shorter than the shortest distance between the connector CN2 and the negative pole of the other end of the capacitor 190-5 to which the ground signal is supplied, The capacitor 190-6 is arranged on the base substrate B1 so that the shortest distance between the connector CN2 and the + pole of one end of the capacitor 190-5 to which the reference voltage signal VBS6 is supplied is shorter than the shortest distance between the connector CN2 and the - pole of the other end of the capacitor 190-6 to which the ground signal is supplied, and the capacitor 190-6 is arranged on the base substrate B1 so that the shortest distance between the connector CN2 and the + pole of one end of the capacitor 190-6 to which the reference voltage signal VBS6 is supplied is longer than the shortest distance between the connector CN2 and the - pole of the other end of the capacitor 190-6 to which the ground signal is supplied, and the shortest distance between the connector CN3b-6 and the + pole of one end of the capacitor 190-6 to which the reference voltage signal VBS6 is supplied is longer than the shortest distance between the connector CN3b-6 and the - pole of the other end of the capacitor 190-6 to which the ground signal is supplied.

[0240] At this time, the capacitor 190-1 is positioned along the Z2 axis so that the positive pole at one end to which the reference voltage signal VBS1 is supplied is on the -Z2 side and the negative pole at the other end to which the ground signal is supplied is on the +Z2 side; the capacitor 190-2 is positioned along the Z2 axis so that the positive pole at one end to which the reference voltage signal VBS2 is supplied is on the -Z2 side and the negative pole at the other end to which the ground signal is supplied is on the +Z2 side; the capacitor 190-3 is positioned along the Z2 axis so that the positive pole at one end to which the reference voltage signal VBS3 is supplied is on the -Z2 side and the negative pole at the other end to which the ground signal is supplied is on the +Z2 side; It is preferable that capacitor 190-4 is positioned along the Z2 axis so that the positive pole at one end to which reference voltage signal VBS4 is supplied is on the -Z2 side and the negative pole at the other end to which a ground signal is supplied is on the +Z2 side, capacitor 190-5 is positioned along the Z2 axis so that the positive pole at one end to which reference voltage signal VBS5 is supplied is on the -Z2 side and the negative pole at the other end to which a ground signal is supplied is on the +Z2 side, and capacitor 190-6 is positioned along the Z2 axis so that the positive pole at one end to which reference voltage signal VBS6 is supplied is on the -Z2 side and the negative pole at the other end to which a ground signal is supplied is on the +Z2 side.

[0241] In addition to the electronic components described above, various other electronic components may be mounted on the base substrate B1.

[0242] Next, an example of an optimum wiring pattern formed on the base substrate B1, which is a multilayer substrate, will be described, which is an example of an optimum wiring pattern formed on the base substrate B1 for propagating the drive signals COMA1-COMA6, COMB1-COMB6, COMC1-COMC6, and reference voltage signals VBS1-VBS6. Fig. 23 is a diagram showing an example of a wiring pattern formed on the base substrate B1 for propagating the drive signals COMA1-COMA6, Fig. 24 is a diagram showing an example of a wiring pattern formed on the base substrate B1 for propagating the drive signals COMB1-COMB6, Fig. 25 is a diagram showing an example of a wiring pattern formed on the base substrate B1 for propagating the drive signals COMC1-COMC6 and reference voltage signals VBS1-VBS3, and Fig. 26 is a diagram showing an example of a wiring pattern formed on the base substrate B1 for propagating the reference voltage signals VBS4-VBS6.

[0243] As shown in FIG. 23, the wirings Wca1 to Wca6 through which the drive signals COMA1 to COMA6 propagate are formed in an internal wiring layer 820-k (k is any one of 1 to m-2).

[0244] The wiring Wca1 electrically connects one of the multiple terminals of the connector CN3b-1, which is electrically connected to the drive circuit module DRV1, that inputs the drive signal COMA1 to the base substrate B1, to one of the multiple terminals of the connector CN2, which is electrically connected to the ejection unit 20, that supplies the drive signal COMA1 to the print head 23-1, and propagates the drive signal COMA1.

[0245] The wiring Wca2 is located on the -Y2 side of the wiring Wca1, and electrically connects one of the multiple terminals of the connector CN3b-2, which is electrically connected to the drive circuit module DRV2, that inputs the drive signal COMA2 to the base substrate B1, to one of the multiple terminals of the connector CN2, which is electrically connected to the ejection unit 20, that supplies the drive signal COMA2 to the print head 23-2, and propagates the drive signal COMA2.

[0246] The wiring Wca3 is located on the -Y2 side of the wiring Wca2, and electrically connects the terminal of the connector CN3b-3, which is electrically connected to the drive circuit module DRV3, that inputs the drive signal COMA3 to the base substrate B1, to the terminal of the connector CN2, which is electrically connected to the ejection unit 20, that supplies the drive signal COMA3 to the print head 23-3, and propagates the drive signal COMA3.

[0247] Wiring Wca4 is located between wiring Wca1 and wiring Wca2 in a plan view of base substrate B1 when viewing base substrate B1 along the X2 axis, and electrically connects a terminal of a connector CN3b-4 electrically connected to drive circuit module DRV4 that inputs a drive signal COMA4 to base substrate B1 to a terminal of a connector CN2 electrically connected to discharge unit 20 that supplies a drive signal COMA4 to print head 23-4, thereby propagating the drive signal COMA4.

[0248] Wiring Wca5 is located between wiring Wca2 and wiring Wca3 in a plan view of base substrate B1 when viewing base substrate B1 along the X2 axis, and electrically connects one of multiple terminals of connector CN3b-5, which is electrically connected to drive circuit module DRV5, that inputs drive signal COMA5 to base substrate B1, to one of multiple terminals of connector CN2, which is electrically connected to discharge unit 20, that supplies drive signal COMA5 to print head 23-5, thereby propagating drive signal COMA5.

[0249] The wiring Wca6 is located on the -Y2 side of the wiring Wca3, and electrically connects the terminal of the connector CN3b-6, which is electrically connected to the drive circuit module DRV6, that inputs the drive signal COMA6 to the base substrate B1, to the terminal of the connector CN2, which is electrically connected to the ejection unit 20, that supplies the drive signal COMA6 to the print head 23-6, and propagates the drive signal COMA6.

[0250] That is, the internal wiring layer 820-k of the base substrate B1 is formed with a wiring Wca1 through which the drive signal COMA1 propagates, a wiring Wca2 through which the drive signal COMA2 propagates, a wiring Wca3 through which the drive signal COMA3 propagates, a wiring Wca4 through which the drive signal COMA4 propagates, a wiring Wca5 through which the drive signal COMA5 propagates, and a wiring Wca6 through which the drive signal COMA6 propagates. In the base substrate B1, the wirings Wca1 to Wca6 are located near the connector CN2 electrically connected to the discharge unit 20 along the Y2 axis, from the +Y2 side to the -Y2 side, in the order of wiring Wca1, wiring Wca4, wiring Wca2, wiring Wca5, wiring Wca3, and wiring Wca6.

[0251] As shown in FIG. 24, the wirings Wcb1 to Wcb6 through which the drive signals COMB1 to COMB6 propagate are formed in the internal wiring layer 820-(k+2).

[0252] The wiring Wcb1 electrically connects one of the multiple terminals of the connector CN3b-1, which is electrically connected to the drive circuit module DRV1, that inputs the drive signal COMB1 to the base substrate B1, to one of the multiple terminals of the connector CN2, which is electrically connected to the ejection unit 20, that supplies the drive signal COMB1 to the print head 23-1, and propagates the drive signal COMB1.

[0253] The wiring Wcb2 is located on the -Y2 side of the wiring Wcb1, and electrically connects the terminal of the connector CN3b-2, which is electrically connected to the drive circuit module DRV2, that inputs the drive signal COMB2 to the base substrate B1, to the terminal of the connector CN2, which is electrically connected to the ejection unit 20, that supplies the drive signal COMB2 to the print head 23-2, and propagates the drive signal COMB2.

[0254] The wiring Wcb3 is located on the -Y2 side of the wiring Wcb2, and electrically connects the terminal of the connector CN3b-3, which is electrically connected to the drive circuit module DRV3, that inputs the drive signal COMB3 to the base substrate B1, to the terminal of the connector CN2, which is electrically connected to the ejection unit 20, that supplies the drive signal COMB3 to the print head 23-3, and propagates the drive signal COMB3.

[0255] Wiring Wcb4 is located between wiring Wcb1 and wiring Wcb2 in a plan view of base substrate B1 when viewing base substrate B1 along the X2 axis, and electrically connects a terminal of a connector CN3b-4 electrically connected to drive circuit module DRV4 that inputs drive signal COMB4 to base substrate B1 with a terminal of a connector CN2 electrically connected to discharge unit 20 that supplies drive signal COMB4 to print head 23-4, thereby propagating drive signal COMB4.

[0256] Wiring Wcb5 is located between wiring Wcb2 and wiring Wcb3 in a plan view of base substrate B1 when viewing base substrate B1 along the X2 axis, and electrically connects the terminal of connector CN3b-5, which is electrically connected to drive circuit module DRV5, that inputs drive signal COMB5 to base substrate B1, to the terminal of connector CN2, which is electrically connected to discharge unit 20, that supplies drive signal COMB5 to print head 23-5, thereby propagating drive signal COMB5.

[0257] Wiring Wcb6 is located on the -Y2 side of wiring Wcb3, and electrically connects the terminal of a connector CN3b-6 electrically connected to the drive circuit module DRV6 that inputs a drive signal COMB6 to the base substrate B1 with the terminal of a connector CN2 electrically connected to the ejection unit 20 that supplies the drive signal COMB6 to the print head 23-6, thereby propagating the drive signal COMB6.

[0258] That is, the base substrate B1 has wiring Wcb1 through which drive signal COMB1 propagates, wiring Wcb2 through which drive signal COMB2 propagates, wiring Wcb3 through which drive signal COMB3 propagates, wiring Wcb4 through which drive signal COMB4 propagates, wiring Wcb5 through which drive signal COMB5 propagates, and wiring Wcb6 through which drive signal COMB6 propagates, which are formed in the internal wiring layer 820-(k+2), and the wirings Wcb1 to Wcb6 are located near the connector CN2 electrically connected to the discharge unit 20, along the Y2 axis from the +Y2 side to the -Y2 side, in the order of wiring Wcb1, wiring Wcb4, wiring Wcb2, wiring Wcb5, wiring Wcb3, wiring Wcb6.

[0259] 25, the wiring lines Wcc1-Wcc6 through which the drive signals COMC1-COMC6 propagate and the wiring lines Wvb1-Wvb3 through which the reference voltage signals VBS1-VBS3 propagate are formed in an internal wiring layer 820-(k+1). In other words, the wiring lines Wcc1-Wcc6 through which the drive signals COMC1-COMC6 propagate and the wiring lines Wvb1-Wvb3 through which the reference voltage signals VBS1-VBS3 propagate are formed in an internal wiring layer 820-(k+1) located between the internal wiring layer 820-k on which the wiring lines Wca1-Wca6 through which the drive signals COMA1-COMA6 propagate are formed and the internal wiring layer 820-(k+2) on which the wiring lines Wcb1-Wcb6 through which the drive signals COMB1-COMB6 propagate are formed.

[0260] The wiring Wvb1 electrically connects a terminal of the connector CN3b-1 electrically connected to the drive circuit module DRV1 that inputs the reference voltage signal VBS1 to the base substrate B1 to a terminal of the connector CN2 electrically connected to the discharge unit 20 that supplies the reference voltage signal VBS1 to the print head 23-1, and propagates the reference voltage signal VBS1. The wiring Wvb1 is also electrically connected to the positive electrode of the capacitor 190-1. The wiring Wvb1 is positioned so that the range of the wiring Wvb1 from the positive electrode of the capacitor 190-1 to the terminal of the connector CN2 that supplies the reference voltage signal VBS1 overlaps with at least a portion of the wiring Wca1 and at least a portion of the wiring Wcb1 when viewed along the X2 axis in a plan view of the base substrate B1.

[0261] The wiring Wvb2 is located on the -Y2 side of the wiring Wvb1 and electrically connects a terminal of the connector CN3b-2, which is electrically connected to the drive circuit module DRV2, that inputs the reference voltage signal VBS2 to the base substrate B1, to a terminal of the connector CN2, which is electrically connected to the discharge unit 20, that supplies the reference voltage signal VBS2 to the print head 23-2, thereby transmitting the reference voltage signal VBS2. The wiring Wvb2 is also electrically connected to the positive electrode of the capacitor 190-2. The wiring Wvb2 is positioned so that, in the range from the positive electrode of the capacitor 190-2 to the terminal of the connector CN2 that supplies the reference voltage signal VBS2, it overlaps with at least a portion of the wiring Wca2 and at least a portion of the wiring Wcb2 when viewed along the X2 axis in a plan view of the base substrate B1.

[0262] The wiring Wvb3 is located on the -Y2 side of the wiring Wvb2 and electrically connects a terminal of the connector CN3b-3 electrically connected to the drive circuit module DRV3 that inputs the reference voltage signal VBS3 to the base substrate B1 and a terminal of the connector CN2 electrically connected to the discharge unit 20 that supplies the reference voltage signal VBS3 to the print head 23-3, thereby propagating the reference voltage signal VBS3. The wiring Wvb3 is also electrically connected to the positive electrode of the capacitor 190-3. The wiring Wvb3 is positioned so that, in the range from the positive electrode of the capacitor 190-3 to the terminal of the connector CN2 that supplies the reference voltage signal VBS3, it overlaps with at least a portion of the wiring Wca3 and at least a portion of the wiring Wcb3 when viewed along the X2 axis in a plan view of the base substrate B1.

[0263] Wire Wcc1 is located on the +Y2 side of wire Wvb1, and propagates the drive signal COMC1 by electrically connecting a terminal of connector CN3b-1, which is electrically connected to drive circuit module DRV1, that inputs the drive signal COMC1 to base substrate B1, to a terminal of connector CN2, which is electrically connected to discharge unit 20, that supplies the drive signal COMC1 to print head 23-1. Wire Wcc1 is located along wire Wvb1, which propagates reference voltage signal VBS1.

[0264] Wire Wcc2 is located on the -Y2 side of wire Wvb1 and on the +Y2 side of wire Wvb2, and electrically connects the terminal of connector CN3b-2, which is electrically connected to drive circuit module DRV2, that inputs drive signal COMC2 to base substrate B1, to the terminal of connector CN2, which is electrically connected to discharge unit 20, that supplies drive signal COMC2 to print head 23-2, and propagates the drive signal COMC2. Wire Wcc2 is located along wire Wvb2, which propagates reference voltage signal VBS2.

[0265] Wire Wcc3 is located on the -Y2 side of wire Wvb2 and on the +Y2 side of wire Wvb3, and electrically connects a terminal of connector CN3b-3 electrically connected to drive circuit module DRV3 that inputs drive signal COMC3 to base substrate B1 to a terminal of connector CN2 electrically connected to discharge unit 20 that supplies drive signal COMC3 to print head 23-3, thereby propagating the drive signal COMC3. Wire Wcc3 is located along wire Wvb3 that propagates reference voltage signal VBS3.

[0266] Wire Wcc4 is located on the -Y2 side of wire Wvb1 and on the +Y2 side of wire Wcc2, and propagates the drive signal COMC4 by electrically connecting the terminal of connector CN3b-4, which is electrically connected to drive circuit module DRV4, that inputs the drive signal COMC4 to base substrate B1, to the terminal of connector CN2, which is electrically connected to discharge unit 20, that supplies the drive signal COMC4 to print head 23-4. Wire Wcc1 is located along wire Wvb1, which propagates reference voltage signal VBS1.

[0267] Wire Wcc5 is located on the -Y2 side of wire Wvb2 and on the +Y2 side of wire Wcc3, and propagates the drive signal COMC5 by electrically connecting a terminal of connector CN3b-5 electrically connected to drive circuit module DRV5 that inputs the drive signal COMC5 to base substrate B1 to a terminal of connector CN2 electrically connected to discharge unit 20 that supplies the drive signal COMC5 to print head 23-5. Wire Wcc5 is located along wire Wvb2 that propagates reference voltage signal VBS2.

[0268] Wire Wcc6 is located on the -Y2 side of wire Wvb3, and propagates the drive signal COMC6 by electrically connecting one of the terminals of connector CN3b-6 electrically connected to drive circuit module DRV6 that inputs the drive signal COMC6 to base substrate B1 to one of the terminals of connector CN2 electrically connected to discharge unit 20 that supplies the drive signal COMC6 to print head 23-6. Wire Wcc6 is located along wire Wvb3 that propagates reference voltage signal VBS3.

[0269] That is, the base substrate B1 includes a wiring Wcc1 through which the drive signal COMC1 propagates, a wiring Wcc2 through which the drive signal COMC2 propagates, a wiring Wcc3 through which the drive signal COMC3 propagates, a wiring Wcc4 through which the drive signal COMC4 propagates, a wiring Wcc5 through which the drive signal COMC5 propagates, and a wiring Wcc6 through which the drive signal COMC6 propagates, as well as a wiring Wvb1 through which the reference voltage signal VBS1 propagates, a wiring Wvb2 through which the reference voltage signal VBS2 propagates, and a wiring Wvb3 through which the reference voltage signal VBS3 propagates. The base substrate B1 has a wiring Wvb2 through which the reference voltage signal VBS2 propagates, and a wiring Wvb3 through which the reference voltage signal VBS3 propagates, and the wirings Wcc1 to Wcc6 and Wvb1 to Wvb3 are located along the Y2 axis in the order of wiring Wcc1, wiring Wvb1, wiring Wcc4, wiring Wcc2, wiring Wvb2, wiring Wcc5, wiring Wcc3, wiring Wvb3, and wiring Wcc6, from the +Y2 side to the -Y2 side, near the connector CN2 electrically connected to the discharge unit 20. When the base substrate B1 is viewed along the X2 axis in a plan view of the base substrate B1, the wiring Wvb1 is located so as to overlap at least a portion of the wiring Wca1 and the wiring Wcb1, and the wiring Wvb2 is located so as to overlap at least a portion of the wiring Wca2 and the wiring Wcb2.

[0270] As shown in FIG. 26, the surface wiring layer 812 is formed with wirings Wvb4 to Wvb6 through which the reference voltage signals VBS4 to VBS6 propagate, and a wiring Wvhv through which the voltage signal VHV propagates.

[0271] The wiring Wvb4 electrically connects, among the multiple terminals of the connector CN3b-4 electrically connected to the drive circuit module DRV4, the terminal that inputs the reference voltage signal VBS4 to the base substrate B1, and among the multiple terminals of the connector CN2 electrically connected to the discharge unit 20, the terminal that supplies the reference voltage signal VBS4 to the print head 23-4, and propagates the reference voltage signal VBS4. The wiring Wvb4 is also electrically connected to the positive electrode of the capacitor 190-4.

[0272] Wire Wvb5 is located on the -Y2 side of wire Wvb4, and propagates the reference voltage signal VBS5 by electrically connecting a terminal of connector CN3b-5 electrically connected to drive circuit module DRV5 that inputs the reference voltage signal VBS5 to base substrate B1 to a terminal of connector CN2 electrically connected to discharge unit 20 that supplies the reference voltage signal VBS5 to print head 23-5. Wire Wvb5 is also electrically connected to the positive terminal of capacitor 190-5.

[0273] The wiring Wvb6 is located on the -Y2 side of the wiring Wvb5, and electrically connects one of the multiple terminals of the connector CN3b-6, which is electrically connected to the drive circuit module DRV6, that inputs the reference voltage signal VBS6 to the base substrate B1, to one of the multiple terminals of the connector CN2, which is electrically connected to the ejection unit 20, that supplies the reference voltage signal VBS6 to the print head 23-6, and propagates the reference voltage signal VBS6.

[0274] One end of the wiring Wvhv is electrically connected to the coil 152a and capacitor 153a of the first step-down circuit 150a. As a result, the wiring Wvhv propagates the voltage signal VHV generated by the first step-down circuit 150a. The wiring Wvhv is also electrically connected to the positive poles of the capacitors 110-1 to 110-6 and to the connectors CN3b-1 to CN3b-6. As a result, the voltage signal VHV propagating through the wiring Wvhv is supplied to each of the drive circuit modules DRV1 to DRV6. The wiring Wvhv also bypasses the +Y2 side of the wiring Wvb4 and is electrically connected to the connector CN2. As a result, the voltage signal VHV propagating through the wiring Wvhv is also supplied to the discharge unit 20.

[0275] That is, the surface wiring layer 812 of the base substrate B1 is formed with a wiring Wvb4 that propagates the reference voltage signal VBS4, a wiring Wvb5 that propagates the reference voltage signal VBS5, a wiring Wvb6 that propagates the reference voltage signal VBS6, and a wiring Wvhv that propagates the voltage signal VHV.

[0276] As described above, among the capacitors 190-1 to 190-6 provided on the base substrate B1, the capacitors 190-1 to 190-3 are positioned farther away from the connector CN2 electrically connected to the discharge unit 20 than the capacitors 190-4 to 190-6. In other words, the shortest distance between the connector CN2 and the capacitors 190-1 to 190-3 is longer than the shortest distance between the connector CN2 and the capacitors 190-4 to 190-6.

[0277] At this time, the wiring Wvb1 electrically connects the capacitor 190-1 located away from the connector CN2 to the connector CN2 and propagates the reference voltage signal VBS1. The wiring Wvb1 is provided in the internal wiring layer 820-(k+1) of the multiple internal wiring layers 820, and the wiring Wca1 propagates the drive signal COMA1 input to the print head 23-1 to which the reference voltage signal VBS1 is supplied. The wiring Wca1 is provided in the internal wiring layer 820 adjacent to the internal wiring layer 820-(k+1). The wiring Wcb1, which is provided in 820-(k) and through which the drive signal COMB1 input to the print head 23-1 to which the reference voltage signal VBS1 is supplied propagates, is provided in the internal wiring layer 820-(k+2) adjacent to the internal wiring layer 820-(k+1) among the multiple internal wiring layers 820, and the wiring Wvb1, the wiring Wca1 and the wiring Wcb1 are in the normal direction to the surface 801 of the base substrate B1 and at least partially overlap when the base substrate B1 is viewed along the X2 axis.

[0278] Similarly, a wiring Wvb2 electrically connecting the capacitor 190-2 located away from the connector CN2 to the connector CN2 and transmitting the reference voltage signal VBS2 is provided in the internal wiring layer 820-(k+1) among the multiple internal wiring layers 820, and a wiring Wca2 transmitting the drive signal COMA2 input to the print head 23-2 to which the reference voltage signal VBS2 is supplied is provided in the internal wiring layer 820-(k+1) among the multiple internal wiring layers 820. 20-(k), and the wiring Wcb2 through which the drive signal COMB2 input to the print head 23-2 to which the reference voltage signal VBS2 is supplied propagates is provided in the internal wiring layer 820-(k+2) adjacent to the internal wiring layer 820-(k+1) among the multiple internal wiring layers 820, and the wiring Wvb2, the wiring Wca2 and the wiring Wcb2 are in the normal direction to the surface 801 of the base substrate B1 and at least partially overlap when the base substrate B1 is viewed along the X2 axis.

[0279] Similarly, a wiring Wvb3 electrically connecting the capacitor 190-3 located away from the connector CN2 to the connector CN2 and transmitting the reference voltage signal VBS3 is provided in an internal wiring layer 820-(k+1) among the multiple internal wiring layers 820, and a wiring Wca3 transmitting a drive signal COMA3 input to the print head 23-3 to which the reference voltage signal VBS3 is supplied is provided in an internal wiring layer 820-(k+1) among the multiple internal wiring layers 820. 20-(k), and the wiring Wcb3 through which the drive signal COMB3 input to the print head 23-3 to which the reference voltage signal VBS3 is supplied propagates is provided in the internal wiring layer 820-(k+2) adjacent to the internal wiring layer 820-(k+1) among the multiple internal wiring layers 820, and the wiring Wvb3, the wiring Wca3 and the wiring Wcb3 are in the normal direction to the surface 801 of the base substrate B1 and at least partially overlap when the base substrate B1 is viewed along the X2 axis.

[0280] That is, the wirings Wvb1 to Wvb3, which propagate the reference voltage signals VBS1 to VBS3 output via capacitors 190-1 to 190-3 located away from connector CN2, are located adjacent to the wirings Wca1 to Wca3, which propagate the corresponding drive signals COMA1 to COMA3, and the wirings Wcb1 to Wcb3, which propagate the corresponding drive signals COMB1 to COMB3.

[0281] On the other hand, wiring Wvb4, which electrically connects capacitor 190-4 located near connector CN2 to connector CN2 and propagates reference voltage signal VBS4, is provided on surface wiring layer 812 formed on surface 802 on which capacitor 190-4 is provided, wiring Wvb5, which electrically connects capacitor 190-5 located near connector CN2 to connector CN2 and propagates reference voltage signal VBS5, is provided on surface wiring layer 812 formed on surface 802 on which capacitor 190-5 is provided, and wiring Wvb6, which electrically connects capacitor 190-6 located near connector CN2 to connector CN2 and propagates reference voltage signal VBS6, is provided on surface wiring layer 812 formed on surface 802 on which capacitor 190-6 is provided.

[0282] In addition, wiring Wvb4 to Wvb6 are provided to electrically connect capacitors 190-4 to 190-6 located near connector CN2 to connector CN2 and to transmit reference voltage signals VBS4 to VBS6, and wiring Wvhv is provided on the surface wiring layer 812 to transmit voltage signal VHV.

[0283] Here, print head 23-1 is an example of a first print head, piezoelectric element 60 of print head 23-1 is an example of a first drive element, at least one of drive circuits 52a1, 52b1, and 52c1 is an example of a first drive circuit, reference voltage signal output circuit 460 of at least one of drive circuits 52a1, 52b1, and 52c1 is an example of a first reference voltage signal output circuit, and drive circuit board DRB on which drive circuits 52a1, 52b1, and 52c1 are mounted is an example of a drive circuit board. Also, print head 23-2 is an example of a second print head, piezoelectric element 60 of print head 23-2 is an example of a second drive element, at least one of drive circuits 52a2, 52b2, and 52c2 is an example of a second drive circuit, and reference voltage signal output circuit 460 of at least one of drive circuits 52a2, 52b2, and 52c2 is an example of a second reference voltage signal output circuit. Furthermore, base substrate B1 is an example of a wiring substrate, side 821 is an example of a first side, side 822 is an example of a second side, surface 801 is an example of a first surface, surface 802 is an example of a second surface, among the electrodes formed on base substrate B1 to which connector CN3b-1 is electrically connected, an electrode through which any of drive signals COMA1, COMB1, or COMC1 propagates is an example of a first supply point, and among the electrodes formed on base substrate B1 to which connector CN3b-2 is electrically connected, an electrode through which any of drive signals COMA2, COMB2, or COMC2 propagates is an example of a second supply point. Any of drive signals COMA1, COMB1, or COMC1 is an example of a first drive signal, reference voltage signal VBS1 is an example of a first reference voltage signal, any of drive signals COMA2, COMB2, or COMC2 is an example of a second drive signal, and reference voltage signal VBS2 is an example of a second reference voltage signal.Furthermore, connector CN2 is an example of an output connector, capacitor 190-1 is an example of a first capacitor, one end electrode of capacitor 190-1 to which reference voltage signal VBS1 is supplied is an example of a first electrode, the other end electrode of capacitor 190-1 to which a ground signal is supplied is an example of a second electrode, capacitor 190-2 is an example of a third capacitor, one end electrode of capacitor 190-2 to which reference voltage signal VBS2 is supplied is an example of a fifth electrode, and the other end electrode of capacitor 190-2 to which a ground signal is supplied is an example of a sixth electrode. Furthermore, the Z2 axis is an example of a first axis, and the X2 axis is an example of a second axis.

[0284] 4. Effects In the liquid ejection device 1 of this embodiment configured as described above, the drive unit 10 of the head unit 5 has a first step-down circuit 150a that outputs a voltage signal VHV by stepping down an externally supplied voltage signal VDC, and a second step-down circuit 150b that outputs a voltage signal VDD by stepping down the externally supplied voltage signal VDC. The amplifier circuit 550 and demodulation circuit 560 of the drive circuit 52 output a drive signal COM corresponding to the voltage signal VHV stepped down by the first step-down circuit 150a, and the integrated circuit 500 of the drive circuit 52 outputs amplification control signals Hgd and Lgd in accordance with the voltage signal VDD stepped down by the second step-down circuit 150b, thereby controlling the driving of the amplifier circuit 550.

[0285] In such a head unit 5, the drive unit 10 of the head unit 5 generates the voltage signal VHV by stepping down the voltage signal VDC input from outside, and therefore, even if fluctuations occur in the voltage value of the voltage signal VDC along the propagation path of the voltage signal VDC input to the head unit 5, it is possible to improve the accuracy of the voltage signal VHV input to the amplifier circuit 550 and demodulation circuit 560 of the drive circuit 52. Therefore, even if the propagation path of the voltage signal VDC input to the head unit 5 becomes longer as the liquid ejection device 1 becomes larger and the voltage value of the voltage signal VDC input to the head unit 5 fluctuates, there is a reduced risk that the fluctuations in voltage value will affect the signal waveform of the drive signal COM output by the amplifier circuit 550 and demodulation circuit 560 of the drive circuit 52, and the accuracy of the signal waveform of the drive signal COM output by the amplifier circuit 550 and demodulation circuit 560 of the drive circuit 52 is improved. As a result, even if the liquid ejection device 1 becomes larger, there is less risk of a decrease in the ink ejection accuracy from the ejection unit 20 that ejects ink in response to the drive signal VOUT based on the drive signal COM.

[0286] Furthermore, in the liquid ejection device 1 of this embodiment, even if the liquid ejection device 1 is enlarged, the risk of a decrease in the ink ejection accuracy from the ejection unit 20, which ejects ink in accordance with the drive signal VOUT based on the drive signal COM, is reduced. Therefore, even if the liquid ejection device 1 is a large machine in which the wiring length of the cable connecting the control unit 2 and the head unit 5 is 2 m or more, or even if the liquid ejection device 1 is a line printer, the risk of a decrease in the ink ejection accuracy from the ejection unit 20 is reduced.

[0287] Furthermore, in the liquid ejection device 1 of this embodiment, the integrated circuit 500 provided in the drive unit 10 controls whether the first step-down circuit 150a outputs the voltage signal VHV obtained by stepping down the voltage signal VDC. In other words, the supply of the voltage signal VHV to the head unit 5 is controlled without relying on the control unit 2. As a result, even if the liquid ejection device 1 has a plurality of head units 5 due to an increase in size of the liquid ejection device 1, the supply of the voltage signal VHV, drive signal COM, and reference voltage signal VBS to the ejection unit 20 can be controlled at an appropriate timing and in a short time.

[0288] Furthermore, in the liquid ejection device 1 of this embodiment, the first step-down circuit 150a has a soft start function that gradually increases the voltage value of the output voltage signal VHV when the first step-down circuit 150a starts outputting the voltage signal VHV obtained by stepping down the voltage signal VDC. This reduces the risk of an inrush current occurring when the first step-down circuit 150a starts outputting the voltage signal VHV obtained by stepping down the voltage signal VDC. Therefore, even if the head unit 5 is configured to have the first step-down circuit 150a that outputs the voltage signal VHV by stepping down the voltage signal VDC supplied from an external device, there is no need to provide an inrush current countermeasure circuit in the head unit 5, and the head unit 5 can be made smaller.

[0289] Furthermore, in the head unit 5 of the liquid ejection device 1 of this embodiment, one end of the piezoelectric element 60 of the print head 23-1 is supplied with a drive signal VOUT based on the drive signals COMA1, COMB1, COMC1 output by the drive circuits 52a1, 52b1, 52c1, and the other end of the piezoelectric element 60 of the print head 23-1 is supplied with a reference voltage signal VBS1 output by the reference voltage signal output circuit 460. In this liquid ejection device 1, the current that flows when the piezoelectric element 60 of the print head 23-1 is driven is output from the drive circuits 52a1, 52b1, 52c1, passes through the piezoelectric element 60 and one end of the capacitor 190-1, and returns to the drive circuits 52a1, 52b1, 52c1 via the other end of the capacitor 190-1 to which a ground signal is supplied.

[0290] In the liquid ejection device 1 of this embodiment, the drive unit 10 includes drive circuits 52a1, 52b1, and 52c1 and a capacitor 190-1. The capacitor 190-1 has one end supplied with a reference voltage signal VBS1 and the other end supplied with a ground signal. The capacitor 190-1 is positioned between a connector CN3b-1, to which the drive circuits 52a1, 52b1, and 52c1 are connected, and a connector CN2, which is electrically connected to the print head 23-1, so that the end supplied with the reference voltage signal VBS1 is on the connector CN2 side and the end supplied with the ground signal is on the connector CN3b-1 side. This shortens the feedback path through which the current flowing when the piezoelectric element 60 of the print head 23-1 is driven returns from the other end of the capacitor 190-1 to the drive circuits 52a1, 52b1, and 52c1 via the wiring pattern through which the ground signal propagates. This reduces the inductance component caused by the current flowing when the piezoelectric element 60 is driven. This reduces the risk of distortion occurring in the signal waveforms of the drive signals COMA1, COMB1, and COMC1 that drive the piezoelectric element 60 due to an inductance component that is generated by the current that flows when the piezoelectric element 60 is driven. As a result, the waveform accuracy of the drive signal VOUT that corresponds to the drive signals COMA1, COMB1, and COMC1 that drive the piezoelectric element 60 is improved.

[0291] In this case, by positioning one end of capacitor 190-1 along the Z2 axis connecting sides 821 and 822, the feedback path along which the current flowing when piezoelectric element 60 of print head 23-1 is driven returns from the other end of capacitor 190-1 to drive circuits 52a1, 52b1, and 52c1 via the wiring pattern through which the ground signal propagates can be further shortened. This further reduces the inductance component caused by the current flowing when piezoelectric element 60 is driven, further reducing the risk of distortion in the signal waveforms of drive signals COMA1, COMB1, and COMC1 that drive piezoelectric element 60 due to the inductance component caused by the current flowing when piezoelectric element 60 is driven. As a result, the waveform accuracy of drive signal VOUT corresponding to drive signals COMA1, COMB1, and COMC1 that drive piezoelectric element 60 is further improved.

[0292] Furthermore, as shown in the liquid ejection device 1 of this embodiment, when the head unit 5 has print heads 23-2 to 23-6 in addition to print head 23-1, by arranging the capacitors 190-2 to 190-6 so that one end of the capacitors 190-2 to 190-6 to which the corresponding reference voltage signals VBS2 to VBS6 are supplied is on the connector CN2 side that is electrically connected to print heads 23-2 to 23-6, and one end of the capacitors 190-2 to 190-6 to which the ground signal is supplied is on the corresponding connector CN3b-2 to CN3b-6 side, it is possible to shorten the feedback path for the current that flows when the piezoelectric element 60 of each of the capacitors 190-2 to 190-6 is driven.

[0293] This reduces the inductance component caused by the current that flows when the piezoelectric elements 60 of the print heads 23-2 to 23-6 are driven, thereby reducing the risk of distortion occurring in the signal waveforms of the drive signals COMA2 to COMA6, COMB2 to COMB6, and COMC2 to COMC6 that drive the piezoelectric elements 60 of the print heads 23-2 to 23-6, respectively.

[0294] Furthermore, the head unit 5 of the liquid ejection device 1 of this embodiment includes a print head 23-1 which includes a piezoelectric element 60 to one end of which is supplied with a drive signal VOUT based on the drive signals COMA1, COMB1, and COMC1 and to the other end of which is supplied with a reference voltage signal VBS1 having a constant voltage value, and which ejects ink in response to the driving of the piezoelectric element 60; a print head 23-4 which includes a piezoelectric element 60 to one end of which is supplied with a drive signal VOUT based on the drive signals COMA4, COMB4, and COMC4 and to the other end of which is supplied with a reference voltage signal VBS4 having a constant voltage value, and which ejects ink in response to the driving of the piezoelectric element 60; and a drive unit 10 which supplies the drive signals COMA1, COMB1, and COMC1 and the reference voltage signal VBS1 to the print head 23-1, and outputs the drive signals COMA4, COMB4, and COMC4 and the reference voltage signal VBS4 to the print head 23-4. a reference voltage signal output circuit 460 included in a drive signal output circuit 50-1 that outputs a reference voltage signal VBS1; a capacitor 190-1 having one end supplied with the reference voltage signal VBS1 and the other end supplied with a ground signal; drive circuits 52a4, 52b4, 52c4 that output drive signals COMA4, COMB4, COMC4; and a drive signal output circuit 50-4 that outputs a reference voltage signal VBS4. a capacitor 190-4 having one end supplied with the reference voltage signal VBS4 and the other end supplied with a ground signal; a connector CN2 electrically connected to the print head 23-1 and the print head 23-4; and a base substrate B1 on which the connector CN2 is provided and on which the drive signals COMA1, COMB1, COMC1, COMA4, COMB4, COMC4 and the reference voltage signals VBS1, VBS4 are transmitted.

[0295] In the base substrate B1 of this head unit 5, a wiring Wvb1 electrically connects the capacitor 190-1, located away from the connector CN2, to the connector CN2, and propagates a reference voltage signal VBS1 supplied to the print head 23-1. The wiring Wvb1 is provided on the internal wiring layer 820-(k+1), a wiring Wca1 propagates a drive signal COMA1 supplied to the print head 23-1, and the wiring Wca1 is provided on the internal wiring layer 820-k adjacent to the internal wiring layer 820-(k+1), and a wiring Wcb1 propagates a drive signal COMB1 supplied to the print head 23-1. The wiring Wvb1, the wiring Wca1, and the wiring Wcb1 are positioned so as to at least partially overlap when viewed from the normal direction to the surface 801 of the base substrate B1.

[0296] As described above, the current flowing when the piezoelectric element 60 of the print head 23-1 is driven is output from the drive circuits 52a1, 52b1, and 52c1, passes through the piezoelectric element 60 and one end of the capacitor 190-1, and returns to the drive circuits 52a1, 52b1, and 52c1 via the other end of the capacitor 190-1, to which a ground signal is supplied. At this time, the direction of the current flowing through the wiring Wvb1 is opposite to the direction of the current flowing through the wiring Wca1 and wiring Wcb1. Therefore, the magnetic fields generated by the current flowing when the piezoelectric element 60 of the print head 23-1 is driven cancel each other out. This reduces the influence of inductance components on the drive signals COMA1 and COMB1 supplied to the print head 23-1. As a result, the risk of distortion in the signal waveforms of the drive signals COMA1 and COMB1 supplied to the print head 23-1 is reduced.

[0297] On the other hand, wiring Wvb4, which electrically connects the capacitor 190-4 located near the connector CN2 to the connector CN2 and propagates the reference voltage signal VBS4 supplied to the print head 23-4, is provided on the surface wiring layer 812 formed on the surface 802 on which the capacitor 190-4 is provided. This reduces the number of vias provided in the propagation path of the reference voltage signal VBS4. The wiring for signals propagating through the connector CN2 is densely packed near the connector CN2. If vias were provided near the connector CN2 where such wiring is densely packed, it would be necessary to route the wiring pattern for propagating the signal input to the connector CN2. This could hinder the miniaturization of the base substrate B1 and complicate the routing of the wiring pattern, increasing the risk of noise and other contaminants being superimposed on the signal input to the connector CN2. That is, in the head unit 5 of this embodiment, the capacitor 190-4 located near the connector CN2 is electrically connected to the connector CN2, and the wiring Wvb4 along which the reference voltage signal VBS4 supplied to the print head 23-4 propagates is provided on the surface wiring layer 812 formed on the surface 802 on which the capacitor 190-4 is provided, thereby reducing the number of vias provided in the propagation path along which the reference voltage signal VBS4 propagates, and as a result, it is possible to miniaturize the base substrate B1 and reduce the risk of noise and the like being superimposed on the signal input to the connector CN2.

[0298] As described above, in the head unit 5 of this embodiment, the capacitor 190-1 located away from the connector CN2 is electrically connected to the connector CN2, and the wiring Wvb1 through which the reference voltage signal VBS1 supplied to the print head 23-1 propagates, the wiring Wca1 through which the drive signal COMA1 supplied to the print head 23-1 propagates, and the wiring Wcb1 through which the drive signal COMB1 propagates are arranged in adjacent wiring layers so that they at least partially overlap when viewed from the normal direction to the surface 801 of the base substrate B1, and the capacitor 190-4 located near the connector CN2 is electrically connected to the connector CN2, and the wiring Wvb4 through which the reference voltage signal VBS4 supplied to the print head 23-4 propagates is arranged in the same wiring layer as the capacitor 190-4, thereby achieving both a compact base substrate B1 and improved signal accuracy.

[0299] 5. Variations In the liquid ejection device 1 and head unit 5 of this embodiment described above, the drive unit 10 may have a capacitor 190-1a connected in parallel with capacitor 190-1, a capacitor 190-2a connected in parallel with capacitor 190-2, a capacitor 190-3a connected in parallel with capacitor 190-3, a capacitor 190-4a connected in parallel with capacitor 190-4, a capacitor 190-5a connected in parallel with capacitor 190-5, and a capacitor 190-6a connected in parallel with capacitor 190-6.

[0300] That is, the driving unit 10 may have a capacitor 190-1a having one end supplied with a reference voltage signal VBS1 at its positive pole and the other end supplied with a ground signal at its negative pole, a capacitor 190-2a having one end supplied with a reference voltage signal VBS2 at its positive pole and the other end supplied with a ground signal at its negative pole, a capacitor 190-3a having one end supplied with a reference voltage signal VBS3 at its positive pole and the other end supplied with a ground signal at its negative pole, a capacitor 190-4a having one end supplied with a reference voltage signal VBS4 at its positive pole and the other end supplied with a ground signal at its negative pole, a capacitor 190-5a having one end supplied with a reference voltage signal VBS5 at its positive pole and the other end supplied with a ground signal at its negative pole, and a capacitor 190-6a having one end supplied with a reference voltage signal VBS6 at its positive pole and the other end supplied with a ground signal at its negative pole.

[0301] In this case, when the base substrate B1 is viewed along the X2 axis, the capacitor 190-1a connected in parallel to the capacitor 190-1 is located between the connector CN2 and the connector CN3b-1, between the connector CN2 and the electrode to which the connector CN3b-1 is electrically connected to the base substrate B1, and is arranged on the base substrate B1 so that the shortest distance between the connector CN2 and the + pole of one end of the capacitor 190-1a to which the reference voltage signal VBS1 is supplied is shorter than the shortest distance between the connector CN2 and the - pole of the other end of the capacitor 190-1a to which the ground signal is supplied, and the shortest distance between the connector CN3b-1 and the + pole of one end of the capacitor 190-1a to which the reference voltage signal VBS1 is supplied is longer than the shortest distance between the connector CN3b-1 and the - pole of the other end of the capacitor 190-1a to which the ground signal is supplied.

[0302] Similarly, when the base substrate B1 is viewed along the X2 axis, capacitor 190-2a connected in parallel to capacitor 190-2 is located between connector CN2 and connector CN3b-2, between connector CN2 and the electrode to which connector CN3b-2 is electrically connected to base substrate B1, and is arranged on base substrate B1 so that the shortest distance between connector CN2 and one end of capacitor 190-2a, the + pole to which the reference voltage signal VBS2 is supplied, is shorter than the shortest distance between connector CN2 and the other end of capacitor 190-2a, the - pole to which the ground signal is supplied, and the shortest distance between connector CN3b-2 and one end of capacitor 190-2a, the + pole to which the reference voltage signal VBS2 is supplied, is longer than the shortest distance between connector CN3b-2 and the other end of capacitor 190-2a, the - pole to which the ground signal is supplied.

[0303] Similarly, when the base substrate B1 is viewed along the X2 axis, capacitor 190-3a connected in parallel to capacitor 190-3 is located between connector CN2 and connector CN3b-3, between connector CN2 and the electrode to which connector CN3b-3 is electrically connected to base substrate B1, and is arranged on base substrate B1 so that the shortest distance between connector CN2 and one end of capacitor 190-3a, the + pole to which the reference voltage signal VBS3 is supplied, is shorter than the shortest distance between connector CN2 and the other end of capacitor 190-3a, the - pole to which the ground signal is supplied, and the shortest distance between connector CN3b-3 and one end of capacitor 190-3a, the + pole to which the reference voltage signal VBS3 is supplied, is longer than the shortest distance between connector CN3b-3 and the other end of capacitor 190-3a, the - pole to which the ground signal is supplied.

[0304] Similarly, when the base substrate B1 is viewed along the X2 axis, capacitor 190-4a connected in parallel to capacitor 190-4 is located between connector CN2 and connector CN3b-4, between connector CN2 and the electrode to which connector CN3b-4 is electrically connected to base substrate B1, and is arranged on base substrate B1 so that the shortest distance between connector CN2 and one end of capacitor 190-4a, the + pole to which the reference voltage signal VBS4 is supplied, is shorter than the shortest distance between connector CN2 and the other end of capacitor 190-4a, the - pole to which the ground signal is supplied, and the shortest distance between connector CN3b-4 and one end of capacitor 190-4a, the + pole to which the reference voltage signal VBS4 is supplied, is longer than the shortest distance between connector CN3b-4 and the other end of capacitor 190-4a, the - pole to which the ground signal is supplied.

[0305] Similarly, capacitor 190-5a connected in parallel with capacitor 190-5 is located between connector CN2 and connector CN3b-5, between connector CN2 and the electrode to which connector CN3b-5 is electrically connected to base substrate B1, and is arranged on base substrate B1 so that the shortest distance between connector CN2 and one end of capacitor 190-5a, the + pole to which the reference voltage signal VBS5 is supplied, is shorter than the shortest distance between connector CN2 and the other end of capacitor 190-5a, the - pole to which the ground signal is supplied, and the shortest distance between connector CN3b-5 and one end of capacitor 190-5a, the + pole to which the reference voltage signal VBS5 is supplied, is longer than the shortest distance between connector CN3b-5 and the other end of capacitor 190-5a, the - pole to which the ground signal is supplied.

[0306] Similarly, capacitor 190-6a connected in parallel with capacitor 190-6 is located between connector CN2 and connector CN3b-6, between connector CN2 and the electrode to which connector CN3b-6 is electrically connected to base substrate B1, and is arranged on base substrate B1 so that the shortest distance between connector CN2 and one end of capacitor 190-6a, the + pole to which the reference voltage signal VBS6 is supplied, is shorter than the shortest distance between connector CN2 and the other end of capacitor 190-6a, the - pole to which the ground signal is supplied, and the shortest distance between connector CN3b-6 and one end of capacitor 190-6a, the + pole to which the reference voltage signal VBS6 is supplied, is longer than the shortest distance between connector CN3b-6 and the other end of capacitor 190-6a, the - pole to which the ground signal is supplied.

[0307] The liquid ejection device 1 and head unit 5 configured as above can also achieve the same effects as those of the above-described embodiment.

[0308] Here, capacitor 190-1a is an example of a second capacitor, one end electrode of capacitor 190-1a to which the reference voltage signal VBS1 is supplied is an example of a third electrode, and the other end electrode of capacitor 190-1a to which the ground signal is supplied is an example of a fourth electrode.

[0309] Furthermore, in the liquid ejection device 1 and head unit 5 of this embodiment described above, the drive circuit modules DRV1 to DRV6 generate drive signals COMA1 to COMA6, COMB1 to COMB6, COMC1 to COMC6, and reference voltage signals VBS1 to VBS6, and supply them to the base substrate B1 via a BtoB connector, but the drive signal output circuits 50-1 to 50-6 that generate and output the drive signals COMA1 to COMA6, COMB1 to COMB6, COMC1 to COMC6, and reference voltage signals VBS1 to VBS6 may be mounted on surface 801 of the base substrate B1.

[0310] Even in this case, the same effects as those of the above-described embodiment can be achieved.

[0311] In this case, an electrode formed on the base substrate B1 to which the other end of the coil 561 of any of the drive circuits 52a1, 52b1, 52c1 or one end of the capacitor 562 of any of the drive circuits 52a1, 52b1, 52c1 is electrically connected is an example of a first supply point, and an electrode formed on the base substrate B1 to which the other end of the coil 561 of any of the drive circuits 52a2, 52b2, 52c2 or one end of the capacitor 562 of any of the drive circuits 52a2, 52b2, 52c2 is electrically connected is an example of a second supply point.

[0312] Although the embodiments and modifications have been described above, the present invention is not limited to these embodiments and can be embodied in various forms without departing from the spirit of the present invention. For example, the above embodiments can be combined as appropriate.

[0313] The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects). The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments or that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0314] The following can be derived from the above-described embodiment.

[0315] One aspect of the head unit is a first print head including a first driving element having one end supplied with a first driving signal and the other end supplied with a first reference voltage signal having a constant voltage value, the first print head ejecting liquid in response to the driving of the first driving element; a driving unit that outputs the first driving signal and the first reference voltage signal to the first print head; Equipped with The drive unit is a first drive circuit that outputs the first drive signal; a first reference voltage signal output circuit that outputs the first reference voltage signal; an output connector electrically connected to the first print head; a first capacitor having a first electrode to which the first reference voltage signal is supplied and a second electrode to which a ground signal is supplied; a wiring board on which the output connector is provided and through which the first drive signal and the first reference voltage signal propagate; and the wiring substrate includes a first side, a second side facing the first side, and a first supply point to which the first driving signal is supplied; the first capacitor is located between the output connector and the first supply point when viewed along a second axis perpendicular to a first axis connecting the first side and the second side; the shortest distance between the output connector and the first electrode is shorter than the shortest distance between the output connector and the second electrode; The shortest distance between the first supply point and the first electrode is longer than the shortest distance between the first supply point and the second electrode.

[0316] In this head unit, the feedback path along which the current generated by the first drive signal supplied by the first drive circuit to the first drive element returns to the first drive circuit can be shortened. As a result, the inductance component in the current path of the current generated by the first drive signal supplied by the first drive circuit to the first drive element is reduced, and the risk of distortion of the signal waveform of the first drive signal supplied to the first drive element due to the inductance component is reduced.

[0317] In one aspect of the head unit, The first electrode and the second electrode may be positioned along the first axis.

[0318] In this head unit, the feedback path of the current generated by the first drive signal supplied by the first drive circuit to the first drive element can be further shortened, which further reduces the inductance component in the current path of the current generated by the first drive signal supplied by the first drive circuit to the first drive element, thereby further reducing the risk of distortion in the signal waveform of the first drive signal supplied to the first drive element due to the inductance component.

[0319] In one aspect of the head unit, The drive unit is a second capacitor having a third electrode to which the first reference voltage signal is supplied and a fourth electrode to which a ground signal is supplied; the second capacitor is located along the second axis between the output connector and the first feed point; the shortest distance between the output connector and the third electrode is shorter than the shortest distance between the output connector and the fourth electrode; The shortest distance between the first supply point and the third electrode may be longer than the shortest distance between the first supply point and the fourth electrode.

[0320] In this head unit, even if a second capacitor is provided in addition to multiple first capacitors in the current path of the current generated in response to the first drive signal supplied by the first drive circuit to the first drive element, the feedback path along which the current generated in response to the first drive signal supplied by the first drive circuit to the first drive element returns to the first drive circuit can be shortened. This reduces the inductance component in the current path of the current generated in response to the first drive signal, reducing the risk of distortion in the signal waveform of the first drive signal supplied to the first drive element due to the inductance component.

[0321] In one aspect of the head unit, a second print head including a second driving element having one end to which a second driving signal is supplied and the other end to which a second reference voltage signal having a constant voltage value is supplied, the second print head ejecting liquid in response to the driving of the second driving element; The drive unit is a second drive circuit that outputs the second drive signal; a second reference voltage signal output circuit that outputs the second reference voltage signal; a third capacitor having a fifth electrode to which the second reference voltage signal is supplied and a sixth electrode to which a ground signal is supplied; and the output connector is electrically connected to the second print head; the wiring substrate includes a second supply point to which the second drive signal is supplied, and propagates the second drive signal and the second reference voltage signal; the third capacitor is located along the second axis between the output connector and the second feed point; the shortest distance between the output connector and the fifth electrode is shorter than the shortest distance between the output connector and the sixth electrode; The shortest distance between the second supply point and the fifth electrode may be longer than the shortest distance between the second supply point and the sixth electrode.

[0322] In this head unit, even if it has a second print head in addition to the first print head, the feedback path through which the current generated by the second drive signal supplied by the second drive circuit to the second drive element returns to the second drive circuit can be shortened, thereby reducing the inductance component in the current path of the current generated by the second drive signal supplied by the second drive circuit to the second drive element, and reducing the risk of distortion in the signal waveform of the second drive signal supplied to the second drive element due to the inductance component.

[0323] In one aspect of the head unit, the wiring substrate includes a first surface and a second surface positioned opposite the first surface; The first drive circuit may be provided on the first surface, and the first capacitor may be provided on the second surface.

[0324] This head unit can be made smaller.

[0325] In one aspect of the head unit, the drive unit includes a drive circuit board on which the first drive circuit is provided, the wiring substrate includes a first surface and a second surface positioned opposite the first surface; The drive circuit board may be electrically connected to the first surface via a BtoB connector, and the first capacitor may be provided on the second surface.

[0326] In this head unit, the mounting area of ​​the first drive circuit is reduced, and the head unit can be made smaller.

[0327] One aspect of the liquid ejection device is a transport unit that transports the medium; a first print head including a first driving element having one end supplied with a first driving signal and the other end supplied with a first reference voltage signal having a constant voltage value, the first print head ejecting liquid onto the medium in response to the driving of the first driving element; a driving unit that outputs the first driving signal and the first reference voltage signal to the first print head; Equipped with The drive unit is a first drive circuit that outputs the first drive signal; a first reference voltage signal output circuit that outputs the first reference voltage signal; an output connector electrically connected to the first print head; a first capacitor having a first electrode to which the first reference voltage signal is supplied and a second electrode to which a ground signal is supplied; a wiring board on which the output connector is provided and through which the first drive signal and the first reference voltage signal propagate; and the wiring substrate includes a first side, a second side facing the first side, and a first supply point to which the first driving signal is supplied; the first capacitor is located between the output connector and the first supply point when viewed along a second axis perpendicular to a first axis connecting the first side and the second side; the shortest distance between the output connector and the first electrode is shorter than the shortest distance between the output connector and the second electrode; The shortest distance between the first supply point and the first electrode is longer than the shortest distance between the first supply point and the second electrode.

[0328] In this liquid ejection device, the feedback path along which the current generated by the first drive signal supplied by the first drive circuit to the first drive element returns to the first drive circuit can be shortened, thereby reducing the inductance component in the current path of the current generated by the first drive signal supplied by the first drive circuit to the first drive element, and reducing the risk of distortion in the signal waveform of the first drive signal supplied to the first drive element due to the inductance component.

[0329] In one aspect of the liquid ejection device, The first electrode and the second electrode may be positioned along the first axis.

[0330] In this liquid ejection device, the feedback path of the current generated in response to the first drive signal supplied by the first drive circuit to the first drive element can be further shortened, thereby further reducing the inductance component in the current path of the current generated in response to the first drive signal supplied by the first drive circuit to the first drive element, and further reducing the risk of distortion of the signal waveform of the first drive signal supplied to the first drive element due to the inductance component.

[0331] In one aspect of the liquid ejection device, The drive unit is a second capacitor having a third electrode to which the first reference voltage signal is supplied and a fourth electrode to which a ground signal is supplied; the second capacitor is located along the second axis between the output connector and the first feed point; the shortest distance between the output connector and the third electrode is shorter than the shortest distance between the output connector and the fourth electrode; The shortest distance between the first supply point and the third electrode may be longer than the shortest distance between the first supply point and the fourth electrode.

[0332] In this liquid ejection device, even if a second capacitor is provided in addition to multiple first capacitors in the current path of the current generated in response to the first drive signal supplied by the first drive circuit to the first drive element, the feedback path along which the current generated in response to the first drive signal supplied by the first drive circuit to the first drive element returns to the first drive circuit can be shortened. This reduces the inductance component in the current path of the current generated in response to the first drive signal, reducing the risk of distortion in the signal waveform of the first drive signal supplied to the first drive element due to the inductance component.

[0333] In one aspect of the liquid ejection device, a second print head including a second driving element having one end to which a second driving signal is supplied and the other end to which a second reference voltage signal having a constant voltage value is supplied, the second print head ejecting liquid in response to the driving of the second driving element; The drive unit is a second drive circuit that outputs the second drive signal; a second reference voltage signal output circuit that outputs the second reference voltage signal; a third capacitor having a fifth electrode to which the second reference voltage signal is supplied and a sixth electrode to which a ground signal is supplied; and the output connector is electrically connected to the second print head; the wiring substrate includes a second supply point to which the second drive signal is supplied, and propagates the second drive signal and the second reference voltage signal; the third capacitor is located along the second axis between the output connector and the second feed point; the shortest distance between the output connector and the fifth electrode is shorter than the shortest distance between the output connector and the sixth electrode; The shortest distance between the second supply point and the fifth electrode may be longer than the shortest distance between the second supply point and the sixth electrode.

[0334] In this liquid ejection device, even if a second print head is provided in addition to the first print head, the feedback path of the current generated in response to the second drive signal supplied by the second drive circuit to the second drive element can be shortened, thereby reducing the inductance component in the current path of the current generated in response to the second drive signal supplied by the second drive circuit to the second drive element, and reducing the risk of distortion in the signal waveform of the second drive signal supplied to the second drive element due to the inductance component.

[0335] In one aspect of the liquid ejection device, the wiring substrate includes a first surface and a second surface positioned opposite the first surface; The first drive circuit may be provided on the first surface, and the first capacitor may be provided on the second surface.

[0336] In this liquid ejection device, the drive unit can be made smaller.

[0337] In one aspect of the liquid ejection device, the drive unit includes a drive circuit board on which the first drive circuit is provided, the wiring substrate includes a first surface and a second surface positioned opposite the first surface; The drive circuit board may be electrically connected to the first surface via a BtoB connector, and the first capacitor may be provided on the second surface.

[0338] In this liquid ejection device, the mounting area of ​​the first drive circuit is reduced, and the drive unit can be made smaller. [Explanation of symbols]

[0339] 1...liquid ejection device, 2...control unit, 3...liquid container, 4...transport unit, 5...head unit, 10...drive unit, 20...ejection unit, 23...print head, 30...connection member, 31...casing, 33...aggregate substrate, 34...flow path structure, 35...head substrate, 37...distribution flow path, 39...fixed plate, 41...transport motor, 42...transport roller, 50...drive signal output circuit, 52...drive circuit, 60...piezoelectric element, 100...control circuit, 110-1 to 110-6...capacitors, 120...conversion circuit, 130...step-down circuit , 140...VHV supply switching circuit, 150a...first step-down circuit, 150b...second step-down circuit, 152a, 152b...coil, 153a, 153b...capacitor, 154a, 155a...resistor, 156a...capacitor, 160a, 160b...integrated circuits, 161...drive circuit, 162...drive control circuit, 163...level shift circuit, 164...switching circuit, 165 to 167...transistor, 190-1 to 190-6...capacitor, 200...drive signal selection circuit, 201...integrated circuit, 210...selection Control circuit, 212...shift register, 214...latch circuit, 216...decoder, 220...restoration circuit, 230...selection circuit, 232a, 232b, 232c...inverters, 234a, 234b, 234c...transfer gates, 311...opening, 313...aggregate substrate insertion portion, 315...holding member, 330...connection portion, 341...introduction portion, 343...through hole, 351...opening, 352, 353, 355...notch portion, 371...opening, 373...introduction portion, 388...wiring member, 391...opening, 400...internal voltage generation generation circuit, 410...oscillation circuit, 411...clock selection circuit, 430...abnormality detection circuit, 431...oscillation abnormality detection unit, 432...operation abnormality detection unit, 433...power supply voltage abnormality detection unit, 440...register control circuit, 441...sequence register, 442...status register, 443...register control unit, 450...drive signal discharge circuit, 451...resistor, 452...transistor, 453...inverter, 460...reference voltage signal output circuit, 461...comparator, 462, 463...transistor, 464, 465,466...resistor, 467...inverter, 470...VHV control signal output circuit, 471...transistor, 472...resistor, 480...status signal input / output circuit, 481...transistor, 482...inverter, 483...resistor, 490...fault signal input / output circuit, 491...transistor, 492...inverter, 493...resistor, 500...integrated circuit, 501...drive signal generating circuit, 502...amplification control signal generating circuit, 510...DAC interface, 520...DAC section, 530...modulation section, 540...gate drive section, 542...transistor, 550...amplification circuit, 551, 552...transistor, 560...demodulation circuit, 561...coil, 562...capacitor, 570...feedback circuit, 571, 572, 576...resistor, 600...emission section, 601...piezoelectric body, 602, 603...electrode, 610...diaphragm, 611...lead electrode, 620...compliance substrate, 621...sealing film, 622...fixed substrate, 6 23...Nozzle plate, 623a...Liquid ejection surface, 630...Communicating plate, 641...Protective substrate, 642...Flow path forming substrate, 643...Through hole, 644...Protective space, 660...Case, 661...Inlet path, 662...Connection port, 665...Recess, 801, 802...Surface, 810...Insulating layer, 811...Surface wiring layer, 812...Surface wiring layer, 820...Internal wiring layer, 821-824...Side, B1...Base substrate, B2...Conversion circuit board, CB...Pressure chamber, CN1, CN2, CN3a ,CN3b,CN4b...connector, DRV...drive circuit module, FC...wiring member, IC1,IC2...integrated circuit, Ln1,Ln2...nozzle array, MN...manifold, N...nozzle, P...medium, RA,RB...supply communication passage, RK1,RK2...pressure chamber communication passage, RR...nozzle communication passage, RX...connection communication passage, Su1,Su2...flow path plate, Wca1 to Wca6,Wcb1 to Wcb6,Wcc1 to Wcc6,Wvb1 to Wvb6,Wvhv...wiring,

Claims

1. a first print head including a first driving element having one end supplied with a first driving signal and the other end supplied with a first reference voltage signal having a constant voltage value, the first print head ejecting liquid in response to the driving of the first driving element; a driving unit that outputs the first driving signal and the first reference voltage signal to the first print head; Equipped with The drive unit is a first drive circuit that outputs the first drive signal; a first reference voltage signal output circuit that outputs the first reference voltage signal; an output connector electrically connected to the first print head; a first capacitor having a first electrode supplied with the first reference voltage signal and a second electrode supplied with a ground signal; a wiring board on which the output connector is provided and through which the first drive signal and the first reference voltage signal propagate; and the wiring substrate includes a first side, a second side facing the first side, and a first supply point to which the first driving signal is supplied; the first capacitor is located between the output connector and the first supply point when viewed along a second axis perpendicular to a first axis connecting the first side and the second side; the shortest distance between the output connector and the first electrode is shorter than the shortest distance between the output connector and the second electrode; the shortest distance between the first supply point and the first electrode is longer than the shortest distance between the first supply point and the second electrode; A head unit characterized by:

2. The first electrode and the second electrode are positioned along the first axis.

2. The head unit according to claim 1.

3. The drive unit is a second capacitor having a third electrode to which the first reference voltage signal is supplied and a fourth electrode to which a ground signal is supplied; the second capacitor is located along the second axis between the output connector and the first feed point; the shortest distance between the output connector and the third electrode is shorter than the shortest distance between the output connector and the fourth electrode; the shortest distance between the first supply point and the third electrode is longer than the shortest distance between the first supply point and the fourth electrode; 2. The head unit according to claim 1.

4. a second print head including a second driving element having one end supplied with a second driving signal and the other end supplied with a second reference voltage signal having a constant voltage value, the second print head ejecting liquid in response to the driving of the second driving element; The drive unit is a second drive circuit that outputs the second drive signal; a second reference voltage signal output circuit that outputs the second reference voltage signal; a third capacitor having a fifth electrode to which the second reference voltage signal is supplied and a sixth electrode to which a ground signal is supplied; and the output connector is electrically connected to the second print head; the wiring substrate includes a second supply point to which the second drive signal is supplied, and propagates the second drive signal and the second reference voltage signal; the third capacitor is located along the second axis between the output connector and the second feed point; the shortest distance between the output connector and the fifth electrode is shorter than the shortest distance between the output connector and the sixth electrode; the shortest distance between the second supply point and the fifth electrode is longer than the shortest distance between the second supply point and the sixth electrode; 2. The head unit according to claim 1.

5. the wiring substrate includes a first surface and a second surface positioned opposite the first surface; the first drive circuit is provided on the first surface, and the first capacitor is provided on the second surface.

2. The head unit according to claim 1.

6. the drive unit includes a drive circuit board on which the first drive circuit is provided, the wiring substrate includes a first surface and a second surface positioned opposite the first surface; the drive circuit board is electrically connected to the first surface via a BtoB connector, and the first capacitor is provided on the second surface.

2. The head unit according to claim 1.

7. a transport unit that transports the medium; a first print head including a first driving element having one end supplied with a first driving signal and the other end supplied with a first reference voltage signal having a constant voltage value, the first print head ejecting liquid onto the medium in response to the driving of the first driving element; a driving unit that outputs the first driving signal and the first reference voltage signal to the first print head; Equipped with The drive unit is a first drive circuit that outputs the first drive signal; a first reference voltage signal output circuit that outputs the first reference voltage signal; an output connector electrically connected to the first print head; a first capacitor having a first electrode supplied with the first reference voltage signal and a second electrode supplied with a ground signal; a wiring board on which the output connector is provided and through which the first drive signal and the first reference voltage signal propagate; and the wiring substrate includes a first side, a second side facing the first side, and a first supply point to which the first driving signal is supplied; the first capacitor is located between the output connector and the first supply point when viewed along a second axis perpendicular to a first axis connecting the first side and the second side; the shortest distance between the output connector and the first electrode is shorter than the shortest distance between the output connector and the second electrode; the shortest distance between the first supply point and the first electrode is longer than the shortest distance between the first supply point and the second electrode; A liquid ejection device characterized by:

8. The first electrode and the second electrode are positioned along the first axis.

8. The liquid ejection device according to claim 7.

9. The drive unit is a second capacitor having a third electrode to which the first reference voltage signal is supplied and a fourth electrode to which a ground signal is supplied; the second capacitor is located along the second axis between the output connector and the first feed point; the shortest distance between the output connector and the third electrode is shorter than the shortest distance between the output connector and the fourth electrode; the shortest distance between the first supply point and the third electrode is longer than the shortest distance between the first supply point and the fourth electrode; 8. The liquid ejection device according to claim 7.

10. a second print head including a second driving element having one end supplied with a second driving signal and the other end supplied with a second reference voltage signal having a constant voltage value, the second print head ejecting liquid in response to the driving of the second driving element; The drive unit is a second drive circuit that outputs the second drive signal; a second reference voltage signal output circuit that outputs the second reference voltage signal; a third capacitor having a fifth electrode to which the second reference voltage signal is supplied and a sixth electrode to which a ground signal is supplied; and the output connector is electrically connected to the second print head; the wiring substrate includes a second supply point to which the second drive signal is supplied, and propagates the second drive signal and the second reference voltage signal; the third capacitor is located along the second axis between the output connector and the second feed point; the shortest distance between the output connector and the fifth electrode is shorter than the shortest distance between the output connector and the sixth electrode; the shortest distance between the second supply point and the fifth electrode is longer than the shortest distance between the second supply point and the sixth electrode; 8. The liquid ejection device according to claim 7.

11. the wiring substrate includes a first surface and a second surface positioned opposite the first surface; the first drive circuit is provided on the first surface, and the first capacitor is provided on the second surface.

8. The liquid ejection device according to claim 7.

12. the drive unit includes a drive circuit board on which the first drive circuit is provided, the wiring substrate includes a first surface and a second surface positioned opposite the first surface; the drive circuit board is electrically connected to the first surface via a BtoB connector, and the first capacitor is provided on the second surface.

8. The liquid ejection device according to claim 7.

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