Liquid crystal device, wavelength selective switching device, and method of inspecting pixels of liquid crystal device

Abstract

To provide a liquid crystal device capable of quickly inspecting pixels, a wavelength selective switching device, and a method of inspecting pixels of the liquid crystal device.SOLUTION: In a liquid crystal device disclosed herein, each pixel in the first row includes a first switching transistor configured to output a voltage of a pixel drive electrode to a corresponding first data line when in pixel inspection mode, and each pixel in the second row includes a second switching transistor configured to output a voltage of the pixel drive electrode to a corresponding second data line when in pixel inspection mode.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present disclosure relates to a liquid crystal device, a wavelength selective switch device, and a pixel inspection method for a liquid crystal device, and more particularly to a liquid crystal device, a wavelength selective switch device, and a pixel inspection method for a liquid crystal device that are suitable for detecting faults with high accuracy. [Background technology]

[0002] The liquid crystal display device disclosed in Patent Document 1 includes a plurality of pixels arranged in a matrix, a plurality of sets of data lines provided corresponding to each column of the plurality of pixels, a plurality of gate lines provided corresponding to each row of the plurality of pixels, a plurality of switches for supplying positive and negative polarity video signals to the plurality of sets of data lines in sequence on a set-by-set basis, and a driving means for driving the plurality of switches and the plurality of gate lines. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-223289 [Patent Document 2] Japanese Patent Publication No. 2020-20847 Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, in order to improve reliability, liquid crystal display devices are required to be inspected for defects or deterioration of characteristics in pixels, for example, before product shipment.

[0005] However, Patent Document 1 does not disclose specific details regarding a pixel inspection method. Therefore, in the liquid crystal display device disclosed in Patent Document 1, for example, a video signal (pixel drive voltage) written to the pixel under inspection is read using a path through which the video signal is written to the pixel during normal operation, and the pixel is inspected based on the read video signal. However, this inspection method has a problem in that the video signal written to the pixel under inspection cannot be read out quickly due to the influence of a large wiring capacitance added to the video signal propagation path, making it impossible to inspect the pixel quickly.

[0006] The present disclosure has been made in consideration of the above points, and aims to provide a liquid crystal device, a wavelength selective switch device, and a pixel inspection method for a liquid crystal device that enable pixel inspection to be performed quickly. [Means for solving the problem]

[0007] A liquid crystal device according to the present disclosure includes a plurality of pixels arranged in a matrix, a plurality of first data lines provided corresponding to each column of the plurality of pixels, a plurality of second data lines provided corresponding to each column of the plurality of pixels, a plurality of first switch elements that switch whether to supply a positive polarity video signal to each of the plurality of first data lines and whether to supply a negative polarity video signal to each of the plurality of second data lines, a plurality of first sense amplifiers that, in a pixel inspection mode, amplify potential differences between a plurality of pixel drive voltages read out to each of the plurality of first data lines from a plurality of the pixels provided in a first row to be inspected and a predetermined voltage, and output the amplified potential differences as a plurality of first detection signals, and a plurality of second sense amplifiers that, in the pixel inspection mode, amplify potential differences between a plurality of pixel drive voltages read out to each of the plurality of second data lines from a plurality of the pixels provided in a second row to be inspected adjacent to the first row, and output the amplified potential differences as a plurality of second detection signals. and a plurality of second sense amplifiers, each of the pixels having a first sample-and-hold circuit that samples and holds a positive-polarity video signal supplied to the corresponding first data line, a second sample-and-hold circuit that samples and holds a negative-polarity video signal supplied to the corresponding second data line, a liquid crystal display element formed of a pixel drive electrode, a common electrode, and liquid crystal sealed therebetween, and a polarity changeover switch that selectively outputs the voltage of the video signal held in the first sample-and-hold circuit and the voltage of the video signal held in the second sample-and-hold circuit to the pixel drive electrode, each of the pixels in the first row further having a first switch transistor that outputs the voltage of the pixel drive electrode to the corresponding first data line in a pixel inspection mode, and each of the pixels in the second row further having a second switch transistor that outputs the voltage of the pixel drive electrode to the corresponding second data line in a pixel inspection mode.

[0008] a plurality of first switch elements that switch whether to supply a positive polarity video signal to each of the plurality of first data lines and whether to supply a negative polarity video signal to each of the plurality of second data lines; a plurality of first sense amplifiers that, in a pixel inspection mode, amplify a potential difference between a plurality of pixel drive voltages read out to each of the plurality of first data lines from a plurality of pixels provided in a first row to be inspected and a predetermined voltage, and output the amplified potential difference as a plurality of first detection signals; and a plurality of second sense amplifiers that, in the pixel inspection mode, amplify a potential difference between a plurality of pixel drive voltages read out to each of the plurality of second data lines from a plurality of pixels provided in a second row to be inspected adjacent to the first row and the predetermined voltage, and output the amplified potential difference as a plurality of second detection signals, a first sample and hold circuit for sampling and holding a negative video signal supplied to the corresponding second data line, a second sample and hold circuit for sampling and holding a negative video signal supplied to the corresponding second data line, a liquid crystal display element formed of a pixel drive electrode, a common electrode, and liquid crystal sealed therebetween, and a polarity changeover switch for selectively outputting to the pixel drive electrode the voltage of the video signal held in the first sample and hold circuit and the voltage of the video signal held in the second sample and hold circuit, wherein each of the pixels in the first row further has a first switch transistor for outputting the voltage of the pixel drive electrode to the corresponding first data line in a pixel inspection mode, and each of the pixels in the second row further has a second switch transistor for outputting the voltage of the pixel drive electrode to the corresponding second data line in a pixel inspection mode,supplying the negative video signal to each of the plurality of second data lines, writing the positive video signal to a plurality of the pixels in a row to be inspected from each of the plurality of first data lines, and writing the negative video signal to a plurality of the pixels in a row to be inspected from each of the plurality of second data lines; turning on the first switch transistor provided in each of the pixels in the first row to be inspected while keeping the plurality of first switch elements off, thereby reading out a plurality of pixel drive voltages from the plurality of the pixels in the first row to be inspected to each of the plurality of first data lines; turning on the second switch transistor provided in each of the pixels in the second row to be inspected while keeping the plurality of first switch elements off, thereby reading out a plurality of pixel drive voltages from the plurality of the pixels in the first row to be inspected to each of the plurality of first data lines; a plurality of pixel drive voltages are read from the pixels onto the plurality of second data lines, and a potential difference between the predetermined voltage and the plurality of pixel drive voltages read onto the plurality of first data lines from the plurality of pixels in the first row to be inspected is amplified using the plurality of first sense amplifiers, and a potential difference between the predetermined voltage and the plurality of pixel drive voltages is amplified using the plurality of second sense amplifiers, and a potential difference between the predetermined voltage and the plurality of pixel drive voltages read onto the plurality of second data lines from the plurality of pixels in the second row to be inspected is amplified using the plurality of second sense amplifiers, and a potential difference between the predetermined voltage and the plurality of pixel drive voltages ... [Effects of the Invention]

[0009] According to the present disclosure, it is possible to provide a liquid crystal device, a wavelength selective switch device, and a pixel inspection method for a liquid crystal device that enable pixel inspection to be performed quickly. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram showing a wavelength selective switch according to the present disclosure as viewed from the x-axis direction. [Figure 2]2 is a diagram showing a wavelength selective switch according to the present disclosure as viewed from the y-axis direction. FIG. [Figure 3] FIG. 10 is a diagram illustrating an example of wavelength channels focused on a reflective liquid crystal element applied to a wavelength selective switch according to the present disclosure. [Figure 4] FIG. 1 is a diagram showing an example of the configuration of a liquid crystal device at the conceptual stage. [Figure 5] 5 is an enlarged view of a horizontal driver and an analog switch section provided in the liquid crystal device shown in FIG. 4. FIG. [Figure 6] 5 is a diagram showing a specific example of the configuration of a pixel provided in the liquid crystal device shown in FIG. 4. FIG. [Figure 7] 5 is a timing chart for explaining a method of driving pixels by the liquid crystal device shown in FIG. [Figure 8] 10A and 10B are diagrams for explaining voltage levels from black to white of a positive polarity video signal and a negative polarity video signal written to a pixel. [Figure 9] 5 is a timing chart showing the operation of the liquid crystal device shown in FIG. 4 in an image display mode. [Figure 10] FIG. 1 is a diagram illustrating a configuration example of a liquid crystal device according to a first embodiment. [Figure 11] 11 is a diagram showing a specific example of the configuration of pixels and their peripheral circuits provided in the liquid crystal device shown in FIG. 10. FIG. [Figure 12] 11 is a diagram showing in more detail the switch section 18, sense amplifier section 19, latch section 20, and shift register circuits 21 and 22 provided in the liquid crystal device shown in FIG. [Figure 13] 11 is a diagram showing a specific example of the configuration of a sense amplifier SAa_i provided in the liquid crystal device shown in FIG. 10. FIG. [Figure 14] 11 is a diagram showing a specific example of the configuration of a shift register circuit 21a provided in the liquid crystal device shown in FIG. [Figure 15] 11 is a timing chart showing the operation of the liquid crystal device shown in FIG. 10 in a pixel inspection mode. DETAILED DESCRIPTION OF THE INVENTION

[0011] <Description of a wavelength selective switch to which a liquid crystal device according to the present disclosure is applied> 1 is a diagram illustrating an example of the configuration of a wavelength selective switch (WSS) array 100 according to the present disclosure, as viewed from the x-axis direction.

[0012] In recent years, optical communication networks have been developed to meet the demand for higher speeds and larger capacities in telecommunications and data networks. Optical communication networks generally employ optical wavelength division multiplexing (WDM) technology, which utilizes as much of the optical spectrum as possible. In optical WDM, as in wireless WDM, data is modulated onto multiple carrier waves with different wavelengths. These multiple carrier waves are called channels (wavelength channels). Compared to wireless WDM, optical WDM uses light waves instead of radio waves, and different wavelength channels correspond to different frequencies (wavelengths) of light. Optical communication typically uses channels within or around the wavelength range of 1 to 2 μm.

[0013] In many optical communication networks, optical nodes corresponding to branch points of the optical communication network are used. Each optical node uses, for example, a reconfigurable optical add-drop multiplexer (ROADM) device with reconfigurable add-drop functionality. Generally speaking, the ROADM functionality allows each optical node to drop or add one or more wavelength channels.

[0014] The WSS array 100 may be used for routing any wavelength channel in a ROADM system. In this case, the WSS array 100 may use an optical beam deflection device, such as a spatial light modulator, which may select a wavelength for deflection to a desired output port. For example, deflecting a wavelength channel to a drop port results in the channel being dropped from the WDM signal. Furthermore, the WSS array 100 may use a spatial light modulator using reflective liquid crystal elements.

[0015] Here, the ROADM function uses a Broadcast-and-Select (BS) scheme, which requires a WSS and an optical splitter at each node. However, future devices may use a Route-and-Select (RS) scheme with multiple WSS devices instead of optical splitters.

[0016] The WSS array 100 according to the present disclosure comprises at least two WSS devices within a single package. While the at least two WSS devices share most of the optical components, the at least two WSS devices are configured to operate independently. This not only reduces the size and optical complexity of the WSS array 100, but also allows for the same independent processing capabilities as larger, more costly devices. The WSS array 100 configured in this manner is suitable for use in optical communication networks, for example, as a reconfigurable optical ROADM, and as a component within a branching node using a route-and-select (RS) architecture. The WSS array 100 also incorporates a liquid crystal device according to the present disclosure as a reflective liquid crystal element.

[0017] As shown in Figure 1, the WSS array 100 includes two independent WSS devices 100a and 100b, each capable of operating as an independent WSS device. As used herein, the term "independent" refers to the ability of one WSS device 100a or 100b to independently process one or more WDM signals independently of the other. As used herein, the term "processing" is used broadly to include, for example, modulating, attenuating, blocking, redirecting, and switching the individual wavelength channels that make up each WDM signal.

[0018] The WSS array 100 includes an input section 110, an optical system 120, and a reflective liquid crystal element .

[0019] The optical system 120 is configured to beam shape each WDM signal beam, spectrally disperse (demultiplex) each WDM signal into its constituent wavelength channels or groups thereof, and spectrally combine (multiplex) the dispersed wavelength channels or groups thereof into one or more WDM signals. The reflective liquid crystal element 130 optically processes the dispersed wavelength channels or groups thereof, for example, to redirect the individual wavelength channels along predetermined paths within the WSS array 100.

[0020] The WSS array 100 is configured to be symmetrical about a symmetry axis Z1 extending in the z-axis direction. This allows a single optical system 120 and a single reflective liquid crystal element 130 to be shared by multiple WSS devices (WSS devices 100a and 100b in this example). While the WSS array 100 allows the WSS devices 100a and 100b to share most of the optical components, the WSS devices 100a and 100b are configured to operate independently. This not only reduces the size and optical complexity of the WSS array 100, but also allows it to have the same independent processing capabilities as larger, more costly devices.

[0021] The input unit 110 has input ports and output ports for transmitting one or more WDM signals to each of the WSS devices 100a and 100b. Each input port and each output port may be, for example, an optical fiber or a planar waveguide, but in this embodiment, an optical fiber will be used as an example. Therefore, hereinafter, each input port will also be referred to as an input fiber, and each output port will also be referred to as an output fiber.

[0022] Specifically, the input unit 110 includes an input fiber FI1 and n (n is an integer equal to or greater than 1) output fibers FO1_1 to FO1_n for the WSS device 100a, and an input fiber FI2 and n output fibers FO2_1 to FO2_n for the WSS device 100b. In the input unit 110, the optical fibers FI1, FO1_1 to FO1_n that make up the fiber stack for the WSS device 100a and the optical fibers FI2, FO2_1 to FO2_n that make up the fiber stack for the WSS device 100b are arranged along the y-axis direction.

[0023] The input unit 110 further includes collimating lenses LI1, LO1_1 to LO1_n corresponding to the optical fibers FI1, FO1_1 to FO1_n for the WSS device 100a, and collimating lenses LI2, LO2_1 to LO2_n corresponding to the optical fibers FI2, FO2_1 to FO2_n for the WSS device 100b. The collimating lenses LI1, LO1_1 to LO1_n and the collimating lenses LI2, LO2_1 to LO2_n form a microlens array. In the input unit 110, each collimating lens is disposed closer to the optical system 120 than each optical fiber. Each collimating lens is any optical element capable of guiding or changing the direction of light rays and focusing a set of light rays.

[0024] In the input section 110, the optical fibers FI1, FO1_1 to FO1_n and collimating lenses LI1, LO1_1 to LO1_n constitute the input section of the WSS device 100a, and the optical fibers FI2, FO2_1 to FO2_n and collimating lenses LI2, LO2_1 to LO2_n constitute the input section of the WSS device 100b.

[0025] In the example of FIG. 1, the WSS array 100 employs a microlens array, but other types of arrays may be employed without departing from the spirit of the invention.

[0026] 1, the optical axes of the collimating lenses LI1, LO1_1 to LO1_n are displaced relative to the optical axes of the optical fibers FI1, FO1_1 to FO1_n, respectively. Due to this relative positional shift between the collimating lenses LI1, LO1_1 to LO1_n and the optical fibers FI1, FO1_1 to FO1_n, the input beam for the WSS device 100a is input to the optical system 120 at an angle θ1 with respect to the axis of symmetry Z1, and each output beam for the WSS device 100a is output from the optical system 120 at an angle θ1 with respect to the axis of symmetry Z1. In other words, the input beam and each output beam for the WSS device 100a are inclined in the negative direction of the y-axis by the angle θ1 with respect to the axis of symmetry Z1 from the input unit 110 to the optical system 120.

[0027] Similarly, the optical axes of the collimating lenses LI2, LO2_1 to LO2_n are displaced relative to the optical axes of the optical fibers FI2, FO2_1 to FO2_n, respectively. Due to this relative positional shift between the collimating lenses LI2, LO2_1 to LO2_n and the optical fibers FI2, FO2_1 to FO2_n, the input beam for the WSS device 100b is input to the optical system 120 at an angle θ2 with respect to the axis of symmetry Z1, and each output beam for the WSS device 100b is output from the optical system 120 at an angle θ2 with respect to the axis of symmetry Z1. In other words, the input beam and each output beam for the WSS device 100b are tilted in the positive direction of the y-axis by the angle θ2 with respect to the axis of symmetry Z1 from the input unit 110 to the optical system 120.

[0028] In the WSS array 100, a first WDM signal input from the outside is supplied to an input fiber FI1. The input fiber FI1 outputs a first WDM signal parallel to the symmetry axis Z1. The first WDM signal output from the input fiber FI1 passes through a collimating lens LI1, whereby the signal is tilted in the negative direction of the y-axis by an angle θ1, and is then supplied to an optical system 120. The first WDM signal supplied to the optical system 120 forms a WDM signal beam BI1 that travels along the y-z plane in the optical system 120. In the optical system 120, the WDM signal beam BI1 is incident on a lens 121 that shapes the WDM signal beam BI1 in the x-direction. The lens 121 is, for example, a cylindrical lens whose cylindrical axis extends in the y-axis direction. Therefore, the lens 121 does not affect the shaping of the WDM signal beam BI1 when viewed from the x-axis direction (in other words, when viewed from the y-z plane).

[0029] The WDM signal beam BI1 that has passed through the lens 121 is incident on the lens 122. The lens 122 is, for example, a cylindrical lens whose cylindrical axis extends in the x-axis direction. The function of the lens 122 depends on a reflective liquid crystal element 130 that is positioned on the focal plane of the lens 122. Furthermore, the center of the lens 122 is located on the symmetry axis Z1.

[0030] In the WSS array 100, a second WDM signal input from the outside is supplied to an input fiber FI2. The input fiber FI2 outputs a second WDM signal parallel to the symmetry axis Z1. The second WDM signal output from the input fiber FI2 passes through a collimating lens LI2, whereby the second WDM signal is tilted in the positive direction of the y-axis by an angle θ2, and is then supplied to the optical system 120. The second WDM signal supplied to the optical system 120 forms a WDM signal beam BI2 that travels along the y-z plane in the optical system 120. In the optical system 120, the WDM signal beam BI2 is incident on a lens 121 that shapes the WDM signal beam BI2 in the x-direction. The lens 121 is, for example, a cylindrical lens whose cylindrical axis extends in the y-axis direction. Therefore, the lens 121 does not affect the shaping of the WDM signal beam BI2 when viewed from the x-axis direction (in other words, when viewed from the y-z plane).

[0031] The WDM signal beam BI2 that has passed through the lens 121 is incident on the lens 122. The lens 122 is, for example, a cylindrical lens whose cylindrical axis extends in the x-axis direction. The function of the lens 122 depends on a reflective liquid crystal element 130 that is positioned on the focal plane of the lens 122. Furthermore, the center of the lens 122 is located on the symmetry axis Z1.

[0032] Here, since reflective liquid crystal element 130 is positioned on the focal plane of lens 122, any pair of light rays reflected from positions having the same distance in the y-axis direction with respect to axis of symmetry Z1 among the light rays reflected by reflective liquid crystal element 130 will be emitted as a pair of parallel light rays from lens 122. Conversely, any pair of parallel light rays incident on lens 122 from the input unit 110 side will be focused in reflective liquid crystal element 130 at positions having the same distance in the y-axis direction with respect to axis of symmetry Z1.

[0033] 1, any incident beam (WDM signal beam BI1 in this example) traveling at an angle θ1 with respect to axis of symmetry Z1 is directed by lens 122 toward position LC1 on reflective liquid crystal element 130. Conversely, light rays (output beams BO1_1 to BO1_n in this example) originating from position LC1 on reflective liquid crystal element 130 are directed by lens 122 as parallel light rays traveling at an angle θ1 with respect to axis of symmetry Z1.

[0034] Similarly, any incident beam (WDM signal beam BI2 in this example) traveling at an angle θ2 with respect to axis of symmetry Z1 is directed by lens 122 toward position LC2 on reflective liquid crystal element 130. Conversely, light rays (output beams BO2_1 to BO2_n in this example) originating at position LC2 on reflective liquid crystal element 130 are directed by lens 122 as parallel light rays traveling at an angle θ2 with respect to axis of symmetry Z1.

[0035] FIG. 2 is a view of the WSS array 100 as seen from the y-axis direction. FIG. 3 is a diagram showing an example of wavelength channels focused on the reflective liquid crystal element 130. As shown in FIG.

[0036] 2 and 3, the WDM signal beam BI1 passes through the lens 122 and then through the dispersive element 124 provided between the lenses 122 and 123. The dispersive element 124 is a transmissive optical component such as a diffraction grating or a prism, and angularly disperses the wavelength channels of the WDM signal beam BI1. The wavelength channels dispersed by the dispersive element 124 pass through the lens 123. The lens 123 is a cylindrical lens, for example, and focuses the wavelength channels dispersed by the dispersive element 124 at a position LC1 on the reflective liquid crystal element 130.

[0037] Similarly, after passing through lens 122, WDM signal beam BI2 passes through dispersive element 124 provided between lenses 122 and 123. Dispersive element 124 angularly disperses the wavelength channels of WDM signal beam BI2. The wavelength channels dispersed by dispersive element 124 pass through lens 123. Lens 123 focuses the wavelength channels dispersed by dispersive element 124 at position LC2 on reflective liquid crystal element 130.

[0038] The reflective liquid crystal element 130 is a two-dimensional pixelated optical element, such as a pixelated spatial light modulator, that may reflect or redirect one or more of the dispersed wavelength channels so that they are routed to any one of the output fibers, as described in more detail below.

[0039] In the WSS device 100a, all light rays originating from a position LC1 on the reflective liquid crystal element 130 are displaced by the lens 122 by an amount corresponding to the deflection angle from the reflective liquid crystal element 130, and are directed as parallel light rays tilted at an angle θ1. Thus, when the deflection angles are appropriately set, the output light rays reflected at the reflective liquid crystal element 130 (e.g., the reflected output light rays corresponding to a group of light rays, each of which may include one or more of the wavelength channels of the WDM signal beam BI1) can be routed to the output fibers FO1_1 through FO1_n, respectively. Here, because the output light rays reflected at the reflective liquid crystal element 130 are displaced by the same amount by the collimating lenses LO1_1 through LO1_n, they can be recombined into the output fibers FO1_1 through FO1_n with improved efficiency.

[0040] Similarly, in WSS device 100b, all light rays originating from position LC2 on reflective liquid crystal element 130 are displaced by lens 122 by an amount corresponding to the deflection angle from reflective liquid crystal element 130 and directed as parallel light rays tilted at angle θ2. Thus, when the deflection angles are appropriately set, output light rays reflected at reflective liquid crystal element 130 (e.g., reflected output light rays corresponding to a group of light rays that may each include one or more wavelength channels of WDM signal beam BI2) can be routed to output fibers FO2_1 through FO2_n, respectively. Here, because the output light rays reflected at reflective liquid crystal element 130 are displaced by the same amount by collimating lenses LO2_1 through LO2_n, they can be recombined into output fibers FO2_1 through FO2_n with improved efficiency.

[0041] Thus, the combination of input section 110 and lens 122 results in a WSS array 100 device that transmits a predetermined set of beams along a predetermined angle (e.g., angle θ1 for WSS device 100a and angle θ2 for WSS device 100b) and then directs these beams toward a position on reflective liquid crystal element 130 that depends only on the input angle (e.g., position LC1 for WSS device 100a and position LC2 for WSS device 100b). As a result, in WSS array 100, the light beams of WSS device 100a and the light beams of WSS device 100b are each processed by a common optical system 120 and reflective liquid crystal element 130, while each wavelength channel is processed separately by the processing capabilities of WSS array 100, as described in more detail below with reference to FIGS.

[0042] Next, the WSS array 100 will be described with reference to Figures 2 and 3. As already explained, Figure 2 is a view of the WSS array 100 as viewed from the y-axis direction. As already explained, Figure 3 is a view showing an example of wavelength channels focused on the reflective liquid crystal element 130. Of the WSS devices 100a and 100b, the following will mainly describe the WSS device 100a, but the same can be said for the WSS device 100b.

[0043] As shown in FIG. 2, in the WSS device 100a, a WDM signal beam BI1 that has passed through an input fiber FI1 is incident on an optical system 120. In the example of FIG. 2, the WDM signal beam BI1 propagates along a plane perpendicular to the paper (the yz plane) at an angle θ1. The WDM signal beam BI1 includes multiple wavelength channels. The multiple wavelength channels range from a longest wavelength λ1 to a shortest wavelength λn. Note that the WDM signal beam BI1 may include multiple wavelength channels, such as 96 wavelength channels spaced at 50 or 100 GHz on a fixed grating. In another example, the WSS device 100a may use a frequency spacing of 12.5 GHz and be used in an adaptive grating system having, for example, 130 or more wavelength channels (i.e., 97 or more wavelength channels).

[0044] In the optical system 120, the WDM signal beam BI1 is incident on a lens 121 that shapes the WDM signal beam BI1 in the x-axis direction. The lens 121 expands the WDM signal beam BI1, for example, so that the WDM signal beam BI1 has a diameter suitable for achieving a desired beam size in the dispersive element 124. Note that the collimating lens provided in the input unit 110 and the lens 121 provided in the optical system 120 may function as a beam expansion telescope.

[0045] In the optical system 120, the dispersive element 124 angularly disperses the wavelength channels of the WDM signal beam BI1. The wavelength channels λ1 to λn dispersed by the dispersive element 124 are each focused on the reflective liquid crystal element 130 by the lens 123. As a result, the wavelength channels λ1 to λn are spatially dispersed on the reflective liquid crystal element 130 in the wavelength dispersion direction (x-axis direction).

[0046] FIG. 3 illustrates an example of the distribution of wavelength channels in the pixel area of ​​the reflective liquid crystal element 130. Note that only wavelength channels λ1 to λ3 are shown in the example of FIG. 3 among the wavelength channels λ1 to λn. More generally, the wavelength channels can be arranged as long strips or elliptical spots on the two-dimensional surface of the reflective liquid crystal element 130. Simply put, each wavelength channel is treated as a discrete wavelength signal that can be independently acted upon by the reflective liquid crystal element 130. However, the reflective liquid crystal element 130 need not be limited to acting on individual wavelength channels but may also act upon groups of wavelength channels. Furthermore, as shown in FIG. 3, the wavelength channels or groups of wavelength channels themselves do not need to have fixed bandwidths because the reflective liquid crystal element 130 can be implemented in the WSS array 100 as a dynamically fully reconfigurable spatial light modulator. Therefore, the WSS array 100 can be used in systems with both conventional fixed-grid architectures and conventional or future-developed adaptive grid architectures.

[0047] As shown in FIG. 2, the reflective liquid crystal element 130 may then redirect wavelength channels λ1 to λn selected from the multiple wavelength channels toward output fibers FO1_1 to FO1_n, respectively. In the example of FIG. 2, the redirection by the reflective liquid crystal element 130 occurs along a plane (yz plane) perpendicular to the paper surface. The wavelength channels redirected by being reflected by the reflective liquid crystal element 130 are incident on the lens 123. The lens 123 redirects the incident wavelength channels so that they are recombined in the dispersive element 124. For example, the dispersive element 124 recombines the multiple wavelength channels to form a single beam (output beam). The output beams BO_1 to BO_n formed in the dispersive element 124 are redirected by the lens 122 and the collimating lens of the input unit 110 to become parallel beams, and are then output to the outside as processed signals via the output fibers FO1_1 to FO1_n.

[0048] For example, consider a case where a WDM signal beam BI1 includes three wavelength channels (hereinafter referred to as wavelength channels λ1 to λ3) having wavelengths λ1, λ2, and λ3 and channel bandwidths δλ1, δλ2, and δλ3, respectively. In this case, in the example of FIG. 1, the WDM signal beam BI1 is incident on the optical system 120 with a tilt angle of θ1. The light rays of the WDM signal beam BI1 traveling with a tilt angle of θ1 pass through the center of the lens 122, and therefore maintain the tilt angle of θ1. The WDM signal beam BI1 that has passed through the lens 122 is dispersed by the dispersive element 124 into multiple wavelength channels including the above-mentioned three wavelength channels along a plane (zx plane) perpendicular to the paper surface of FIG. 1. However, all of the multiple wavelength channels that have passed through the dispersive element 124 maintain the tilt angle of θ1 in a plane (yz plane) parallel to the paper surface of FIG. 1. The above three dispersed wavelength channels are then focused by a lens 123 onto different positions on the pixel area of ​​a reflective liquid crystal element 130, as shown in FIG.

[0049] It should be noted that several different routing functions may be combined in the routing function of the device. For example, consider the case where all three wavelength channels λ1-λ3 described above are routed to a common output fiber FO_n. After being reflected from reflective liquid crystal element 130, wavelength channels λ1-λ3 are deflected by lens 123 and focused before reaching dispersive element 124, where they are then recombined (multiplexed) to form a single output beam BO1_n. After passing through dispersive element 124, output beam BO1_n is redirected by lens 122 at an angle θ1.

[0050] The output beam BO1_n that has passed through the lens 122 travels along the yz plane at an angle θ1 with respect to the axis of symmetry Z1, passes through the lens 121, and is then incident on the collimating lens LO1_n. The collimating lens LO1_n changes the direction of the output beam BO1_n so that it is parallel to the axis of symmetry Z1. The output beam BO1_n that has passed through the collimating lens LO1_n is emitted outside the WSS array 100 via the output fiber FO1_n.

[0051] Note that the present invention is not limited to the case where multiple wavelength channels are routed to a common output fiber, and multiple wavelength channels may be routed to different output fibers. For example, consider the case where the above-mentioned three wavelength channels λ1 to λ3 are routed to different output fibers FO1_1 to FO1_3, respectively. Wavelength channels λ1 to λ3 reflected by reflective liquid crystal element 130 are deflected by lens 123 and then redirected by dispersive element 124 to form fan-shaped output beams BO1_1 to BO1_3. After passing through dispersive element 124, the fan-shaped output beams BO1_1 to BO1_3 are redirected by lens 122 so that they are each tilted by angle θ.

[0052] After passing through lens 122, the parallel output beams BO1_1 to BO1_3 travel along the yz plane at an angle θ1 with respect to the axis of symmetry Z1. After passing through lens 121, they are incident on collimating lenses LO1_1 to LO1_3, respectively. The collimating lenses LO1_1 to LO1_3 redirect the output beams BO1_1 to BO1_3 so that they are parallel to the axis of symmetry Z1. After passing through collimating lenses LO1_1 to LO1_3, the output beams BO1_1 to BO1_3 are emitted outside the WSS array 100 via output fibers FO1_1 to FO1_3, respectively. That is, in the WSS device 100a, wavelength channels λ1 to λ3 are routed from input fiber FI1_1 to each of output fibers FO1_1 to FO1_3 via the reflective liquid crystal element 130.

[0053] As described above, any wavelength channel of a WDM signal in WSS device 100a can be routed to one or more of the multiple output fibers as needed. The same can be said for any wavelength channel of a WDM signal in WSS device 100b. That is, any wavelength channel of a WDM signal in WSS device 100b can be routed to one or more of the multiple output fibers as needed. This is because, in WSS array 100, optical system 120 and reflective liquid crystal element 130 are configured to be symmetrical about axis of symmetry Z1, and the wavelength channels dispersed in WSS device 100a and the wavelength channels dispersed in WSS device 100b are focused at different positions on reflective liquid crystal element 130.

[0054] 1 to 3, a case where one input port (input fiber) and n output ports (output fibers) are provided for each WSS device has been described, but this is not limited thereto, and any number of input ports and any number of output ports may be provided for each WSS device. Furthermore, some or all of the n output ports may be reconfigured as input ports, and one input port may be reconfigured as an output port. Furthermore, in the example of FIGS. 1 to 3, a case where the WSS array 100 is configured with two WSS devices 100a and 100b has been described, but this is not limited thereto, and the WSS array 100 may be configured with three or more WSS devices.

[0055] Next, the reflective liquid crystal element 130 applied to the WSS array 100 will be described in detail.

[0056] <Preliminary study of liquid crystal devices> First, a liquid crystal device 50 previously studied by the present inventor will be described. The liquid crystal device 50 can also be used as the reflective liquid crystal element 130 of the WSS array 100.

[0057] (Configuration of liquid crystal device 50 at the concept stage) FIG. 4 is a diagram showing an example of the configuration of an active matrix liquid crystal device 50 at the conceptual stage.

[0058] 4, the liquid crystal device 50 includes an image display unit 11, a timing generator 13, a polarity switching control circuit 14, a vertical shift register & level shifter 15, a horizontal driver 16, an analog switch unit 17, and AND circuits ADA1 to ADAn and ADB1 to ADBn. The horizontal driver 16, together with the analog switch unit 17, forms a data line driving circuit and includes a shift register circuit 161, a one-line latch circuit 162, a comparator unit 163, and a gradation counter 164. Note that FIG. 4 also shows a ramp signal generator 40 that is connected to the liquid crystal device 50 during normal operation.

[0059] 5 is an enlarged view of the horizontal driver 16 and the analog switch section 17 provided in the liquid crystal device 50. The comparator section 163 includes m comparators 163_1 to 163_m corresponding to m (m is an integer of 2 or more) columns of pixels 12. The analog switch section 17 includes m sets of switch elements SW1+, SW1- to SWm+, SWm- corresponding to m columns of pixels 12.

[0060] Wired in the pixel arrangement region of the image display unit 11 are n rows (n is an integer of 2 or more) of row scanning lines G1 to Gn and n rows of readout switch selection lines TG1 to TGn extending in the horizontal direction (I-axis direction), and m columns of data lines D1+, D1- to Dm+, Dm- extending in the vertical direction (J-axis direction). Also wired in the pixel arrangement region of the image display unit 11 are gate control signal lines S+, S- and gate control signal line B.

[0061] The image display unit 11 has a plurality of regularly arranged pixels 12. Here, the plurality of pixels 12 are arranged in a two-dimensional matrix at n×m intersections in total where n row scanning lines G1 to Gn extending in the horizontal direction (I-axis direction) intersect with m sets of data lines D1+, D1− to Dm+, Dm− extending in the vertical direction (J-axis direction).

[0062] The row scanning line Gj (j is any integer from 1 to n) and the read switch selection line TGj are commonly connected to each of the m pixels 12 arranged in the jth row. Furthermore, the data lines Di+, Di- (i is any integer from 1 to m) are commonly connected to each of the n pixels 12 arranged in the i-th column. Furthermore, the gate control signal lines S+, S- and the gate control signal line B are all commonly connected to all of the pixels 12. However, the gate control signal lines S+, S- and the gate control signal line B may each be provided individually for each row.

[0063] Based on the timing signal generated by the timing generator 13, the polarity switching control circuit 14 outputs a gate control signal for positive polarity (hereinafter referred to as gate control signal S+) to the gate control signal line S+, outputs a gate control signal for negative polarity (hereinafter referred to as gate control signal S-) to the gate control signal line S-, and further outputs a gate control signal (hereinafter referred to as gate control signal B) to the gate control signal line B.

[0064] The vertical shift register & level shifter 15 outputs scan pulses for n rows, one row at a time, from the first row to the nth row, in a cycle of one horizontal scan period HST. The AND circuits ADA1 to ADAn each control whether or not to output the n scan pulses sequentially outputted row by row from the vertical shift register & level shifter 15 to the row scan lines G1 to Gn, based on a mode switching signal MD supplied from the outside. The AND circuits ADB1 to ADBn each control whether or not to output the n scan pulses sequentially outputted row by row from the vertical shift register & level shifter 15 to the read switch selection lines TG1 to TGn, based on a mode switching signal MD supplied from the outside.

[0065] For example, in the case of an operation in which a video signal is written to the pixels 12 (image writing operation), an H-level mode switching signal MD is supplied from the outside. In this case, the AND circuits ADA1 to ADAn output the n-row scanning pulses sequentially output one row at a time from the vertical shift register & level shifter 15 to the row scanning lines G1 to Gn, respectively. On the other hand, the AND circuits ADB1 to ADBn do not output the n-row scanning pulses sequentially output one row at a time from the vertical shift register & level shifter 15 to the read switch selection lines TG1 to TGn, respectively. Therefore, all of the read switch selection lines TG1 to TGn are fixed to the L level.

[0066] On the other hand, in the case of an operation for reading out the video signals written to the pixels 12 (image readout operation), an L-level mode switching signal MD is supplied from the outside. In this case, the AND circuits ADB1 to ADBn output the n-row scanning pulses sequentially output one row at a time from the vertical shift register & level shifter 15 to the readout switch selection lines TG1 to TGn, respectively. On the other hand, the AND circuits ADA1 to ADAn do not output the n-row scanning pulses sequentially output one row at a time from the vertical shift register & level shifter 15 to the row scanning lines G1 to Gn, respectively. Therefore, all of the row scanning lines G1 to Gn are fixed to the L level.

[0067] (Specific configuration example of pixel 12) 6 is a diagram showing a specific configuration example of the pixel 12. Here, the pixel 12 provided in the j-th row and the i-th column of the pixels 12 arranged in n rows and m columns will be described.

[0068] As shown in Figure 6, pixel 12 has N-channel MOS transistors (hereinafter simply referred to as transistors) Tr1, Tr2, Tr5, Tr6, and Tr9, P-channel MOS transistors (hereinafter simply referred to as transistors) Tr3, Tr4, Tr7, and Tr8, storage capacitors Cs1 and Cs2, and a liquid crystal display element LC.

[0069] The transistor Tr1 and the storage capacitor Cs1 constitute a sample-and-hold circuit that samples and holds a positive-polarity video signal supplied via the data line Di+. Specifically, the source of the transistor Tr1 is connected to one data line Di+ of the pair of data lines, the drain is connected to the gate of the transistor Tr3, and the gate is connected to the row scanning line Gj. The storage capacitor Cs1 is provided between the gate of the transistor Tr3 and the ground voltage terminal Vss.

[0070] The transistor Tr2 and the storage capacitor Cs2 form a sample-and-hold circuit that samples and holds a negative video signal supplied via the data line Di-. Specifically, the source of the transistor Tr2 is connected to the other data line Di- of the data line pair, the drain is connected to the gate of the transistor Tr4, and the gate is connected to the row scanning line Gj. The storage capacitor Cs2 is provided between the gate of the transistor Tr3 and the ground voltage terminal Vss. The storage capacitors Cs1 and Cs2 are provided independently of each other and store positive and negative video signals in parallel, respectively.

[0071] The transistors Tr3 and Tr7 form a source follower buffer (impedance conversion buffer) that outputs the voltage held in the holding capacitor Cs1. Specifically, the drain of the source follower transistor Tr3 is connected to the ground voltage line Vss, and the source is connected to a node Np. The transistor Tr7, which is used as a bias-controllable constant current load, has its source connected to the power supply voltage line Vdd, its drain connected to the node Np, and its gate connected to a gate control signal line B.

[0072] The transistors Tr4 and Tr8 form a source-follower buffer that outputs the voltage held in the holding capacitor Cs2. Specifically, the source-follower transistor Tr4 has its drain connected to the ground voltage line Vss and its source connected to node Nn. The transistor Tr8, used as a bias-controllable constant-current load, has its source connected to the power supply voltage line Vdd, its drain connected to node Nn, and its gate connected to the gate control signal line B.

[0073] The transistors Tr5 and Tr6 constitute a polarity switch. Specifically, the source of the transistor Tr5 is connected to the node Np, the drain is connected to the pixel drive electrode PE, and the gate is connected to one gate control signal line S+ of the pair of gate control signal lines. The source of the transistor Tr6 is connected to the node Nn, the drain is connected to the pixel drive electrode PE, and the gate is connected to the other gate control signal line S- of the pair of gate control signal lines.

[0074] The liquid crystal display element LC is composed of a pixel drive electrode (reflective electrode) PE that has light-reflecting properties, a common electrode CE that is optically transparent and arranged opposite the pixel drive electrode at a distance, and liquid crystal LCM that fills the space between them. A common voltage Vcom is applied to the common electrode CE. The transistor Tr9 is provided between the pixel drive electrode PE and the data line Di+ and is switched on and off by the read switch selection line TGj.

[0075] The pair of data lines Di+ and Di- are supplied with video signals of mutually opposite polarities sampled by the analog switch unit 17. When a scanning pulse output from the vertical shift register & level shifter 15 is supplied to the row scanning line Gj, the transistors Tr1 and Tr2 are simultaneously turned on. As a result, the voltages of the positive and negative video signals are accumulated and held in the storage capacitors Cs1 and Cs2, respectively.

[0076] The input resistance of each of the positive and negative source follower buffers is almost infinite, so the charge stored in each of the storage capacitors Cs1 and Cs2 is retained without leaking until one vertical scanning period has elapsed and a new video signal is written.

[0077] Transistors Tr5 and Tr6, which constitute the polarity switching switch, are switched on and off in response to gate control signals S+ and S-, alternately selecting the output voltage of the positive-side source follower buffer (positive-polarity video signal voltage) and the output voltage of the negative-side source follower buffer (negative-polarity video signal voltage) and outputting this to the pixel drive electrode PE. This causes a video signal voltage whose polarity periodically inverts to be applied to the pixel drive electrode PE. Because the pixels themselves have a polarity inversion function, this liquid crystal device enables high-frequency AC driving, regardless of the vertical scanning frequency, by quickly switching the polarity of the video signal voltage supplied to the pixel drive electrode PE in each pixel.

[0078] (Explanation of AC driving method for pixel 12) 7 is a timing chart for explaining a method of AC driving the pixels 12 by the liquid crystal device 50. Here, the AC driving method for the pixel 12 provided in the jth row and the ith column of the pixels 12 arranged in n rows and m columns will be explained.

[0079] In FIG. 7, VST represents a vertical synchronization signal that is the reference for vertical scanning of the video signal. B represents a gate control signal supplied to each gate of transistors Tr7 and Tr8 used as constant current loads for two types of source follower buffers. S+ represents a gate control signal supplied to the gate of transistor Tr5 on the positive side of the polarity changeover switch. S- represents a gate control signal supplied to the gate of transistor Tr6 on the negative side of the polarity changeover switch. VPE represents a voltage applied to the pixel drive electrode PE. Vcom represents a voltage applied to the common electrode CE. VLC represents an AC voltage applied to the liquid crystal LCM.

[0080] 8 is a diagram illustrating the voltage levels, from black to white, of the positive and negative video signals written to the pixel 12. In the example of FIG. 8, the positive video signal represents the black level when the voltage level is minimum and the white level when the voltage level is maximum. In contrast, the negative video signal represents the white level when the voltage level is minimum and the black level when the voltage level is maximum. However, the positive video signal may represent the white level when the voltage level is minimum and the black level when the voltage level is maximum. Also, the negative video signal may represent the black level when the voltage level is minimum and the white level when the voltage level is maximum. The dashed dotted lines in the diagram indicate the inversion centers of the positive and negative video signals.

[0081] In pixel 12, transistor Tr9 remains off because the read switch selection line TGj is fixed at the L level. On the other hand, transistors Tr1 and Tr2 are temporarily turned on when a scan pulse is supplied to row scan line Gj. When transistors Tr1 and Tr2 are turned on, the voltages of the positive and negative video signals are accumulated and held in storage capacitors Cs1 and Cs2, respectively.

[0082] As shown in Figure 7, while the gate control signal S+ is at the H level, the positive-side transistor Tr5 is on. At this time, by setting the gate control signal B to the L level, transistor Tr7 is on, activating the positive-side source follower buffer. This charges the pixel drive electrode PE to the voltage level of the positive video signal. Setting the gate control signal B to the L level also turns on transistor Tr8, activating the negative-side source follower buffer. However, because the negative-side transistor Tr6 is off, the pixel drive electrode PE is not charged to the voltage level of the negative video signal. Once the pixel drive electrode PE is fully charged, the gate control signal B is switched from the L level to the H level, and the gate control signal S+ is switched from the H level to the L level. This causes the pixel drive electrode PE to enter a floating state, maintaining a positive drive voltage across the liquid crystal capacitance.

[0083] Meanwhile, while the gate control signal S- is at the H level, the negative-side transistor Tr6 is turned on. At this time, by setting the gate control signal B to the L level, the negative-side transistor Tr8 is turned on, activating the negative-side source follower buffer. This charges the pixel drive electrode PE to the voltage level of the negative video signal. Setting the gate control signal B to the L level also turns on the transistor Tr7, activating the positive-side source follower buffer. However, because the positive-side transistor Tr5 is off, the pixel drive electrode PE is not charged to the voltage level of the positive video signal. Once the pixel drive electrode PE is fully charged, the gate control signal B is switched from the L level to the H level, and the gate control signal S- is switched from the H level to the L level. This causes the pixel drive electrode PE to enter a floating state, maintaining a negative drive voltage across the liquid crystal capacitance.

[0084] By alternately repeating the above-mentioned positive and negative side operations, an AC driving voltage VPE is applied to the pixel driving electrode PE using the voltages of the positive and negative video signals.

[0085] In addition, the charges held in the storage capacitors Cs1 and Cs2 are not transferred directly to the pixel drive electrode PE but are transferred via a source follower buffer. Therefore, even when the pixel drive electrode PE is repeatedly charged and discharged with positive and negative video signal voltages, the charges are not neutralized and pixel drive without attenuation of the voltage level can be achieved.

[0086] 7, the voltage level of the voltage Vcom applied to the common electrode CE is switched to the opposite level to that of the applied voltage VPE in synchronization with the switching of the voltage level of the voltage VPE applied to the pixel drive electrode PE. Note that the voltage Vcom applied to the common electrode CE has an inversion reference voltage that is approximately equal to the inversion reference voltage of the voltage VPE applied to the pixel drive electrode PE.

[0087] Here, the substantial AC voltage VLC applied to the liquid crystal LCM is the difference voltage between the voltage VPE applied to the pixel drive electrode PE and the voltage Vcom applied to the common electrode CE, and therefore an AC voltage VLC containing no DC component is applied to the liquid crystal LCM. In this way, by switching the voltage Vcom applied to the common electrode CE to be in opposite phase to the voltage VPE applied to the pixel drive electrode PE, the amplitude of the voltage to be applied to the pixel drive electrode PE can be reduced, thereby reducing the breakdown voltage and power consumption of the transistors that make up the pixel circuitry.

[0088] Even if the current steadily flowing through the source follower buffer per pixel is as small as 1 μA, the current steadily flowing through all pixels of the liquid crystal device may be large enough to be significant. For example, in a 2-megapixel liquid crystal device for full high-definition television, the current consumption may reach 2 A. Therefore, in pixel 12, transistors Tr7 and Tr8 used as constant current loads are not always on, but are only on for a limited period of time while the positive and negative transistors Tr5 and Tr6, respectively, are on. This allows the operation of one source follower buffer to be stopped while the other is operating, thereby suppressing an increase in current consumption.

[0089] The AC drive frequency of the liquid crystal display element LC can be freely adjusted by adjusting the pixel inversion control period, regardless of the vertical scanning frequency. For example, assume that the vertical scanning frequency is 60 Hz, the frequency used for general television video signals, and that the number of vertical scanning lines (n) in full high-definition television is 1,125 lines. Furthermore, assume that the polarity switching for each pixel occurs every 15 lines. In other words, assume that the number of lines (r) per polarity switching period for each pixel is 30 lines. In this case, the AC drive frequency of the liquid crystal is 60 Hz × 1,125 / (15 × 2) = 2.25 kHz. In other words, the liquid crystal device 50 can dramatically increase the AC drive frequency of the liquid crystal. This significantly improves the reliability, stability, and display quality of images displayed on the LCD screen, which were previously problematic when the AC drive frequency of the liquid crystal was low.

[0090] Next, the operation of the liquid crystal device 50 in each operation mode will be described.

[0091] (Operation of the liquid crystal device 50 in the image display mode) First, the operation of the liquid crystal device 50 in the image display mode (pixel writing mode) will be described with reference to Fig. 9. Fig. 9 is a timing chart showing the operation of the liquid crystal device 50 in the image display mode.

[0092] 9, when a pulse signal of the horizontal synchronization signal HST is supplied, the shift register circuit 161 sequentially captures m columns of video signals each having an N-bit width (N is an integer equal to or greater than 2) in synchronization with the clock signal HCK. The one-line latch circuit 162 simultaneously outputs the m columns of video signals captured by the shift register circuit 161 when the trigger signal REG_S temporarily becomes active.

[0093] The gradation counter 164 counts the number of rising edges of the clock signal CNT_CK and outputs a gradation signal Cout with a gradation level corresponding to the count value. Here, the gradation counter 164 outputs a gradation signal Cout with a minimum level at the start of one horizontal ramp period R (a transition period of the ramp signal within one horizontal scanning period) (at the rising edge of the horizontal synchronization signal HST), increases the gradation level of the gradation signal Cout as the count value increases, and outputs a gradation signal Cout with a maximum level at the end of one horizontal ramp period R (the time S before the next rising edge of the horizontal synchronization signal HST). The count value of the gradation counter 164 is initialized to "0" when the reset signal CNT_R becomes active in response to the rising edge of the horizontal synchronization signal HST, for example.

[0094] The m columns of comparators 163_1 to 163_m provided in the comparator section 163 operate in synchronization with the clock signal CMP_CK, and activate (for example, to L level) the match signals P1 to Pm at the timing when the gradation signal Cout output from the gradation counter 164 matches each of the m columns of video signals (line data) output simultaneously from the 1-line latch circuit 162.

[0095] Of the m sets of switch elements SW1+, SW1- to SWm+, and SWm- provided in the analog switch unit 17, the positive-side switch elements SW1+ to SWm+ are provided between the data lines D1+ to Dm+ and the common wiring Dcom+, respectively. Also, the negative-side switch elements SW1- to SWm- are provided between the data lines D1- to Dm- and the common wiring Dcom-, respectively. The m sets of switch elements SW1+, SW1- to SWm+, and SWm- are switched on and off by match signals P1 to Pm from the comparators 163_1 to 163_m, respectively.

[0096] The common wiring Dcom+ is supplied with a reference ramp voltage Ref_R+, which is a positive ramp signal output from the ramp signal generator 40. The common wiring Dcom- is supplied with a reference ramp voltage Ref_R-, which is a negative ramp signal output from the ramp signal generator 40.

[0097] The reference ramp voltage Ref_R+ is a sweep signal whose image level changes from black to white from the start to the end of each horizontal scanning period. The reference ramp voltage Ref_R- is a sweep signal whose image level changes from white to black from the start to the end of each horizontal scanning period. Therefore, the reference ramp voltage Ref_R+ relative to the common voltage Vcom and the reference ramp voltage Ref_R- relative to the common voltage Vcom are inversely related to each other.

[0098] The switch elements SW1+, SW1- to SWm+, and SWm- are simultaneously turned on when the start signal SW_Start becomes active (for example, H level) at the start of the horizontal ramp period R. Thereafter, the switch elements SW1+, SW1- to SWm+, and SWm- are switched from on to off when the match signals P1 to Pm output from the comparators 163_1 to 163_m become active (for example, L level). After the horizontal ramp period R ends, the start signal SW_Start becomes inactive (for example, L level).

[0099] In the example of FIG. 9, a waveform SPk indicates the timing of switching on and off the switch elements SWq+ and SWq- (q is an integer between 1 and m) provided corresponding to a pixel column to which a video signal of gradation level k is written. Referring to FIG. 9, the switch elements SWq+ and SWq- are turned on at the rising edge of the start signal SW_Start, and then switched from on to off when the match signal Pq becomes active. Here, the switch elements SWq+ and SWq- sample reference ramp voltages Ref_R+ and Ref_R- (voltages P and Q in FIG. 9) at the timing of switching from on to off. These sampled voltages P and Q are supplied to data lines Dq+ and Dq-. In other words, analog voltages P and Q, which are the results of DA conversion of the video signal of gradation level k, are supplied to the data lines Dq+ and Dq-, respectively.

[0100] In the image display mode, an H-level mode switching signal MD is externally supplied. Therefore, n-row scanning pulses, sequentially output row by row from the vertical shift register & level shifter 15, are supplied to the row scanning lines G1 to Gn, respectively. This temporarily turns on the transistors Tr1 and Tr2 provided in each pixel 12 in, for example, the j-th row. As a result, the voltages of the corresponding positive and negative video signals are accumulated and held in the storage capacitors Cs1 and Cs2 provided in each pixel 12 in the j-th row. Meanwhile, the transistor Tr9 provided in each pixel 12 remains in the off state. The subsequent AC driving method for each pixel 12 is as described above.

[0101] As described above, the switch elements SW1+, SW1- to SWm+, and SWm- are simultaneously turned on at the start of each horizontal scanning period, but are each turned off at an arbitrary timing according to the gradation level of the image to be displayed in the corresponding pixel 12. That is, the switch elements SW1+, SW1- to SWm+, and SWm- may all be turned off at the same time, or may be turned off at different times. The order in which they are turned off is also not fixed.

[0102] In this way, the liquid crystal device 50 can improve the linearity of the image by using the ramp signal to perform DA conversion on the video signal and then writing it to the pixel 12.

[0103] (Operation of the liquid crystal device 50 in pixel inspection mode) Next, an operation of the liquid crystal device 50 in a pixel inspection mode (pixel readout mode) will be described. In the pixel inspection mode, an inspection device (not shown) is provided instead of the ramp signal generator 40. Alternatively, in the pixel inspection mode, the ramp signal generator 40 functions as the inspection device.

[0104] In the pixel inspection mode, first, a video signal for inspection is written to the m pixels 12 in the jth row to be inspected. The operation at this time is basically the same as the operation in the pixel display mode. Then, the video signal (pixel drive voltage VPE) written to the m pixels 12 in the jth row to be inspected is read out.

[0105] During pixel readout, the externally supplied mode switching signal MD switches from H level to L level. Therefore, the scan pulse for the jth row output from the vertical shift register & level shifter 15 is supplied to the readout switch selection line TGj. This temporarily turns on the transistor Tr9 provided in each pixel 12 in the jth row being inspected. Meanwhile, the transistors Tr1 and Tr2 provided in each pixel 12 remain off.

[0106] For example, in pixel 12 located on the jth row and the ith column, transistor Tr9 is turned on, thereby bringing the pixel drive electrode PE and data line Di+ into a conductive state. At this time, by activating transistors Tr7 and Tr8 and turning on either transistor Tr5 or Tr6, the pixel drive electrode PE is driven by a source follower buffer consisting of transistors Tr3 and Tr7 or transistors Tr4 and Tr8. As a result, the drive voltage VPE applied to the pixel drive electrode PE by the source follower buffer is read out to the data line Di+.

[0107] The m pixel drive voltages VPE read out from the m pixels 12 in the jth row to the data lines D1+ to Dm+, respectively, are sequentially supplied to the common wiring Dcom+ by sequentially turning on m sets of SW1+, SW1- to SWm+, and SWm- provided in the analog switch unit 17. An inspection device (not shown) provided in place of the ramp signal generator 40 detects whether or not there are any failures (pixel defects and characteristic degradation) in the m pixels 12 in the jth row, based on the m pixel drive voltages VPE sequentially supplied via the common wiring Dcom+.

[0108] Such an inspection is performed row by row from the m pixels 12 in the first row to the m pixels 12 in the nth row.

[0109] Here, in the pixel 12 to be inspected, the voltage VPE of the pixel drive electrode PE driven by the source follower buffer with low output impedance is read out as is, so that defects and characteristic degradation of the pixel 12 to be inspected can be accurately and easily detected.

[0110] However, the pixel drive voltage VPE read from the pixel 12 under test is output to an external testing device via the data line Di+, the switch element SWi+, and the common wiring Dcom+. Therefore, the source follower buffer of the pixel 12 under test needs to drive wiring with a large load capacitance and a large resistance.

[0111] Specifically, the data line Di+ is supplemented with the wiring capacitance of n rows of pixels 12. For example, in the case of FHD (Full High Definition), the data line Di+ is supplemented with a wiring capacitance (e.g., 1 pF) equivalent to 1080 pixels. Furthermore, the common wiring Dcom+ is supplemented with a wiring capacitance of, e.g., 5 pF. Therefore, the source follower buffer of the pixel 12 under test must be charged with a high load capacitance totaling approximately 6 pF over a long period of time to stabilize the pixel drive voltage VPE at a level equivalent to the hold voltage of either of the hold capacitors Cs1 and Cs2. Furthermore, in pixel inspection mode, the pixel drive voltages VPE of all pixels 12 are serially read, which significantly lengthens the inspection time required by the inspection device. In other words, the liquid crystal device 50 suffers from the problem of being unable to quickly inspect the pixels 12 using the inspection device. Longer inspection times result in increased inspection costs.

[0112] If the pixel 12 to be inspected is inspected without waiting for the pixel drive voltage VPE to stabilize in order to shorten the inspection time, the inspection device will not be able to accurately detect defects or characteristic degradation in the pixel 12 to be inspected. In this case, for example, pixel defects cannot be identified unless the entire image is displayed on the image display unit 11, which increases the number of steps required for liquid crystal assembly, projection evaluation, etc., resulting in increased costs.

[0113] A solution to this problem is also disclosed in, for example, Patent Document 2. The liquid crystal display device disclosed in Patent Document 2 has a path for reading out a video signal from a pixel, separate from a path for writing a video signal to the pixel. Here, when reading out a video signal written to a pixel under test, this liquid crystal display device electrically separates a part of the path for writing the video signal to the pixel from the data line. As a result, when reading out a video signal written to the pixel under test, this liquid crystal display device does not need to charge the wiring capacitance of the wiring on the write path provided in common to multiple pixels, allowing the pixel under test to be inspected quickly.

[0114] However, in the liquid crystal display device disclosed in Patent Document 2, in order to inspect multiple pixels arranged in a matrix, it is necessary to repeat the transition of the clock signal supplied to the shift register circuit provided on the readout path of the video signal for each row by the number of horizontal pixels (1920 times in the case of FHD) and the number of vertical pixels (1080 times in the case of FHD), which still poses the problem of a long time required to inspect all the pixels.

[0115] In wafer inspection using a prober, all of the multiple liquid crystal display (liquid crystal device) chips printed on the wafer are inspected in order. Furthermore, multiple wafers (25 wafers in one lot) are inspected at once during wafer inspection. Therefore, even a slight delay in inspecting one liquid crystal device can significantly extend the time required for the entire wafer inspection.

[0116] Therefore, a liquid crystal device and an inspection method thereof according to a first embodiment have been found, which are capable of quickly inspecting pixels.

[0117] <First Embodiment> 10 is a diagram showing an example of the configuration of the liquid crystal device 1 according to the first embodiment. The liquid crystal device 1 is also used as a reflective liquid crystal element 130 of the WSS array 100.

[0118] Compared to the liquid crystal device 50, the liquid crystal device 1 further includes a path for reading out a video signal from the pixel 12 in addition to a path for writing a video signal to the pixel 12.

[0119] Specifically, the liquid crystal device 1 further includes a switch section 18, a sense amplifier section 19, a latch section 20, and shift register circuits 21a and 21b compared to the liquid crystal device 50. Note that Fig. 10 also shows a ramp signal generator 40 that is connected to the liquid crystal device 1 during normal operation. The other configurations of the liquid crystal device 1 are the same as those of the liquid crystal device 50, and therefore description thereof will be omitted.

[0120] Fig. 11 is a diagram showing a specific example of the configuration of the pixel 12 and its peripheral circuits provided in the liquid crystal device 1. Fig. 12 is a diagram showing in more detail the switch section 18, sense amplifier section 19, latch section 20, and shift register circuits 21 and 22 provided in the liquid crystal device 1.

[0121] 11, two pixels 12a and 12b are shown in the ja and jb rows and the ith column of the n rows and m columns of pixels 12. ja is any odd number between 1 and n, and jb is an even number between 1 and n that satisfies ja+1. Hereinafter, pixel 12 in any column of the ja row will also be referred to as pixel 12a, and pixel 12 in any column of the jb row will also be referred to as pixel 12b.

[0122] Pixel 12a, which is a pixel 12 in an odd-numbered row (row ja), has transistors Tr1a to Tr9a, storage capacitors Cs1a and Cs2a, and a liquid crystal display element LCa. Note that the transistors Tr1a to Tr9a, storage capacitors Cs1a and Cs2a, and liquid crystal display element LCa correspond to the transistors Tr1 to Tr9, storage capacitors Cs1 and Cs2, and liquid crystal display element LC, respectively.

[0123] Pixel 12b, which is a pixel 12 in an even-numbered row (jb-th row), has transistors Tr1b to Tr9b, storage capacitors Cs1b and Cs2b, and a liquid crystal display element LCb. Note that the transistors Tr1b to Tr9b, storage capacitors Cs1b and Cs2b, and liquid crystal display element LCb correspond to the transistors Tr1 to Tr9, storage capacitors Cs1 and Cs2, and liquid crystal display element LC, respectively.

[0124] In pixel 12a in the ja-th row and i-th column, transistor Tr9a is provided between pixel drive electrode PEa and data line Di+ and is switched on and off by read switch selection line TGja. In contrast, in pixel 12b in the jb-th row and i-th column, transistor Tr9b is provided between pixel drive electrode PEb and data line Di- and is switched on and off by read switch selection line TGjb.

[0125] The switch unit 18 switches whether to output to nodes Nd1_1 to Nd1_m the voltages of m positive-polarity video signals read out as positive-polarity pixel drive voltages from m pixels 12 in the row under test to m data lines D1+ to Dm+, respectively. The switch unit 18 also switches whether to output to nodes Nd2_1 to Nd2_m the voltages of m negative-polarity video signals read out as negative-polarity pixel drive voltages from m pixels 12 in the row under test to m data lines D1- to Dm-, respectively. The switch unit 18 also switches whether to output to m sets of data lines D1+, D1- to Dm+, Dm- a predetermined voltage (predetermined voltage mid) of the voltage supply line mid. The predetermined voltage mid indicates, for example, an intermediate voltage value between the power supply voltage Vdd and the ground voltage Vss.

[0126] The sense amplifier unit 19 amplifies the potential difference between the voltages output from the m data lines D1+ to Dm+ via the switch unit 18 to the nodes Nd1_1 to Nd1_m, respectively, and a predetermined voltage mid, and outputs amplified signals ea_1 to ea_m. The sense amplifier unit 19 also amplifies the potential difference between the voltages output from the m data lines D1- to Dm- via the switch unit 18 to the nodes Nd2_1 to Nd2_m, respectively, and a predetermined voltage mid, and outputs amplified signals eb_1 to eb_m. The latch unit 20 latches the m sets of amplified signals ea_1, eb_1 to ea_m, and eb_m output from the sense amplifier unit 19 and outputs them all at once.

[0127] 12, the switch unit 18 includes m switch elements SW2_1 to SW2_m, m switch elements SW3_1 to SW3_m, m switch elements SW7_1 to SW7_m, and m switch elements SW8_1 to SW8_m. The sense amplifier unit 19 includes m sets of sense amplifiers SAa_1, SAb_1 to SAa_m, and SAb_m. The latch unit 20 includes m sets of switch elements SW4a_1, SW4b_1 to SW4a_m, and SW4b_m.

[0128] In the switch section 18, switch elements SW2_1 to SW2_m are provided between the data lines D1+ to Dm+ and nodes Nd1_1 to Nd1_m, respectively, and are switched on and off by a switching signal KSW. Switch elements SW3_1 to SW3_m are provided between nodes Nd1_1 to Nd1_m and a voltage supply line mid, respectively, and are switched on and off by a switching signal nut. Switch elements SW7_1 to SW7_m are provided between the data lines D1- to Dm- and nodes Nd2_1 to Nd2_m, respectively, and are switched on and off by a switching signal KSW. Switch elements SW8_1 to SW8_m are provided between nodes Nd2_1 to Nd2_m and a voltage supply line mid, respectively, and are switched on and off by a switching signal nut.

[0129] In the sense amplifier unit 19, sense amplifiers SAa_1-SAa_m amplify the potential difference between the voltage of each of nodes Nd1_1-Nd1_m and a predetermined voltage mid, and output amplified signals ea_1-ea_m. Also, sense amplifiers SAb_1-SAb_m amplify the potential difference between the voltage of each of nodes Nd2_1-Nd2_m and a predetermined voltage mid, and output amplified signals eb_1-eb_m.

[0130] In the latch unit 20, switch elements SW4a_1-SW4a_m are provided on signal lines through which amplified signals ea_1-ea_m propagate, respectively, and are switched on and off by a trigger signal Tlat. Also, switch elements SW4b_1-SW4b_m are provided on signal lines through which amplified signals eb_1-eb_m propagate, respectively, and are switched on and off by a trigger signal Tlat.

[0131] For example, by turning on switch elements SW2_1 to SW2_m and switch elements SW3_1 to SW3_m, m data lines D1+ to Dm+ are shorted to the voltage supply line mid. As a result, the voltages of the m data lines D1+ to Dm+ are refreshed to a predetermined voltage mid. Similarly, by turning on switch elements SW7_1 to SW7_m and switch elements SW8_1 to SW8_m, m data lines D1- to Dm- are shorted to the voltage supply line mid. As a result, the voltages of the m data lines D1- to Dm- are refreshed to a predetermined voltage mid.

[0132] Furthermore, for example, by turning on switch elements SW2_1 to SW2_m and turning off switch elements SW3_1 to SW3_m, m pixel drive voltages read out from m pixels 12a in the test row ja to m data lines D1+ to Dm+ are output to nodes Nd1_1 to Nd1_m. Similarly, by turning on switch elements SW7_1 to SW7_m and turning off switch elements SW8_1 to SW8_m, m pixel drive voltages read out from m pixels 12b in the test row jb to m data lines D1- to Dm- are output to nodes Nd2_1 to Nd2_m. At this time, sense amplifiers SAa_1 to SAa_m amplify the potential difference between the voltages of nodes Nd1_1 to Nd1_m and a predetermined voltage mid, and output amplified signals ea_1 to ea_m represented by H or L levels. At this time, the sense amplifiers SAb_1 to SAb_m amplify the potential difference between the voltage of each of the nodes Nd2_1 to Nd2_m and a predetermined voltage mid, and output amplified signals eb_1 to eb_m expressed at H or L level. In the latch unit 20, the switch elements SW4a_1 to SW4a_m latch the amplified signals ea_1 to ea_m of the sense amplifiers SAa_1 to SAa_m, and the switch elements SW4b_1 to SW4b_m latch the amplified signals eb_1 to eb_m of the sense amplifiers SAb_1 to SAb_m and output them all at once.

[0133] (Specific example of the configuration of the sense amplifier SAa_i) 13 is a circuit diagram showing a specific example of the configuration of the sense amplifier SAa_i, which also shows a voltage source circuit 30.

[0134] 13, the sense amplifier SAa_i includes transistors Tr11 to Tr17. Transistors Tr13 to Tr16 are all P-channel MOS transistors, and transistors Tr11, Tr12, and Tr17 are all N-channel MOS transistors. The voltage source circuit 30 includes transistors Tr21 to Tr25. Transistors Tr21 and Tr24 are all P-channel MOS transistors, and transistors Tr22, Tr23, and Tr25 are all N-channel MOS transistors.

[0135] Transistors Tr15 and Tr16 are connected in parallel between the power supply voltage terminal Vdd and the ground voltage terminal Vss, and the voltage at node N2 is applied to their gates. Transistors Tr13 and Tr14 are connected in series with transistors Tr15 and Tr16, respectively, and the output voltage Va from the voltage source circuit 30 is applied to their gates. Transistors Tr11 and Tr12 are connected in series with transistors Tr13 and Tr14, respectively, and their gates are connected to a non-inverting input terminal to which the voltage at node Nd1_i is supplied and an inverting input terminal to which a predetermined voltage mid is supplied. Transistor Tr17 is connected between transistors Tr11 and Tr12 and the ground voltage terminal Vss, and the output voltage Vb from the voltage source circuit 30 is applied to its gate. The voltage at node N1 between transistors Tr11 and Tr13 is inverted by inverter INV3 and then output as an amplified signal ea_i.

[0136] In the voltage source circuit 30, the transistors Tr21 to Tr23 are all diode-connected and connected in series between the power supply voltage terminal Vdd and the ground voltage terminal Vss. The gate voltages of the transistors Tr21 and Tr22 are output as the voltage Va of the voltage source circuit 30. The transistors Tr24 and Tr25 are all diode-connected and connected in series between the power supply voltage terminal Vdd and the ground voltage terminal Vss. The gate voltage of the transistor Tr25 is output as the voltage Vb of the voltage source circuit 30.

[0137] The configuration of the sense amplifier SAa_i is not limited to the configuration shown in FIG. 13, but can be changed as appropriate to another configuration that can achieve the same function, or to a configuration of a high-performance sense amplifier with a higher gain.

[0138] The configuration of the sense amplifier SAb_i is the same as that of the sense amplifier SAa_i, except that the voltage of node Nd2_i is supplied to the non-inverting input terminal instead of the voltage of node Nd1_i, and the amplified signal eb_i is output from inverter INV3 instead of the amplified signal ea_i, so its explanation will be omitted.

[0139] The shift register circuit 21a has a dynamic shift register configuration, takes in the amplified signals ea_1 to ea_m output all at once from the latch unit 20, shifts them, and outputs them one by one in order as the inspection signal (detection signal) TOUT1. The shift register circuit 21b has a dynamic shift register configuration, takes in the amplified signals eb_1 to eb_m output all at once from the latch unit 20, shifts them, and outputs them one by one in order as the inspection signal (detection signal) TOUT2.

[0140] 14 is a diagram showing in more detail the shift register circuit 21a provided in the liquid crystal device 1. The shift register circuit 21a includes inverters INV1_1 to INV1_m, inverters INV2_1 to INV2_m, switch elements SW5_1 to SW5_m, switch elements SW6_1 to SW6_m, and a buffer BF1.

[0141] In the shift register circuit 21a, m combinations of series-connected switch elements SW5_i, inverters INV1_i, SW6_i, and inverters INV2_i are provided between the ground voltage terminal Vss and the output terminal OUT. A buffer BF1 is provided downstream of the inverter INV2_m, outputting an inspection signal TOUT1 to the outside via the output terminal OUT. Amplified signals ea_1 to ea_m simultaneously output from the latch unit 20 are supplied to the output terminals of the inverters INV1_1 to INV1_m, respectively. The switch elements SW5_1 to SW5_m are switched on and off by a clock signal TCK. The switch elements SW6_1 to SW6_m are switched on and off complementarily to the switch elements SW5_1 to SW5_m by a clock signal TCKb. The configuration of the shift register circuit 21a is not limited to the configuration shown in FIG. 14 and can be modified as needed to other configurations that can achieve equivalent functions.

[0142] The configuration of the shift register circuit 21b is the same as that of the shift register circuit 21a, except that amplified signals eb_1 to eb_m are supplied instead of amplified signals ea_1 to ea_m, and TOUT2 is output from the output terminal OUT instead of inspection signal TOUT1, so a description thereof will be omitted.

[0143] (Operation of liquid crystal device 1 in pixel inspection mode) Next, the operation of the liquid crystal device 1 in the pixel inspection mode will be described with reference to Figures 10, 11, etc., as well as Figure 15. Figure 15 is a timing chart showing the operation of the liquid crystal device 1 in the pixel inspection mode.

[0144] First, a test video signal is written to the plurality of pixels 12 in the ja and jb rows to be tested (times t1a and t1b). As already explained, ja is any odd number between 1 and n, and jb is an even number between 1 and n that satisfies ja+1.

[0145] The operation at this time is basically the same as the operation of writing a video signal in the image display mode. Specifically, a mode switching signal MD of H level is supplied from the outside.

[0146] As a result, first, the test video signal is written to the m pixels 12a in the ja-th row (time t1a). Specifically, the scan pulse for the ja-th row output from the vertical shift register & level shifter 15 is supplied to the row scan line Gja for the ja-th row. Therefore, for example, the transistors Tr1a and Tr2a provided in each pixel 12a in the ja-th row are temporarily turned on by the scan pulse being supplied to the row scan line Gja (time t1a). As a result, the voltages of the corresponding positive and negative video signals are accumulated and held in the storage capacitors Cs1a and Cs2a provided in each pixel 12a in the ja-th row. Meanwhile, the transistor Tr9a provided in each pixel 12a remains off.

[0147] Thereafter, the inspection video signal is written to the m pixels 12b in the jbth row (time t1b). Specifically, the scanning pulse for the jbth row output from the vertical shift register & level shifter 15 is supplied to the row scanning line Gjb for the jbth row. Therefore, for example, the transistors Tr1b and Tr2b provided in each pixel 12b in the jbth row are temporarily turned on by the scanning pulse being supplied to the row scanning line Gjb (time t1b). As a result, the voltages of the corresponding positive and negative video signals are accumulated and held in the storage capacitors Cs1b and Cs2b provided in each pixel 12b in the jbth row. On the other hand, the transistor Tr9b provided in each pixel 12b remains off.

[0148] Next, the video signals written to the plurality of pixels 12 in the ja and jb rows to be inspected are read out. At this time, the mode switching signal MD supplied from the outside is switched from H level to L level. At this time, the switch elements SW1+, SW1- to SWm+, SWm- provided in the analog switch unit 17 are all controlled to be off (the control signal A_SW (in other words, the signals P1 to Pm) that control the on / off of each switch element of the analog switch unit 17 are controlled to be inactive (L level)).

[0149] First, the switching signal KSW is set active (for example, to H level) to switch the switch elements SW2_1 to SW2_m and SW7_1 to SW7_m from off to on (time t2), thereby bringing the non-inverting input terminals of the sense amplifiers SAa_1 to SAa_m into a conductive state with the data lines D1+ to Dm+, and bringing the non-inverting input terminals of the sense amplifiers SAb_1 to SAb_m into a conductive state with the data lines D1- to Dm-.

[0150] Thereafter, the switching signal nut is temporarily set active (for example, to H level) to temporarily turn on the switch elements SW3_1 to SW3_m and SW8_1 to SW8_m (time t3). As a result, the data lines D1+ to Dm+ are shorted to the voltage supply line mid, so the voltages of the data lines D1+ to Dm+ are refreshed to the predetermined voltage mid. Also, the data lines D1- to Dm- are shorted to the voltage supply line mid, so the voltages of the data lines D1- to Dm- are refreshed to the predetermined voltage mid.

[0151] Next, the positive polarity video signals written in the storage capacitors Cs1a of the m pixels 12a in the ja-th row to be inspected are read out to the data lines D1+ to Dm+, and the positive polarity video signals written in the storage capacitors Cs1b of the m pixels 12b in the jb-th row to be inspected are read out to the data lines D1- to Dm-. At this time, an H-level mode switching signal TMD is supplied from the outside.

[0152] First, of the gate control signals S+ and S−, only the gate control signal S+ is made active (H level) (time t4). This turns on the transistor Tr5a of each pixel 12a in the ja-th row and the transistor Tr5b of each pixel 12b in the jb-th row. At this time, the gate control signal B is made active (L level) to operate the positive-side source follower buffers consisting of the transistors Tr3a and Tr7a of each pixel 12a in the ja-th row, and also operate the positive-side source follower buffers consisting of the transistors Tr3b and Tr7b of each pixel 12b in the jb-th row (time t4). This causes the pixel drive electrode PEa of each pixel 12a in the ja-th row to be charged with the voltage of the positive-side video signal held in the storage capacitor Cs1a, and the pixel drive electrode PEb of each pixel 12b in the jb-th row to be charged with the voltage of the positive-side video signal held in the storage capacitor Cs1b.

[0153] Thereafter, the scanning pulses for the ja and jb rows output from the vertical shift register and level shifter 15 are supplied to the read switch selection lines TGja and TGjb for the ja and jb rows, respectively (time t5).

[0154] As a result, the transistor Tr9a provided in each pixel 12a in the ja-th row is temporarily turned on by supplying a scan pulse to the readout switch selection line TGja, and the transistor Tr9b provided in each pixel 12b in the jb-th row is temporarily turned on by supplying a scan pulse to the readout switch selection line TGjb. As a result, the pixel drive electrodes PEa of the m pixels 12a in the ja-th row are each conductive with the data lines D1+ to Dm+, and the pixel drive electrodes PEb of the m pixels 12b in the jb-th row are each conductive with the data lines D1- to Dm-. As a result, the positive video signal voltage VPEa charged to the pixel drive electrodes PEa of the m pixels 12a in the ja-th row is read out and held on the data lines D1+ to Dm+ as a positive pixel drive voltage. Furthermore, the voltages VPEb of the positive video signals charged to the pixel drive electrodes PEb of the m pixels 12b in the jbth row are read out as positive pixel drive voltages to the data lines D1- to Dm-, respectively, and held there.

[0155] Here, because all switches in the analog switch unit 17 are controlled to be off, the data line Di+ is not subjected to the wiring capacitance of about 5 pF of the common wiring Dcom+, and only the wiring capacitance of the pixels 12 for n rows is applied. For example, in the case of FHD, only the wiring capacitance of about 1 pF for 1080 pixels is applied to the data line Di+. Therefore, in the liquid crystal device 1, the source follower buffer (Tr3a, Tr7a) provided in the pixel 12a in the j-th row and i-th column to be tested can charge the data line Di+ in a short time without being affected by the wiring capacitance or wiring resistance of the common wiring Dcom+.

[0156] Similarly, because all switches in the analog switch unit 17 are controlled to be off, the data line Di- does not have the wiring capacitance of about 5 pF of the common wiring Dcom-, and only the wiring capacitance of the pixels 12 for n rows is added. For example, in the case of FHD, only the wiring capacitance of about 1 pF for 1080 pixels is added to the data line Di-. Therefore, in the liquid crystal device 1, the source follower buffer (Tr3b, Tr7b) provided in the pixel 12b in the jbth row and the ith column to be tested can charge the data line Di- in a short time without being affected by the wiring capacitance or wiring resistance of the common wiring Dcom-.

[0157] The voltages of the positive video signals (positive pixel drive voltages) of the m pixels 12a in the ja-th row read out to the data lines D1+ to Dm+ are supplied to the non-inverting input terminals of the sense amplifiers SAa_1 to SAa_m, respectively. The voltages of the positive video signals (positive pixel drive voltages) of the m pixels 12b in the jb-th row read out to the data lines D1- to Dm- are supplied to the non-inverting input terminals of the sense amplifiers SAb_1 to SAb_m, respectively.

[0158] The sense amplifiers SAa_1 to SAa_m amplify the potential differences between the voltages of m positive-polarity video signals read out from the m pixels 12a in the ja-th row to the data lines D1+ to Dm+, respectively, and a predetermined voltage mid, and output amplified signals ea_1 to ea_m expressed at H or L level. Also, the sense amplifiers SAb_1 to SAb_m amplify the potential differences between the voltages of m positive-polarity video signals read out from the m pixels 12b in the jb-th row to the data lines D1- to Dm-, respectively, and a predetermined voltage mid, and output amplified signals eb_1 to eb_m expressed at H or L level.

[0159] Then, the switch elements SW4a_1 to SW4a_m and switch elements SW4b_1 to SW4b_m provided in the latch section 20 simultaneously output the amplified signals ea_1 to ea_m and the amplified signals eb_1 to eb_m at the timing when the trigger signal Tlat temporarily becomes active (time t6).

[0160] Thereafter, the shift register circuit 21a takes in the amplified signals ea_1 to ea_m simultaneously output from the latch unit 20, and shifts them to output them one by one in order as the checking signal TOUT1 (time t7). Also, the shift register circuit 21b takes in the amplified signals eb_1 to eb_m simultaneously output from the latch unit 20, and shifts them to output them one by one in order as the checking signal TOUT2 (time t7).

[0161] An inspection device (not shown) provided outside the liquid crystal device 1 detects failures (defects, characteristic degradation, etc.) in the m pixels 12 in the jth row being inspected by comparing the values ​​of these inspection signals TOUT1 and TOUT2 with expected values.

[0162] Such an inspection is performed in order, two rows at a time, from the m pixels 12 in the first row to the m pixels 12 in the nth row.

[0163] After the inspection of the signals written to the storage capacitors Cs1 (Cs1a, Cs1b) of all pixels 12 is completed, inspection is then performed on the signals written to the storage capacitors Cs2 (Cs2a, Cs2b) of all pixels 12. The specific processing is the same as the inspection of the signals written to the storage capacitors Cs1 (Cs1a, Cs1b) of all pixels 12, except that at time t4, the gate control signal S− is made active (H level) instead of the gate control signal S+ to turn on the transistor Tr6a of each pixel 12a in the ja-th row and the transistor Tr6b of each pixel 12b in the jb-th row, and therefore a description thereof will be omitted.

[0164] As described above, the liquid crystal device 1 according to the present embodiment includes a path for reading out a video signal from the pixel 12, separate from a path for writing a video signal to the pixel 12, and when reading out a video signal written to the pixel 12 under test, a part of the path for writing the video signal to the pixel 12 is electrically separated from the data line. As a result, when reading out a video signal written to the pixel 12 under test, the liquid crystal device 1 according to the present embodiment does not need to charge the wiring capacitance of the common wirings Dcom+ and Dcom-, for example, and therefore can shorten the time required for the source follower buffer of each pixel 12 to stabilize the pixel drive voltage VPE, and as a result, the pixel 12 can be inspected quickly using an inspection device.

[0165] Furthermore, the liquid crystal device 1 according to this embodiment can also test vertical pixel connections. For example, the liquid crystal device 1 can detect whether the pixel drive electrodes PEa and PEb of vertically adjacent pixels 12a and 12b are short-circuited due to a manufacturing defect.

[0166] For example, in the normal state where pixel drive electrodes PEa and PEb are not shorted, if a 1V video signal voltage is written to storage capacitor Cs1a of pixel 12a and a 4V video signal voltage is written to storage capacitor Cs1b of pixel 12b vertically adjacent to pixel 12a, transistors Tr5a, Tr7a, and Tr9a of pixel 12a are turned on, outputting a pixel drive voltage of 1V to data line Di+, and transistors Tr5b, Tr7b, and Tr9b of pixel 12b are turned on, outputting a pixel drive voltage of 1V to data line Di-. Here, if the predetermined voltage mid is set to 2V, sense amplifier SAa_i outputs an amplified signal ea_i at an L level, and sense amplifier SAb_i outputs an amplified signal eb_i at an H level.

[0167] In contrast, when pixel drive electrodes PEa and PEb are shorted, if a 1V video signal voltage is written to storage capacitor Cs1a of pixel 12a and a 4V video signal voltage is written to storage capacitor Cs1b of pixel 12b vertically adjacent to pixel 12a, transistors Tr5a, Tr7a, and Tr9a of pixel 12a turn on, outputting a pixel drive voltage of 2.5V to data line Di+, and transistors Tr5b, Tr7b, and Tr9b of pixel 12b turn on, outputting a pixel drive voltage of 2.5V to data line Di-. Here, if the predetermined voltage mid is set to 2V, sense amplifier SAa_i outputs an H-level amplified signal ea_i, and sense amplifier SAb_i outputs an H-level amplified signal eb_i.

[0168] In this way, the liquid crystal device 1 can detect that the pixel drive electrodes PEa and PEb of the vertically adjacent pixels 12a and 12b are short-circuited due to a manufacturing defect.

[0169] Furthermore, the liquid crystal device 1 according to this embodiment can also inspect for leakage of charges accumulated in the storage capacitors Cs1 and Cs2 provided in each pixel 12. In other words, it can also inspect for leakage of charges accumulated in the storage capacitors Cs1a and Cs2a provided in each pixel 12a, and leakage of charges accumulated in the storage capacitors Cs1b and Cs2b provided in each pixel 12b.

[0170] In each pixel 12a, the N-type diffusion layer forming the drain of the transistor Tr1a and the P-well are PN junctioned. Therefore, if a defect occurs in the PN junction during the manufacturing process, the charge stored in the storage capacitor Cs1a may leak to the P-well via the PN junction. As a result, the voltage of the storage capacitor Cs1a may gradually decrease toward the ground voltage level. Similarly, the N-type diffusion layer forming the drain of the transistor Tr2a and the P-well are PN junctioned. Therefore, if a defect occurs in the PN junction during the manufacturing process, the charge stored in the storage capacitor Cs2a may leak to the P-well via the PN junction. As a result, the voltage of the storage capacitor Cs2a may gradually decrease toward the ground voltage level. In this case, a pixel defect occurs in the image displayed on the liquid crystal display panel (the display screen of the image display unit 11).

[0171] In each pixel 12b, an N-type diffusion layer forming the drain of transistor Tr1b and a P-well are PN-junctioned. Therefore, if a defect occurs in the PN junction during the manufacturing process, the charge stored in storage capacitor Cs1b may leak to the P-well via the PN junction. As a result, the voltage of storage capacitor Cs1b may gradually decrease toward the ground voltage level. Similarly, an N-type diffusion layer forming the drain of transistor Tr2b and a P-well are PN-junctioned. Therefore, if a defect occurs in the PN junction during the manufacturing process, the charge stored in storage capacitor Cs2b may leak to the P-well via the PN junction. As a result, the voltage of storage capacitor Cs2b may gradually decrease toward the ground voltage level. In this case, a pixel defect occurs in the image displayed on the liquid crystal display panel (the display screen of the image display unit 11).

[0172] Therefore, in the liquid crystal device 1 according to the present embodiment, when inspecting for leakage of electric charges accumulated in the storage capacitors Cs1a and Cs2a provided in each pixel 12a, the time from when a video signal is written to the storage capacitor Cs1a of the pixel 12a to be inspected until the video signal written to the storage capacitor Cs1a is read out is made longer than that during normal inspection. Similarly, the time from when a video signal is written to the storage capacitor Cs2a of the pixel 12a to be inspected until the video signal written to the storage capacitor Cs2a is read out is made longer than that during normal inspection.

[0173] As a result, if charge is leaking from the storage capacitor Cs1a, the voltage held in the storage capacitor Cs1a will decrease over time, and the source follower buffer (Tr3a, Tr7a) will output this decreased voltage as the pixel drive voltage. Similarly, if charge is leaking from the storage capacitor Cs2a, the voltage held in the storage capacitor Cs2a will decrease over time, and the source follower buffer (Tr4a, Tr8a) will output this decreased voltage as the pixel drive voltage.

[0174] When testing for charge leakage from the storage capacitor Cs1a of the pixel 12a under test, for example, the expected value of the pixel drive voltage read from the storage capacitor Cs1a is set to 2.6V, and the predetermined voltage mid is set to 2.5V. If the storage capacitor Cs1a of the pixel 12a under test is not leaking charge, the pixel drive voltage read from the pixel 12a will be 2.6V, and the sense amplifier output will be H level, indicating that the pixel 12a is normal. On the other hand, if the storage capacitor Cs1a of the pixel 12a under test is leaking charge, the pixel drive voltage read from the pixel 12a will be lower than the expected value (e.g., 2.4V), and the sense amplifier output will be L level, indicating that the storage capacitor Cs1a of the pixel 12a under test is leaking charge. By subsequently repeating fine-tuning and testing the expected value of the pixel drive voltage, the amount of leakage from the storage capacitor Cs1a can be determined.

[0175] Similarly, when testing for charge leakage from the storage capacitor Cs2a of the pixel 12a under test, the expected value of the pixel drive voltage read from the storage capacitor Cs2a is set to 2.6V, and the predetermined voltage mid is set to 2.5V. If the storage capacitor Cs2a of the pixel 12a under test is not leaking charge, the pixel drive voltage read from the pixel 12a will be 2.6V, and the sense amplifier output will be H level, indicating that the pixel 12a is normal. On the other hand, if the storage capacitor Cs2a of the pixel 12a under test is leaking charge, the pixel drive voltage read from the pixel 12a will be lower than the expected value (e.g., 2.4V), and the sense amplifier output will be L level, indicating that the storage capacitor Cs2a of the pixel 12a under test is leaking charge. By then repeatedly fine-tuning the expected value of the pixel drive voltage and testing, the amount of leakage from the storage capacitor Cs2a can be determined.

[0176] Furthermore, in the liquid crystal device 1 according to the present embodiment, when inspecting for leakage of electric charges accumulated in the storage capacitors Cs1b and Cs2b provided in each pixel 12b, the time from when a video signal is written to the storage capacitor Cs1b of the pixel 12b to be inspected until the video signal written to the storage capacitor Cs1b is read out is made longer than during normal inspection. Similarly, the time from when a video signal is written to the storage capacitor Cs2b of the pixel 12b to be inspected until the video signal written to the storage capacitor Cs2b is read out is made longer than during normal inspection.

[0177] As a result, if charge is leaking from storage capacitor Cs1b, the voltage held in storage capacitor Cs1b will decrease over time, and this decreased voltage will be output as is as a pixel drive voltage by the source follower buffer (Tr3b, Tr7b). Similarly, if charge is leaking from storage capacitor Cs2b, the voltage held in storage capacitor Cs2b will decrease over time, and this decreased voltage will be output as is as a pixel drive voltage by the source follower buffer (Tr4b, Tr8b).

[0178] When testing for charge leakage from the storage capacitor Cs1b of the pixel 12b under test, for example, the expected value of the pixel drive voltage read from the storage capacitor Cs1b is set to 2.6V, and the predetermined voltage mid is set to 2.5V. If the storage capacitor Cs1b of the pixel 12b under test is not leaking charge, the pixel drive voltage read from the pixel 12b will be 2.6V, and the sense amplifier output will be H level, indicating that the pixel 12b under test is normal. On the other hand, if the storage capacitor Cs1b of the pixel 12b under test is leaking charge, the pixel drive voltage read from the pixel 12b will be lower than the expected value (e.g., 2.4V), and the sense amplifier output will be L level, indicating that the storage capacitor Cs1b of the pixel 12b under test is leaking charge. By subsequently repeating fine-tuning and testing the expected value of the pixel drive voltage, the amount of leakage from the storage capacitor Cs1b can be determined.

[0179] Similarly, when testing for charge leakage from the storage capacitor Cs2b of the pixel 12b under test, the expected value of the pixel drive voltage read from the storage capacitor Cs2b is set to 2.6V, and the predetermined voltage mid is set to 2.5V. If the storage capacitor Cs2b of the pixel 12b under test is not leaking charge, the pixel drive voltage read from the pixel 12b will be 2.6V, and the sense amplifier output will be H level, indicating that the pixel 12b is normal. On the other hand, if the storage capacitor Cs2b of the pixel 12b under test is leaking charge, the pixel drive voltage read from the pixel 12b will be lower than the expected value (e.g., 2.4V), and the sense amplifier output will be L level, indicating that the storage capacitor Cs2b of the pixel 12b under test is leaking charge. By subsequently repeating fine-tuning and testing the expected value of the pixel drive voltage, the amount of leakage from the storage capacitor Cs2b can be determined.

[0180] In this way, the liquid crystal device 1 can be inspected for leakage from the storage capacitors Cs1 and Cs2 provided in each pixel 12. In other words, the liquid crystal device 1 can be inspected for leakage from the storage capacitors Cs1a and Cs2a provided in each pixel 12a, and leakage from the storage capacitors Cs1b and Cs2b provided in each pixel 12a.

[0181] If the amount of leakage from the storage capacitors Cs1a, Cs2a and Cs1b, Cs2b and their locations can be identified, it is possible to correct the amount of leakage during normal operation. This allows chips that would otherwise be discarded to be corrected and reused, thereby improving yield.

[0182] Furthermore, since the PADs added for the probe test (for example, PADs to which signals TCK, TCKb, Tlat, nut, mid, KSW, and TOUT are supplied externally) are not used after the test, the pixel inspection circuit is initialized and fixed, for example, by pulling down or pulling up. This prevents unintended operation and unintended leakage current even if the PADs added for the probe test are floating with no external signal voltage input.

[0183] As described above, the liquid crystal device 1 according to this embodiment not only makes it possible to quickly check whether the transistors Tr1 to Tr9 and the storage capacitors Cs1 and Cs2 constituting the pixel 12 to be tested are operating normally, but also makes it possible to identify the amount of leakage from the storage capacitors Cs1 and Cs2.

[0184] Furthermore, in the pixel inspection mode, the liquid crystal device 1 according to this embodiment executes both the operation of writing a video signal to the pixel 12 and the operation of reading a video signal from the pixel 12. Therefore, it is possible to inspect not only the pixel 12 but also the peripheral circuitry thereof to check whether it is operating normally. It goes without saying that the pixel inspection method for the liquid crystal device 1 according to this embodiment may be used in combination with other inspection methods.

[0185] The present disclosure is not limited to the above-described embodiment, and can be modified as appropriate within the scope of the present disclosure. [Explanation of symbols]

[0186] 1 Liquid crystal devices 11 Image display section 12 pixels 13 Timing Generator 14 Polarity switching control circuit 15 Vertical shift register & level shifter 16 Horizontal Driver 17 Analog switch section 18 Switch section 19 Sense amplifier section 20 Latch section 21a Shift register circuit 21b Shift register circuit 30 Voltage Source Circuit 40 Ramp Signal Generator 50 Liquid Crystal Devices 100 WSS Array 100a WSS device 100b WSS device 110 Input section 120 Optical system 121 Lens 122 Lens 123 Lens 124 Dispersion element 130 Reflective liquid crystal element 161 Shift register circuit 162 1-line latch circuit 163 Comparator section 163_1~163_m Comparator 164 Gradation Counter ADA1~ADAn AND circuit ADB1~ADBn AND circuit B Gate control signal line BF1 buffer CE common electrode Cs1,Cs2 retention capacity D1+,D1-~Dm+,Dm- data lines Dcom+, Dcom- common wiring FI1 Input Fiber (Input Port) FI2 Input Fiber (Input Port) FO1_1~FO1_n Output fibers (output ports) FO2_1~FO2_n Output fibers (output ports) G1~Gn row scanning line INV1_1~INV1_m inverters INV2_1~INV2_m inverters INV3 inverter LC liquid crystal display element LCM LCD LI1 Collimating Lens LI2 Collimating Lens LO1_1~LO1_n Collimating lenses LO2_1~LO2_n Collimating lenses N1,N2 nodes Np,Nn nodes Nd1_1~Nd1_m nodes Nd2_1~Nd2_m nodes PE Pixel driving electrode (reflective electrode) S+, S- Gate control signal lines SAa_1~SAa_m Sense amplifier SAb_1~SAb_m Sense amplifier SW1+, SW1- to SWm+, SWm- Switch elements SW2_1~SW2_m Switch elements SW3_1~SW3_m Switch elements SW4a_1~SW4a_m Switch elements SW4b_1~SW4b_m Switch elements SW5_1~SW5_m Switch elements SW6_1~SW6_m Switch elements SW7_1~SW7_m Switch elements SW8_1~SW8_m Switch elements TG1~TGn Readout switch selection lines Tr1 to Tr9 transistors Tr11~Tr17 transistors Tr21~Tr25 Transistors

Claims

1. A plurality of pixels arranged in a matrix; a plurality of first data lines provided corresponding to each column of the plurality of pixels; a plurality of second data lines provided corresponding to each column of the plurality of pixels; a plurality of first switch elements that switch whether or not a positive polarity video signal is supplied to each of the plurality of first data lines, and switch whether or not a negative polarity video signal is supplied to each of the plurality of second data lines; a plurality of first sense amplifiers configured to amplify potential differences between a plurality of pixel drive voltages read out to the plurality of first data lines from the plurality of pixels provided in a first row to be inspected and a predetermined voltage in a pixel inspection mode, and output the amplified potential differences as a plurality of first detection signals; a plurality of second sense amplifiers configured to amplify potential differences between a plurality of pixel drive voltages read out to the plurality of second data lines from a plurality of pixels provided in a second row to be inspected adjacent to the first row and the predetermined voltage in a pixel inspection mode, and output the amplified potential differences as a plurality of second detection signals; Equipped with Each of the pixels is a first sample-and-hold circuit that samples and holds a positive-polarity video signal supplied to the corresponding first data line; a second sample-and-hold circuit that samples and holds a negative video signal supplied to the corresponding second data line; a liquid crystal display element including a pixel drive electrode, a common electrode, and liquid crystal sealed between them; a polarity changeover switch that selectively outputs the voltage of the video signal held in the first sample-and-hold circuit and the voltage of the video signal held in the second sample-and-hold circuit to the pixel drive electrode; and Each of the pixels in the first row comprises: a first switch transistor for outputting a voltage of the pixel driving electrode to the corresponding first data line in a pixel inspection mode; Each of the pixels in the second row comprises: a second switch transistor for outputting the voltage of the pixel driving electrode to the corresponding second data line in a pixel testing mode; Liquid crystal device.

2. a first shift register circuit that receives output signals from the plurality of first sense amplifiers, and shifts and sequentially outputs the received output signals; a second shift register circuit that receives output signals from the second sense amplifiers, shifts the received output signals, and outputs them in order; Furthermore, 10. The liquid crystal device according to claim 1.

3. Each of the pixels is a first source follower buffer that outputs the voltage of the video signal held by the first sample-and-hold circuit; a second source follower buffer that outputs the voltage of the video signal held by the second sample-and-hold circuit; Furthermore, the polarity switching switch is configured to selectively output the output voltages of the first and second source follower buffers to the pixel drive electrodes.

10. The liquid crystal device according to claim 1.

4. a plurality of second switch elements that supply predetermined voltages to the plurality of first data lines, respectively, before a plurality of pixel drive voltages are read out from the plurality of pixels in the first row to be tested, in a pixel test mode; a plurality of third switch elements that supply the predetermined voltages to the second data lines, respectively, before a plurality of pixel drive voltages are read out from the pixels in the second row to be tested to the second data lines, in a pixel test mode; Furthermore, 10. The liquid crystal device according to claim 1.

5. a driver that controls the plurality of first switch elements to be turned on and the first or second switch transistor provided in each of the pixels to be turned off when writing the video signal, and controls the plurality of first switch elements to be turned on and the first or second switch transistor provided in each of the pixels in a row to be inspected to be turned on when reading out the video signal, 10. The liquid crystal device according to claim 1.

6. An input port; one or more output ports; a reflective liquid crystal element, which is the liquid crystal device according to any one of claims 1 to 5, having a plurality of pixels that deflect an optical signal that is incident on the input port and outputs the deflected optical signal from any one of the one or more output ports; A wavelength selective switch device comprising:

7. A plurality of pixels arranged in a matrix; a plurality of first data lines provided corresponding to each column of the plurality of pixels; a plurality of second data lines provided corresponding to each column of the plurality of pixels; a plurality of first switch elements that switch whether or not a positive polarity video signal is supplied to each of the plurality of first data lines, and switch whether or not a negative polarity video signal is supplied to each of the plurality of second data lines; a plurality of first sense amplifiers configured to amplify potential differences between a plurality of pixel drive voltages read out to the plurality of first data lines from the plurality of pixels provided in a first row to be inspected and a predetermined voltage in a pixel inspection mode, and output the amplified potential differences as a plurality of first detection signals; a plurality of second sense amplifiers configured to amplify potential differences between a plurality of pixel drive voltages read out to the plurality of second data lines from a plurality of pixels provided in a second row to be inspected adjacent to the first row and the predetermined voltage in a pixel inspection mode, and output the amplified potential differences as a plurality of second detection signals; Equipped with Each of the pixels is a first sample-and-hold circuit that samples and holds a positive-polarity video signal supplied to the corresponding first data line; a second sample-and-hold circuit that samples and holds a negative video signal supplied to the corresponding second data line; a liquid crystal display element including a pixel drive electrode, a common electrode, and liquid crystal sealed between them; a polarity changeover switch that selectively outputs the voltage of the video signal held in the first sample-and-hold circuit and the voltage of the video signal held in the second sample-and-hold circuit to the pixel drive electrode; and Each of the pixels in the first row comprises: a first switch transistor for outputting a voltage of the pixel driving electrode to the corresponding first data line in a pixel inspection mode; Each of the pixels in the second row comprises: a second switch transistor for outputting the voltage of the pixel driving electrode to the corresponding second data line in a pixel testing mode; A pixel inspection method for a liquid crystal device, comprising: supplying the positive video signal to each of the plurality of first data lines and the negative video signal to each of the plurality of second data lines by turning on the plurality of first switch elements while keeping the first or second switch transistor provided in each of the pixels off; writing the positive video signal to the plurality of pixels in the row to be inspected from each of the plurality of first data lines, and writing the negative video signal to the plurality of pixels in the row to be inspected from each of the plurality of second data lines; turning on the first switch transistors provided in the pixels in the first row to be inspected while keeping the first switch elements in an off state, thereby reading out a plurality of pixel drive voltages from the plurality of pixels in the first row to be inspected to the plurality of first data lines, respectively; turning on the second switch transistors provided in the pixels in the second row to be tested while keeping the first switch elements in an off state, thereby reading out a plurality of pixel drive voltages from the pixels in the second row to be tested to the second data lines, respectively; using the plurality of first sense amplifiers, amplifying potential differences between a plurality of pixel drive voltages read out from a plurality of the pixels in the first row to be inspected onto the plurality of first data lines, respectively, and the predetermined voltage, and outputting the amplified potential differences as a plurality of first detection signals; using the plurality of second sense amplifiers, amplifying potential differences between a plurality of pixel drive voltages read out from a plurality of the pixels in the second row to be inspected onto the plurality of second data lines, respectively, and the predetermined voltage, and outputting the amplified potential differences as a plurality of second detection signals; detecting whether or not there is a failure in the plurality of pixels in the first and second rows to be inspected based on the plurality of first and second detection signals output from the plurality of first and second sense amplifiers, respectively; A pixel inspection method for liquid crystal devices.

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