Imaging element and imaging device

Abstract

To improve the signal-to-noise ratio at high sensitivity readout while allowing for expansion of the dynamic range.SOLUTION: A solid-state imaging element 4 has a plurality of pixel blocks BL having one photoelectric conversion part PD, a node P, and one transfer switch TX provided corresponding to one photoelectric conversion part PD to transfer charge from the photoelectric conversion part PD to the node P, an electrical connection provided between a node P of one pixel block BL and a node P in one other pixel block BL, and a plurality of connecting switches SWa and SWb per one of the pixel blocks BL provided in the connection.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a solid-state imaging device and an imaging apparatus using the same. [Background technology]

[0002] Patent Document 1 listed below discloses a solid-state imaging device having a plurality of pixels, at least two of which each include (a) a photodetector, (b) a charge-voltage conversion region forming a floating capacitance portion, and (c) an input portion to an amplifier, and a connecting switch that selectively connects the charge-voltage conversion regions together. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2008-546313 Summary of the Invention [Problem to be solved by the invention]

[0004] In the conventional solid-state imaging device, by turning on the connection switch to connect the charge-voltage conversion regions together, the number of saturated electrons in all connected charge-voltage conversion regions is increased, thereby expanding the dynamic range.

[0005] Furthermore, in the conventional solid-state imaging device, by turning off the connection switch and isolating the charge-voltage conversion region from other charge-voltage conversion regions, the charge-voltage conversion capacity becomes smaller and the charge-voltage conversion coefficient becomes larger, thereby increasing the signal-to-noise ratio during high-sensitivity readout.

[0006] However, in the conventional solid-state imaging device, even if the connection switch is turned off, the signal-to-noise ratio during high-sensitivity readout cannot be increased significantly.

[0007] The present invention has been made in view of the above circumstances, and aims to provide a solid-state imaging element that can expand the dynamic range and improve the signal-to-noise ratio during high-sensitivity readout, and an imaging device using the same. [Means for solving the problem]

[0008] The following aspects are presented as means for solving the above problems: A solid-state imaging device according to a first aspect includes a plurality of pixel blocks each having one photoelectric conversion unit, a node, and a transfer switch provided corresponding to the one photoelectric conversion unit for transferring charges from the photoelectric conversion unit to the node, an electrical connection unit provided between the node of one of the pixel blocks and the node of another of the pixel blocks, and a plurality of linking switches provided in the connection unit for each of the pixel blocks.

[0009] The pixel block may have only one photoelectric conversion unit and be configured with one pixel, or may have two or more photoelectric conversion units and be configured with a plurality of pixels, as in each aspect described below.

[0010] A solid-state imaging element according to a second aspect is the same as in the first aspect, and includes a control unit that controls the connecting switch, and in a first operating mode, the control unit controls the connecting switch so that the connection portion is electrically disconnected from the node of the pixel block, and in a second operating mode, the control unit controls the connecting switch so that the connection portion is electrically connected to the node of the pixel block.

[0011] In the solid-state imaging element according to the third aspect, in the second aspect, the control unit controls the connecting switches so that, in the second operating mode, a predetermined number of at least one of the connecting switches that are in an on state are electrically connected to the node of the pixel block.

[0012] A solid-state imaging device according to a fourth aspect is the first aspect, wherein the nodes of three or more pixel blocks among the plurality of pixel blocks are connected in a daisy chain manner by a plurality of the connection portions.

[0013] A solid-state imaging element according to a fifth aspect is the same as in the fourth aspect, and includes a control unit that controls the connecting switch, and in a first operating mode, the control unit controls the connecting switch so that the connection portion is electrically disconnected from the node of one of the three or more pixel blocks, and in a second operating mode, the control unit controls the connecting switch so that the connection portion is electrically connected to the node of the one of the three or more pixel blocks.

[0014] A solid-state imaging element according to a sixth aspect is the fifth aspect, wherein the control unit controls the connecting switches in the second operating mode so that a predetermined number of one or more of the connecting switches that are in an on state are electrically connected to the node of one of the three or more pixel blocks.

[0015] A solid-state imaging device according to a seventh aspect is the solid-state imaging device according to any one of the first to sixth aspects, wherein each of the pixel blocks includes a plurality of the photoelectric conversion units and a plurality of the transfer switches.

[0016] A solid-state imaging element according to an eighth aspect comprises a plurality of pixel blocks each having a plurality of photoelectric conversion units, a node, and a plurality of transfer switches each corresponding to the plurality of photoelectric conversion units and transferring electric charges from the plurality of photoelectric conversion units to the node, and a plurality of connecting switches each provided between the nodes of two adjacent pixel blocks.

[0017] A solid-state imaging element according to a ninth aspect is the same as that of the eighth aspect, and includes a control unit that controls the connecting switches, and in a first operating mode, the control unit controls the connecting switches so that none of the connecting switches that are in an on state among the connecting switches are electrically connected to the node of one of the two pixel blocks, and in a second operating mode, the control unit controls the connecting switches so that one or more predetermined number of the connecting switches that are in an on state among the connecting switches are electrically connected to the node of the one pixel block.

[0018] The solid-state imaging element according to the tenth aspect is the eighth aspect, in which the nodes of three or more pixel blocks among the plurality of pixel blocks are connected in a daisy chain manner by two or more sets of the plurality of connecting switches.

[0019] The solid-state imaging element according to the 11th aspect is the same as in the 10th aspect, and includes a control unit that controls the connecting switches, and in a first operating mode, the control unit controls the connecting switches so that none of the connecting switches that are in an on state among the connecting switches are electrically connected to the node of one of the three or more pixel blocks, and in a second operating mode, the control unit controls the connecting switches so that one or more predetermined number of the connecting switches that are in an on state among the connecting switches are electrically connected to the node of the one pixel block.

[0020] A solid-state imaging element according to a twelfth aspect is an element of any one of the seventh to eleventh aspects, wherein the transfer switches are made of transistors, and in each of the pixel blocks, a diffusion region serving as the source or drain of one of the transfer switches and a diffusion region serving as the source or drain of another of the transfer switches are shared by a single diffusion region provided between one of the photoelectric conversion units and another of the photoelectric conversion units, and in each of the pixel blocks, the gate electrode of the one transfer switch is arranged on the side of the one photoelectric conversion unit of the one diffusion region, and in each of the pixel blocks, the gate electrode of the other transfer switch is arranged on the side of the other photoelectric conversion unit of the one diffusion region.

[0021] A solid-state imaging device according to a thirteenth aspect is the solid-state imaging device according to any one of the seventh to twelfth aspects, wherein the number of the plurality of photoelectric conversion units and the number of the plurality of transfer switches are each two.

[0022] A solid-state imaging element according to the 14th aspect is the 13th aspect, in which the number of the plurality of connecting switches is two, and the amount of positional deviation in a predetermined direction between one connecting switch of the plurality of connecting switches and another connecting switch of the plurality of connecting switches is greater than the pitch in the predetermined direction of the plurality of photoelectric conversion units and less than twice the pitch.

[0023] A solid-state imaging element according to a 15th aspect is one in which, in any one of the first to fourteenth aspects, the number of the plurality of connecting switches is two, and when the plurality of connecting switches are off, the value of the capacitance between the connection between the plurality of connecting switches and the reference potential is within a range of ±20% of the value of the capacitance between the node and the reference potential when the plurality of connecting switches are off.

[0024] A solid-state imaging element according to the 16th aspect is one that, in any of the first to 15th aspects, satisfies any one of the following: the number of the plurality of connecting switches is two; when the plurality of connecting switches are off, the width of at least a portion of the wiring that constitutes the connection between the plurality of connecting switches is wider than the width of the other wiring within the pixel block; a MOS capacitance is connected to the connection; and a diffusion capacitance that does not constitute each of the connecting switches is connected to the connection.

[0025] A solid-state imaging element according to a seventeenth aspect comprises a plurality of pixel blocks each having one photoelectric conversion unit, a first node, and one transfer switch corresponding to the one photoelectric conversion unit for transferring electric charges from the photoelectric conversion unit to the first node; two second nodes corresponding respectively to the first node of one of the pixel blocks and the first node of another of the pixel blocks; two first switch units electrically connecting and disconnecting the first node of one of the pixel blocks and the first node of the other of the pixel blocks to the two second nodes, respectively; and a second switch unit electrically connecting and disconnecting the two second nodes.

[0026] The solid-state imaging element according to the 18th aspect is the same as the 17th aspect, and further includes a control unit that controls each of the first switch units and the second switch units, wherein the control unit controls the first switch units so that, in a first operating mode, the first switch units that electrically connect and disconnect between the first node of the one pixel block and the corresponding second node are turned off, and the control unit controls the first switch units and the second switch units so that, in a second operating mode, a predetermined number of the first switch units and the second switch units that are in an on state are electrically connected to the first node of the one pixel block.

[0027] A solid-state imaging element according to a 19th aspect is the same as that of the 17th aspect, except that it includes three or more first switch units that electrically connect and disconnect the first nodes of three or more pixel blocks among the plurality of pixel blocks to three or more second nodes corresponding to these three or more first nodes, and the three or more second nodes are connected in a daisy chain manner by a plurality of second switch units.

[0028] A solid-state imaging element according to a 20th aspect is the same as that of the 19th aspect, and includes a control unit that controls each of the first switch units and each of the second switch units, wherein the control unit controls the first switch unit of one of the three or more pixel blocks so that, in a first operating mode, the first switch unit that electrically connects and disconnects between the first node of one of the three or more pixel blocks and the corresponding second node is turned off, and the control unit controls each of the first switch units and each of the second switch units so that, in a second operating mode, a predetermined number of on-state switch units of each of the first switch units and each of the second switch units are electrically connected to the first node of the one of the three or more pixel blocks.

[0029] A solid-state imaging device according to a 21st aspect is the solid-state imaging device according to any one of the 17th to 20th aspects, wherein each of the pixel blocks has a plurality of the photoelectric conversion units and the transfer switches.

[0030] A solid-state imaging element according to a 22nd aspect is the 21st aspect, wherein the transfer switches are transistors, and in each of the pixel blocks, a diffusion region serving as the source or drain of one of the transfer switches and a diffusion region serving as the source or drain of another of the transfer switches are shared by a single diffusion region provided between one of the photoelectric conversion units and another of the photoelectric conversion units, and in each of the pixel blocks, the gate electrode of the one transfer switch is arranged on the side of the one photoelectric conversion unit of the one diffusion region, and in each of the pixel blocks, the gate electrode of the other transfer switch is arranged on the side of the other photoelectric conversion unit of the one diffusion region.

[0031] A solid-state imaging device according to a 23rd aspect is the 21st or 22nd aspect, wherein the number of the plurality of photoelectric conversion units and the number of the plurality of transfer switches are each two.

[0032] A solid-state imaging element according to the 24th aspect is any one of the 17th to 23rd aspects, wherein the value of the capacitance between the second node and the reference potential when each of the first switch sections and each of the second switch sections is in the off state is within a range of ±20% of the value of the capacitance between the first node and the reference potential when the first switch section is in the off state.

[0033] A solid-state imaging element according to the 25th aspect is one in which, in any of the 17th to 24th aspects, the width of at least a portion of the wiring connected to the second node is wider than the width of other wiring within the pixel block, a MOS capacitance is connected to the second node, and a diffusion capacitance that does not constitute either the first switch section or the second switch section is connected to the second gate.

[0034] An imaging device according to a 26th aspect includes the solid-state imaging element according to any one of the first to 25th aspects.

[0035] An imaging device according to the 27th aspect includes a solid-state imaging element according to any one of the second, third, fifth, sixth, ninth, eleventh, eighteenth and twentieth aspects, and a control means for switching between the first operating mode and the second operating mode depending on the set value of ISO sensitivity. [Effects of the Invention]

[0036] According to the present invention, it is possible to provide a solid-state imaging device that can expand the dynamic range and improve the S / N ratio during high-sensitivity readout, and an imaging apparatus using the same. [Brief explanation of the drawings]

[0037] [Figure 1] 1 is a schematic block diagram showing an electronic camera according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging device in FIG. [Figure 3] FIG. 3 is an enlarged circuit diagram showing the vicinity of three pixel blocks in FIG. 2. [Figure 4] FIG. 4 is a schematic plan view showing the vicinity of the three pixel blocks shown in FIG. 3. [Figure 5] 5 is a schematic plan view showing an enlarged view of the vicinity of one pixel block in FIG. 4. FIG. [Figure 6] 3 is a timing chart showing a predetermined operation mode of the solid-state imaging device shown in FIG. 2. [Figure 7] 3 is a timing chart showing another operation mode of the solid-state imaging device shown in FIG. 2. [Figure 8] 10 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. [Figure 9] FIG. 10 is a circuit diagram showing the vicinity of three pixel blocks of a solid-state imaging device according to a comparative example. [Figure 10]10 is a schematic plan view showing the vicinity of the three pixel blocks shown in FIG. 9. FIG. [Figure 11] FIG. 10 is a circuit diagram showing the vicinity of three pixel blocks of a solid-state imaging device of an electronic camera according to a second embodiment of the present invention. [Figure 12] 12 is a schematic plan view showing the vicinity of the three pixel blocks shown in FIG. 11. FIG. [Figure 13] FIG. 10 is a circuit diagram showing a schematic configuration of a solid-state imaging device of an electronic camera according to a third embodiment of the present invention. [Figure 14] FIG. 10 is a circuit diagram showing a schematic configuration of a solid-state imaging device of an electronic camera according to a fourth embodiment of the present invention. [Figure 15] FIG. 15 is an enlarged circuit diagram showing the vicinity of four pixel blocks in FIG. 14. [Figure 16] 15 is a timing chart showing a predetermined operation mode of the solid-state imaging device shown in FIG. 14. [Figure 17] 15 is a timing chart showing another operation mode of the solid-state imaging device shown in FIG. 14. [Figure 18] 15 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. [Figure 19] 15 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. [Figure 20] 15 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. [Figure 21] FIG. 10 is a circuit diagram showing a schematic configuration of a solid-state imaging device of an electronic camera according to a fifth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0038] A solid-state imaging device and an imaging apparatus according to the present invention will be described below with reference to the drawings.

[0039] [First embodiment] FIG. 1 is a schematic block diagram showing an electronic camera 1 according to a first embodiment of the present invention.

[0040] The electronic camera 1 according to this embodiment is configured as, for example, a single-lens reflex digital camera, but the imaging device according to the present invention is not limited to this and can be applied to various imaging devices such as other electronic cameras such as compact cameras, electronic cameras mounted on mobile phones, and electronic cameras such as video cameras that capture moving images.

[0041] A photographing lens 2 is attached to the electronic camera 1. The focus and aperture of this photographing lens 2 are driven by a lens control unit 3. In the image space of this photographing lens 2, the imaging surface of a solid-state imaging device 4 is arranged.

[0042] The solid-state imaging device 4 is driven by commands from the imaging control unit 5 and outputs a digital image signal. During normal actual shooting (still image shooting), the imaging control unit 5 controls the solid-state imaging device 4 to perform a predetermined readout operation after, for example, performing a so-called global reset in which all pixels are reset simultaneously, followed by exposure using a mechanical shutter (not shown). In addition, during electronic viewfinder mode or video shooting, the imaging control unit 5 controls the solid-state imaging device 4 to perform a predetermined readout operation while using, for example, a so-called rolling electronic shutter. In these cases, the imaging control unit 5 controls the solid-state imaging device 4 to perform a readout operation in each operating mode, as described below, according to the ISO sensitivity setting. The digital signal processing unit 6 performs image processing, such as digital amplification, color interpolation, and white balance adjustment, on the digital image signal output from the solid-state imaging device 4. The image signal processed by the digital signal processing unit 6 is temporarily stored in a memory 7. The memory 7 is connected to a bus 8. The bus 8 is also connected to the lens control unit 3, the imaging control unit 5, the CPU 9, a display unit 10 such as an LCD panel, a recording unit 11, an image compression unit 12, and an image processing unit 13. An operation unit 14 such as a release button is connected to the CPU 9. The ISO sensitivity can be set using the operation unit 14. A recording medium 11a is detachably attached to the recording unit 11.

[0043] When an instruction for electronic viewfinder mode, video recording, or normal main shooting (still image recording) is issued via the operation unit 14, the CPU 9 in the electronic camera 1 drives the imaging control unit 5 accordingly. At this time, the lens control unit 3 adjusts the focus and aperture as appropriate. The solid-state imaging element 4 is driven by commands from the imaging control unit 5 to output a digital image signal. The digital image signal from the solid-state imaging element 4 is processed by the digital signal processing unit 6 and then stored in the memory 7. In the electronic viewfinder mode, the CPU 9 displays the image signal on the display unit 10, and during video recording, the CPU 9 records the image signal on the recording medium 11a. During normal main shooting (still image recording), the CPU 9 processes the digital image signal from the solid-state imaging element 4 in the digital signal processing unit 6 and stores it in the memory 7. Based on commands from the operation unit 14, the CPU 9 then performs desired processing as necessary via the image processing unit 13 or image compression unit 12, and then causes the recording unit 11 to output the processed signal, which is then recorded on the recording medium 11a.

[0044] Fig. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging element 4 in Fig. 1. Fig. 3 is a circuit diagram showing an enlarged view of the vicinity of three pixel blocks BL arranged in sequence in the column direction in Fig. 2. Fig. 4 is a schematic plan view showing a schematic enlarged view of the vicinity of the three pixel blocks BL shown in Fig. 3. Fig. 5 is a schematic plan view showing an enlarged view of the vicinity of one pixel block BL in Fig. 4. In this embodiment, the solid-state imaging element 4 is configured as a CMOS-type solid-state imaging element, but is not limited to this and may be configured as, for example, another XY-address type solid-state imaging element.

[0045] As shown in Figures 2 to 4, the solid-state imaging element 4 includes pixel blocks BL arranged in a two-dimensional matrix of N rows and M columns, each having two pixels PX (PXA, PXB), connecting transistors SWa and SWb as multiple connecting switches per pixel block BL, a vertical scanning circuit 21, control lines 22 to 27 provided for each row of the pixel blocks BL, multiple (M) vertical signal lines 28 provided for each column of pixels PX (for each column of the pixel blocks BL) and receiving signals from the pixels PX (pixel blocks BL) in the corresponding column, a constant current source 29 provided for each vertical signal line 28, a column amplifier 30, a CDS circuit (correlated double sampling circuit) 31 and an A / D converter 32 provided corresponding to each vertical signal line 28, and a horizontal readout circuit 33.

[0046] An analog amplifier or a so-called switched capacitor amplifier may be used as the column amplifier 30. Also, the column amplifier 30 does not necessarily have to be provided.

[0047] For convenience of illustration, FIG. 2 shows M=2, but in reality, the number of columns M can be any larger number. The number of rows N is also not limited. When pixel blocks BL are distinguished by row, the pixel block BL in the jth row is indicated by the symbol BL(j). This also applies to other elements and control signals described later. Three pixel blocks BL(n-1) to BL(n+1) are shown in FIGS. 2 and 3, one for the n-1th row through the other for the n+1th row.

[0048] In the drawings, the pixel in the pixel block BL at the bottom in FIGS. 2 and 3 is designated PXA, and the pixel in the upper in FIGS. 2 and 3 is designated PXB, to distinguish between them. However, when describing the two without distinguishing between them, the symbol PX may be used to refer to both. In the drawings, the photodiode in pixel PXA is designated PDA, and the photodiode in pixel PXB is designated PDB, to distinguish between them. However, when describing the two without distinguishing between them, the symbol PD may be used to refer to both. Similarly, the transfer transistor in pixel PXA is designated TXA, and the transfer transistor in pixel PXB is designated TXB, to distinguish between them. However, when describing the two without distinguishing between them, the symbol TX may be used to refer to both. In this embodiment, the photodiodes PD of the pixels PX are arranged in a two-dimensional matrix of 2N rows and M columns.

[0049] In this embodiment, each pixel PX has a photodiode PD as a photoelectric conversion unit that generates and accumulates signal charge in response to incident light, and a transfer transistor TX as a transfer switch that transfers the charge from the photodiode PD to a node P.

[0050] In this embodiment, the pixels PX form a pixel block BL, with each pair of pixels PX (PXA, PXB) having photodiodes PD arranged in sequence in the column direction. As shown in FIGS. 2 and 3 , for each pixel block BL, the two pixels PX (PXA, PXB) belonging to that pixel block BL share a set of a node P, an amplifier transistor AMP, a reset transistor RST, and a selection transistor SEL. A capacitance (charge-voltage conversion capacitance) is formed between the node P and a reference potential, and the charge transferred to the node P is converted into a voltage by this capacitance. The amplifier transistor AMP constitutes an amplifier unit that outputs a signal corresponding to the potential of the node P. The reset transistor RST constitutes a reset switch that resets the potential of the node P. The selection transistor SEL constitutes a selection unit for selecting the pixel block BL. The photodiode PD and the transfer transistor TX are not shared by the two pixels PX (PXA, PXB), but are provided for each pixel PX. In FIGS. 2 and 3 , n indicates the row of the pixel block BL. For example, the pixel block BL of the first row is composed of the pixel PX (PXA) of the first row and the pixel PX (PXB) of the second row, and the pixel block BL of the second row is composed of the pixel PX (PXA) of the third row and the pixel PX (PXB) of the fourth row.

[0051] In the present invention, for example, a pixel block BL may be configured for every three or more pixels PX in which photodiodes PD are sequentially arranged in the column direction.

[0052] Although not shown in the drawings, in this embodiment, a plurality of types of color filters, each of which transmits light of a different color component, are arranged in a predetermined color array (e.g., a Bayer array) on the light incident side of the photodiode PD of each pixel PX. The pixel PX outputs an electrical signal corresponding to each color through color separation by the color filters.

[0053] For each pair of pixel blocks BL adjacent to each other in the column direction, two coupling transistors SWa and SWb are provided in series as two coupling switches in an electrical connection path (connection section) provided between a node P of one pixel block BL and a node P of the other pixel block BL, the connection path (connection section) being a unique connection path (connection section) therebetween. Thus, in this embodiment, the nodes P of three or more pixel blocks BL are connected in a daisy-chain fashion by a plurality of the connection paths (connection sections). Of the two coupling transistors SWa and SWb, the coupling transistor SWa is disposed on the side of the node P of the lower pixel block BL in FIGS. 2 and 3, and the coupling transistor SWb is disposed on the side of the node P of the upper pixel block BL in FIGS. 2 and 3.

[0054] For example, two coupling transistors SWa(n) and SWb(n) are connected in series in a unique electrical connection path between a node P(n) in a pixel block BL(n) on the nth row and a node P(n+1) in a pixel block BL on the n+1th row. As shown in FIG. 4, the coupling transistor SWa(n) is formed within the pixel block BL(n), while the coupling transistor SWb(n) is formed within the pixel block BL(n+1). However, the same (n) is added to the end of the reference numerals of these coupling transistors SWa(n) and SWb(n) to indicate that they are connected in series in the same unique connection path. Note that, although three or more coupling switches may be connected in series in each unique connection path in the present invention, it is preferable to connect two coupling transistors SWa and SWb in series in each unique connection path, as in this embodiment, in order to simplify the structure.

[0055] 2 and 3, VDD is a power supply potential. In this embodiment, the transistors TXA, TXB, AMP, RST, SEL, SWa, and SWb are all nMOS transistors.

[0056] The gates of the transfer transistors TXA for each row are connected in common to a control line 26, to which a control signal φTXA is supplied from the vertical scanning circuit 21. The gates of the transfer transistors TXB for each row are connected in common to a control line 25, to which a control signal φTXB is supplied from the vertical scanning circuit 21. The gates of the reset transistors RST for each row are connected in common to a control line 24, to which a control signal φRST is supplied from the vertical scanning circuit 21. The gates of the selection transistors SEL for each row are connected in common to a control line 23, to which a control signal φSEL is supplied from the vertical scanning circuit 21. The gates of the connecting transistors SWa for each row are connected in common to a control line 22, to which a control signal φSWa is supplied from the vertical scanning circuit 21. The gates of the connecting transistors SWb for each row are connected in common to a control line 27, to which a control signal φSWb is supplied from the vertical scanning circuit 21. For example, a control signal φTXA(n) is supplied to the gate of the transfer transistor TXA(n), a control signal φTXB(n) is supplied to the gate of the transfer transistor TXB(n), a control signal φRST(n) is supplied to the gate of the reset transistor RST(n), a control signal φSEL(n) is supplied to the gate of the selection transistor SEL(n), a control signal φSWa(n) is supplied to the gate of the linking transistor SWa(n), and a control signal φSWb(n) is supplied to the gate of the linking transistor SWb(n).

[0057] The transistors TXA, TXB, RST, SEL, SWa, and SWb are turned on when the corresponding control signals φTXA, φTXB, φRST, φSEL, φSWa, and φSWb are at high level (H), and turned off when they are at low level (L).

[0058] 1, the vertical scanning circuit 21 outputs control signals φTXA, φTXB, φRST, φSEL, φSWa, and φSWb for each row of the pixel block BL to control the pixel block BL and the connecting transistors SWa and SWb, thereby realizing still image readout operations, moving image readout operations, and the like. In this control, readout operations in various operation modes, which will be described later, are performed according to, for example, the ISO sensitivity setting. Through this control, signals (analog signals) from the pixels PX in the corresponding column are supplied to each vertical signal line 28.

[0059] In this embodiment, the vertical scanning circuit 21 constitutes a control unit that switches between each operation mode, which will be described later, in response to a command (control signal) from the imaging control unit 5 in FIG.

[0060] The signals read out to the vertical signal lines 28 are amplified by a column amplifier 30 for each column, and then processed by a CDS circuit 31 to obtain the difference between the optical signal (a signal containing optical information photoelectrically converted by the pixel PX) and the dark signal (a difference signal containing a noise component to be subtracted from the optical signal), and then converted into a digital signal by an A / D converter 32, and the digital signal is held in the A / D converter 32. The digital image signals held in each A / D converter 32 are horizontally scanned by a horizontal readout circuit 33, converted into a predetermined signal format as necessary, and output to the outside (digital signal processing unit 6 in FIG. 1).

[0061] The CDS circuit 31 receives a dark signal sampling signal φDARKC from a timing generation circuit (not shown) under the control of the imaging control unit 5 in Fig. 1, and samples the output signal of the column amplifier 30 as a dark signal when φDARKC is at a high level (H), and also receives a light signal sampling signal φSIGC from the timing generation circuit under the control of the imaging control unit 5 in Fig. 1, and samples the output signal of the column amplifier 30 as a light signal when φSIGC is at H. The CDS circuit 31 then outputs a signal corresponding to the difference between the sampled dark signal and light signal, based on the clock and pulses from the timing generation circuit. A known configuration can be adopted for the configuration of this CDS circuit 31.

[0062] Here, the structure of the pixel block BL will be described with reference to Figures 4 and 5. In reality, a color filter, a microlens, etc. are arranged above the photodiode PD, but these are omitted in Figures 4 and 5. Note that in Figures 4 and 5, the layout of the power supply lines, ground lines, control lines 22 to 27, etc. is omitted.

[0063] In this embodiment, a P-type well (not shown) is provided on an N-type silicon substrate (not shown), and elements in the pixel block BL, such as photodiodes PD, are disposed in the P-type well. In Fig. 5, reference numerals 41 to 49 denote N-type impurity diffusion regions that form part of the aforementioned transistors. Reference numerals 61 to 67 denote gate electrodes of the transistors made of polysilicon. The diffusion regions 42 and 45 are regions to which a power supply voltage VDD is applied via a power supply line (not shown).

[0064] The photodiodes PDA(n) and PDB(n) are buried photodiodes consisting of an N-type charge accumulation layer (not shown) provided in the P-type well and a P-type depletion prevention layer (not shown) disposed on the surface side of the N-type charge accumulation layer. The photodiodes PDA(n) and PDB(n) photoelectrically convert incident light and accumulate the generated charges in the charge accumulation layer.

[0065] The transfer transistor TXA(n) is an nMOS transistor with the charge storage layer of the photodiode PDA(n) as its source, the diffusion region 41 as its drain, and the gate electrode 61 as its gate. The transfer transistor TXB(n) is an nMOS transistor with the charge storage layer of the photodiode PDB(n) as its source, the diffusion region 41 as its drain, and the gate electrode 62 as its gate. The diffusion region 41 is provided between the photodiode PDA(n) and the photodiode PDB(n). The diffusion region 41 serves as both the diffusion region that becomes the drain of the transfer transistor TXA(n) and the diffusion region that becomes the drain of the transfer transistor TXB(n). The gate electrode 61 of the transfer transistor TXA(n) is located on the photodiode PDA(n) side of the diffusion region 41. The gate electrode 62 of the transfer transistor TXB(n) is located on the photodiode PDB(n) side of the diffusion region 41.

[0066] The amplification transistor AMP(n) is an nMOS transistor with the diffusion region 42 as its drain, the diffusion region 43 as its source, and the gate electrode 63 as its gate. The selection transistor SEL(n) is an nMOS transistor with the diffusion region 43 as its drain, the diffusion region 44 as its source, and the gate electrode 64 as its gate. The diffusion region 44 is connected to the vertical signal line 28. The reset transistor RST(n) is an nMOS transistor with the diffusion region 45 as its drain, the diffusion region 46 as its source, and the gate electrode 65 as its gate.

[0067] The linking transistor SWa(n) is an nMOS transistor with the diffusion region 46 as its source, the diffusion region 47 as its drain, and the gate electrode 66 as its gate. The linking transistor SWb(n-1) is an nMOS transistor with the diffusion region 48 as its drain, the diffusion region 49 as its source, and the gate electrode 67 as its gate.

[0068] The gate electrode 63 and diffusion regions 41, 46 of the pixel block BL(n) and the diffusion region 48 of the linking transistor SWb(n-1) are electrically connected to each other and are conductive by a wiring 71(n). In this embodiment, the node P(n) corresponds to the wiring 71(n) and all of the parts electrically connected to and conductive with the wiring 71(n).

[0069] The structure of pixel blocks BL other than the nth row is the same as the structure of pixel block BL(n) in the nth row described above. The structure of connecting transistors SWa other than connecting transistor SWa(n) is the same as the structure of connecting transistor SWa(n) described above. The structure of connecting transistors SWb other than connecting transistor SWb(n) is the same as the structure of connecting transistor SWb(n) described above.

[0070] For the two linking transistors SWa and SWb connected in series in each unique connection path, the diffusion region 47 of the linking transistor SWa and the diffusion region 49 of the linking transistor SWb are connected by a wiring 72. For example, the diffusion region 47 of the linking transistor SWa(n-1) and the diffusion region 49 of the linking transistor SWb(n-1) are electrically connected by a wiring 72(n-1). The wiring 72(n-1) forms a connection between the linking transistors SWa(n-1) and SWb(n-1) when the linking transistors SWa(n-1) and SWb(n-1) are off. The diffusion region 47 of the linking transistor SWa(n) and the diffusion region 49 of the linking transistor SWb(n) are electrically connected by a wiring 72(n). The wiring 72(n) forms a connection between the linking transistors SWa(n) and SWb(n) when the linking transistors SWa(n) and SWb(n) are off.

[0071] Here, as shown in FIG. 4, the amount of misalignment in the column direction between two connection transistors SWa and SWb provided in series in each of the respective unique connection paths is defined as Ls, and the pitch in the column direction of the photodiode PD is defined as Pg. In the present invention, the relationship between the pitch Pg and the misalignment Ls is not limited, but in order to reduce the capacitance value Cfd1 of the capacitance CA described later, it is preferable that pg < Ls < 2 × Pg. In the present embodiment, for example, the connection transistor SWb(n - 1) is arranged in the vicinity of the connection transistor SWa(n), and the misalignment amount Ls is set to be slightly less than 2 × Pg, so that the length of the wiring 71(n) is made as short as possible, and the capacitance value Cfd1 of the capacitance CA(n) described later is made as small as possible.

[0072] In FIGS. 2 to 5, CA(n) is the capacitance between the node P(n) and the reference potential when the connection transistors SWa(n) and SWb(n - 1) are off. Let the capacitance value of the capacitance CA(n) be Cfd1. CB(n) indicates the capacitance between the wiring 72(n) and the reference potential when the connection transistors SWa(n) and SWb(n) are off. Let the capacitance value of the capacitance CB(n) be Cfd2. These points are the same for the rows of other pixel blocks BL.

[0073] The capacitance CA(n) is composed of the capacitance of the drain diffusion region 41 of the transfer transistors TXA(n) and TXB(n), the capacitance of the source diffusion region 46 of the reset transistor RST(n), the capacitance of the source diffusion region 46 of the connection transistor SWa(n), the capacitance of the drain diffusion region 48 of the connection transistor SWb(n - 1), the capacitance of the gate electrode 63 of the amplification transistor AMP(n), and the wiring capacitance of the wiring 71(n), and the sum of their capacitance values becomes the capacitance value Cfd1 of the capacitance CA(n). These points are the same for the rows of other pixel blocks BL.

[0074] Here, the channel capacitance values of the connection transistor SWa and the connection transistor SWb when they are on are both defined as Csw. Usually, the capacitance value Csw is a small value compared to the capacitance values Cfd1 and Cfd2.

[0075] Now, focusing on pixel block BL(n), when both linking transistors SWa(n) and SWb(n-1) are turned off (i.e., the linking transistor that is on among the linking transistors SWa and SWb is not electrically connected to node P(n), and the connection path through which the linking transistors SWa and SWb are provided is not electrically connected to node P(n)), the capacitance (charge-voltage conversion capacitance) between node P(n) and the reference potential becomes capacitance CA(n). Therefore, the capacitance value of the charge-voltage conversion capacitance of node P(n) becomes Cfd1. This state corresponds to the state of period T2 in FIG. 6, which shows the first operating mode described below.

[0076] Furthermore, with respect to pixel block BL(n), when the linking transistor SWa(n) is turned on, unless the linking transistors SWa and SWb that are on except for the linking transistor SWa(n) are electrically connected to node P(n) (specifically, if the linking transistors SWb(n-1) and SWb(n) are off), the capacitance (charge-voltage conversion capacitance) between node P(n) and the reference potential is the sum of the capacitance CA(n) and the channel capacitance of the linking transistor SWa(n) when it is on. Therefore, the capacitance value of the charge-voltage conversion capacitance of node P(n) is Cfd1+Cfd2+Csw≈Cfd1+Cfd2. This state corresponds to the state during period T2 in FIG. 7, which illustrates the second A operating mode, described later.

[0077] Furthermore, for pixel block BL(n), when both connecting transistors SWa(n) and SWb(n) are turned on, if none of the connecting transistors SWa and SWb that are on are electrically connected to node P(n) (specifically, if connecting transistors SWb(n-1) and SWa(n+1) are off), the charge-voltage conversion capacitance of node P(n) is the sum of capacitance CA(n), capacitance CB(n), the channel capacitance of connecting transistors SWa(n) and SWb(n) when they are on, and capacitance CA(n+1). Therefore, the capacitance value of the charge-voltage conversion capacitance of node P(n) is 2×Cfd1+Cfd2+2×Csw≈2×Cfd1+Cfd2. This state corresponds to the state during period T2 in FIG. 8, which illustrates the second-B operating mode described below.

[0078] In this way, if none of the linking transistors SWa and SWb is in the on state and electrically connected to node P(n), the capacitance value of the charge-voltage conversion capacitance of node P(n) will be minimized, and the charge-voltage conversion coefficient due to that charge-voltage conversion capacitance will be large, making it possible to read with the highest S / N ratio.

[0079] On the other hand, if the number of on-state linking transistors electrically connected to node P(n) among the linking transistors SWa and SWb is increased to a desired number greater than or equal to one, the capacitance value of the charge-voltage conversion capacitance of node P(n) can be increased to a desired value, allowing a larger amount of signal charge to be handled, thereby increasing the number of saturation electrons and thereby expanding the dynamic range.

[0080] The above has been a description of the node P(n) of the pixel block BL(n), but the same applies to the nodes P of the other pixel blocks BL.

[0081] 6 is a timing chart illustrating a first operation mode of the solid-state imaging device 4 shown in FIG. 2. In this first operation mode, each pixel block BL is sequentially selected row by row. When none of the coupling transistors SWa and SWb in the selected pixel block BL is in an on-state and electrically connected to the node P of the selected pixel block BL (when the charge-voltage conversion capacity of the node P is at a minimum), the transfer transistors TXA and TXB in the selected pixel block BL are selectively turned on. The example shown in FIG. 6 reads out signals from all pixels PXA and PXB. However, this is not limiting. For example, thinning-out readout, in which pixel rows are thinned out and readout is also possible. This also applies to the examples shown in FIGS. 7 and 8, which will be described later.

[0082] 6 shows a situation in which pixel block BL(n-1) in the n-1th row is selected in period T1, pixel block BL(n) in the nth row is selected in period T2, and pixel block BL(n+1) in the n+1th row is selected in period T3. Since the operation is the same when pixel block BL in any row is selected, only the operation when pixel block BL(n) in the nth row is selected will be described here.

[0083] Before the start of period T2, the exposure of photodiodes PDA(n), PDB(n) has already been completed during a predetermined exposure period. During normal actual shooting (still image shooting), this exposure is performed by a mechanical shutter (not shown) after a so-called global reset, which resets all pixels simultaneously. In electronic viewfinder mode or video shooting, the exposure is performed by a so-called rolling electronic shutter operation. Immediately before the start of period T2, all transistors SEL, RST, TXA, TXB, SWa, and SWb are off.

[0084] In period T2, φSEL(n) on the nth row is set to H, the selection transistor SEL(n) of the pixel block BL(n) on the nth row is turned on, and the pixel block BL(n) on the nth row is selected.

[0085] Furthermore, during period T2, φSWa(n) and φSWb(n-1) are set to L, and the linking transistors SWa(n) and SWb(n-1) are turned off. As a result, during period T2, none of the linking transistors SWa and SWb are in the on state and electrically connected to node P(n) of the selected pixel block BL(n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of node P(n) becomes Cfd1, which is the minimum.

[0086] Immediately after the start of the period T2, for a certain period of time, φRST(n) is set to H, the reset transistor RST(n) in the nth row is temporarily turned on, and the potential of the node P(n) is temporarily reset to the power supply potential VDD.

[0087] After that, from time t1 during the period T2, for a certain period of time, the dark signal sampling signal φDARKC is set to H, and the potential appearing at the node P(n) is amplified by the amplifier transistor AMP(n) in the nth row, and then passes through the select transistor SEL(n) and the vertical signal line 28. The signal is then amplified by the column amplifier 30 and sampled as a dark signal by the CDS circuit 31.

[0088] After that, from time t2 during period T2, φTXA(n) is set to H for a fixed period of time, turning on the transfer transistor TXA(n) in the nth row. As a result, the signal charge accumulated in the photodiode PDA(n) of the pixel block BL(n) in the nth row is transferred to the charge-voltage conversion capacitance of node P(n). The potential of node P(n), excluding noise components, is proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitance of node P(n).

[0089] At a later time point t3 during the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the node P(n) is amplified by the amplifier transistor AMP(n) on the nth row, and then passes through the select transistor SEL(n) and the vertical signal line 28 and is further amplified by the column amplifier 30. The signal is then sampled as an optical signal by the CDS circuit 31.

[0090] After that, after φSIGC goes low, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled over a fixed period from time t1 and the optical signal sampled over a fixed period from time t3. The A / D converters 32 convert the signal corresponding to this difference into a digital signal and hold it. The digital image signals held in each A / D converter 32 are horizontally scanned by the horizontal readout circuit 33 and output as digital image signals to the outside (digital signal processing unit 6 in FIG. 1).

[0091] Then, for a fixed period from time t4 during period T2, φRST(n) is set to H, the reset transistor RST(n) in the nth row is temporarily turned on, and the potential of node P(n) is temporarily reset to the power supply potential VDD.

[0092] After that, from time t5 during the period T2, for a certain period of time, the dark signal sampling signal φDARKC is set to H, and the potential appearing at the node P(n) is amplified by the amplifier transistor AMP(n) in the nth row, and then passes through the select transistor SEL(n) and the vertical signal line 28. The signal is then amplified by the column amplifier 30 and sampled as a dark signal by the CDS circuit 31.

[0093] After that, from time t6 during period T2, φTXB(n) is set to H for a fixed period of time, turning on the transfer transistor TXB(n) in the nth row. As a result, the signal charge accumulated in the photodiode PDB(n) of the pixel block BL(n) in the nth row is transferred to the charge-voltage conversion capacitance of node P(n). The potential of node P(n), excluding noise components, is proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitance of node P(n).

[0094] At a later time point t7 during the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the node P(n) is amplified by the amplifier transistor AMP(n) on the nth row, and then passes through the select transistor SEL(n) and the vertical signal line 28 and is further amplified by the column amplifier 30. The signal is then sampled as an optical signal by the CDS circuit 31.

[0095] After that, after φSIGC goes low, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled over a fixed period from time t5 and the optical signal sampled over a fixed period from time t7. The A / D converters 32 convert the signal corresponding to this difference into a digital signal and hold it. The digital image signals held in each A / D converter 32 are horizontally scanned by the horizontal readout circuit 33 and output as digital image signals to the outside (the digital signal processing unit 6 in FIG. 1).

[0096] In this way, in the first operation mode, none of the coupling transistors SWa, SWb are in an on-state and electrically connected to the node P of the selected pixel block BL, so the capacitance value of the charge-voltage conversion capacitance of the node P of the selected pixel block BL is minimized, and the charge-voltage conversion coefficient due to the charge-voltage conversion capacitance is increased, enabling readout with the highest S / N ratio. For example, when the ISO sensitivity setting is highest, the imaging control unit 5 issues a command to perform the first operation mode.

[0097] 7 is a timing chart showing the 2A operation mode of the solid-state imaging device 4 shown in FIG. 2. The 2A operation mode is one of the second operation modes. This second operation mode is an example of an operation in which each pixel block BL is selected row by row, and while a predetermined number of at least one of the coupling transistors SWa and SWb in the ON state are electrically connected to the node P of the selected pixel block BL, the transfer transistors TXA and TXB of the selected pixel block BL are selectively turned on in sequence, thereby reading out signals from each photodiode PDA and PDB of the selected pixel block BL row by row. The 2A operation mode is an example of an operation in the second operation mode in which the predetermined number is one.

[0098] 7, like Fig. 6, shows a situation in which pixel block BL(n-1) in the n-1th row is selected in period T1, pixel block BL(n) in the nth row is selected in period T2, and pixel block BL(n+1) in the n+1th row is selected in period T3. The differences between the second A operation mode shown in Fig. 7 and the first operation mode shown in Fig. 6 are as follows.

[0099] In the 2A operation mode shown in FIG. 7, during a period T2 in which the n-th row pixel block BL(n) is selected, φSWa(n) is set to H and φSWb(n-1) is set to L, turning on the connecting transistor SWa(n) and turning off the connecting transistor SWb(n-1). As a result, during period T2, one of the connecting transistors SWa and SWb that is in the on state (here, the connecting transistor SWa(n)) is electrically connected to the node P(n) of the selected pixel block BL(n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the node P(n) is Cfd1+Cfd2+Csw≈Cfd1+Cfd2, which is, so to speak, one step larger than that of the first operation mode shown in FIG. 6.

[0100] Here, the period T2 in which the pixel block BL(n) in the nth row is selected has been described, but the same applies to the periods in which other pixel blocks BL are selected.

[0101] In this way, in the 2A operation mode, one of the linking transistors SWa and SWb that is in the on state is electrically connected to the node P of the selected pixel block BL, so that the capacitance value of the charge-voltage conversion capacitance of the node P of the selected pixel block BL increases by one step, so to speak, and the number of saturated electrons in the charge-voltage conversion capacitance of the node P can be increased by one step. This makes it possible to expand the dynamic range by one step. For example, when the ISO sensitivity setting is one step lower than the highest value, the imaging control unit 5 issues a command to perform the 2A operation mode.

[0102] Fig. 8 is a timing chart showing the 2B operation mode of the solid-state imaging device 4 shown in Fig. 2. The 2B operation mode is another operation mode of the second operation modes, and is an example of operation in which the predetermined number is two.

[0103] 6 and 7, Fig. 8 also shows a situation in which pixel block BL(n-1) in the n-1th row is selected in period T1, pixel block BL(n) in the nth row is selected in period T2, and pixel block BL(n+1) in the n+1th row is selected in period T3. The differences between the operation mode 2B shown in Fig. 8 and the first operation mode shown in Fig. 6 and the operation mode 2A shown in Fig. 7 are as follows.

[0104] In the second-B operating mode shown in FIG. 8, during a period T2 in which the nth-row pixel block BL(n) is selected, φSWa(n) and φSWb(n) are set to H, and φSWb(n-1) and φSWa(n+1) are set to L, turning on the connecting transistors SWa(n) and SWb(n) and turning off the connecting transistors SWb(n-1) and SWa(n+1). As a result, during the period T2, two of the connecting transistors SWa and SWb that are in the ON state (here, connecting transistors SWa(n) and SWb(n)) are electrically connected to node P(n) of the selected pixel block BL(n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of node P(n) is 2×Cfd1+Cfd2+2Csw≈2×Cfd1+Cfd2, which is two stages larger than that of the first operating mode shown in FIG. 6.

[0105] Here, the period T2 in which the pixel block BL(n) in the nth row is selected has been described, but the same applies to the periods in which other pixel blocks BL are selected.

[0106] In this way, in the second-B operation mode, two of the linking transistors SWa and SWb that are in the on state are electrically connected to the node P of the selected pixel block BL, so that the capacitance value of the charge-voltage conversion capacitance of the node P of the selected pixel block BL increases by two steps, so to speak, and the number of saturated electrons in the charge-voltage conversion capacitance of the node P can be increased by two steps. This makes it possible to expand the dynamic range by two steps. For example, when the ISO sensitivity setting is two steps lower than the highest value, the imaging control unit 5 issues a command to perform the second-B operation mode.

[0107] In the second operation mode, the predetermined number may be three or more.

[0108] Here, a solid-state imaging device according to a comparative example, which is compared with the solid-state imaging device 4 according to the present embodiment, will be described. FIG. 9 is a circuit diagram showing the vicinity of three pixel blocks BL of the solid-state imaging device according to this comparative example, and corresponds to FIG. 3. FIG. 10 is a schematic plan view showing the vicinity of the three pixel blocks BL shown in FIG. 9, and corresponds to FIGS. 4 and 5. In FIGS. 9 and 10, elements that are the same as or correspond to elements in FIGS. 3, 4, and 5 are given the same reference numerals, and redundant explanations will be omitted. Note that although reference numerals are not given to diffusion regions and gate electrodes in FIG. 10, these reference numerals are the same as those in FIG. 5, so please refer to FIG. 5.

[0109] This comparative example differs from the present embodiment in that each linking transistor SWb is removed, and the location of each removed linking transistor SWb is short-circuited by a wiring 171 including wirings 71 and 72. For example, in the present embodiment, the linking transistor SWb(n-1) is removed, and the gate electrode 63 and diffusion regions 41 and 46 of the pixel block BL(n) and the diffusion region 47 of the linking transistor SWa(n-1) are electrically connected to one another and are conductive by a wiring 171(n) including wirings 71(n) and 72(n-1).

[0110] 9 and 10, CAB(n) is the capacitance between node P(n) and the reference potential when the coupling transistors SWa(n) and SWa(n-1) are off. The capacitance value of the capacitance CAB(n) is Cfd. These points also apply to the other rows of the pixel block BL.

[0111] The capacitance CAB(n) is composed of the capacitance of the drain diffusion regions 41 of the transfer transistors TXA(n) and TXB(n), the source diffusion region 46 of the reset transistor RST(n), the source diffusion region 46 of the linking transistor SWa(n), the capacitance of the drain diffusion region 47 of the linking transistor SWa(n-1), the capacitance of the gate electrode 63 of the amplifier transistor AMP(n), and the wiring capacitance of the wiring 171(n), and the sum of these capacitance values ​​is the capacitance value Cfd of the capacitance CAB(n). This is also true for the other rows of the pixel block BL.

[0112] The wiring capacitance of the wiring 171(n) is approximately equal to the sum of the wiring capacitance (stray capacitance) of the wiring 71(n) and the wiring capacitance of the wiring 171(n). Therefore, the capacitance value Cfd of the capacitance CAB(n) is approximately equal to the sum of the capacitance value Cfd1 of the capacitance CA(n) and the capacitance value Cfd2 of the capacitance CB(n) described above in this embodiment, and Cfd≈Cfd1+Cfd2.

[0113] In this comparative example, focusing on pixel block BL(n), when both linking transistors SWa(n) and SWa(n-1) are turned off, the charge-voltage conversion capacitance of node P(n) becomes capacitance CAB(n). Therefore, the capacitance value of the charge-voltage conversion capacitance of node P(n) becomes Cfd, which is the minimum in the comparative example, and the charge-voltage conversion coefficient due to this charge-voltage conversion capacitance becomes large, enabling readout with the highest S / N ratio in the comparative example.

[0114] In this comparative example, focusing on pixel block BL(n), when a predetermined number of at least one of the linking transistors SWa in the on state are electrically connected to node P(n), the capacitance value of the charge-voltage conversion capacitance of node P(n) increases in accordance with the number of the linking transistors in the on state, thereby increasing the number of saturation electrons, thereby expanding the dynamic range.

[0115] However, in this comparative example, the capacitance value of the charge-voltage conversion capacitance of node P(n) cannot be made smaller than Cfd≈Cfd1+Cfd2. Therefore, according to this comparative example, the charge-voltage conversion coefficient cannot be made very large, and reading with a very high SNR cannot be performed.

[0116] In contrast to this, according to the present embodiment, the linking transistor SWb is added, and therefore, as described above, the minimum capacitance value of the charge-voltage conversion capacitance of the node P(n) can be set to Cfd1 ≈ Cfd - Cfd2, which can be made smaller than that of the comparative example.

[0117] Therefore, according to this embodiment, the dynamic range can be expanded, and the S / N ratio during high-sensitivity readout can be improved compared to the comparative example.

[0118] In this embodiment, the linking transistors SWa and SWb are provided between every two adjacent nodes P in the column direction, but the present invention is not necessarily limited to this. For example, between every qth (q is an integer of 2 or more) node P aligned in the column direction and the adjacent node P below the node P in the figure, the linking transistors SWa and SWb may not be provided, and the gap between them may always be open. In this case, the smaller the number q, the smaller the maximum number of the predetermined number in the second operation mode, and the degree of expansion of the dynamic range decreases, but the signal-to-noise ratio during high-sensitivity readout can be improved compared to the comparative example.

[0119] 6 to 8 are examples of operations in which the signal charge of the photodiode PD of each pixel PX is read out without being mixed with the signal charge of the photodiode PD of other pixels PX. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be read out by mixing it with the signal charge of the photodiode PD of other pixels PX of the same color.

[0120] For example, if the coupling transistors SWa(n-1), SWb(n-1), SWa(n), and SWb(n) are turned on to couple the nodes P(n-1), P(n), and P(n+1) to each other, and TXA(n-1), TXA(n), and TXA(n+1) are turned on simultaneously, the signal charges of the photodiodes PDA(n-1), PDA(n), and PDA(n-1) of the three same-color pixels PXA(n-1), PXA(n), and PXA(n-1) in a Bayer array or the like are averaged at the coupled nodes P(n-1), P(n), and P(n+1), thereby realizing the same-color three-pixel mixed readout function. In this case, by turning off the connecting transistors SWb(n-2) and SWa(n+1) and minimizing the number of on-state connecting transistors electrically connected to the nodes P(n-1), P(n), and P(n+1), the charge-voltage conversion capacitance values ​​at the connected nodes P(n-1), P(n), and P(n+1) are minimized, and same-color three-pixel mixed readout can be performed with the highest S / N ratio. On the other hand, if one or more on-state connecting transistors in addition to the connecting transistors SWa(n-1), SWb(n-1), SWa(n), and SWb(n) are electrically connected to the nodes P(n-1), P(n), and P(n+1), the charge-voltage conversion capacitance values ​​at the connected nodes P(n-1), P(n), and P(n+1) increase in accordance with the number of connecting transistors, and the dynamic range of same-color three-pixel mixed readout can be expanded.

[0121] [Second embodiment] Fig. 11 is a circuit diagram showing the vicinity of three pixel blocks BL of a solid-state imaging device of an electronic camera according to a second embodiment of the present invention, and corresponds to Fig. 3. Fig. 12 is a schematic plan view showing the vicinity of the three pixel blocks BL shown in Fig. 9, and corresponds to Figs. 4 and 5. In Figs. 11 and 12, elements that are the same as or correspond to elements in Figs. 3, 4 and 5 are given the same reference numerals, and redundant explanations will be omitted.

[0122] This embodiment differs from the first embodiment in that a regulating capacitance CB' having a capacitance value Cfd3 is added to each wiring 72. Because the capacitance CB(n) is the capacitance between the wiring 72(n) and the reference potential when the linking transistors SWa(n) and SWb(n) are off, the regulating capacitance CB'(n) is also included in the capacitance CB(n). However, to clearly indicate that the regulating capacitance CB' is a component that adds a capacitance value Cfd3 to the capacitance CB(n) having a capacitance value Cfd2 in the first embodiment, the regulating capacitance CB' is shown separately from the capacitance CB(n) in FIGS. 11 and 12 . In the first embodiment, the capacitance value of the capacitance CB(n) is Cfd2, whereas in this embodiment, the capacitance value of the capacitance CB(n) is Cfd2+Cfd3. These points also apply to the other capacitances CB, wiring 72, and regulating capacitances CB'.

[0123] According to this embodiment, in addition to obtaining the same advantages as those of the first embodiment, the provision of an adjustment capacitor CB' allows the capacitance value of the capacitor CB to be set to any desired capacitance value.

[0124] Specifically, the adjustment capacitance CB' can be configured by combining one or more of the following: (i) making the width of at least a portion of the wiring 72 wider than the wiring width of other wirings in the pixel block BL, thereby making the area of ​​the wiring 72 wider than the area of ​​the wiring 72 in the first embodiment; (ii) connecting a MOS capacitance to the wiring 72; (iii) connecting a diffusion capacitance that does not constitute the linking transistors SWa and SWb; (iv) making the area of ​​the drain diffusion region 47 of the linking transistor SWa wider than the area of ​​the drain diffusion region 47 in the first embodiment; and (v) making the area of ​​the source diffusion region 49 of the linking transistor SWb wider than the area of ​​the source diffusion region 49 in the first embodiment.

[0125] Here, an example of setting the capacitance value Cfd3 of the regulating capacitance CB' will be described. It is desirable that the capacitance value of the charge-voltage conversion capacitance of node P be an integer multiple of the reference capacitance value. However, in the structure of the first embodiment described above, if the regulating capacitance CB' is not added, the capacitance value Cfd2 of capacitance CB will generally be smaller than the capacitance value Cfd1 of capacitance CA. Therefore, for example, to make the capacitance value of the charge-voltage conversion capacitance of node P(n) twice the reference capacitance value, the linking transistors SWa(n) and SWb(n) are turned on, the capacitance value of the charge-voltage conversion capacitance of node P(n) is set to 2×Cfd1+Cfd2+2×Csw, and two pixel blocks BL(n) and BL(n+1) are used.

[0126] In contrast, in this embodiment, if the adjustment capacitor CB' is formed so that its capacitance value Cfd3 is Cfd1-Cfd2, the capacitance value of capacitor CB becomes cfd2+Cfd3=Cfd1. Therefore, to double the capacitance value of the charge-voltage conversion capacitor at node P(n), it is sufficient to turn on the linking transistor SWa(n) and use only one pixel block BL(n). Furthermore, when handling even larger amounts of saturation charge, the number of linked pixel blocks BL can be significantly reduced.

[0127] Such a setting example of the capacitance value Cfd3 of the adjustment capacitance CB' is merely an example, and the present invention is not limited to this.

[0128] In addition, in order to bring the capacitance value of the charge-voltage conversion capacitance of node P close to an integer multiple of the reference capacitance value, it is preferable that the capacitance value of capacitance CB be within a range of ±20% of the capacitance value of capacitance CA, and it is more preferable that the capacitance value of capacitance CB be within a range of ±10% of the capacitance value of capacitance CA.

[0129] [Third embodiment] Figure 13 is a circuit diagram showing a schematic configuration of a solid-state imaging device 84 of an electronic camera according to a third embodiment of the present invention, and corresponds to Figure 2. In Figure 13, elements that are the same as or correspond to elements in Figure 2 are given the same reference numerals, and redundant explanations will be omitted.

[0130] This embodiment differs from the first embodiment in that in the first embodiment, the photodiodes PDB and transfer transistors TXB are removed from each pixel block BL, and each pixel block BL is replaced with a pixel PXA. However, in the present embodiment, the column density of the photodiodes PDA is double that of the first embodiment, and is the same as the column density of the photodiodes PDA and PDB as a whole in the first embodiment. In the present embodiment, n indicates the row of the pixel block BL as well as the row of the pixel PXA.

[0131] In other words, in the first embodiment, each pixel block BL is made up of two pixels PX (PXA, PXB), whereas in this embodiment, each pixel block BL is made up of one pixel PX (PXA). And, in the first embodiment, the two pixels PX (PXA, PXB) belonging to a pixel block BL share a set of a node P, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL, whereas in this embodiment, each pixel PX (only PXA in this embodiment) has a set of a node P, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL.

[0132] Basically, the description of the first embodiment is applicable to this embodiment by replacing pixel blocks BL with pixels PXA, and therefore a detailed description of this embodiment will be omitted here.

[0133] This embodiment also provides the same advantages as the first embodiment.

[0134] In the present invention, the same modifications as those made by modifying the first embodiment to obtain the present embodiment may be applied to the second embodiment.

[0135] [Fourth embodiment] FIG. 14 is a circuit diagram showing the schematic configuration of a solid-state imaging element 94 of an electronic camera according to a fourth embodiment of the present invention, and corresponds to FIG. 2. FIG. 15 is a circuit diagram showing an enlarged view of the vicinity of four pixel blocks BL arranged in sequence in the column direction in FIG. 14, and corresponds to FIG. 3. In FIGS. 14 and 15, elements that are the same as or correspond to elements in FIGS. 2 and 3 are given the same reference numerals, and redundant explanations will be omitted. This embodiment differs from the first embodiment in the points described below.

[0136] In this embodiment, the first coupling transistor SWa, the second coupling transistor SWb, and the wirings 71 and 72 in the first embodiment are removed, and instead, a first transistor SWA as a first switch unit that electrically connects and disconnects between a first node Pa and a corresponding second node Pb, a second transistor SWB as a second switch unit that electrically connects and disconnects between two second nodes Pb, and wirings 97 and 98 are provided.

[0137] The first node Pa(n) of the pixel block BL(n) corresponds to the node P(n) in the first embodiment. The transfer transistor TXA(n) transfers charges from the photodiode PDA(n) to the first node Pa(n), and the transfer transistor TXB(n) transfers charges from the photodiode PDB(n) to the first node Pa(n). A capacitance (charge-voltage conversion capacitance) is formed between the first node Pa(n) and a reference potential, and this capacitance converts the charges transferred to the first node Pa(n) into a voltage. The amplification transistor AMP(n) outputs a signal corresponding to the potential of the first node Pa(n). The reset transistor RST(n) resets the potential of the first node Pa(n). These points are similar for the other rows of the pixel block BL.

[0138] The first transistor SWA(n) constitutes a first switch unit that electrically connects and disconnects the first node Pa(n) and the corresponding second node Pb(n). Although such a first switch unit can be configured by combining switches such as multiple transistors, it is preferable to configure it with a single first transistor SWA(n) as in this embodiment to simplify the structure. These points also apply to the other first transistors SWA.

[0139] Each second transistor SWB constitutes a second switch unit provided for each pair of pixel blocks BL adjacent to each other in the column direction to electrically connect and disconnect the second node Pb corresponding to the first node Pa of one pixel block BL to the second node Pb corresponding to the first node Pa of the other pixel block BL. As a result, in this embodiment, the first nodes Pa of three or more pixel blocks BL are connected in a daisy-chain fashion by a plurality of the second switch units. While the second switch unit described above can be formed by combining a plurality of switches such as transistors, it is preferable to form it with a single second transistor SWB, as in this embodiment, in order to simplify the structure.

[0140] For example, the second transistor SWB(n) is provided to electrically connect and disconnect the second node Pb(n) corresponding to the first node Pa(n) of the pixel block BL(n) on the nth row and the second node Pb(n-1) corresponding to the first node Pa(n-1) of the pixel block BL(n-1) on the n-1th row, as in the other second transistors SWB.

[0141] The gate electrode of the amplifier transistor AMP(n), the source region of the reset transistor RST(n), the drain diffusion regions of the transfer transistors TXA(n) and TXB(n), and the source diffusion region of the first transistor SWA(n) of the pixel block BL(n) are electrically connected to one another by a wiring 97(n), thereby providing conduction. The first node Pa(n) corresponds to the wiring 97(n) and all of the locations electrically connected to and conducting thereto. This also applies to the rows of the other pixel blocks BL.

[0142] The drain diffusion region of the first transistor SWA(n), the drain diffusion region of the second transistor SWB(n), and the source diffusion region of the second transistor SWB(n+1) are electrically connected to each other and are conductive via a wiring 98(n). A second node Pb(n) corresponds to the wiring 98(n) and all of the parts electrically connected to and conductive with it. This also applies to the other first transistors SWA and other second transistors SWB.

[0143] The gates of the first transistors SWA for each row are commonly connected to a control line 95, to which a control signal φSWA is supplied from the vertical scanning circuit 21. The gates of the second transistors SWB for each row are commonly connected to a control line 96, to which a control signal φSWB is supplied from the vertical scanning circuit 21.

[0144] 14 and 15, CC(n) is the capacitance between the first node Pa(n) and the reference potential when the first transistor SWA(n) is off. The capacitance value of the capacitance CC(n) is Cfd1'. CD(n) is the capacitance between the wiring 98(n) and the reference potential when the first transistor SWA(n) and the second transistors SWB(n), SWB(n+1) are off. The capacitance value of the capacitance CD(n) is Cfd2'. The same applies to the other first transistors SWA and the other second transistors SWB.

[0145] The capacitance CC(n) is composed of the capacitance of the drain diffusion regions of the transfer transistors TXA(n) and TXB(n), the capacitance of the source diffusion region of the reset transistor RST(n), the capacitance of the source diffusion region of the first transistor SWA(n), the capacitance of the gate electrode of the amplifier transistor AMP(n), and the wiring capacitance of the wiring 97(n), and the sum of these capacitance values ​​is the capacitance value Cfd1' of the capacitance CC(n). This also applies to the rows of the other pixel blocks BL.

[0146] Note that the capacitance of the source diffusion region of the second transistor SWB(n) is not a component of the capacitance CC(n), so the capacitance value Cfd1' of the capacitance CC(n) is smaller by that amount. In contrast, in the first embodiment, not only the capacitance of the source diffusion region 46 of the linking transistor SWa(n) but also the capacitance of the drain diffusion region 48 of the linking transistor SWb(n-1) are components of the capacitance CB, so the capacitance value Cfd1 of the capacitance CB is larger by that amount. In other words, the capacitance value Cfd1' in this embodiment is smaller than the capacitance value Cfd1 in the first embodiment by one transistor diffusion capacitance.

[0147] Here, the channel capacitance value of the first transistor SWA when it is on and the channel capacitance value of the second transistor SWB when it is on are both denoted as Csw. Typically, the capacitance value Csw is smaller than the capacitance values ​​Cfd1′ and Cfd2′.

[0148] Now, focusing on pixel block BL(n), when the first transistor SWA(n) is turned off (i.e., the on-state transistors of each first transistor SWA and each second transistor SWB are not electrically connected to the first node Pa(n)), the capacitance (charge-voltage conversion capacitance) between the first node Pa(n) and the reference potential becomes capacitance CC(n). Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) becomes Cfd1'. This state corresponds to the state of period T2 in FIG. 16, which shows the first operation mode described later.

[0149] Furthermore, for pixel block BL(n), when the first transistor SWA(n) is turned on, unless any of the first transistors SWA and second transistors SWB that are turned on except for the first transistor SWA(n) are electrically connected to the first node Pa(n) (specifically, if the second transistors SWB(n) and SWB(n+1) are turned off), the capacitance (charge-voltage conversion capacitance) between the first node Pa(n) and the reference potential is the sum of the capacitance CC(n) and the channel capacitance of the first transistor SWA(n) when it is turned on. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is Cfd1'+Cfd2'+Csw≈Cfd1'+Cfd2'. This state corresponds to the state during period T2 in FIG. 17, which illustrates the second A operation mode described later.

[0150] Furthermore, with respect to pixel block BL(n), when the first transistor SWA(n) and the second transistor SWB(n+1) are turned on, unless any of the first transistors SWA and second transistors SWB that are turned on except for the transistors SWA(n) and SWB(n+1) are electrically connected to the first node Pa(n) (specifically, if the transistors SWB(n), SWA(n+1), and SWB(n+2) are turned off), the charge-voltage conversion capacitance of the first node Pa(n) is calculated by adding the capacitances CD(n), CD(n+1), and the channel capacitances of the transistors SWA(n) and SWB(n+1) when they are on to the capacitance CC(n). Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is Cfd1'+2×Cfd2'+2×Csw≈Cfd1'+2×Cfd2'. This state corresponds to the state of period T2 in FIG. 18, which shows the second B operation mode, which will be described later.

[0151] Furthermore, focusing on pixel block BL(n), when the first transistors SWA(n), SWA(n+1) and second transistor SWB(n+1) are turned on, if none of the first transistors SWA and second transistors SWB that are on, other than transistors SWA(n), SWA(n+1), and SWB(n+1), are electrically connected to the first node Pa(n) (specifically, if transistors SWB(n) and SWB(n+2) are off), then the charge-voltage conversion capacitance of the first node Pa(n) will be calculated by adding capacitance CD(n), capacitance CD(n+1), capacitance CC(n+1), and the channel capacitances of transistors SWA(n), SWA(n+1), and SWB(n+1) when they are on to capacitance CC(n). Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is 2×Cfd1′+2×Cfd2′+3×Csw≈2×Cfd1′+2×Cfd2′. This state corresponds to the state of period T2 in FIG. 19, which shows the second C operation mode described later.

[0152] Furthermore, focusing on pixel block BL(n), when the first transistor SWA(n) and the second transistors SWB(n+1), SWB(n+2) are turned on, if none of the first transistors SWA and second transistors SWB that are on are electrically connected to the first node Pa(n) (specifically, if the transistors SWA(n+1), SWA(n+2), SWB(n), SWB(n+3) are off), then the charge-voltage conversion capacitance of the first node Pa(n) will be calculated by adding the capacitances CD(n), CD(n+1), and CD(n+2) and the channel capacitances of the transistors SWA(n), SWB(n+1), and SWB(n+2) when they are on to the capacitance CC(n). Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is Cfd1'+3×Cfd2'+3×Csw≈Cfd1'+3×Cfd2'. This state corresponds to the state of period T2 in Figure 20, which shows the second C operation mode, which will be described later.

[0153] In this way, if none of the first transistors SWA and second transistors SWB are electrically connected to the first node Pa(n) in an on-state, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) becomes the minimum capacitance value Cfd1', and the charge-voltage conversion coefficient due to this charge-voltage conversion capacitance becomes large, enabling readout with the highest S / N ratio. As described above, since the capacitance value Cfd1' is smaller than the minimum capacitance value Cfd1 in the first embodiment by one transistor diffusion capacitance, according to this embodiment, the charge-voltage conversion coefficient becomes even larger than in the first embodiment, enabling readout with an even higher S / N ratio.

[0154] On the other hand, if the number of on-state transistors electrically connected to the first node Pa(n) among the first transistors SWA and second transistors SWB is increased to a desired number equal to or greater than one, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) can be increased to a desired value, allowing a larger amount of signal charge to be handled, thereby increasing the number of saturation electrons and thereby expanding the dynamic range.

[0155] The first node Pa(n) of the pixel block BL(n) has been described above, but the same applies to the first nodes Pa of the other pixel blocks BL.

[0156] FIG. 16 is a timing chart illustrating a first operation mode of the solid-state imaging device 94 shown in FIG. 14. In this first operation mode, each pixel block BL is sequentially selected row by row. In a state where none of the first transistors SWA and second transistors SWB are electrically connected to the first node Pa of the selected pixel block BL in an ON state (a state where the charge-voltage conversion capacity of the first node Pa is minimum), the transfer transistors TXA and TXB of the selected pixel block BL are selectively turned on in sequence, thereby sequentially reading out signals from the photodiodes PDA and PDB of the selected pixel block BL row by row. In the example shown in FIG. 16, signals from all pixels PXA and PXB are read out. However, this is not limiting. For example, thinning-out readout, in which pixel rows are thinned out and readout, may also be performed. This also applies to the examples shown in FIGS. 17 to 20, which will be described later.

[0157] Since the operation of the first operation mode shown in FIG. 16 is clear from the above description, a detailed description thereof will be omitted.

[0158] 17 is a timing chart showing the 2A operation mode of the solid-state imaging device 94 shown in FIG. 14. The 2A operation mode is one of the second operation modes. This second operation mode is an example of an operation in which each pixel block BL is selected row by row, and while a predetermined number of at least one of the first transistors SWA and the second transistors SWB are electrically connected to the first node Pa of the selected pixel block BL, the transfer transistors TXA and TXB of the selected pixel block BL are selectively turned on in sequence, thereby reading out signals from each photodiode PDA and PDB of the selected pixel block BL row by row. The 2A operation mode is an example of an operation in the second operation mode in which the predetermined number is one (one of the first transistors SWA).

[0159] Since the operation of the 2A operation mode shown in FIG. 17 is clear from the above description, a detailed description thereof will be omitted.

[0160] Fig. 18 is a timing chart showing the 2B operation mode of the solid-state imaging device 94 shown in Fig. 14. The 2B operation mode is another of the second operation modes, and is an example of operation in which the predetermined number is two (one for the first transistor SWA and one for the second transistor SWB). Since the operation of the 2B operation mode shown in Fig. 18 is clear from the explanation so far, a detailed explanation thereof will be omitted.

[0161] Fig. 19 is a timing chart showing the 2C operation mode of the solid-state imaging device 94 shown in Fig. 14. The 2C operation mode is yet another operation mode of the second operation mode, and is an operation example in which the predetermined number is three (two of the first transistors SWA and one of the second transistors SWB). Since the operation of the 2C operation mode shown in Fig. 19 is clear from the explanation so far, a detailed explanation thereof will be omitted.

[0162] Fig. 20 is a timing chart showing the 2D operation mode of the solid-state imaging device 94 shown in Fig. 14. The 2D operation mode is yet another operation mode of the second operation mode, and is an operation example in which the predetermined number is three (one for the first transistor SWA and two for the second transistor SWB). Since the operation of the 2D operation mode shown in Fig. 20 is clear from the explanation so far, a detailed explanation thereof will be omitted.

[0163] According to this embodiment, similar to the first embodiment, the dynamic range can be expanded and the S / N ratio during high-sensitivity readout can be improved compared to the comparative example. Furthermore, according to this embodiment, the charge-voltage conversion coefficient is even larger than in the first embodiment, enabling high-sensitivity readout with an even higher S / N ratio.

[0164] In this embodiment, a second transistor SWB is provided between every two adjacent second nodes Pb in the column direction, but the present invention is not necessarily limited to this. For example, a second transistor SWB may not be provided between a second node Pb arranged every r (r is an integer greater than or equal to 2) in the column direction and a second node Pb adjacent to the second node Pb on the lower side in the figure, and the gap between the second node Pb and the adjacent second node Pb may be always open. In this case, the smaller the value of r, the smaller the maximum value of the predetermined number in the second operating mode, and the degree of expansion of the dynamic range decreases, but the signal-to-noise ratio during high-sensitivity readout can be improved compared to the comparative example. Also, for example, a second transistor SWB may not be provided between a second node Pb arranged every s (s is an integer greater than or equal to 1) in the column direction and a second node Pb adjacent to the second node Pb on the lower side in the figure, and the gap between the second node Pb and the adjacent second node Pb may be electrically shorted. Furthermore, for example, second transistors SWB may be provided only between second nodes Pb arranged every u (u is an integer greater than or equal to 1) in the column direction and second nodes Pb adjacent to the second nodes Pb on the lower side in the figure, while second nodes Pb other than those arranged every u in the column direction may be electrically short-circuited between second nodes Pb adjacent to the second nodes Pb on the lower side in the figure.

[0165] As in the second embodiment, in this embodiment, an adjustment capacitor may be provided on the wiring 98. Also in this embodiment, the capacitance value of the capacitor CD may be set to a value within a range of ±20% of the capacitance value of the capacitor CC, or may be set to a value within a range of ±10% of the capacitance value of the capacitor CC. These points also apply to the fifth embodiment described later.

[0166] 16 to 20 are examples of operations in which the signal charge of the photodiode PD of each pixel PX is read out without being mixed with the signal charge of the photodiode PD of other pixels PX. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be read out by mixing it with the signal charge of the photodiode PD of other pixels PX of the same color.

[0167] For example, when the first transistors SWA(n-1), SWA(n), SWA(n+1) and the second transistors SWB(n), SWB(n+1) are turned on to interconnect the first nodes Pa(n-1), Pa(n), Pa(n+1), and TXA(n-1), TXA(n), TXA(n+1) are turned on simultaneously, the signal charges of the photodiodes PDA(n-1), PDA(n), PDA(n-1) of the three same-color pixels PXA(n-1), PXA(n), PXA(n-1) in a Bayer array or the like are averaged at the interconnected first nodes Pa(n-1), Pa(n), Pa(n+1), and the same-color three-pixel mixed readout function can be realized. At this time, by turning off the second transistors SWB(n-2), SWB(n+2) and minimizing the number of first or second transistors in the on state that are electrically connected to the first nodes Pa(n-1), Pa(n), Pa(n+1), the charge-voltage conversion capacitance value at the connected first nodes Pa(n-1), Pa(n), Pa(n+1) is minimized, and same-color three-pixel mixed readout can be performed with the highest signal-to-noise ratio. On the other hand, if one or more on-state transistors among the first transistors SWA(n-1), SWA(n), SWA(n+1) and second transistors SWB(n), SWB(n+1) are electrically connected to the first nodes Pa(n-1), Pa(n), Pa(n+1), in addition to the first transistors SWA(n-1), SWA(n), SWA(n+1), the charge-voltage conversion capacitance value at the connected first nodes Pa(n-1), Pa(n), Pa(n+1) will increase in accordance with the number of on-state transistors, and the dynamic range of same-color three-pixel mixed readout can be expanded.

[0168] [Fifth embodiment] Fig. 21 is a circuit diagram showing a schematic configuration of a solid-state imaging element 104 of an electronic camera according to a fifth embodiment of the present invention, and corresponds to Fig. 14. In Fig. 21, elements that are the same as or correspond to elements in Fig. 14 are given the same reference numerals, and redundant explanations will be omitted.

[0169] This embodiment differs from the fourth embodiment in that in the fourth embodiment, the photodiodes PDB and transfer transistors TXB are removed from each pixel block BL, and each pixel block BL is replaced with a pixel PXA. However, in the present embodiment, the column density of the photodiodes PDA is double that of the fourth embodiment, and is the same as the column density of the photodiodes PDA and PDB as a whole in the fourth embodiment. In the present embodiment, n indicates the row of the pixel block BL as well as the row of the pixel PXA.

[0170] In other words, in the fourth embodiment, each pixel block BL is composed of two pixels PX (PXA, PXB), whereas in the present embodiment, each pixel block BL is composed of one pixel PX (PXA). And, in the fourth embodiment, the two pixels PX (PXA, PXB) belonging to the pixel block BL share a set of the first node Pa, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL, whereas in the present embodiment, each pixel PX (only PXA in the present embodiment) has a set of the first node Pa, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL.

[0171] Basically, the description of the fourth embodiment is applicable to this embodiment by replacing pixel blocks BL with pixels PXA, and therefore a detailed description of this embodiment will be omitted here.

[0172] This embodiment also provides the same advantages as the fourth embodiment.

[0173] Although the embodiments and modifications of the present invention have been described above, the present invention is not limited to these. [Explanation of symbols]

[0174] 4. Solid-state imaging element BL pixel block PX pixels PD photodiode TXA,TXB transfer transistor P-node AMP Amplifying transistor SWa, SWb connected transistor

Claims

1. the pixel block includes a first photoelectric conversion unit that converts light into electric charges, a second photoelectric conversion unit that converts light into electric charges and is disposed adjacent to the first photoelectric conversion unit in the column direction, a first transistor that transfers the electric charges converted in the first photoelectric conversion unit, a second transistor that transfers the electric charges converted in the second photoelectric conversion unit, a first diffusion unit to which the electric charges converted in the first photoelectric conversion unit and the electric charges converted in the second photoelectric conversion unit are transferred, a third transistor that is electrically connected to the first diffusion unit, and a fourth transistor that has a gate portion that is electrically connected to the first diffusion unit; a gate portion of the first transistor and a gate portion of the second transistor are arranged such that a direction in which the charges converted in the first photoelectric conversion portion are transferred from the first photoelectric conversion portion to the first diffusion portion is different from a direction in which the charges converted in the second photoelectric conversion portion are transferred from the second photoelectric conversion portion to the first diffusion portion; the third transistor of a first pixel block among the plurality of pixel blocks and the third transistor of a second pixel block among the plurality of pixel blocks that is arranged adjacent to the first pixel block are connected in series by a connection path that electrically connects the first diffusion portion of the first pixel block and the first diffusion portion of the second pixel block; Image sensor.

2. 2. The imaging device according to claim 1, the gate portion of the first transistor and the gate portion of the second transistor are arranged such that a direction in which the charges converted in the first photoelectric conversion portion are transferred from the first photoelectric conversion portion to the first diffusion portion is opposite to a direction in which the charges converted in the second photoelectric conversion portion are transferred from the second photoelectric conversion portion to the first diffusion portion. Image sensor.

3. 3. The imaging device according to claim 1, a gate portion of the third transistor is smaller than a gate portion of at least one of the gate portion of the first transistor and the gate portion of the second transistor; Image sensor.

4. 4. The imaging device according to claim 3, a gate width of the third transistor is smaller than a gate width of at least one of the first transistor and the second transistor; Image sensor.

5. 5. The imaging device according to claim 3, a gate length of the third transistor is smaller than a gate length of at least one of the first transistor and the second transistor; Image sensor.

6. 6. The imaging device according to claim 1, a gate portion of the third transistor is smaller than a gate portion of the fourth transistor; Image sensor.

7. 7. The imaging device according to claim 6, a gate width of the third transistor is smaller than a gate width of the fourth transistor; Image sensor.

8. 8. The imaging device according to claim 6, a gate length of the third transistor is smaller than a gate length of the fourth transistor; Image sensor.

9. 9. The imaging device according to claim 1, each of the plurality of pixel blocks includes a fifth transistor electrically connected to a supply unit to which a predetermined voltage is supplied; Image sensor.

10. 10. The imaging device according to claim 9, the fifth transistor is formed to share one diffusion region with the third transistor; Image sensor.

11. The imaging device according to claim 10, the fifth transistor has a second diffusion portion electrically connected to the supply portion and a third diffusion portion shared with the third transistor; Image sensor.

12. 3. The imaging device according to claim 2, the first diffusion portion is electrically connected to the supply portion via the third diffusion portion; Image sensor.

13. The imaging device according to any one of claims 9 to 12, a gate portion of the fifth transistor is smaller than a gate portion of the fourth transistor; Image sensor.

14. The imaging device according to claim 13, a gate width of the fifth transistor is smaller than a gate width of the fourth transistor; Image sensor.

15. 15. The imaging device according to claim 13, The gate length of the fifth transistor is smaller than the gate length of the fourth transistor. Image sensor.

16. 16. The imaging device according to claim 9, the gate portion of the third transistor and the gate portion of the fifth transistor are arranged adjacent to each other along the row direction. Image sensor.

17. 17. The imaging device according to claim 9, a distance from a gate portion of the fifth transistor to a gate portion of the third transistor is shorter than a distance from a gate portion of the fourth transistor to a gate portion of the third transistor; Image sensor.

18. 18. The imaging device according to claim 9, a gate portion of the third transistor is disposed at a position farther from a gate portion of the fourth transistor than a gate portion of the fifth transistor; Image sensor.

19. 19. The imaging device according to claim 1, each of the plurality of pixel blocks has a selection unit including a transistor electrically connected to a signal line through which a first signal based on the charge converted by the first photoelectric conversion unit and a second signal based on the charge converted by the second photoelectric conversion unit are output; Image sensor.

20. 20. The imaging device according to claim 19, the transistor included in the selection unit is formed to share one diffusion region with the fourth transistor; Image sensor.

21. 21. The imaging device according to claim 19, a gate portion of the transistor included in the selection unit is smaller than a gate portion of the fourth transistor; Image sensor.

22. 22. The imaging device according to claim 21, a gate width of the transistor included in the selection unit is smaller than a gate width of the fourth transistor; Image sensor.

23. 23. The imaging device according to claim 21 or 22, a gate length of the transistor included in the selection unit is shorter than a gate length of the fourth transistor; Image sensor.

24. 24. The imaging device according to claim 19, a gate portion of the fourth transistor and a gate portion of the transistor included in the selection unit are arranged adjacent to each other; Image sensor.

25. 25. The imaging device according to claim 19, a distance from a gate portion of the fifth transistor to a gate portion of the third transistor is shorter than a distance from a gate portion of the transistor included in the selection unit to a gate portion of the third transistor; Image sensor.

26. 26. The imaging device according to claim 19, a gate portion of the third transistor is disposed at a position farther from the gate portion of the transistor included in the selection unit than a gate portion of the fifth transistor. Image sensor.

27. 27. The imaging device according to claim 1, An imaging element including a capacitance section electrically connected to the connection path and having a first capacitance.

28. 28. The imaging device according to claim 27, the capacitance section is electrically connected to a connection path between the third transistor of the first pixel block and the third transistor of the second pixel block, among the connection paths; Image sensor.

29. 29. The imaging device according to claim 1, the connection path includes three or more transistors including the third transistor of the first pixel block and the third transistor of the second pixel block; Image sensor.

30. 30. The imaging device according to claim 29, the three or more transistors are connected in series by the connection path; Image sensor.

31. 31. The imaging device according to claim 1, the third transistor of the first pixel block and the third transistor of the second pixel block are arranged in the connection path such that a length from the first diffusion portion of the first pixel block to the third transistor of the first pixel block is shorter than a length from the third transistor of the first pixel block to the third transistor of the second pixel block. Image sensor.

32. 32. The imaging device according to claim 31, the gate portion of the third transistor of the first pixel block and the gate portion of the third transistor of the second pixel block are arranged in the connection path such that a length from the first diffusion portion of the first pixel block to the gate portion of the third transistor of the first pixel block is shorter than a length from the gate portion of the third transistor of the first pixel block to the gate portion of the third transistor of the second pixel block. Image sensor.

33. 33. The imaging device according to claim 1, the first diffusion portion and the third transistor are electrically connected to each other via a wiring in the connection path; Image sensor.

34. 34. The imaging device according to claim 1, the third transistor of the first pixel block and the third transistor of the second pixel block are electrically connected to each other via a wiring in the connection path; Image sensor.

35. 35. The imaging device according to claim 1, the plurality of pixel blocks each include a third photoelectric conversion unit that converts light into an electric charge; The first diffusion unit receives the charges converted by the third photoelectric conversion unit. Image sensor.

36. 35. The imaging device according to claim 1, each of the plurality of pixel blocks includes three or more photoelectric conversion units including the first photoelectric conversion unit and the second photoelectric conversion unit; the first diffusion portion transfers the charges converted by the three or more photoelectric conversion portions; Image sensor.

37. 37. The imaging device according to claim 1, the second pixel block is disposed adjacent to the first pixel block in the column direction; Image sensor.

38. 38. The imaging device according to claim 1, a control unit that controls a first timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block, and a second timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block, so that these timings are different from each other; the control unit controls the third transistor of the first pixel block to be turned off at the first timing, and controls the third transistor of the second pixel block to be turned off at the second timing; Image sensor.

39. 38. The imaging device according to claim 1, a control unit that controls a first timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block, and a second timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block, so that these timings are different from each other; the control unit controls the third transistor of the first pixel block to be turned off and the third transistor of the second pixel block to be turned off at the first timing, and controls the third transistor of the first pixel block to be turned off and the third transistor of the second pixel block to be turned off at the second timing; Image sensor.

40. 38. The imaging device according to claim 1, a control unit that controls a first timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block, and a second timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block, so that these timings are different from each other; the control unit controls the third transistor of the first pixel block to be on and the third transistor of the second pixel block to be off at the first timing, and controls the third transistor of the first pixel block to be off and the third transistor of the second pixel block to be on at the second timing; Image sensor.

41. 38. The imaging device according to claim 1, a control unit that controls a first timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block, and a second timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block, so that these timings are different from each other; the control unit controls the third transistor of the first pixel block to be on and the third transistor of the second pixel block to be on at the first timing, and controls the third transistor of the first pixel block to be on and the third transistor of the second pixel block to be on at the second timing; Image sensor.

42. 38. The imaging device according to claim 1, a control unit that controls a first timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block, and a second timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block, so that these timings are different from each other; the control unit executes one of a first mode in which the control unit controls the third transistor of the first pixel block to be turned off at the first timing and the third transistor of the second pixel block to be turned off at the second timing, and a second mode in which the control unit controls the third transistor of the first pixel block to be turned on and the third transistor of the second pixel block to be turned off at the first timing and the third transistor of the first pixel block to be turned off and the third transistor of the second pixel block to be turned on at the second timing. Image sensor.

43. 38. The imaging device according to claim 1, a control unit that controls a first timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block, and a second timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block, so that these timings are different from each other; the control unit executes one of a first mode in which, at the first timing, the third transistor of the first pixel block is controlled to be off and the third transistor of the second pixel block is controlled to be off, and at the second timing, the third transistor of the first pixel block is controlled to be off and the third transistor of the second pixel block is controlled to be off; and a second mode in which, at the first timing, the third transistor of the first pixel block is controlled to be on and the third transistor of the second pixel block is controlled to be off, and at the second timing, the third transistor of the first pixel block is controlled to be off and the third transistor of the second pixel block is controlled to be on. Image sensor.

44. 38. The imaging device according to claim 1, a control unit that controls a first timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block, and a second timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block, so that these timings are different from each other; the control unit executes one of a first mode in which the control unit controls the third transistor of the first pixel block to be turned off at the first timing and the third transistor of the second pixel block to be turned off at the second timing, and a second mode in which the control unit controls the third transistor of the first pixel block to be turned on and the third transistor of the second pixel block to be turned on at the first timing and the third transistor of the first pixel block to be turned on and the third transistor of the second pixel block to be turned on at the second timing. Image sensor.

45. 38. The imaging device according to claim 1, a control unit that controls a first timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block, and a second timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block, so that these timings are different from each other; the control unit executes one of a first mode in which, at the first timing, the third transistor of the first pixel block is controlled to be off and the third transistor of the second pixel block is controlled to be off, and at the second timing, the third transistor of the first pixel block is controlled to be off and the third transistor of the second pixel block is controlled to be off; and a second mode in which, at the first timing, the third transistor of the first pixel block is controlled to be on and the third transistor of the second pixel block is controlled to be on, and at the second timing, the third transistor of the first pixel block is controlled to be on and the third transistor of the second pixel block is controlled to be on. Image sensor.

46. 38. The imaging device according to claim 1, a control unit that controls a first timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block, and a second timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block, so that these timings are different from each other; the control unit executes one of a first mode in which, at the first timing, the third transistor of the first pixel block is controlled to be on and the third transistor of the second pixel block is controlled to be off, and at the second timing, the third transistor of the first pixel block is controlled to be off and the third transistor of the second pixel block is controlled to be on; and a second mode in which, at the first timing, the third transistor of the first pixel block is controlled to be on and the third transistor of the second pixel block is controlled to be on, and at the second timing, the third transistor of the first pixel block is controlled to be on and the third transistor of the second pixel block is controlled to be on. Image sensor.

47. 38. The imaging device according to claim 1, a control unit that controls a first timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block, and a second timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block, so that these timings are different from each other; the control unit executes one of a first mode in which the control unit controls the third transistor of the first pixel block to be off at the first timing and the third transistor of the second pixel block to be off at the second timing; a second mode in which the control unit controls the third transistor of the first pixel block to be on and the third transistor of the second pixel block to be off at the first timing and the third transistor of the first pixel block to be off and the third transistor of the second pixel block to be on at the second timing; and a third mode in which the control unit controls the third transistor of the first pixel block to be on and the third transistor of the second pixel block to be on at the first timing and the third transistor of the first pixel block to be on and the third transistor of the second pixel block to be on at the second timing. Image sensor.

48. 38. The imaging device according to claim 1, a control unit that controls a first timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the first pixel block are transferred to the first diffusion unit of the first pixel block, and a second timing of either one of a timing at which the charges converted by the first photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block and a timing at which the charges converted by the second photoelectric conversion unit of the second pixel block are transferred to the first diffusion unit of the second pixel block, so that these timings are different from each other; the control unit executes one of a first mode in which, at the first timing, the third transistor of the first pixel block is turned off and the third transistor of the second pixel block is turned off, and at the second timing, the third transistor of the first pixel block is turned off and the third transistor of the second pixel block is turned off; a second mode in which, at the first timing, the third transistor of the first pixel block is turned on and the third transistor of the second pixel block is turned off, and at the second timing, the third transistor of the first pixel block is turned off and the third transistor of the second pixel block is turned on; and a third mode in which, at the first timing, the third transistor of the first pixel block is turned on and the third transistor of the second pixel block is turned on, and at the second timing, the third transistor of the first pixel block is turned on and the third transistor of the second pixel block is turned on. Image sensor.

49. An imaging device comprising the imaging element according to any one of claims 1 to 48.

50. 50. The imaging device of claim 49, An imaging device comprising an imaging control unit that controls the imaging element.

51. 51. The imaging device of claim 50, the imaging control unit controls the operation of the third transistor. Imaging device.

52. 52. The imaging device of claim 51, the imaging control unit controls the operation of the third transistor based on a set ISO sensitivity. Imaging device.

53. 53. The imaging device according to any one of claims 49 to 52, an imaging device including a driving unit for driving a photographing lens that emits light to the imaging element;

54. 54. The imaging device of claim 53, An imaging device comprising the above-mentioned photographic lens.

Images