Semiconductor chip manufacturing method and laminated wafer dicing method

Abstract

To provide a semiconductor chip manufacturing method and a laminated wafer dicing method in which peeling of the substrate at the bonding interface is suppressed.SOLUTION: A semiconductor chip manufacturing method for manufacturing multiple semiconductor chips from a single laminated wafer includes a dicing step of cutting the laminated wafer in which a first wafer and a second wafer are bonded together with an adhesive along a cutting line by fracturing in a modified region formed by irradiating laser light from the first wafer side, and at least one of a first substrate and the second wafer in the laminated wafer includes an intermediate layer formed on the side bonded to the adhesive, and the laminated wafer has an area where the first wafer or the intermediate layer has been removed along the cutting line.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing semiconductor chips and a method for dicing stacked wafers. [Background technology]

[0002] In recent years, stealth dicing has been used in semiconductor wafer dicing processes as a wafer dicing method that can cut multilayered wafers with high precision.

[0003] In stealth dicing, a laser beam is focused along a specified dicing line to a specified depth on the wafer, creating a modified region with low crystal strength. Applying external force, such as during an expansion process, from the modified region creates a crack that extends in the thickness direction of the wafer, allowing the wafer to be separated. In this way, stealth dicing is a non-contact, dry process that cuts the wafer, minimizing damage and contamination to the wafer.

[0004] Patent Document 1 discloses a stealth dicing method for an SOI (Silicon On Insulator) substrate as a wafer having multiple layers with different refractive indices. In Patent Document 1, before irradiating with laser light, layers (modified region non-forming layers) located on the laser light incident side among layers on the dicing line where laser light is to be irradiated, other than the layer for forming the modified region (modified region forming layer), are removed. This allows the incident laser light to be incident on the wafer and form the modified region without being reflected or scattered by the modified region non-forming layer. This enables appropriate cutting using the modified region in the appropriate position. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-286727 Summary of the Invention [Problem to be solved by the invention]

[0006] Among multilayer wafers, there are laminated wafers in which multiple substrates are bonded together with an adhesive layer such as an adhesive. For example, chips used in liquid ejection heads of inkjet printers and the like have a laminated structure in which an ink flow path substrate, a substrate with ejection ports, a substrate with an actuator for ejecting liquid, and a substrate with a liquid flow path are bonded together with an adhesive layer. Furthermore, the bonding interface of laminated chips often has a laminated structure in which, in addition to the adhesive layer, a layer for maintaining the adhesion and insulating properties of the wafer is provided on the bonding surface of the substrate to be bonded.

[0007] In stealth dicing of stacked wafers to obtain such stacked chips, even if the technology of Patent Document 1 is used to prevent laser reflection and scattering, the thermal effects of the laser generated during wafer modification may be transmitted to the bonding interface of the stacked wafers. This may cause stress resulting from the difference in linear expansion between the multiple layers at the bonding interface, which may lead to peeling of the wafer or substrate at the bonding interface.

[0008] In view of the above problems, the present disclosure aims to provide a method for manufacturing semiconductor chips and a method for dicing stacked wafers in which peeling of substrates at the bonding interface is suppressed. [Means for solving the problem]

[0009] One embodiment of a semiconductor chip manufacturing method that solves the above problem is a semiconductor chip manufacturing method that manufactures multiple semiconductor chips from a single laminated wafer, and includes a dicing process in which the laminated wafer, in which a first wafer and a second wafer are bonded with an adhesive, is cut along a cutting line by fracturing caused in a modified region formed by irradiating laser light from the first wafer side, and in the laminated wafer, at least one of the first substrate and the second wafer has an intermediate layer formed on the side that is bonded to the adhesive, and the laminated wafer has a region where the first wafer has been removed along the cutting line.

[0010] One embodiment of a semiconductor chip manufacturing method that solves the above problem is a semiconductor chip manufacturing method that manufactures multiple semiconductor chips from a single laminated wafer, and includes a dicing process in which the laminated wafer, in which a first wafer and a second wafer are bonded with an adhesive, is cut along a cutting line by fracturing caused in a modified region formed by irradiating laser light from the first wafer side, and in the laminated wafer, at least one of the first wafer and the second wafer has an intermediate layer formed on the side that is bonded with the adhesive, and the laminated wafer has an area where the intermediate layer has been removed along the cutting line. [Effects of the Invention]

[0011] According to the present disclosure, it is possible to obtain a method for manufacturing semiconductor chips and a method for dicing stacked wafers in which peeling of substrates at the bonding interface is suppressed. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a perspective view showing an example of a liquid ejection device. [Figure 2] FIG. 1 is a perspective view showing an example of a liquid ejection head. [Figure 3] FIG. 2 is a perspective view showing a liquid ejection unit according to the first embodiment. [Figure 4] FIG. 2 is an exploded perspective view showing the liquid ejection unit according to the first embodiment. [Figure 5] FIG. 2 is a cross-sectional view showing the discharge tip according to the first embodiment. [Figure 6] FIG. 2 is a perspective view showing a discharge tip according to the first embodiment. [Figure 7] Stealth dicing flowchart. [Figure 8] FIG. 2 is a perspective view showing a partial structure of laminated wafers in the first embodiment. [Figure 9] FIG. 2 is an enlarged cross-sectional view showing the layer structure of laminated wafers in the first embodiment. [Figure 10] FIG. 10 is an enlarged cross-sectional view showing the layer structure of laminated wafers in the second embodiment. [Figure 11] FIG. 10 is an enlarged cross-sectional view showing the layer structure of laminated wafers in a third embodiment. [Figure 12] FIG. 11 is an enlarged cross-sectional view showing a layer structure of laminated wafers in a modified example of the third embodiment. [Figure 13] FIG. 10 is an enlarged cross-sectional view showing the layer structure of laminated wafers in a fourth embodiment. [Figure 14] FIG. 13 is an enlarged cross-sectional view showing a layer structure of laminated wafers in a modified example of the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. However, the dimensions, materials, and shapes of the components described below, as well as the relative arrangement of the components, should be appropriately changed depending on the configuration of the device to which the technical concept of the present disclosure can be applied and various conditions. Furthermore, in each of the following embodiments, an example in which the present invention is applied to the manufacture of semiconductor chips used in liquid ejection heads will be described, but the present invention is not limited to the manufacture of semiconductor chips for liquid ejection heads.

[0014] <Liquid discharge device> [First embodiment] <Description of the liquid ejection device> 1 is a schematic perspective view illustrating the general configuration of a liquid ejection device 1000 according to one embodiment of a liquid ejection device to which the present disclosure can be applied. The liquid ejection device 1000 of this embodiment is a one-pass type that records an image on the recording medium 2 by moving the recording medium 2 in one go, and has ejection ports arranged to eject liquid across the entire width of the recording medium 2. The liquid ejection device 1000 is provided with a liquid ejection head 100 of the present invention, for example, in a detachable manner.

[0015] The recording medium 2 is transported in the direction of arrow A by a transport unit 3, and recording is performed by a liquid ejection head 100. The liquid ejection head 100 is a liquid ejection head in which liquid ejection units 10 having ejection tips 20 capable of ejecting liquid are arranged on a support member (described below). The liquid ejection heads 100 are positioned within the liquid ejection device 1000 by a reference member. FIG. 1 shows the liquid ejection device 1000 equipped with a total of eight liquid ejection heads 100 (100Ka, 100Kb, 100Ya, 100Yb, 100Ma, 100Mb, 100Ca, 100Cb) capable of ejecting four colors of ink: black, yellow, magenta, and cyan, two for each color.

[0016] In this specification, the direction parallel to and opposite to the transport direction A of the recording medium 2 is referred to as the Y direction, the direction from the liquid ejection head 100 toward the recording medium 2 is referred to as the Z direction, and the direction perpendicular to both the Y direction and the Z direction and perpendicular to the transport direction of the recording medium 2 is referred to as the X direction.

[0017] <Explanation of liquid ejection head> FIG. 2 shows a perspective view of a liquid ejection head 100, and FIG. 3 shows a perspective view of a liquid ejection unit 10. In the liquid ejection head 100 according to this embodiment, a plurality of liquid ejection units 10, each equipped with an ejection chip 20 having an ejection port for ejecting liquid, are fixed to a support member 17. The liquid ejection head 100 has a cover member 16 on the surface of the ejection chip 20 opposite the support member 17. The liquid ejection head 100 further has a housing that houses an electric board and the like. Note that the liquid ejection head to which the present invention can be applied can be embodied in any form, including the example of FIG. 2, and is not limited to other forms.

[0018] FIG. 4 shows an exploded perspective view of the liquid ejection unit 10 as viewed from the side opposite to the surface (front side) on which the ejection ports 231 of the ejection tip 20 are provided. The liquid ejection unit 10 includes the ejection tip 20, an electrical wiring member 12, and a flow path member 13. The ejection tip 20 includes the ejection ports 231 for ejecting liquid, an actuator (see FIG. 5) for ejecting liquid from the ejection ports 231, and terminals 27 (see FIG. 5) electrically connected to the actuator. The electrical wiring member 12 is connected to the terminals 27 and supplies power for driving the actuator from outside the ejection tip 20 to a pressure-generating element of the actuator. The flow path member 13 has a flow path for supplying liquid to the ejection ports 231 and is disposed adjacent to the ejection tip 20 on the back side, which is the surface opposite to the front side of the ejection tip 20. The electrical wiring member 12 is connected to the terminals 27 of the ejection tip 20 on the back side of the ejection tip 20 to form an electrical connection. In this embodiment, the liquid discharge unit 10 further includes a cover member 16 for protecting the surface of the discharge tip 20. In this embodiment, as an example, alumina is used for the flow path member 13, and titanium is used for the cover member.

[0019] FIG. 5 is an enlarged cross-sectional view of a portion of the ejection chip 20 of the liquid ejection head of this embodiment. The ejection chip 20 is composed of four substrates: an ejection port substrate 23, an actuator substrate 22, a flow path substrate 21, and a damper substrate 24. The ejection port substrate 23 has ejection ports 231 formed therein. Multiple ejection ports 231 are arranged along the X direction of the substrate to form an ejection port array, and multiple ejection port arrays are further arranged along the Y direction. The actuator substrate 22 has pressure chambers 221, a vibration plate 227, and pressure-generating elements 228. The flow path substrate 21 has grooves that form voids 219 surrounding the individual flow paths 212, the common flow path 213, and the pressure-generating elements 228. When the pressure-generating elements 228 are piezoelectric elements, the voids 219 are necessary to efficiently transmit the deformation of the piezoelectric elements caused by applied voltage to the vibration plate 227. The damper substrate 24 has a damper film 300, a damper chamber 301, and a common opening 315. Ink is supplied from the common opening 315 formed in the damper substrate 24 to the ejection port substrate 23 via the flow path substrate 21, and the ink is ejected from the ejection ports 231 and applied to the recording medium 2. Note that although the liquid ejection head of this embodiment uses a piezoelectric element as the pressure generating element, the present invention can also be suitably applied to an ejection chip and liquid ejection head that use a heat generating resistor element as the pressure generating element.

[0020] In this embodiment, the ejection port substrate 23, actuator substrate 22, and flow path substrate 21 are made up of silicon substrates, and hereinafter these are collectively referred to as a stacked chip 30. The stacked chip has an electrical wiring member 12 and terminals 27 for electrical connection. Any connection method, such as wire bonding or NCP bonding, can be used for the electrical connection between the terminals 27 and the electrical wiring member 12. The liquid ejection head according to the present disclosure can be embodied in any form, including the example shown in FIG. 2, and is not limited to other forms.

[0021] FIG. 6 is a schematic perspective view showing the laminated chip of this embodiment. FIG. 6 mainly shows the laminated structure of the substrates, and the flow paths of each substrate are not shown. As shown in FIG. 6, in this embodiment, terminals 27 are arranged at the ends along the sides of the discharge chip 20 (laminated chip 30). This allows electrical wiring to be drawn from both ends of the laminated chip 30, thereby increasing the number of terminals 27 that can be mounted on one discharge chip 20. As a result, the arrangement density of discharge ports in the discharge chip can be increased. In this embodiment, terminals 27 are arranged along the two long sides of the discharge chip 20 to connect the electrical wiring member 12 (see also FIGS. 3 and 4). The present invention can also be suitably used in discharge chips in which the terminals 27 are arranged along the short sides of the discharge chip 20 or in which the terminals 27 are arranged along only one side of the discharge chip 20.

[0022] The bonding interface 25b between the flow path substrate 21 and the actuator substrate 22, and the bonding interface 25a between the actuator substrate 22 and the ejection port substrate 23 are bonded together via an adhesive.

[0023] <Method of manufacturing the ejection tip> In this embodiment, the stacked chip 30 (the outlet substrate 23, the actuator substrate 22, and the flow path substrate 21) of the ejection chip 20 can be manufactured by bonding wafers that will become each substrate with adhesive and then cutting them by stealth dicing.

[0024] Here, an outline of a stealth dicing method that can be applied to the present disclosure will be described. Figure 7 is a flowchart of stealth dicing that can be applied to the present disclosure.

[0025] As shown in Figure 7, first, a wafer mounting process is performed to mount the wafer (S10). Specifically, dicing tape is applied to one side of the wafer. The dicing tape is attached to a general dicing frame that is larger than the periphery of the wafer and then attached to the wafer. The dicing tape can be applied to either side of the wafer. It is desirable for the dicing tape to have enough adhesive strength to hold the wafer in place during dicing, and to be easy to peel off the wafer from the dicing tape after cutting. For example, tape whose adhesive hardens when exposed to UV light can be used so that its adhesive strength can be weakened after dicing.

[0026] Next, a stealth dicing process is performed (S11), in which a laser is irradiated onto the wafer. Specifically, the laser is irradiated along a predetermined dicing line set on the wafer. Furthermore, by varying the focal length of the laser to irradiate at multiple depths, multiple modified regions are formed within the wafer in a direction perpendicular to the wafer surface (thickness direction of the wafer). The laser may be incident on either side of the wafer (either the side with dicing tape or the side without dicing tape). When the laser is incident on the side with dicing tape, it is desirable to use a dicing tape with high laser transparency and appropriately adjust the laser output, taking into account laser attenuation by the dicing tape. Furthermore, when the laser is irradiated deep within the wafer thickness direction or when the laser passes through multiple layers, the laser is attenuated due to absorption and reflection within the wafer. Therefore, the amount of laser attenuation within the wafer is large, and laser irradiation from one side may not be able to irradiate the entire wafer thickness direction. In such a case, it is effective to irradiate the wafer with laser from both sides, for example, by irradiating the wafer with laser from the surface opposite to the boundary at a certain portion in the wafer thickness direction.

[0027] Finally, the wafer is cleaved by an expanding process (S12). By expanding the dicing tape with a predetermined force, cracks are generated starting from the modified region, and the generated cracks extend completely across the entire thickness of the wafer, cleaving the wafer. The expanding method is not particularly limited. For example, the wafer can be cleaved by stretching the dicing tape using an expander.

[0028] A method for manufacturing a laminated chip 30 as a semiconductor chip in the first embodiment of the present disclosure will be described below. Fig. 8 is a schematic diagram showing a partial structure of a laminated wafer 200 before dicing. The laminated wafer 200 has a discharge port wafer 230 that will become the discharge port substrate 23, an actuator wafer 220 that will become the actuator substrate 22, and a flow path wafer 210 that will become the flow path substrate 21.

[0029] The flow channel wafer 210 has a structure with a recess, and is bonded to the actuator wafer 220 so as to cover the recess, thereby forming a hollow portion 26. A plurality of terminals 27 are formed in the hollow portion 26. Dicing lines (cutting lines) 28 (28a, 28b, 28c, 28d) are laser irradiation lines for dividing the laminated wafers 200 into laminated chips 30. In the cutting process of the laminated wafers 200, a laser is irradiated along the dicing lines 28 in a predetermined depth direction of the laminated wafers 200. The rectangular parallelepiped region surrounded by the dicing lines 28a, 28b of the flow channel wafer 210 and the hollow portion 26 is the portion that will be removed after dicing. To ensure that this portion is removed after cutting, the dicing lines 28a, 28b are positioned within the hollow portion 26 when viewed from a direction perpendicular to the surface of the substrate.

[0030] In this embodiment, the dicing tape is attached to the flow path wafer 210 side, and the unnecessary portion is discarded while remaining on the dicing tape. The laser is irradiated from both sides of the wafer, the flow path wafer 210 side and the discharge port substrate 23 side, with the hollow portion 26 as the boundary, and the laser corresponding to the dicing lines 28a and 28b is irradiated from the flow path wafer 210 side, and the laser corresponding to the dicing line 28c is irradiated from the discharge port substrate 23 side. One side of the wafer is irradiated with the laser, and then the wafer is flipped over and the other side of the wafer is irradiated with the laser. When cutting by laser irradiation, either side can be cut first. The laser can also be irradiated from both sides of the wafer simultaneously.

[0031] 9 is a schematic cross-sectional view showing an enlarged view of the bonding interface 25a between the actuator wafer 220 and the ejection port wafer 23 before dicing in this embodiment. Cutting along the dicing line 28c at the bonding interface 25a between the actuator wafer 220 (second wafer) and the ejection port wafer 230 (first wafer) will be described in detail below. In the laminated wafers 20, an adhesion improving layer 222 for improving adhesion and an insulating layer 223 are formed as intermediate layers on the bonding interface 25a side of the actuator wafer 220. An adhesion improving layer 232 and an insulating layer 233 are formed as intermediate layers on the bonding interface 25a side of the ejection port substrate 23. The actuator wafer 220 and the ejection port substrate 23 are bonded together via an adhesive layer 41.

[0032] Examples of materials used for the insulating layer include common insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The thickness of the insulating layer is preferably 0.1 μm or more and 2.0 μm or less, and more preferably 0.1 μm or more and 0.5 μm or less. The material used for the adhesion improving layer may be selected appropriately depending on the materials of the substrate and adhesive.

[0033] In this embodiment, the insulating layer 223 and the insulating layer 233 are made of SiO, and the adhesion improving layer 222 and the adhesion improving layer 232 are made of SiC. Also, in this embodiment, an adhesive containing BCB (benzocyclobutene) is used for the adhesive layer 41.

[0034] In this embodiment, a region 40 is formed in the laminated wafer 20 along the dicing line 28c, where the ejection port wafer 23 has been removed over a predetermined width centered on the dicing line 28c. The width of the region 40 in this embodiment (the width in the direction perpendicular to the dicing line 28c) is 100 μm centered on the dicing line 28c. The width of the region 40 may be determined based on the laser irradiation depth and the corresponding laser incident width, and is preferably greater than the sum of the incident width and the tolerance of the laser cutting position. Furthermore, TaO is formed on the surfaces of the ejection port wafer 23 and the region 40 as a protective layer 44 to protect the substrate from ink, which is the ejection liquid.

[0035] The effect of providing the aforementioned region 40 will now be described in detail. Heat is generated at the laser focal point during wafer modification during stealth dicing. Therefore, when a laser is irradiated from the ejection port wafer side along the dicing lines 28c and 28d in a predetermined depth direction of the laminated wafers 20, the heat may be transferred to the bonding interface 25a. This may result in wafer peeling between the actuator wafer 220 and the ejection port wafer 230 at the bonding interface 25a due to stress caused by differences in linear expansion between the multiple layers at the bonding interface 25a. In particular, the ejection port wafer 230 in this embodiment is very thin, at 15 μm, to meet the ejection quality requirements of a liquid ejection head. Therefore, when a laser is irradiated onto the ejection port wafer 23 to modify the ejection port substrate 23, heat is likely to be transferred to the bonding interface 25a, increasing the risk of wafer peeling. In particular, in this embodiment, the combination of a silicon wafer, SiO as an insulating layer, and SiC as an adhesion-improving layer has a linear expansion coefficient of 3.9×10 for silicon. ―6 / K, SiO is 0.5 × 10 ―6 ~0.65×10 ―6 / K, SiC is 4.3 × 10 ―6 ~4.5×10 ―6The difference in linear expansion coefficient between the SiO insulating layer and the other bonded layers is approximately 1 / K, which is large. Therefore, the difference in linear expansion coefficient between the silicon wafer and the insulating layer, and between the insulating layer and the adhesion improving layer, is larger than the difference in linear expansion coefficient between the silicon wafer and the adhesion improving layer. In other words, the difference in linear expansion coefficient between the SiO insulating layer and the other bonded layers is large, and thermal stress is likely to occur in the insulating layer during laser irradiation. Therefore, in this embodiment, the region 40 is provided to prevent laser irradiation of the discharge port wafer 230. At the dicing line 28c where the laser is irradiated, the interfaces where the discharge port wafer 230, the insulating layer 233, and the adhesion improving layer 232, which have different linear expansion coefficients, are bonded are removed on the side of the discharge port wafer 230 where the laser is irradiated. This prevents stress caused by the difference in linear expansion from occurring, which could lead to wafer peeling. Furthermore, even if a laser is irradiated near the bonding interface 25a of the actuator wafer 220 and the laser heat affects the bonding interface 25a, with the configuration of this embodiment, the outlet wafer 230 is not present at the laser irradiation position, so peeling of the wafer at the bonding interface 25a can be suppressed.

[0036] In addition, at dicing line 28d, which intersects with dicing line 28c and is used to cut the bonding interface 25a between the actuator wafer 220 and the discharge port wafer 230 of the laminated wafer 20, an area 40 where the discharge port wafer 230 has been removed is formed along dicing line 28d over a predetermined width centered on dicing line 28d, as in Figure 9.

[0037] As described above, in this embodiment, an area 40 where the discharge port wafer 230 is removed is provided along the dicing lines 28c, 28d over a predetermined width centered on the dicing lines 28c, 28d. This makes it possible to prevent the wafer from peeling off at the bonding interface 25a even if the thermal influence of the wafer modification by laser irradiation affects the bonding interface 25a.

[0038] [Second embodiment] The following description will focus on the differences from the first embodiment described above, and will omit a description of the same parts as in the first embodiment.

[0039] 10 is a schematic enlarged cross-sectional view of the bonding interface 25a between the actuator wafer 220 and the discharge port wafer 230 in this embodiment. As shown in FIG. 10, this embodiment and the first embodiment differ in the layer removal configuration of the bonding interface 25a. In this embodiment, a region 50 is formed along the dicing line 28c over a predetermined width centered on the dicing line 28c, where the discharge port wafer 230, the insulating layer 233, and the adhesion improving layer 232 have been removed.

[0040] In the configuration of this embodiment, similarly to the first embodiment, wafer peeling at the bonding interface 25a can be suppressed because there is no discharge port wafer 230. Furthermore, compared to the first embodiment, although a process for removing the adhesion improving layer 232 and the insulating layer 223 is required, these layers are not present at the laser irradiation position, so it is possible to reduce the attenuation effect during laser irradiation.

[0041] 10, a region 50 is formed along a dicing line 28d that intersects with the dicing line 28c, over a predetermined width centered on the dicing line 28d.

[0042] As described above, in this embodiment, along dicing lines 28c and 28d, a region 50 is provided in which discharge port wafer 230, insulating layer 233, and adhesion improving layer 232 are removed over a predetermined width centered on dicing lines 28c and 28d. This makes it possible to prevent wafer peeling at bonding interface 25a even if the thermal influence of wafer modification by laser irradiation affects bonding interface 25a.

[0043] [Third embodiment] The following description will focus on the differences from the first embodiment described above, and will omit a description of the same parts as in the first embodiment.

[0044] FIG. 11 is a schematic cross-sectional view showing an enlarged view of the bonding interface 25a between the actuator wafer 220 and the discharge port wafer 230 in this embodiment. As shown in FIG. 11, the configuration of layer removal at the bonding interface 25a differs between this embodiment and the first and second embodiments. In this embodiment, a region 60 is formed along the dicing line 28c over a predetermined width centered on the dicing line 28c, where all layers at the bonding interface 25a except for the adhesive layer 41 have been removed. Specifically, a region 60 is formed along the dicing line 28c over a predetermined width centered on the dicing line 28c, where the insulating layer 223 and the adhesion improving layer 222 of the actuator wafer 220 and the insulating layer 233 and the adhesion improving layer 232 of the discharge port wafer 230 have been removed. The region 60 is a space surrounded by the actuator wafer 220 and the discharge port wafer 230, with the adhesive layer 41 remaining. In the configuration of this embodiment, there is no interface between the substrate and a layer with significantly different linear expansion coefficients at the dicing line 28c, where the laser is irradiated. Therefore, even if the thermal effect of the laser is transmitted to the bonding interface 25a, it is possible to prevent the wafer from peeling off due to stress caused by the difference in linear expansion between the layers.

[0045] 11, the adhesive layer 41 is present on the actuator wafer 220 side of the region 60, but the position of the adhesive layer 41 varies depending on which substrate the adhesive layer 41 is applied to. When the adhesive layer 41 is applied to the ejection port wafer 230 side, the adhesive layer 41 is present on the ejection port wafer 230 side of the region 60. In this embodiment, the width of the region 60 was set to 100 μm, centered on the dicing line 28 c.

[0046] In this embodiment, compared to the first and second embodiments, a space exists between the discharge port wafer 230 and the bonding interface 25a. This can cause laser attenuation due to transmission through the discharge port wafer 230 or passing through the interface between the discharge port wafer 230 and the space, which can complicate the setting of the laser output for cutting. On the other hand, this has the advantage that it is only necessary to bond wafers with patterned layers (insulating layer 223, adhesion improving layer 222, adhesion improving layer 232, and insulating layer 233) formed on the bonding surface, and there is no need to remove the discharge port wafer 230 by etching or the like.

[0047] Also at dicing line 28d that intersects with dicing line 28c, similarly to FIG. 11, region 60 is formed along dicing line 28d over a predetermined width centered on dicing line 28d.

[0048] A modified example of this embodiment is shown in Fig. 12. Like Fig. 11, Fig. 12 is a schematic cross-sectional view showing an enlarged view of the bonding interface 25a between the actuator substrate 22 and the ejection port wafer 230. The configuration shown in Fig. 12 differs from the configuration shown in Fig. 11 in that an adhesive layer 41 is filled in the region 60. Even with the configuration shown in Fig. 12, like the configuration shown in Fig. 11, there is no layer other than the adhesive layer 41 at the bonding interface 25a at the position where the laser is irradiated, making it possible to prevent wafer peeling due to stress caused by differences in linear expansion between multiple layers.

[0049] As described above, in this embodiment, a region 60 is provided along dicing lines 28c and 28d over a predetermined width centered on dicing lines 28c and 28d, in which layers other than adhesive layer 41 have been removed from the multiple layers constituting bonding interface 25a. This makes it possible to suppress wafer peeling due to stress caused by differences in linear expansion between the multiple layers, even if bonding interface 25a is affected by the heat effect of wafer modification by laser irradiation.

[0050] [Fourth embodiment] The following description will focus on differences from the first and third embodiments, and will omit a description of similar portions to the first and third embodiments. FIG. 13 is a schematic cross-sectional view of an enlarged bonded interface 25a between the actuator substrate 22 and the ejection port wafer 230 in this embodiment. As shown in FIG. 13, this embodiment and the third embodiment differ in the layer removal configuration at the bonded interface 25a. In this embodiment, along the dicing line 28c, a region 70 is formed over a predetermined width centered on the dicing line 28c, where layers at the bonded interface 25a that may be due to wafer peeling have been removed. Specifically, the layer that may be due to wafer peeling is a layer whose linear expansion coefficient is significantly different from that of the other layers. In this embodiment, the SiO layers, i.e., the insulating layers 223 and 233, are removed. In this manner, by removing at least one of the layers with the largest difference in linear expansion coefficient between the two layers at the bonded interface of the laminated wafers, wafer peeling can be suppressed.

[0051] With the configuration of this embodiment, it is possible to reduce the number of layers to be patterned along the dicing lines 28c.

[0052] 13, a region 80 is formed along the dicing line 28d that intersects with the dicing line 28c, over a predetermined width centered on the dicing line 28d.

[0053] FIG. 14 shows a modified example of this embodiment. Similar to FIG. 13, FIG. 14 is a schematic cross-sectional view showing an enlarged view of the bonding interface 25a between the actuator substrate 22 and the ejection port wafer 230. The configuration shown in FIG. 14 differs from the configuration shown in FIG. 13 in that an adhesive layer 41 is filled in the region 70. In the configuration shown in FIG. 14, similar to the configuration shown in FIG. 13, the bonding interface 25a at the position where the laser is irradiated does not have a bonding interface with a large difference in linear expansion coefficient, such as the interface between the actuator substrate 22 and the layer 223 or the interface between the ejection port wafer 230 and the layer 233. This makes it possible to prevent wafer peeling due to stress caused by the difference in linear expansion.

[0054] As described above, in this embodiment, along dicing lines 28c and 28d, a region 70 is provided over a predetermined width centered on dicing lines 28c and 28d, in which layers other than adhesive layer 41 have been removed from the multiple layers constituting bonding interface 25a. This makes it possible to suppress wafer peeling due to stress caused by the difference in linear expansion between adjacent layers, even if bonding interface 25a is affected by the heat effect of wafer modification by laser irradiation.

[0055] The present disclosure includes the following embodiments.

[0056] (Method 1) A semiconductor chip manufacturing method for manufacturing a plurality of semiconductor chips from one laminated wafer, comprising: a dicing step of cutting the laminated wafer, in which a first wafer and a second wafer are bonded together with an adhesive, along a cutting line by cleaving the laminated wafer in a modified region formed by irradiating the first wafer with laser light; In the laminated wafers, at least one of the first wafer and the second wafer has an intermediate layer formed on a side bonded to the adhesive, The laminated wafers have an area where the first wafer has been removed along the cutting line.

[0057] (Method 2) The method for manufacturing a semiconductor chip according to Method 1, wherein the intermediate layer is formed on the first substrate.

[0058] (Method 3) 3. The method for manufacturing a semiconductor chip according to method 1 or 2, wherein the first wafer has a region where the intermediate layer has been removed in the region where the first wafer has been removed.

[0059] (Method 4) A semiconductor chip manufacturing method for manufacturing a plurality of semiconductor chips from one laminated wafer, comprising: a dicing step of cutting the laminated wafer, in which a first wafer and a second wafer are bonded together with an adhesive, along a cutting line by cleaving the laminated wafer in a modified region formed by irradiating the first wafer with laser light; In the laminated wafers, at least one of the first wafer and the second wafer has an intermediate layer formed on a side bonded to the adhesive, The laminated wafers have regions where the intermediate layer has been removed along the cutting lines.

[0060] (Method 5) The method for manufacturing a semiconductor chip according to method 4, wherein the adhesive is filled in the area where the intermediate layer has been removed.

[0061] (Method 6) The method for manufacturing a semiconductor chip described in Method 4 or 5, wherein, before the dicing step, the area where the intermediate layer is removed is formed, and then the first wafer and the second wafer are bonded together with the adhesive.

[0062] (Method 7) the intermediate layer includes a first intermediate layer included in the first wafer and a second intermediate layer included in the second wafer; 7. The method for manufacturing a semiconductor chip according to any one of methods 1 to 6, wherein both the first intermediate layer and the second intermediate layer are removed in the region.

[0063] (Method 8) A method for manufacturing a semiconductor chip described in any one of methods 1 to 7, wherein the intermediate layer includes a first adhesion improving layer, which is a layer where the first wafer comes into contact with the adhesive, a first insulating layer provided in contact with the first adhesion improving layer, a second adhesion improving layer, which is a layer where the second wafer comes into contact with the adhesive, and a second insulating layer provided in contact with the second adhesion improving layer.

[0064] (Method 9) 9. The method for manufacturing a semiconductor chip according to Method 8, wherein the first wafer is silicon and the first insulating layer is SiO.

[0065] (Method 10) the intermediate layer includes a first adhesion improving layer, which is a layer of the first wafer that comes into contact with the adhesive, a first insulating layer provided in contact with the first adhesion improving layer, a second adhesion improving layer, which is a layer of the second wafer that comes into contact with the adhesive, and a second insulating layer provided in contact with the second adhesion improving layer; 4. The method for manufacturing a semiconductor chip according to claim 1, wherein the first insulating layer is removed in the region where the first wafer is removed.

[0066] (Method 11) the intermediate layer includes a first adhesion improving layer, which is a layer of the first wafer that comes into contact with the adhesive, a first insulating layer provided in contact with the first adhesion improving layer, a second adhesion improving layer, which is a layer of the second wafer that comes into contact with the adhesive, and a second insulating layer provided in contact with the second adhesion improving layer; 11. The method for manufacturing a semiconductor chip according to any one of methods 1 to 10, wherein the first insulating layer and the second insulating layer are removed in the region.

[0067] (Method 12) The method for manufacturing a semiconductor chip according to any one of methods 8 to 10, wherein the difference in the linear expansion coefficient between the first wafer and the first insulating layer is greater than the difference in the linear expansion coefficient between the first wafer and the Tao 1 adhesion improving layer.

[0068] (Method 13) A method for manufacturing a liquid ejection head having a semiconductor chip in which a first substrate and a second substrate are bonded with an adhesive, comprising: A process for manufacturing a plurality of semiconductor chips from one laminated wafer, the process comprising a dicing step of cutting the laminated wafer, in which a first wafer serving as the first substrate and a second wafer serving as the second substrate are bonded together with an adhesive, along a cutting line by cleaving the laminated wafer in a modified region formed by irradiating the first wafer with laser light, In the laminated wafers, at least one of the first wafer and the second wafer has an intermediate layer formed on a side bonded to the adhesive, The method for manufacturing a liquid ejection head, wherein the laminated wafer has an area where the first wafer has been removed along the cutting line.

[0069] (Method 14) A method for manufacturing a liquid ejection head having a semiconductor chip in which a first substrate and a second substrate are bonded with an adhesive, comprising: A process for manufacturing a plurality of semiconductor chips from one laminated wafer, the process comprising a dicing step of cutting the laminated wafer, in which a first wafer serving as the first substrate and a second wafer serving as the second substrate are bonded together with an adhesive, along a cutting line by cleaving the laminated wafer in a modified region formed by irradiating the first wafer with laser light, In the laminated wafers, at least one of the first wafer and the second wafer has an intermediate layer formed on a side bonded to the adhesive, The laminated wafers have regions where the intermediate layer has been removed along the cutting lines.

[0070] (Method 15) 15. The method for manufacturing a liquid ejection head according to Method 13 or 14, wherein the first wafer has ejection ports for ejecting liquid. [Explanation of symbols]

[0071] 20 stacked wafers 210 Flow path wafer 220 Actuator Wafer 230 outlet wafer 223, 233 insulating layer 222, 232 Adhesion improving layer 28 Dicing Line 30 stacked chips 41 Adhesive layer

Claims

1. A semiconductor chip manufacturing method for manufacturing a plurality of semiconductor chips from one laminated wafer, comprising: a dicing step of cutting the laminated wafer, in which a first wafer and a second wafer are bonded together with an adhesive, along a cutting line by cleaving the laminated wafer along a cutting line by irradiating a laser beam from the first wafer side with the laser beam, the dicing step being performed on a modified region formed by the laser beam irradiation; In the laminated wafers, at least one of the first wafer and the second wafer has an intermediate layer formed on a side bonded to the adhesive, The laminated wafers have regions where the first wafer has been removed along the cutting lines.

2. The method for manufacturing a semiconductor chip according to claim 1 , wherein the intermediate layer is formed on the first wafer.

3. 3. The method for manufacturing a semiconductor chip according to claim 2, wherein the region where the first wafer is removed has a region where the intermediate layer is removed.

4. A semiconductor chip manufacturing method for manufacturing a plurality of semiconductor chips from one laminated wafer, comprising: a dicing step of cutting the laminated wafer, in which a first wafer and a second wafer are bonded together with an adhesive, along a cutting line by cleaving the laminated wafer along a cutting line by irradiating a laser beam from the first wafer side with the laser beam, the dicing step being performed on a modified region formed by the laser beam irradiation; In the laminated wafers, at least one of the first wafer and the second wafer has an intermediate layer formed on a side bonded to the adhesive, The laminated wafers have regions where the intermediate layer has been removed along the cutting lines.

5. The method for manufacturing a semiconductor chip according to claim 4 , wherein the adhesive is filled in the area where the intermediate layer has been removed.

6. 5. The method for manufacturing semiconductor chips according to claim 4, wherein, before the dicing step, the region where the intermediate layer is removed is formed, and then the first wafer and the second wafer are bonded together with the adhesive.

7. the intermediate layer includes a first intermediate layer included in the first wafer and a second intermediate layer included in the second wafer; 5. The method for manufacturing a semiconductor chip according to claim 4, wherein both the first intermediate layer and the second intermediate layer are removed in the region.

8. 5. The method for manufacturing a semiconductor chip according to claim 1, wherein the intermediate layer includes a first adhesion improving layer, which is a layer where the first wafer comes into contact with the adhesive, a first insulating layer provided in contact with the first adhesion improving layer, a second adhesion improving layer, which is a layer where the second wafer comes into contact with the adhesive, and a second insulating layer provided in contact with the second adhesion improving layer.

9. 9. The method of claim 8, wherein the first wafer is silicon and the first insulating layer is SiO.

10. the intermediate layer includes a first adhesion improving layer which is a layer of the first wafer that comes into contact with the adhesive, a first insulating layer provided in contact with the first adhesion improving layer, a second adhesion improving layer which is a layer of the second wafer that comes into contact with the adhesive, and a second insulating layer provided in contact with the second adhesion improving layer; 2. The method of claim 1, wherein the first insulating layer is removed in the area where the first wafer is removed.

11. the intermediate layer includes a first adhesion improving layer which is a layer of the first wafer that comes into contact with the adhesive, a first insulating layer provided in contact with the first adhesion improving layer, a second adhesion improving layer which is a layer of the second wafer that comes into contact with the adhesive, and a second insulating layer provided in contact with the second adhesion improving layer; 5. The method for manufacturing a semiconductor chip according to claim 4, wherein the first insulating layer and the second insulating layer are removed in the region.

12. 12. The method for manufacturing a semiconductor chip according to claim 11, wherein a difference in linear expansion coefficient between the first wafer and the first insulating layer is larger than a difference in linear expansion coefficient between the first wafer and the first adhesion improving layer.

13. A method for manufacturing a liquid ejection head having a semiconductor chip in which a first substrate and a second substrate are bonded with an adhesive, comprising: A process for manufacturing a plurality of semiconductor chips from one laminated wafer, the process comprising a dicing step of cutting the laminated wafer, in which a first wafer serving as the first substrate and a second wafer serving as the second substrate are bonded together with an adhesive, along a cutting line by cleaving the laminated wafer in a modified region formed by irradiating the first wafer with laser light, In the laminated wafers, at least one of the first wafer and the second wafer has an intermediate layer formed on a side bonded to the adhesive, The method for manufacturing a liquid ejection head, wherein the laminated wafer has an area where the first wafer has been removed along the cutting line.

14. A method for manufacturing a liquid ejection head having a semiconductor chip in which a first substrate and a second substrate are bonded with an adhesive, comprising: A process for manufacturing a plurality of semiconductor chips from one laminated wafer, the process comprising a dicing step of cutting the laminated wafer, in which a first wafer serving as the first substrate and a second wafer serving as the second substrate are bonded together with an adhesive, along a cutting line by cleaving the laminated wafer in a modified region formed by irradiating the first wafer with laser light, In the laminated wafers, at least one of the first wafer and the second wafer has an intermediate layer formed on a side bonded to the adhesive, The laminated wafers have regions where the intermediate layer has been removed along the cutting lines.

15. 15. The method for manufacturing a liquid ejection head according to claim 13, wherein the first wafer has ejection ports for ejecting liquid.

Images