Data memory access method, apparatus, storage medium, and electronic device

Abstract

To relate to a data memory access method, an apparatus, a storage medium, and an electronic device.SOLUTION: A data memory access method includes the steps of: obtaining data access configuration information; determining a data size, data address constraint information, and a data grouping storage mode based on the data access configuration information; determining a plurality of grouping identifiers based on the data size and the data grouping storage mode; and determining a storage address for corresponding grouped data of each of the plurality of grouping identifiers based on the data address constraint information. A data memory access circuit can support transferring of multidimensional data with various data sizes, having high flexibility and versatility, thereby being helpful in shortening a design cycle of a chip and saving development costs of the chip.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to chip technology, and in particular to a data memory access method, device, storage medium and electronic device. [Background technology]

[0002] Currently, the application of chips is very wide. In some scenarios, it is necessary to transfer multidimensional data inside the chip, and the data size of the multidimensional data that needs to be transferred may be different in different scenarios. How to support the transfer of multidimensional data of various data sizes is a hot topic for those skilled in the art. Summary of the Invention [Problem to be solved by the invention]

[0003] To solve the above problems, the present disclosure provides a data memory access method, device, storage medium, and electronic device for supporting transfer of multidimensional data of various data sizes by a data memory access circuit. [Means for solving the problem]

[0004] A data memory access method according to an aspect of an embodiment of the present disclosure includes: obtaining data memory access setting information; determining a data size, data address limit information and data grouping storage format based on the data memory access setting information; determining a plurality of group identifiers based on the data size and the data grouping storage format; and determining, based on the data address restriction information, storage addresses of group data corresponding to each of the plurality of group identifiers.

[0005] A data memory access device according to another aspect of the embodiment of the present disclosure; an acquisition module for acquiring data memory access setting information; a first determination module for determining a data size, data address limit information and a data grouping storage format according to the data memory access setting information acquired by the acquisition module; a second determining module for determining a plurality of group identifiers based on the data size and the data grouping storage form determined by the first determining module; and a third determination module for determining, based on the data address restriction information determined by the first determination module, storage addresses of group data corresponding to each of the plurality of group identifiers determined by the second determination module.

[0006] A computer-readable storage medium according to yet another aspect of the present disclosure stores a computer program for executing the above-described data memory access method.

[0007] In yet another aspect of the present disclosure, an electronic device includes: a processor; a memory for storing instructions executable by the processor; The processor implements the data memory access method by reading and executing the executable instructions from the memory.

[0008] According to yet another aspect of an embodiment of the present disclosure, a computer program product having processor-executable instructions performs the above-described data memory access method when the executable instructions are executed by a processor. [Effects of the Invention]

[0009] According to the data memory access method, device, storage medium, electronic device, and computer program product of the above embodiments of the present disclosure, the data memory access circuit can determine the data size, data address limit information, and data grouping storage format based on the data memory access setting information, and then perform a group identifier determination operation and a storage address determination operation based on the data size, data address limit information, and data grouping storage format. In this way, the data memory access circuit can determine the storage addresses corresponding to each of the multiple group data, and can read the required multidimensional data from the memory or write the required multidimensional data to the memory based on the determined storage addresses. Therefore, by adopting the embodiments of the present disclosure, the data memory access circuit can efficiently realize the transfer of multidimensional data. Furthermore, for different scenarios, the data memory access setting information obtained by the data memory access circuit can be different to match the data size of the multidimensional data to be transferred. In this way, the data memory access circuit can support the transfer of multidimensional data of various data sizes, which is highly flexible and versatile, and eliminates the need to design separate data memory access circuits for various data sizes, which is advantageous for shortening the chip design cycle and reducing chip development costs. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a circuit diagram of a data memory access circuit according to some exemplary embodiments of the present disclosure. [Figure 2] 1 is a flowchart of a data memory access method according to some example embodiments of the present disclosure. [Figure 3] FIG. 2 is a schematic diagram of multi-dimensional data in some exemplary embodiments of the present disclosure. [Figure 4] 1 is a flowchart of a method for determining a storage address according to some example embodiments of the present disclosure. [Figure 5] 1 is a flowchart of a method for determining a first reference address according to some example embodiments of the present disclosure. [Figure 6] 10 is a flowchart of a method for determining a storage address according to some further example embodiments of the present disclosure. [Figure 7] 1 is a flowchart of a data acquisition and processing method according to some example embodiments of the present disclosure. [Figure 8] 1 is a flowchart of a method for reading grouped data according to some example embodiments of the present disclosure. [Figure 9] 10 is a flowchart of a data acquisition and processing method according to some further example embodiments of the present disclosure. [Figure 10] 1 is a flowchart of a method for writing data according to some example embodiments of the present disclosure. [Figure 11] 10 is a flowchart of a method for writing data according to some further exemplary embodiments of the present disclosure. [Figure 12] FIG. 1 is a schematic diagram of operations performed to implement multi-dimensional data transfer in some embodiments of the present disclosure. [Figure 13] 1 is a structural schematic diagram of a data memory access device according to some example embodiments of the present disclosure; [Figure 14] FIG. 10 is a structural schematic diagram of a third determination module in some exemplary embodiments of the present disclosure. [Figure 15] FIG. 1 is a schematic diagram of a module for data acquisition and processing in some embodiments of the present disclosure. [Figure 16] FIG. 10 is a schematic diagram of a module for data acquisition and processing in accordance with some alternative embodiments of the present disclosure. [Figure 17] FIG. 1 is a schematic diagram of a module for obtaining and writing data in some embodiments of the present disclosure. [Figure 18] 1 is a structural schematic diagram of an electronic device according to some example embodiments of the present disclosure. Modes for carrying out the invention

[0011] In order to interpret the present disclosure, exemplary embodiments of the present disclosure will be described in detail below with reference to the drawings. The described embodiments are not all embodiments but only some embodiments of the present disclosure, and the present disclosure is not limited to the exemplary embodiments.

[0012] The relative arrangement of components and steps, numerical expressions and values ​​described in these examples do not limit the scope of the present disclosure unless specifically stated otherwise.

[0013] [Summary of the Application] At present, the applications of chips are becoming increasingly widespread, for example, in the field of driving technology, the applications of intelligent driving chips are becoming increasingly widespread.

[0014] In some scenarios, it is necessary to transfer multidimensional data within a chip. For example, in some scenarios, it is necessary to read multidimensional data from or write multidimensional data to a memory within a chip. The memory within a chip can be an on-chip memory, including, for example, a static random-access memory (SRAM). It should be noted that the data size of the multidimensional data that needs to be transferred may be different in different scenarios.

[0015] How to support the transfer of multi-dimensional data with various data sizes is a notable issue for those skilled in the art.

[0016] [Example System] In the embodiment of the present disclosure, the data memory access circuit can support the transfer of multidimensional data of various data sizes. The circuit configuration diagram of the data memory access circuit can be seen in FIG. 1, and the data memory access circuit includes a parameter configuration module 10, an address mapping module 20, an instruction generation module 30, and a data processing module 40.

[0017] The parameter setting module 10 can obtain data memory access setting information via a data bus 50. Optionally, the data bus 50 can include an Advanced Peripheral Bus (APB).

[0018] The address mapping module 20 can determine a plurality of storage addresses for multidimensional data that needs to be read from or written to the memory based on the data memory access setting information. Optionally, the memory can include a storage unit and an instruction processing unit. The storage unit is for storing data, and correspondingly, the plurality of storage addresses determined based on the data memory access setting information can be a plurality of storage addresses in the storage unit. The instruction processing unit is for processing instructions, such as read instructions, write instructions, etc.

[0019] The instruction generation module 30 can generate a read instruction based on the storage addresses determined by the address mapping module 20 for the multidimensional data that needs to be read from the memory, and send the read instruction to the memory. In response to the read instruction, the instruction processing unit in the memory can obtain the corresponding data from the storage unit in the memory, and the data can be returned to the data memory access circuit. In this way, the data memory access circuit reads the multidimensional data from the memory.

[0020] The instruction generation module 30 can further generate a write instruction based on the storage addresses determined by the address mapping module 20 for the multidimensional data to be written to the memory, and send the generated write instruction to the memory. The instruction processing unit in the memory can store the corresponding data in the storage unit in the memory in response to the write instruction. In this way, the data memory access circuit writes the multidimensional data to the memory.

[0021] The data processing module 40 takes the data obtained by the read command and processes this data to generate processed data as called for by the write command.

[0022] For different scenarios, the data memory access setting information acquired by the data memory access circuit can be different to suit the multidimensional data size that needs to be transferred, and in this way the data memory access circuit can support the transfer of multidimensional data of various data sizes.

[0023] [Exemplary Method] 2 is a flowchart of a data memory access method according to some example embodiments of the present disclosure. The method shown in FIG. 2 can be applied to a data memory access circuit. The method shown in FIG. 2 can include steps 210, 220, 230, and 240.

[0024] In step 210, data memory access setting information is obtained.

[0025] Alternatively, data memory access setting information can be obtained via data bus 50 of FIG.

[0026] The data memory access setting information may be setting information for supporting the transfer of multidimensional data. The operation process of the data memory access circuit mainly involves two steps: a first step for reading multidimensional data from the memory and a second step for writing multidimensional data to the memory. Accordingly, the data memory access setting information may include two parts: first setting information corresponding to the first step and second setting information corresponding to the second step.

[0027] Optionally, the first setting information includes, but is not limited to, data size, data address limit information, data grouping storage form, etc.

[0028] Alternatively, the data size in the first setting information may be the size of multidimensional data that needs to be read from memory in the first stage. The multidimensional data that needs to be read from memory in the first stage may be tensor data, including, but not limited to, image data, feature map data, etc. For convenience of explanation, this tensor data may hereinafter be referred to as first tensor data. The data size in the first setting information may include sizes corresponding to each of a plurality of data dimensions. The plurality of data dimensions may include, but are not limited to, a batch size dimension, a height dimension, a width dimension, a channel dimension, etc. The batch size dimension may also be referred to as the Batch dimension or the N dimension. The size corresponding to the batch size dimension may be denoted as n_size. The height dimension may also be referred to as the Height dimension or the H dimension. The size corresponding to the height dimension may be expressed as h_size. The width dimension may also be referred to as the Width dimension or the W dimension. The size corresponding to the width dimension may be expressed as w_size. The channel dimension may also be referred to as the Channel dimension or the C dimension. The size corresponding to the channel dimension may be expressed as c_size.

[0029] In one example, the first tensor data may be as shown in FIG. 3, and the data size in the first setting information may be 4n16h16w16c, representing that the size corresponding to the batch size dimension is 4, the size corresponding to the height dimension is 16, the size corresponding to the width dimension is 16, and the size corresponding to the channel dimension is 16.

[0030] In another example, the data size in the first setting information may be 3h19w19c, representing that the size corresponding to the batch size dimension is 1, the size corresponding to the height dimension is 3, the size corresponding to the width dimension is 19, and the size corresponding to the channel dimension is 19.

[0031] Optionally, the data address restriction information in the first setting information may be information for restricting storage addresses of the first tensor data in memory. The data address restriction information may include, but is not limited to, an initial address, an address offset, an address range, and strides corresponding to each of multiple data dimensions. The strides corresponding to different data dimensions may be the same or different.

[0032] In one example, the initial address can be 0, the address offset can be 100, and the address range can be [0, 1023], which indicates that the first tensor data is stored from the address 0+100=100, and the first tensor data is stored in the address range [0, 1023].

[0033] In another example, the strides corresponding to the batch size dimension, height dimension, width dimension, and channel dimension may all be 1.

[0034] In yet another example, the strides corresponding to the batch size dimension and the height dimension may both be 1, and the strides corresponding to the width dimension and the channel dimension may both be 2.

[0035] In addition, since the data size of the first tensor data is often not very small, it is usually impossible to store the entire first tensor data at a single storage address in memory. In view of this, the first tensor data can be divided and stored into multiple groups, each group including a portion of the data in the first tensor data. Therefore, in an embodiment of the present disclosure, the first setting information can include a data grouping storage form for instructing how the first tensor data is to be grouped and stored (grouped storage).

[0036] Optionally, the data grouping storage format in the first setting information can indicate that when the first tensor data is grouped and stored, a single group corresponds to the size of the height dimension, width dimension, and channel dimension, respectively.

[0037] In one example, the data grouping storage format can be 2h8w8c, and when grouping storage of the first tensor data is performed, a single group can represent a size of 2 corresponding to the height dimension, a size of 8 corresponding to the width dimension, and a size of 8 corresponding to the channel dimension.

[0038] In another example, the data grouping storage format can be 4w4h8c, and when grouping storage of the first tensor data is performed, a single group can represent a size corresponding to the height dimension of 4, a size corresponding to the width dimension of 4, and a size corresponding to the channel dimension of 8.

[0039] The configuration of the first setting information has been introduced above. The second setting information may include, but is not limited to, data size, data address restriction information, and data grouping storage format, similar to the first setting information. The data size in the second setting information may be the size of multidimensional data that needs to be written to memory in the second stage. The multidimensional data that needs to be written to memory in the second stage may be tensor data, and for convenience of explanation, this tensor data may hereinafter be referred to as second tensor data. The data address restriction information in the second setting information may be information for restricting the storage address of the second tensor data in memory. The data grouping storage format in the second setting information may indicate that, when grouping and storing the second tensor data, a single group corresponds to the size of the height dimension, the width dimension, and the channel dimension, respectively.

[0040] In step 220, the data size, data address limit information and data grouping storage format are determined based on the data memory access setting information.

[0041] Optionally, for the first stage, the data size, data address limit information and data grouping storage format can be obtained from the first setting information.

[0042] Optionally, for the second stage, the data size, data address limit information and data grouping storage format can be obtained from the second setting information.

[0043] In step 230, a number of group identifiers are determined based on the data size and the data grouping storage format.

[0044] Furthermore, by dividing the first tensor data according to the data grouping storage format acquired from the first setting information, a plurality of grouped data can be obtained, and the plurality of grouped data can correspond one-to-one to a plurality of group identifiers. Conversely, to obtain a plurality of grouped data, a plurality of group identifiers can be determined in advance. In view of this, in step 230, a plurality of packet identifiers can be determined for the first stage based on the data size and data grouping storage format acquired from the first setting information.

[0045] In one example, the first tensor data size is 3h19w19c, and the data grouping storage form is 2h8w8c. According to the data grouping storage form of 2h8w8c, the first tensor data can be divided into a plurality of grouped data, where the first grouped data is a portion of the first tensor data where the subscript of h is 0-1, the subscript of w is 0-7, and the subscript of c is 0-7, and this portion can be expressed as h0-1, w0-7, c0-7. The second grouped data is a portion of the first tensor data where the subscript of h is 0-1, the subscript of w is 0-7, and the subscript of c is 8-15, and this portion can be expressed as h0-1, w0-7, c8-15. The third grouped data is a portion of the first tensor data where the subscript of h is 0-1, the subscript of w is 0-7, and the subscript of c is 16-16. The fourth grouped data is a part of the first tensor data where the subscript of h is 0-1, the subscript of w is 8-15, and the subscript of c is 0-7, and this part can be expressed as h0-1, w8-15, and c0-7. The fifth grouped data is a part of the first tensor data where the subscript of h is 0-1, the subscript of w is 8-15, and the subscript of c is 0-7, and this part can be expressed as h0-1, w8-15, and c0-7. The sixth grouped data is a portion of the first tensor data where the subscript of h is 0 to 1, the subscript of w is 8 to 15, and the subscript of c is 8 to 15, and this portion can be expressed as h0 to 1, w8 to 15, c8 to 15, and the sixth grouped data is a portion of the first tensor data where the subscript of h is 0 to 1, the subscript of w is 8 to 15, and the subscript of c is 16 to 18, and this portion can be expressed as h0 to 1, w8 to 15, c16 to 18, and the same applies below, so explanation will be omitted here. Here, h0 to 1, w0 to 7, and c0 to 7 are group identifiers corresponding to the first grouped data, h0 to 1, w0 to 7, and c8 to 15 are group identifiers corresponding to the second grouped data, ..., h0 to 1, w8 to 15, and c16 to 18 can be group identifiers corresponding to the sixth grouped data.

[0046] Of course, the grouping identifier is not limited to the above-mentioned form. For example, the group identifier can be a group name, a group ID, etc. In one example, h0 to 1, w0 to 7, and c0 to 7 can be converted into group IDs based on a predetermined rule, and the group ID obtained by the conversion can be used as the group identifier corresponding to the first grouping data.

[0047] The above describes a specific method for determining multiple group identifiers for the first stage, and a similar method can be used to determine multiple group identifiers for the second stage, so we will not explain it here.

[0048] In step 240, the storage addresses of the grouped data corresponding to each of the plurality of group identifiers are determined based on the data address restriction information.

[0049] As described above, a plurality of group identifiers can be determined for the first stage. Based on the data address restriction information obtained from the first setting information, storage addresses of grouped data corresponding to each of the plurality of group identifiers can be determined, where the storage address of grouped data corresponding to a group identifier can be a physical address at which the grouped data corresponding to this group identifier is stored in memory. Based on the storage addresses of grouped data corresponding to each of the plurality of group identifiers, the grouped data corresponding to each of the plurality of group identifiers can be read from memory, which corresponds to reading the complete first tensor data from memory.

[0050] As described above, a plurality of group identifiers can be determined for the second stage. Based on the data address restriction information obtained from the second setting information, storage addresses of grouped data corresponding to each of the plurality of group identifiers can be determined, where the storage address of grouped data corresponding to a group identifier can be a physical address at which the grouped data corresponding to this group identifier is stored in memory. In this way, when grouped data corresponding to each of the plurality of group identifiers exists in the data memory access circuit, the grouped data corresponding to each of the plurality of group identifiers can be written to memory based on the storage addresses of the grouped data corresponding to each of the plurality of group identifiers, which corresponds to writing the complete second tensor data to memory.

[0051] In an embodiment of the present disclosure, the data memory access circuit determines the data size, data address limit information, and data grouping storage format based on the data memory access setting information, and then performs a group identifier determination operation and a storage address determination operation based on the data size, data address limit information, and data grouping storage format. In this way, the data memory access circuit can determine the storage addresses corresponding to each of the plurality of grouped data, and can read the required multidimensional data from the memory or write the required multidimensional data to the memory based on the determined storage addresses. Therefore, by adopting an embodiment of the present disclosure, the data memory access circuit can efficiently realize the transfer of multidimensional data. Note that, for different scenarios, the data memory access setting information obtained by the data memory access circuit can be different to match the data size of the multidimensional data to be transferred. In this way, the data memory access circuit can support the transfer of multidimensional data of various data sizes, which is highly flexible and versatile, and eliminates the need to design separate data memory access circuits for various data sizes, which is advantageous for shortening the chip design cycle and reducing chip development costs.

[0052] 4 is a flowchart of a storage address determination method according to some exemplary embodiments of the present disclosure. The method shown in FIG. 4 may include step 410, step 420, and step 430. Optionally, a combination of steps 410 to 430 may be an alternative embodiment of step 240 of the present disclosure. The embodiment shown in FIG. 4 may be applied to either the first stage or the second stage. For ease of understanding, the following description will mainly take as an example a situation in which the embodiment shown in FIG. 4 is applied to the first stage.

[0053] In step 410, for a target group identifier in the plurality of group identifiers, index values ​​corresponding to each of a plurality of data dimensions are determined.

[0054] Alternatively, the target group identifier may be any one of the plurality of group identifiers determined in the first stage.

[0055] Optionally, index values ​​corresponding to each of the batch size dimension, height dimension, width dimension and channel dimension can be determined based on the distribution position in the first tensor data of the grouped data corresponding to the target group identifier.

[0056] In addition, during the operation of the data memory access circuit, each time the data memory access circuit reads one grouped data, it processes the grouped data to obtain processed grouped data for invoking a write command. In this case, determining index values ​​corresponding to each of the multiple data dimensions for the target group identifier can be determining sort values ​​along the batch size dimension, height dimension, width dimension, and channel dimension of the grouped data corresponding to the target group identifier in the entire first tensor data, and each determined sort value can be an index value corresponding to the corresponding data dimension, thus having a total of four index values.

[0057] In one example, as shown in FIG. 3, the first tensor data size is 4n16h16w16c, and the data grouping storage format is 2h8w8c. According to the grouping storage format of 2h8w8c, the first tensor data can be divided into 128 grouped data. As can be seen from FIG. 3, the first tensor data may include four subtensor data. Taking the subtensor data located in the lower left corner of FIG. 3 (which may be the third subtensor data) as an example, it may be divided into 32 grouped data. Among these 32 grouped data, the first grouped data may be represented as h0~1, w0~7, c0~7; the second grouped data may be represented as h0~1, w0~7, c8~15; the third grouped data may be represented as h0~1, w8~15, c0~7; the fourth grouped data may be represented as h0~1, w8~15, c8~15; the fifth grouped data may be represented as h2~3, w0~7, c0~7; and the sixth grouped data may be represented as h2~3, w0~7, c8~15. The same applies below, so further description will be omitted. In an embodiment of the present disclosure, when determining the sort values, based on the determination rule that the initial sort value is 0, the sort value increments, and the incremented value is 1 each time, the first of the 32 grouped data may have a batch size dimension sort value of 2, and the height, width, and channel dimension sort values ​​all being 0. The second of the 32 grouped data may have a batch size dimension sort value of 2, and the height and width dimension sort values ​​all being 0, and the channel dimension sort value is 1. The third of the 32 grouped data may have a batch size dimension sort value of 2, and the width dimension sort value is 1, and the height and channel dimension sort values ​​are 0.

[0058] According to the method introduced above, one sorting value can be determined for each of the batch size dimension, height dimension, width dimension, and channel dimension, and thus a total of four sorting values ​​can be obtained, which is equivalent to obtaining four index values. Therefore, the above method can be considered as a four-layer index modeling form.

[0059] In some embodiments, during the operation of the data memory access circuit, the data memory access circuit reads multiple grouped data and processes the multiple grouped data collectively, rather than processing each grouped data piece each time it is read. In this case, the above-described four-layer index modeling format is not applied, and a seven-layer index modeling format can be adopted. Correspondingly, determining index values ​​corresponding to each of the multiple data dimensions for a target group identifier can be determining sort values ​​along the batch size dimension, height dimension, width dimension, and channel dimension of the target data block to which the grouped data corresponding to the target group identifier in the entire first tensor data belongs (each grouped data piece in the target data block is grouped data that needs to be processed collectively), and sort values ​​along the height dimension, width dimension, and channel dimension of the grouped data corresponding to the target group identifier in the target data block, and each determined sort value can be used as an index value corresponding to the corresponding data dimension. In this way, the number of index values ​​corresponding to the batch size dimension can be one, and the number of index values ​​corresponding to the height dimension, width dimension, and channel dimension can each be two, so there can be a total of seven index values.

[0060] 3, assuming the size of the target data block is 2h8w16c, the target data block may include grouped data represented as h0~1, w0~7, and c0~7 among the subtensor data located in the lower left corner of Fig. 3, and grouped data represented as h0~1, w0~7, and c8~15 among the subtensor data located in the lower left corner of Fig. 3. For the grouped data represented as h0~1, w0~7, and c0~7 among the subtensor data located in the lower left corner of Fig. 3, the target data block in which it is located has index values ​​of 2, 0, 0, and 0 along the batch size dimension, height dimension, width dimension, and channel dimension, respectively, in the first tensor data, and this grouped data has index values ​​of 0, 0, and 0 along the height dimension, width dimension, and channel dimension, respectively, in the target data block. Among the subtensor data located in the lower left corner of Figure 3, for the grouped data represented as h0~1, w0~7, and c8~15, the target data block in which it is located has index values ​​of 2, 0, 0, 0 along the batch size dimension, height dimension, width dimension, and channel dimension, respectively, and this grouped data has index values ​​of 0, 0, 1 along the height dimension, width dimension, and channel dimension, respectively, in the target data block.

[0061] In addition, the index values ​​along the batch size dimension, height dimension, width dimension, and channel dimension in the first tensor data of the target data block can be outer layer index values, and the index values ​​along the height dimension, width dimension, and channel dimension in the target data block of the grouping data can be inner layer index values. In the seven-layer index modeling form, the combination of the outer layer index values ​​and the inner layer index values ​​can be a complete index value determined for the target group identifier.

[0062] In step 420, a first reference address is determined based on the data address restriction information and index values ​​corresponding to each of the plurality of data dimensions.

[0063] In some alternative embodiments of the present disclosure, step 420 may include step 4201 and step 4203, as shown in FIG.

[0064] In step 4201, strides corresponding to each of a plurality of data dimensions are determined based on the data address restriction information.

[0065] Optionally, the data address restriction information may include strides corresponding to each of the plurality of data dimensions, so that the strides corresponding to each of the plurality of data dimensions can be obtained from the data address restriction information.

[0066] In step 4203, a first reference address is determined based on the index values ​​corresponding to each of the plurality of data dimensions and the strides corresponding to each of the plurality of data dimensions.

[0067] Optionally, step 4203 includes: A step of determining a first sort value along each of a plurality of data dimensions of a target data block to which grouping data corresponding to a target group identifier in tensor data having a data size (specifically, the above-mentioned first tensor data) belongs based on an index value corresponding to each of a plurality of data dimensions, wherein the target data block is a data block in which each grouping data included in any of the data dimensions shares the same first sort value; determining second sorting values ​​along the height dimension, the width dimension, and the channel dimension of each of the plurality of data dimensions of the grouped data corresponding to the target group identifier in the target data block according to the index values ​​corresponding to each of the plurality of data dimensions; determining a sorted sum value for each of the height dimension, the width dimension, and the channel dimension based on the corresponding first sorted value and the corresponding second sorted value; a step of fusing the sorted sum values ​​corresponding to the height dimension, the width dimension, and the channel dimension, and the first sorted values ​​corresponding to the batch size dimension in the plurality of data dimensions, based on strides corresponding to the plurality of data dimensions, to obtain a fused value; determining a first reference address based on the fused value.

[0068] Optionally, the index value corresponding to any data dimension may include a sort value along the data dimension of the target data block to which the grouped data corresponding to the target group identifier in the first tensor data belongs, and this sort value may be the first sort value corresponding to this data dimension.

[0069] Optionally, the index value corresponding to any one of the three data dimensions, the height dimension, the width dimension, and the channel dimension, may include a sort value along the data dimension of the grouping data corresponding to the target grouping identifier in the target data block, and this sort value may be the second sort value corresponding to this data dimension.

[0070] Assuming that the first sorted values ​​corresponding to the batch size dimension, height dimension, width dimension, and channel dimension are denoted as r, a1, b1, and c1, respectively, and the second sorted values ​​corresponding to the height dimension, width dimension, and channel dimension are denoted as a2, b2, and c2, respectively, a sorted total value can be determined for each of the height dimension, width dimension, and channel dimension based on the corresponding first sorted value and the corresponding second sorted value. In this way, the sorted total value corresponding to the height dimension can be denoted as a1+a2, the sorted total value corresponding to the width dimension can be denoted as b1+b2, and the sorted total value corresponding to the channel dimension can be denoted as c1+c2. Assuming that the strides corresponding to the batch size dimension, height dimension, width dimension, and channel dimension are denoted as s1, s2, s3, and s4, respectively, and the fusion value is denoted as K, K can be calculated using the following formula: K=r*s1+(a1+a2)*s2+(b1+b2)*s3+(c1+c2)*s4

[0071] Optionally, the fused value may be determined as the first reference address.

[0072] In this way, the index values ​​corresponding to each of the multiple data dimensions and the strides corresponding to each of the multiple data dimensions can be combined to efficiently and reliably determine the first reference address through geometric calculations.

[0073] The above-mentioned configurations are optional embodiments of step 4203 when a seven-layer modeling configuration is adopted. If a four-layer modeling configuration is adopted, step 4203 can be implemented as follows: According to the index values ​​corresponding to each of the plurality of data dimensions, determining a third sort value along each of the plurality of data dimensions of the group corresponding to the target group identifier in the tensor data having a data size (specifically, it may be the first tensor data mentioned above); fusing the third sorted values ​​corresponding to each of the plurality of data dimensions based on strides corresponding to each of the plurality of data dimensions to obtain a fused value; determining a first reference address based on the fused value.

[0074] Assuming that the strides corresponding to the batch size dimension, height dimension, width dimension, and channel dimension are s1, s2, s3, and s4, respectively, the third sorting values ​​corresponding to the multiple data dimensions are denoted as r, a3, b3, and c3, respectively, and the fusion value is denoted as K, K can be calculated using the following formula. K=r*s1+a3*s2+b3*s3+c3*s4

[0075] In the embodiment shown in FIG. 5 , the data address restriction information can provide a very effective reference for determining the strides corresponding to each of the multiple data dimensions, and by combining the index values ​​corresponding to each of the multiple data dimensions and the strides corresponding to each of the multiple data dimensions, the first reference address can be determined efficiently and reliably, thereby providing a very effective reference for determining the storage address.

[0076] In step 430, a storage address of the grouped data corresponding to the target group identifier is determined based on the data address restriction information and the first reference address.

[0077] In some alternative embodiments of the present disclosure, step 430 may include step 4301, step 4303, step 4305, and step 4307, as shown in FIG.

[0078] In step 4301, the initial address, address offset amount and address range are determined based on the data address restriction information.

[0079] Optionally, the data address restriction information may include an initial address, an address offset, and an address range, so that the initial address, the address offset, and the address range can be obtained from the data address restriction information.

[0080] In step 4303, the initial address, the address offset amount and the first reference address are combined to obtain a second reference address.

[0081] Alternatively, the initial address, the address offset, and the first reference address can be added together, and the resulting addition result can be used as the second reference address.

[0082] In step 4305, the distribution information for the address range of the second reference address is determined.

[0083] Optionally, the second reference address can be matched with the address range to determine distribution information, which can indicate whether the second reference address is within the address range.

[0084] In step 4307, the storage address of the grouped data corresponding to the target group identifier is determined based on the distribution information.

[0085] Optionally, step 4307 includes: The method may include determining, in response to the distribution information indicating that the second reference address is within the address range, the second reference address as a storage address of the grouping data corresponding to the target group identifier.

[0086] Alternatively, step 4307 is determining a target value for representing the size of the address range in response to the distribution information indicating that the second reference address is outside the address range; determining a numerical relationship between the target numerical value and a preset numerical value; determining a remainder obtained by dividing the second reference address and the target numerical value in response to the numerical relationship indicating that the target numerical value is an exponential power of a predetermined numerical value, and determining a storage address of the grouped data corresponding to the target group identifier based on the remainder; The method may include determining a difference between the second reference address and the target numerical value in response to the numerical relationship indicating that the target numerical value is not an exponential power of the predetermined numerical value, and determining a storage address of the grouping data corresponding to the target group identifier based on the difference.

[0087] Alternatively, an address range can be expressed as [x1, x2]. The target value for expressing the size of the address range can be x2-x1+1. In one example, if x1 is 0 and x2 is 1023, the target value can be 1023-0+1=1024.

[0088] Alternatively, the preset value may be 2. The numerical relationship between the target value and the preset value may represent whether the target value is an exponential power of the preset value.

[0089] When the numerical relationship indicates that the target numerical value is a power of a predetermined numerical value, the second reference address and the target numerical value can be divided to obtain a remainder, and the storage address of the grouped data corresponding to the target group identifier can be determined based on the remainder. For example, the result of adding the initial address and the address offset is called a third reference address, and if the remainder is between the initial address and the third reference address, the remainder can be determined as the storage address of the grouped data corresponding to the target group identifier. If the remainder exceeds the third reference address, it is determined that an error has occurred in the process of determining the storage address, and an error report can be output.

[0090] If the numerical relationship indicates that the target numerical value is not a power of the preset numerical value, the second reference address and the target numerical value can be subtracted to obtain a difference, and the storage address of the grouped data corresponding to the target group identifier can be determined based on the difference. For example, if there is a difference between the initial address and the third reference address, the difference can be determined as the storage address of the grouped data corresponding to the target group identifier information. If the difference exceeds the third reference address, it is determined that an error has occurred in the process of determining the storage address, and an error report can be output.

[0091] In one example, if the initial address is 0, the address offset is 100, and the address range is [0, 1023], the target numeric value is 1024. The second reference address is represented as k. If k is within [0, 1023], k can be determined as the storage address of the grouped data corresponding to the target group identifier. If k is outside [0, 1023], for example, if k is 10000, 1024 is an exponential power of 2, so 10000 can be divided by 1024 to obtain 784 as the remainder. If the address 784 is not occupied by other data, 784 can be determined as the storage address of the grouped data corresponding to the target group identifier.

[0092] In another example, if the initial address is 0, the address offset is 100, and the address range is [0, 1024], the target numeric value is 1025. The second reference address is represented as k. If k is within [0, 1025], k can be determined as the storage address of the grouped data corresponding to the target group identifier. If k is outside [0, 1025], for example, 10000, 1025 is not an exponential power of 2, so 10000 can be subtracted by 1025 to obtain the difference of 8975. Since 8975 exceeds the address range of [0, 1024], an error report can be output.

[0093] As can be seen from the above, when the second reference address is outside the address range, a method of calculating the remainder or a method of calculating the difference can be selected based on the numerical relationship between the target numerical value and the preset numerical value, and then a storage address can be specified for the grouping data corresponding to the target group identifier. In this way, the storage address can be determined by the iterative address specification means, thereby making use of the address range indicated by the data memory access setting information as much as possible to store the first tensor data.

[0094] Of course, step 430 is not limited to the embodiment shown in Fig. 6. For example, as described above, when determining the first reference address based on the fusion value, the fusion value, the initial address, and the address offset amount can be combined to obtain the combined result as the first reference address. Correspondingly, in step 430, an address range can be determined based on data address restriction information, and a storage address of the grouped data corresponding to the target group identifier can be determined based on distribution information for the address range of the first reference address. Also, for example, without using a repeat address designation means, an error report can be output if the second reference address is out of the address range.

[0095] In the embodiment shown in FIG. 4, index values ​​corresponding to each of a plurality of data dimensions are determined for a target group identifier, and a first reference address is determined based on the data address restriction information and the index values ​​corresponding to each of the plurality of data dimensions. Thus, the data address restriction information and the first reference address provide a very effective reference for determining the storage address of the grouped data corresponding to the target group identifier, and can ensure the accuracy and rationality of the finally determined storage address.

[0096] 7 is a flowchart of a data acquisition and processing method according to some exemplary embodiments of the present disclosure. The method shown in FIG. 7 may include steps 710, 720, and 730. Optionally, the method shown in FIG. 7 may be performed after step 240 of the present disclosure. The method shown in FIG. 7 may be applied to the first stage.

[0097] In step 710, a target number of memories and a first distributed storage form for the target number of memories for a single grouped data are determined based on the data memory access setting information.

[0098] Optionally, the data memory access setting information may include a target number of memories and a first distributed storage format in the memory for the target number of single grouped data, so that the target number and the first distributed storage format can be obtained from the data memory access setting information.

[0099] Optionally, the target number can be one or more, for example, four, six, eight, etc.

[0100] Alternatively, the first distributed storage form may be a specific form in which a single grouped data is distributed and stored in a target number of memories. For example, the first distributed storage form may instruct distributed storage along the width direction or distributed storage along the channel direction.

[0101] In one example, if the number of memories is eight and the first distributed storage form indicates distributed storage along the width direction, for the grouped data whose group identifiers are h0-1, w0-7, and c0-7, the data stored in the first memory can be expressed as h0-1, w0, c0-7, the data stored in the second memory can be expressed as h0-1, w1, c0-7, the data stored in the third memory can be expressed as h0-1, w2, c0-7, ..., the data stored in the eighth memory can be expressed as h0-1, w7, c0-7.

[0102] In another example, if the number of memories is eight and the first distributed storage format indicates distributed storage along the channel direction, for the grouped data whose group identifiers are h0~1, w0~7, c0~7, the data stored in the first memory can be expressed as h0~1, w0~7, c0, the data stored in the second memory can be expressed as h0~1, w0~7, c1, the data stored in the third memory can be expressed as h0~1, w0~7, c2, ..., the data stored in the eighth memory can be expressed as h0~1, w0~7, c7.

[0103] In step 720, the grouped data corresponding to each of the plurality of group identifiers is read from a target number of memories based on the first distributed storage format and the storage addresses of the grouped data corresponding to each of the plurality of group identifiers.

[0104] In some alternative embodiments of the present disclosure, step 720 may include step 7201, step 7203, step 7205, and step 7207, as shown in FIG.

[0105] In step 7201, for a target group identifier among the plurality of group identifiers, a first target memory that needs to be involved in data reading is determined from the target number of memories based on the first distributed storage format.

[0106] In one example, the above-mentioned h0-1, w0-7, and c16-18 are target group identifiers, the number of memories is eight, and the first distributed storage mode indicates distributed storage along the channel direction. For a target group identifier, data stored in the first memory can be represented as h0-1, w0-7, and c16, data stored in the second memory can be represented as h0-1, w0-7, and c17, and data stored in the third memory can be represented as h0-1, w0-7, and c18. Obviously, the first to third memories can be used to store all the grouped data corresponding to the target group identifier, and the remaining memories do not need to be used. In this case, the first target memory that needs to be involved in data reading can include only the first, second, and third memories.

[0107] In another example, h0-1, w16-18, and c0-7 are target group identifiers, the number of memories is eight, and the first distributed storage mode indicates distributed storage along the width direction. For a target group identifier, data stored in the first memory can be represented as h0-1, w16, and c0-7, data stored in the second memory can be represented as h0-1, w17, and c0-7, and data stored in the third memory can be represented as h0-1, w18, and c0-7. Obviously, the first to third memories can be used to store all of the group data corresponding to the target group identifier, and the remaining memories do not need to be used. In this case, the first target memory that needs to be involved in data reading can include only the first, second, and third memories.

[0108] In step 7203, a read command corresponding to each of the target number of memories is generated based on the storage address of the grouped data corresponding to the target group identifier.

[0109] In one example, if the storage address of the grouped data corresponding to the target group identifier is storage address A and the number of memories is eight, read commands for storage address A can be generated for the first memory to the eighth memory, respectively.

[0110] In step 7205, a read command corresponding to the first target memory is sent, and packet data corresponding to the target group identifier returned by the first target memory in response to the received read command is received.

[0111] Optionally, a data memory access circuit can be electrically connected to each memory. The data memory access circuit can transmit a read command corresponding to the first target memory through the corresponding electrical connection. The first target memory can receive the read command from the data memory access circuit. The command processing unit in the first target memory can obtain data indicated by the read command from the storage unit in the first target memory, and this data can be returned to the data memory access circuit. In this way, the data memory access circuit can obtain grouped data corresponding to the target group identifier.

[0112] Step 7207 filters the remaining read instructions other than the read instruction corresponding to the first target memory.

[0113] Optionally, filtering of the remaining read instructions can be realized by discarding the remaining read instructions other than the read instruction corresponding to the first target memory.

[0114] In one example, the target group identifiers are h0-1, w0-7, and c16-18. The number of memories is eight. The first target memory includes only the first, second, and third memories. Therefore, the first target memory can send only read commands corresponding to the first, second, and third memories, respectively, and filter read commands corresponding to the fourth through eighth memories. In this way, the first memory can return data that can be represented as h0-1, w0-7, and c16 to the data memory access circuit in response to a read command corresponding to the first memory. The second memory can return data that can be represented as h0-1, w0-7, and c17 to the data memory access circuit in response to a read command corresponding to the second memory. The third memory can return data that can be represented as h0-1, w0-7, and c18 to the data memory access circuit in response to a read command corresponding to the third memory. Clearly, the data memory access circuit completely obtains the grouped data corresponding to the target group identifier.

[0115] 8, read commands can be generated for all memories, but referring to the first distributed storage mode, only read commands corresponding to memories where required data is actually stored can be sent, and the remaining read commands can be filtered, i.e., not all read commands need to be sent, which is advantageous in saving bandwidth and power consumption. Optionally, generating the remaining read commands but not sending them can be referred to as an invalid read operation or a fake read operation.

[0116] Of course, the embodiment of step 720 is not limited thereto. For example, instead of employing an invalid read operation, all read commands corresponding to each memory may be sent.

[0117] Step 730 processes the grouping data corresponding to each of the plurality of group identifiers.

[0118] Alternatively, the grouped data corresponding to each of the plurality of group identifiers can be processed according to a preset processing rule. For example, each time a grouped data is read, the grouped data can be processed independently. Alternatively, multiple grouped data can be read and processed collectively. For example, after two grouped data are read, some elements of the two grouped data can be exchanged.

[0119] In the embodiment shown in FIG. 7, multiple memories can be introduced, thus providing a larger storage space for storing tensor data. Referring to the first distributed storage form, data can be retrieved from multiple memories to completely obtain the required grouped data, which is advantageous for finally reading the complete first tensor data.

[0120] 9 is a flowchart of a data acquisition and processing method according to some exemplary embodiments of the present disclosure. The method shown in FIG. 9 may include steps 910, 920, 930, 940, and 950. Optionally, the method shown in FIG. 9 may be performed after step 240 of the present disclosure. The method shown in FIG. 9 may be applied to the first stage.

[0121] In step 910, a plurality of read commands are generated based on the storage addresses of the grouped data corresponding to each of the plurality of group identifiers.

[0122] In one example, if the storage address of the grouped data corresponding to any group identifier is storage address B, a read command for storage address B can be generated.

[0123] In step 920, multiple read commands are sent to the memory.

[0124] Optionally, the data memory access circuitry can be electrically connected to the memory, and the data memory access circuitry can send multiple read commands to the memory via the electrical connection between the data memory access circuitry and the memory.

[0125] In step 930, the memory receives the plurality of grouped data returned in response to the plurality of read commands received.

[0126] Optionally, for each read command among the plurality of received read commands, the memory can return corresponding data to the data memory access circuit, and in this way, the data memory access circuit can obtain a plurality of grouped data.

[0127] In step 940, the arrangement order of the received grouped data is adjusted according to the transmission order of the read commands.

[0128] In one example, the multiple read instructions include read instruction 1, read instruction 2, and read instruction 3, and the transmission order of read instruction 1, read instruction 2, and read instruction 3 is to first send read instruction 1, then send read instruction 2, and then send read instruction 3. When receiving grouped data, assume that first the grouped data corresponding to read instruction 2 is received, then the grouped data corresponding to read instruction 3 is received, and then the grouped data corresponding to read instruction 1 is received. Then, the order of the grouped data can be adjusted, i.e., the grouped data corresponding to read instruction 1 is arranged in the first place, the grouped data corresponding to read instruction 2 is arranged in the second place, and the grouped data corresponding to read instruction 3 is arranged in the third place.

[0129] In step 950, the plurality of grouped data whose arrangement order has been adjusted is processed.

[0130] For the specific implementation of step 950, please refer to the related introduction of step 730 above, and the description will be omitted here.

[0131] In the embodiment shown in FIG. 9, after the memory receives a plurality of grouped data returned in response to the received plurality of read commands, it can first adjust the arrangement order of the received plurality of grouped data based on the sending order of the plurality of read commands, and then process the plurality of grouped data whose arrangement order has been adjusted. In this way, errors caused by data order confusion can be avoided by maintaining the data order.

[0132] 10 is a flowchart of a data writing method according to some exemplary embodiments of the present disclosure. The method shown in FIG. 10 may include steps 1010, 1020, and 1030. Optionally, the method shown in FIG. 10 may be performed after step 240 of the present disclosure. The method shown in FIG. 10 may be applied to the second stage.

[0133] In step 1010, grouping data corresponding to each of a plurality of group identifiers is determined based on the tensor data to be stored having a data size.

[0134] Alternatively, the second tensor data may be tensor data to be stored, which may have a data size. The tensor data to be stored may be a processing result obtained by processing the first tensor data read from the memory in the first stage.

[0135] Optionally, the tensor data to be stored can be divided based on the data grouping storage format in the second setting information, and thus multiple grouped data can be obtained, and the multiple grouped data obtained can include grouped data corresponding to each of the multiple group identifiers in step 1010.

[0136] In step 1020, a target number of memories and a second distributed storage form for the target number of memories for the single grouped data are determined based on the data memory access setting information.

[0137] For a specific embodiment of step 1020, please refer to the related description of step 710 above, and the description will be omitted here.

[0138] In step 1030, the grouped data corresponding to each of the plurality of group identifiers is written to a target number of memories based on the second distributed storage format and the storage addresses of the grouped data corresponding to each of the plurality of group identifiers.

[0139] In some alternative embodiments of the present disclosure, step 1030 may include step 10301, step 10303, step 10305, and step 10307, ​​as shown in FIG.

[0140] In step 10301, for grouped data corresponding to a target group identifier among a plurality of group identifiers, a second target memory that needs to be involved in data writing is determined from the target number of memories based on the second distributed storage format.

[0141] For a specific implementation of step 10301, please refer to the related description of step 7201 above, and the description will be omitted here.

[0142] In step 10303, a write command corresponding to each of the target number of memories is generated based on the storage address of the grouped data corresponding to the target group identifier.

[0143] In one example, if the storage address of the grouped data corresponding to the target group identifier is storage address C and the number of memories is eight, write commands for storage address C can be generated for the first memory to the eighth memory, respectively.

[0144] In step 10305, a write command corresponding to the second target memory is sent to the second target memory so that the second target memory writes data in response to the received write command.

[0145] Optionally, after sending the corresponding write command to the second target memory, the second target memory can receive the write command from the data memory access circuit, and the command processing unit in the second target memory can store the corresponding data in the storage unit in the second target memory in response to the write command.

[0146] In step 10307, ​​the remaining write commands other than the write command corresponding to the second target memory are filtered.

[0147] Optionally, the remaining write instructions other than the write instruction corresponding to the second target memory can be discarded to realize filtering of the remaining write instructions.

[0148] In one example, the above-mentioned h0-1, w0-7, and c16-18 are used as target group identifiers, the number of memories is eight, and thus the second target memory can include only the first memory, the second memory, and the third memory. Then, a write command can be sent to the first memory to instruct it to store data that can be represented as h0-1, w0-7, and c16, a write command can be sent to the second memory to instruct it to store data that can be represented as h0-1, w0-7, and c17, and a write command can be sent to the third memory to instruct it to store data that can be represented as h0-1, w0-7, and c18, and the write commands corresponding to the fourth memory to the eighth memory, respectively, can be filtered. In this way, the first memory can store data represented as h0~1, w0~7, c16 in response to a write command corresponding to the first memory, the second memory can store data represented as h0~1, w0~7, c16 in response to a write command corresponding to the second memory, and the third memory can store data represented as h0~1, w0~7, c18 in response to a write command corresponding to the third memory. Obviously, the grouping data corresponding to the target group identifier is completely written into the memory.

[0149] 11, write commands can be generated for all memories, but referring to the second distributed storage mode, only read commands corresponding to memories where required data is actually stored can be sent, and the remaining read commands can be filtered, i.e., not all read commands need to be sent, which is advantageous in saving bandwidth and power consumption. Optionally, generating the remaining read commands but not sending them can be referred to as an invalid read operation or a fake read operation.

[0150] Of course, the embodiment of step 1030 is not limited thereto. For example, it is also possible to send all read commands corresponding to each memory without adopting invalid read operations.

[0151] In the embodiment shown in FIG. 10, multiple memories can be introduced, thus providing a larger storage space for storing tensor data, and the second distributed storage form can be referenced and the corresponding data can be written to each memory, thereby advantageously writing the complete second tensor data to the memory.

[0152] In some alternative examples, as shown in FIG. 12, the embodiments of the present disclosure may perform the following operations to effectively realize the transfer of multi-dimensional data.

[0153] (1) Parameter settings The data memory access circuit can acquire data memory access setting information. The data memory access setting information can include hardware parameter settings and software parameter settings. The hardware parameter settings can include a target number of memories. The software parameter settings can include data sizes corresponding to the first and second stages, data address limit information corresponding to the first and second stages, and data grouping storage formats corresponding to the first and second stages.

[0154] (2) Address mapping The data memory access circuit can determine a plurality of group identifiers through a seven-layer modeling form, and determine the storage addresses of the grouped data based on these group identifiers.

[0155] (3)Fake operation Specifically, see the above-mentioned fake read operation and fake write operation. When using the fake read operation and fake write operation, read instructions and write instructions are generated for all memories, but only some of the read instructions and write instructions are sent, and other read instructions and other write instructions can be recalled at the port of the data memory access circuit without actually accessing the memory. Optionally, the port of the data memory access circuit can return invalid data and an invalid data flag bit for the recalled read instruction. The port of the data memory access circuit can send a write response for the recalled write instruction.

[0156] (4) Data processing Before data processing is performed, data order preservation processing can be performed.

[0157] As described above, in the embodiments of the present disclosure, the data memory access circuit can support the transfer of multidimensional data of various data sizes, and is highly flexible and versatile, which is advantageous in shortening the chip design cycle and reducing chip development costs.

[0158] [Example Device] 13 is a structural schematic diagram of a data memory access device according to some exemplary embodiments of the present invention. The data memory access device shown in FIG. an acquisition module 1310 for acquiring data memory access setting information; a first determining module 1320 for determining data size, data address limit information and data grouping storage format according to the data memory access setting information acquired by the acquiring module 1310; a second determining module 1330 for determining a plurality of group identifiers according to the data size and the data grouping storage form determined by the first determining module 1320; and a third determination module 1340 for determining, based on the data address restriction information determined by the first determination module 1320, storage addresses of grouped data corresponding to each of the plurality of group identifiers determined by the second determination module 1330.

[0159] In some alternative examples, as shown in FIG. 14, the third determination module 1340: a first determining sub-module 1410 for determining index values ​​corresponding to each of a plurality of data dimensions for a target group identifier in the plurality of group identifiers determined by the second determining module 1330; a second determining sub-module 1420 for determining a first reference address according to the data address restriction information determined by the first determining module 1320 and the index values ​​corresponding to each of the plurality of data dimensions determined by the first determining sub-module 1410; and a third determination sub-module 1430 for determining a storage address of the grouped data corresponding to the target group identifier based on the data address restriction information determined by the first determination module 1320 and the first reference address determined by the second determination sub-module 1420.

[0160] In some alternative examples, the second determination sub-module 1420: a first determination unit for determining strides corresponding to each of a plurality of data dimensions according to the data address limit information determined by the first determination module 1320; a second determination unit for determining a first reference address based on the index values ​​corresponding to each of the plurality of data dimensions determined by the first determination sub-module 1410 and the strides corresponding to each of the plurality of data dimensions determined by the first determination unit.

[0161] In some alternative examples, the third determination sub-module 1430: a third determination unit for determining an initial address, an address offset amount and an address range according to the data address restriction information determined by the first determination module 1320; a superimposing unit for superimposing the initial address determined by the third determining unit, the address offset determined by the third determining unit, and the first reference address determined by the second determining sub-module 1420 to obtain a second reference address; a fourth determining unit for determining distribution information of the second reference address obtained by the overlapping unit with respect to the address range determined by the first determining module 1320; a fifth determining unit for determining a storage address of the grouped data corresponding to the target group identifier according to the distribution information determined by the fourth determining unit.

[0162] In some alternative examples, the fifth determining unit is: a first determining sub-unit for determining a target value representing the size of the address range in response to the distribution information determined by the fourth determining unit indicating that the second reference address obtained by the superposition unit is outside the address range determined by the first determining module 1320; a second determination subunit for determining a numerical relationship between the target numerical value determined by the first determination subunit and a preset numerical value; a third determination subunit for determining a remainder obtained by dividing the second reference address obtained by the superposition unit and the target numerical value determined by the first determination subunit in response to the numerical relationship determined by the second determination subunit indicating that the target numerical value determined by the first determination subunit is an exponential power of a predetermined numerical value, and determining a storage address of grouped data corresponding to the target group identifier based on the remainder; and a fourth determination subunit for determining a difference between the second reference address obtained by the superposition unit and the target numerical value in response to the numerical relationship determined by the second determination subunit indicating that the target numerical value determined by the first determination subunit is not an exponential power of a preset numerical value, and determining a storage address of the grouped data corresponding to the target group identifier based on the difference.

[0163] In some alternative examples, the second determination unit: a fifth determination subunit for determining, based on the index values ​​corresponding to each of the plurality of data dimensions determined by the first determination submodule 1410, a first sort value along each of the plurality of data dimensions of a target data block to which grouped data corresponding to a target group identifier in the tensor data having a data size belongs, the target data block being a data block in which each of the grouped data included in any of the data dimensions shares the same first sort value; a sixth determining subunit for determining second sorting values ​​along a height dimension, a width dimension, and a channel dimension in each of the plurality of data dimensions of the grouped data corresponding to the target group identifier in the target data block according to the index values ​​corresponding to each of the plurality of data dimensions determined by the first determining submodule 1410; a seventh determining subunit for determining a sorted total value based on the corresponding first sorted value determined by the fifth determining subunit and the corresponding second sorted value determined by the sixth determining subunit for each of the height dimension, the width dimension, and the channel dimension; a fusion subunit for fusing, according to strides corresponding to each of the plurality of data dimensions determined by the first determination unit, the sorted total values ​​corresponding to each of the height dimension, the width dimension, and the channel dimension determined by the seventh determination subunit and the first sorted value corresponding to the batch size dimension in the plurality of data dimensions determined by the fifth determination subunit, to obtain a fusion value; and an eighth determining subunit for determining the first reference address based on the fused value obtained by the fusion subunit.

[0164] In some alternative examples, as shown in FIG. 15, a data memory access device according to an embodiment of the present disclosure includes: a fourth determination module 1510 for determining a target number of memories and a first distributed storage form for the target number of memories for a single grouped data according to the data memory access setting information acquired by the acquisition module 1310 after the third determination module 1340 determines the storage addresses of the grouped data corresponding to each of the plurality of group identifiers according to the data address restriction information; a reading module 1520 for reading grouped data corresponding to each of the plurality of group identifiers from a target number of memories based on the first distributed storage format determined by the fourth determination module 1510 and the storage addresses of the grouped data corresponding to each of the plurality of group identifiers; The device may further include a first processing module 1530 for processing grouping data corresponding to each of the plurality of group identifiers read by the reading module 1520.

[0165] In some alternative examples, the read module 1520 a fourth determination sub-module for determining a first target memory that needs to be involved in data reading from the target number of memories according to the first distributed storage form determined by the fourth determination module 1510 for a target group identifier in the plurality of group identifiers determined by the second determination module 1330; a first generating sub-module for generating a read command corresponding to each of the target number of memories based on a storage address of the grouped data corresponding to the target group identifier; a transmitting sub-module for transmitting a read command corresponding to the first target memory determined by the fourth determining sub-module, and receiving grouping data corresponding to the target group identifier returned by the first target memory determined by the fourth determining sub-module in response to the received read command; a first filtering sub-module for filtering remaining read commands other than the read command corresponding to the first target memory determined by the fourth determining sub-module.

[0166] In some alternative examples, as shown in FIG. 16, a data memory access device according to an embodiment of the present disclosure includes: a generating module 1610 for generating a plurality of read commands according to the storage addresses of the grouped data corresponding to each of the plurality of group identifiers after the third determining module 1340 determines the storage addresses of the grouped data corresponding to each of the plurality of group identifiers according to the data address restriction information; a sending module 1620 for sending the plurality of read instructions generated by the generating module 1610 to a memory; a receiving module 1630 for receiving a plurality of grouped data returned in response to a plurality of read commands received by the memory; an adjusting module 1640 for adjusting the arrangement order of the received grouped data according to the sending order of the read commands generated by the generating module 1610; The system may further include a second processing module 1650 for processing the plurality of grouped data whose arrangement order has been adjusted by the adjustment module 1640.

[0167] In some alternative examples, as shown in FIG. 17, a data memory access device according to an embodiment of the present disclosure includes: a fifth determination module 1710 for determining the grouped data corresponding to each of the plurality of group identifiers based on the tensor data to be stored and having a data size, after the third determination module 1340 determines the storage addresses of the grouped data corresponding to each of the plurality of group identifiers based on the data address limit information; a sixth determination module 1720 for determining a target number of memories and a second distributed storage form for the target number of memories of the single grouped data according to the data memory access setting information acquired by the acquisition module 1310; The storage device may further include a write module 1730 for writing the grouped data corresponding to each of the plurality of group identifiers determined by the fifth determination module 1710 into a target number of memories based on the second distributed storage form determined by the sixth determination module 1720 and the storage addresses of the grouped data corresponding to each of the plurality of group identifiers.

[0168] In some alternative examples, the write module 1730 a fifth determination submodule for determining a second target memory that needs to be involved in data writing from the target number of memories based on the second distributed storage format determined by the sixth determination module 1720 for the grouped data corresponding to the target group identifier among the plurality of group identifiers determined by the second determination module 1330; a second generating submodule for generating a write command corresponding to each of the target number of memories based on a storage address of the grouped data corresponding to the target group identifier; a sending sub-module for sending a write command corresponding to the second target memory determined by the fifth determining sub-module, so that the second target memory determined by the fifth determining sub-module performs data writing in response to the received write command; a second filtering sub-module for filtering remaining write commands other than the write command corresponding to the second target memory determined by the fifth determining sub-module.

[0169] In the device of the present disclosure, the various optional embodiments, optional embodiments, and optional examples disclosed above can all be flexibly selected and combined as needed to achieve corresponding functions and effects, and will not be listed one by one in the present disclosure.

[0170] The beneficial technical effects corresponding to the exemplary embodiments of the present apparatus may refer to the corresponding beneficial technical effects of the exemplary method parts above, and will not be described here.

[0171] [Example electronic devices] FIG. 18 illustrates a block diagram of an electronic device 1800 according to an embodiment of the present disclosure, where the electronic device 1800 includes one or more processors 1810 and a memory 1820.

[0172] The processor 1810 may be a central processing unit (CPU) or other form of processing unit having data processing and / or instruction execution capabilities, and may control other components in the electronic device 1800 to perform desired functions.

[0173] The memory 1820 may include one or more computer program products, which may include various types of computer-readable storage media, such as, for example, volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. The computer-readable storage media may store one or more computer program instructions, which the processor 1810 may execute to implement the methods of the embodiments of the present disclosure described above and / or other desired functions.

[0174] As an example, electronic device 1800 may further include input device(s) 1830 and output device(s) 1840 connected to each other via a bus system and / or other form of connection (not shown).

[0175] The input device 1830 may further include, for example, a keyboard, a mouse, and the like.

[0176] The output device 1840 can output various types of information to the outside, and can include a display, a speaker, a printer, a communication network, and remote output devices connected thereto.

[0177] 18 shows only some of the components related to the present disclosure in the electronic device 1800, and omits components such as a bus, an input / output interface, etc. In addition, the electronic device 1800 may further include any other appropriate components depending on a specific application situation.

[0178] Exemplary Computer Program Products and Computer-Readable Storage Media In addition to the methods and apparatus described above, embodiments of the present disclosure may further provide a computer program product including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the methods of various embodiments of the present disclosure described in the "Exemplary Methods" section above of this specification.

[0179] The computer program product may be written in any combination of one or more programming languages ​​to create program code for carrying out operations of embodiments of the present disclosure, including object-oriented programming languages ​​such as Java, C++, etc., and may further include general procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user equipment, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or a server.

[0180] Additionally, embodiments of the present disclosure may further provide a computer-readable storage medium having computer program instructions stored thereon that, when executed by a processor, cause the processor to perform method steps of various embodiments of the present disclosure as described in the "Exemplary Methods" section above.

[0181] The computer-readable storage medium can be any combination of one or more types of readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include an electrical connection having one or more wires, a portable disk, a hard drive, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0182] Although the basic principles of the present disclosure have been described above with reference to specific embodiments, the benefits, advantages, effects, etc. mentioned in the present disclosure are merely illustrative and not limiting, and various embodiments of the present disclosure do not necessarily have these benefits, advantages, effects, etc. Furthermore, the specific details of the above disclosure are merely for the purpose of illustrative and easy-to-understand functions and are not limiting, and the details do not necessarily limit the present disclosure to be realized by the specific details.

[0183] The foregoing description has been provided for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the present disclosure to the precise form disclosed herein. While several exemplary aspects and embodiments have been described above, those skilled in the art may recognize certain variations, modifications, variations, additions, and subcombinations thereof.

Claims

1. A data memory access method, each step of which is performed by a data memory access device, obtaining data memory access setting information; determining a data size, data address limit information and data grouping storage format based on the data memory access setting information; determining a plurality of group identifiers based on the data size and the data grouping storage format; determining storage addresses of grouped data corresponding to each of the plurality of group identifiers based on the data address restriction information; 1. A data memory access method comprising:

2. The step of determining storage addresses of grouped data corresponding to each of the plurality of group identifiers based on the data address restriction information includes: determining index values ​​corresponding to each of a plurality of data dimensions for a target group identifier among the plurality of group identifiers; determining a first reference address based on the data address restriction information and the index values ​​corresponding to each of the plurality of data dimensions; 2. The data memory access method according to claim 1, further comprising: determining a storage address of the grouped data corresponding to the target group identifier based on the data address restriction information and the first reference address.

3. determining a first reference address based on the data address restriction information and the index values ​​corresponding to each of the plurality of data dimensions, determining strides corresponding to each of the plurality of data dimensions based on the data address restriction information; determining a first reference address based on the index values ​​corresponding to each of a plurality of the data dimensions and the strides corresponding to each of the plurality of the data dimensions.

4. determining a storage address of the grouped data corresponding to the target group identifier according to the data address restriction information and the first reference address, determining an initial address, an address offset amount, and an address range based on the data address restriction information; superimposing the initial address, the address offset amount, and the first reference address to obtain a second reference address; determining distribution information for the address range of the second reference address; 3. The data memory access method according to claim 2, further comprising: determining a storage address of the grouped data corresponding to the target group identifier based on the distribution information.

5. The step of determining a storage address of the grouping data corresponding to the target group identifier according to the distribution information includes: determining a target value representing a size of the address range in response to the distribution information indicating that the second reference address is outside the address range; determining a numerical relationship between the target numerical value and a preset numerical value; determining a remainder obtained by dividing the second reference address by the target numerical value in response to the numerical relationship indicating that the target numerical value is an exponential power of the preset numerical value, and determining a storage address of grouped data corresponding to the target group identifier based on the remainder; 5. The data memory access method according to claim 4, further comprising: determining a difference between the second reference address and the target numerical value in response to the numerical relationship indicating that the target numerical value is not an exponential power of the preset numerical value; and determining a storage address of the grouped data corresponding to the target group identifier based on the difference.

6. determining a first reference address based on the index values ​​corresponding to each of the plurality of data dimensions and the strides corresponding to each of the plurality of data dimensions, A step of determining a first sort value along each of the plurality of data dimensions of a target data block to which grouped data corresponding to the target group identifier in tensor data having the data size belongs, based on the index value corresponding to each of the plurality of data dimensions, wherein the target data block is a data block in which each of the grouped data included in any of the data dimensions shares the same first sort value; determining second sort values ​​along a height dimension, a width dimension, and a channel dimension of each of the plurality of data dimensions of the grouped data corresponding to the target group identifier in the target data block based on the index values ​​corresponding to each of the plurality of data dimensions; determining a sorted sum value for each of the height dimension, the width dimension, and the channel dimension based on the corresponding first sorted value and the corresponding second sorted value; fusing the sorted sum values ​​corresponding to each of the height dimension, the width dimension, and the channel dimension, and the first sorted value corresponding to a batch size dimension in the plurality of data dimensions, based on the stride corresponding to each of the plurality of data dimensions, to obtain a fused value; 4. The method of claim 3, further comprising the step of: determining a first reference address based on the fused value.

7. The data memory access method includes, after a step of determining storage addresses of grouped data corresponding to each of the plurality of group identifiers based on the data address restriction information, determining a target number of memories and a first distributed storage format for the target number of single grouped data in the memories based on the data memory access setting information; reading the grouped data corresponding to each of the plurality of group identifiers from the target number of memories based on the first distributed storage format and storage addresses of the grouped data corresponding to each of the plurality of group identifiers; 7. The data memory access method according to claim 1, further comprising the step of: processing the grouped data corresponding to each of a plurality of the group identifiers.

8. the step of reading the grouped data corresponding to each of the plurality of group identifiers from the target number of memories based on the first distributed storage format and storage addresses of the grouped data corresponding to each of the plurality of group identifiers, determining a first target memory that needs to participate in data reading from the target number of memories based on the first distributed storage format for a target group identifier among the plurality of group identifiers; generating a read command corresponding to each of the target number of memories based on a storage address of the grouped data corresponding to the target group identifier; transmitting the read command corresponding to the first target memory, and receiving the grouping data corresponding to the target group identifier returned by the first target memory in response to the received read command; and filtering the remaining read instructions other than the read instruction corresponding to the first target memory.

9. The data memory access method includes, after a step of determining storage addresses of grouped data corresponding to each of the plurality of group identifiers based on the data address restriction information, generating a plurality of read instructions based on storage addresses of the grouped data corresponding to each of the plurality of group identifiers; sending a plurality of read commands to the memory; receiving a plurality of the grouped data returned in response to a plurality of the read commands received by the memory; adjusting the arrangement order of the received grouped data based on the transmission order of the read commands; 7. The data memory access method according to claim 1, further comprising the step of processing the plurality of grouped data whose arrangement order has been adjusted.

10. The data memory access method includes, after a step of determining storage addresses of grouped data corresponding to each of the plurality of group identifiers based on the data address restriction information, determining grouping data corresponding to each of the plurality of group identifiers based on tensor data to be stored having the data size; determining a target number of memories and a second distributed storage format for the target number of the single grouped data in the memory based on the data memory access setting information; The data memory access method according to any one of claims 1 to 6, further comprising a step of writing the grouped data corresponding to each of the plurality of group identifiers into the memory by the target number based on the second distributed storage form and the storage addresses of the grouped data corresponding to each of the plurality of group identifiers.

11. the step of writing the grouped data corresponding to each of the plurality of group identifiers into the target number of memories based on the second distributed storage format and storage addresses of the grouped data corresponding to each of the plurality of group identifiers, determining, for the grouped data corresponding to a target group identifier among the plurality of group identifiers, a second target memory that needs to be involved in data writing from the target number of memories based on the second distributed storage format; generating a write command corresponding to each of the target number of memories based on a storage address of the grouped data corresponding to the target group identifier; sending the write command corresponding to the second target memory so that the second target memory writes data in response to the received write command; and filtering the remaining write instructions other than the write instruction corresponding to the second target memory.

12. an acquisition module for acquiring data memory access setting information; a first determination module for determining a data size, data address limit information and a data grouping storage format according to the data memory access setting information acquired by the acquisition module; a second determining module for determining a plurality of group identifiers based on the data size and the data grouping storage format determined by the first determining module; a third determination module for determining, based on the data address restriction information determined by the first determination module, storage addresses of grouped data corresponding to each of the plurality of group identifiers determined by the second determination module; A data memory access device comprising:

13. A computer-readable storage medium, comprising:

10. A computer-readable storage medium having stored thereon a computer program for executing the data memory access method according to claim 1.

14. 1. An electronic device including a processor and a memory for storing instructions executable by the processor, The processor implements the data memory access method according to any one of claims 1 to 6 by reading and executing the executable instructions from the memory. An electronic device characterized by:

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