Multilayer ceramic capacitor and circuit board

Abstract

To provide a thin-type multilayer ceramic capacitor which is hard to break and in which an increase of ESR is suppressed, and a circuit board on which the multilayer ceramic capacitor is loaded.SOLUTION: A multilayer ceramic capacitor 100 comprises: a laminate 20 in which a ceramic layer 21 formed from ceramic and an internal electrode 22 containing a metal as a main component are alternately laminated; a rectangular parallelepiped element assembly 10 which is disposed while penetrating the ceramic layer 21 in a lamination direction of a protective part 30 covering a surface of the laminate 20 and the laminate 20, has at least one end reaching a surface of the protective part 30 and includes a plurality of via conductors 23a and 23b electrically connected to the internal electrode 22; and a plurality of terminal electrodes 40a and 40b disposed on a surface of the element assembly 10 and electrically connected with ends of the via conductors 23a and 23b reaching the surface of the protective part 30. The via conductors 23a and 23b internally include cavities 231 which extend in the lamination direction of the laminate 10 and has the ends closed by the via conductors.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor and a circuit board. [Background technology]

[0002] A wide variety of ceramic electronic components are used in high-frequency communication systems, such as mobile phones. These ceramic electronic components are required to be smaller and thinner, and efforts are being made to make them smaller and thinner in multilayer ceramic capacitors as well.

[0003] Patent Document 1 discloses a thin, break-resistant multilayer ceramic capacitor in which via-hole electrodes electrically connecting internal electrode layers to each other and internal electrode layers to terminal electrodes are formed with voids extending over substantially the entire length from the ends connected to the terminal electrodes. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-072263 Summary of the Invention [Problem to be solved by the invention]

[0005] In the multilayer ceramic capacitor disclosed in Patent Document 1, the contact area between the via-hole electrode and the terminal electrode is reduced by the amount of the gap, which makes it prone to peeling between the via-hole electrode and the terminal electrode, and increases the equivalent series resistance (ESR).

[0006] The present invention has been made to solve the above problems, and has an object to provide a thin multilayer ceramic capacitor that is resistant to breakage and in which an increase in ESR is suppressed, and a circuit board on which the multilayer ceramic capacitor is mounted. [Means for solving the problem]

[0007] The inventors conducted various studies to solve the above-mentioned problems and found that in a multilayer ceramic capacitor in which internal electrodes are electrically connected to each other through via conductors, the above-mentioned object can be achieved by forming a void inside the via conductor that extends in the stacking direction and has its ends blocked by the via conductor, thereby completing the present invention.

[0008] That is, a first aspect of the present invention for solving the above problem is a multilayer ceramic capacitor comprising: a laminate in which ceramic layers formed of ceramic and internal electrodes mainly composed of metal are alternately stacked; a protective portion covering the surface of the laminate; and a rectangular parallelepiped element body having a plurality of via conductors arranged to penetrate the ceramic layers in the stacking direction of the laminate, at least one end of which reaches the surface of the protective portion and is electrically connected to the internal electrodes; and a plurality of terminal electrodes arranged on the surface of the element body and electrically connected to an end of each of the via conductors that reaches the surface of the protective portion, wherein the via conductors include voids therein extending in the stacking direction of the laminate, and the voids have their ends blocked by the via conductors.

[0009] A second aspect of the present invention for solving the above problem is a circuit board on which the multilayer ceramic capacitor according to the first aspect is mounted. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a thin multilayer ceramic capacitor that is resistant to breakage and in which an increase in ESR is suppressed, and a circuit board on which the multilayer ceramic capacitor is mounted. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a schematic view (perspective view) showing the structure of a multilayer ceramic capacitor according to a first embodiment of the present invention. [Figure 2] 2 is a cross-sectional view taken along line AA (LT cross-sectional view) in FIG. 1. [Figure 3] 10A and 10B are diagrams for explaining a procedure for determining whether a void extending in the stacking direction of the laminate exists inside a via conductor and whether the end of the void is blocked by a via conductor. [Figure 4] 10 is a diagram for explaining a procedure for determining the percentage of the contact area between a void present inside a via conductor and the laminate, the void extending in the stacking direction of the laminate, relative to the total surface area of ​​the void. FIG. [Figure 5] 10A and 10B are diagrams for explaining a procedure for determining whether voids extending in the stacking direction of the laminate are present only in the periphery of via conductors. [Figure 6] FIG. 4 is a schematic view (LT cross-sectional view) showing the structure of a multilayer ceramic capacitor according to a second embodiment of the present invention. [Figure 7] FIG. 10 is a schematic view (LT cross-sectional view) showing the structure of a multilayer ceramic capacitor according to a third embodiment of the present invention. [Figure 8] FIG. 10 is a schematic view (perspective view) showing the structure of a multilayer ceramic capacitor according to a fourth embodiment of the present invention. [Figure 9] 3A to 3C are diagrams showing an example of a procedure for forming via conductor patterns when manufacturing a multilayer ceramic capacitor according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] The configuration and effects of the present invention will be described below, along with the technical concept, with reference to the drawings. However, the mechanism of action includes assumptions, and the correctness of such assumptions does not limit the present invention.

[0013] [Multilayer ceramic capacitors] First Embodiment An embodiment of a multilayer ceramic capacitor according to a first aspect of the present invention is shown in FIGS. 1 and 2 as a first embodiment. The multilayer ceramic capacitor 100 according to the first embodiment has a rectangular parallelepiped shape and includes a pair of faces perpendicular to each of three mutually orthogonal axes, i.e., the L-axis, which is the length direction, the W-axis, which is the width direction, and the T-axis, which is the height direction. The rectangular parallelepiped is not limited to a mathematically defined rectangular parallelepiped, and may have any shape that is recognized as a rectangular parallelepiped when observed as a whole. Therefore, a rectangular parallelepiped in the present disclosure also includes a capacitor with rounded edges and corners, a capacitor with curved edges, and a capacitor with curved faces with a small curvature. The length (L), width (W), and height (T) dimensions of the ceramic capacitor 100 can each independently take any value.

[0014] The dimensions of the multilayer ceramic capacitor 100 are, for example, an L-direction dimension of 200 μm to 2000 μm, a W-direction dimension of 100 μm to 2000 μm, and a T-direction dimension of 30 μm to 220 μm, with a value W / L (the ratio of the W-direction dimension to the L-direction dimension) of 0.3 to 1.0. It is preferable that the L-direction dimension be 400 μm to 1200 μm, the W-direction dimension be 400 μm to 1200 μm, and the T-direction dimension be 40 μm to 150 μm, with a value W / L (the ratio of the W-direction dimension to the L-direction dimension) of 0.4 to 1.0. It is more preferable that the T-direction dimension be 100 μm or less, as this is less subject to design constraints on the circuit board on which it is mounted.

[0015] 2 (LT cross section), the multilayer ceramic capacitor 100 according to the first embodiment includes a laminate 20 in which ceramic layers 21 made of ceramic and internal electrodes 22 mainly composed of metal are alternately stacked in the T direction, and an element body 10 having a protective part 30 covering the surface of the laminate 20. The internal electrodes 22 include internal electrodes 22a of one polarity that are electrically connected to each other, and internal electrodes 22b of a polarity different from that of the internal electrodes 22a that are electrically connected to each other.

[0016] A protective portion 30 is arranged on the surface of the element body 10, covering the surface of the laminate 20. The protective portion 30 includes a cover portion 31 arranged on a plane perpendicular to the T direction, and margin portions 32 arranged on a plane perpendicular to the W direction and a plane perpendicular to the L direction, respectively.

[0017] The element body 10 has a plurality of via conductors 23 that are arranged to penetrate the ceramic layers 21 in the stacking direction of the laminate 20, with at least one end reaching the surface of the protective part 30 (cover part 31) and electrically connected to the internal electrodes 22. The via conductors 23 include a via conductor 23a electrically connected to the internal electrode 22a and a via conductor 23b electrically connected to the internal electrode 22b. Note that although the multilayer ceramic capacitor 100 shown in FIGS. 1 and 2 includes two via conductors 23, the number of via conductors in the multilayer ceramic capacitor according to the first aspect of the present invention is not limited to this.

[0018] Within the via conductors 23 (23a, 23b), there are voids 231 extending in the stacking direction of the laminate 20, and the ends of the voids 231 are blocked by the via conductors. This makes the multilayer ceramic capacitor 100 less susceptible to breakage and suppresses an increase in ESR. This is presumably because the voids 231 extending in the stacking direction of the laminate 20 relieve stress generated in the via conductors 23 (23a, 23b), making it less likely for stress to be transmitted to the laminate 20, and the ends of the voids 231 being blocked by the via conductors 23 (23a, 23b) ensure a contact area between the via conductors 23 (23a, 23b) and the terminal electrodes 40 (described later). Because the via conductors 23 (23a, 23b) are fired integrally with the laminate 20 during manufacturing, materials are selected taking into consideration heat resistance and compatibility with the laminate 20 in terms of shrinkage behavior. As a result, the via conductors 23 (23a, 23b) tend to have a higher resistivity than the terminal electrodes 40. Therefore, increasing the contact area with the terminal electrode 40 is effective in suppressing an increase in ESR. Note that, in the multilayer ceramic capacitor 100 shown in FIG. 2, two voids 231 extending in the stacking direction of the laminate 20 are formed inside the via conductors 23 (23a, 23b), but the number of voids 231 is not limited to this. Furthermore, the via conductors 23 (23a, 23b) may contain voids of shapes other than those extending in the stacking direction of the laminate 20, such as spherical shapes, within a range in which the desired conductivity is obtained. Details of the shape and structure of the via conductors 23 (23a, 23b) and the voids 231 extending in the stacking direction will be described later.

[0019] The multilayer ceramic capacitor 100 according to the first embodiment is arranged at least on a mounting surface 11, which is the surface that faces the circuit board when mounted on the circuit board, among the surfaces that form the surface of the element body 10, and includes a plurality of terminal electrodes 40 electrically connected to via conductors 23 (23a, 23b). The terminal electrodes 40 include a terminal electrode 40a electrically connected to the via conductor 23a and a terminal electrode 40b electrically connected to the via conductor 23b. Note that although the multilayer ceramic capacitor 100 shown in FIGS. 1 and 2 includes two terminal electrodes 40, the number of terminal electrodes in the multilayer ceramic capacitor according to the first aspect of the present invention is not limited to this.

[0020] The thickness of the element body 10, obtained by subtracting the thickness of the terminal electrodes 40 (40a, 40b) from the T-direction dimension of the multilayer ceramic capacitor 100 described above, is, for example, 20 μm to 200 μm, and preferably 30 μm to 180 μm.

[0021] Hereinafter, each component constituting the multilayer ceramic capacitor 100 according to the first embodiment will be described in detail.

[0022] (ceramic layer) The ceramic layer 21 is made of ceramic. The ceramic composition is not particularly limited as long as it forms a dense ceramic layer 21 by co-firing with the internal electrodes 22 described later, and may be appropriately selected depending on the properties required for the multilayer ceramic capacitor. Examples of ceramic compositions include those containing barium titanate (BaTiO3) as the main component, those containing strontium titanate (SrTiO3) as the main component, and those containing BaTiO3 having a perovskite structure. 1-x-y Ca x Sr y Ti 1-z Zr z Examples of such ceramics include those containing O3 as a main component. The ceramic may contain an additive element in addition to the main component. Examples of the additive element include at least one selected from Mo, Nb, Ta, W, Mg, Mn, V, Cr, rare earth elements (Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, and Yb), and Co, Ni, Li, B, Na, K, and Si. The additive element may be contained as a simple element or in the form of a compound such as an oxide, nitride, or carbide. The additive element may exist in a solid solution state in the main component, or may form a different phase from the elements constituting the main component or other additive elements.

[0023] (Internal electrode) The internal electrodes 22 (22a, 22b) are primarily composed of a metal. The type of metal is not particularly limited, and nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof can be used. Among these, nickel (Ni) is preferred as the primary element because of its high heat resistance, which allows the firing temperature to be increased when co-firing with the ceramic layer 21 to form a dense ceramic layer 21, and it is relatively inexpensive. Here, the term "primary element" as used herein refers to the element with the highest content expressed in atomic percentage (atomic %).

[0024] The internal electrodes 22 (22a, 22b) may contain, in addition to metal, ceramic particles having the same composition as the ceramic constituting the ceramic layer 21, or a glass component.

[0025] (Protection Department) The protective part 30 has a function of protecting the ceramic layers 21 and the internal electrodes 22. The material of the protective part 30 is not limited as long as it has high electrical insulation and low permeability to deterioration factors such as moisture. From the viewpoints of making shrinkage during firing when manufacturing the multilayer ceramic capacitor 100 uniform and alleviating internal stress within the multilayer ceramic capacitor 100, it is preferable that the main component of the protective part 30 be the same as the ceramic that forms the ceramic layers 21.

[0026] (Via conductor) Like the internal electrodes 22 (22a, 22b), the via conductors 23 (23a, 23b) are primarily composed of metal. Usable metals include those similar to those of the internal electrodes 22 (22a, 22b) described above. The composition of the via conductors may be different from that of the internal electrodes 22 (22a, 22b), but is preferably the same as that of the internal electrodes 22 (22a, 22b). By making the via conductors (23a, 23b) and the internal electrodes 22 (22a, 22b) the same composition, the magnitude of shrinkage caused by firing during manufacturing of the multilayer ceramic capacitor 100 is uniform, suppressing deformation, and the resistivity of the conductive paths of the multilayer ceramic capacitor 100 is uniform, suppressing localized heat generation during use.

[0027] As described above, inside the via conductors 23 (23a, 23b), there are voids 231 extending in the stacking direction of the laminate 20, and the ends of the voids 231 are closed by the via conductors.

[0028] Here, whether a void 231 extending in the stacking direction of the laminate 20 exists inside the via conductor 23 (23a, 23b) and whether the end of the void is blocked by the via conductor is determined by the following procedure. First, a surface perpendicular to the mounting surface 11 of the multilayer ceramic capacitor 100, i.e., the surface that faces the circuit board when mounted on the circuit board, is ground to expose the via conductor 23a. Grinding is performed up to the vicinity of the center of gravity of the figure obtained by projecting the via conductor 23a onto the mounting surface 11. Grinding may also be performed on the multilayer ceramic capacitor 100 embedded in resin. Next, the ground surface where the via conductor 23a is exposed is observed with an optical microscope or a scanning electron microscope (SEM) to obtain an image in which the boundary between the via conductor 23a and the laminate 20, the terminal electrode 40a, the mounting surface 11, and the surface facing it are all in the same field of view, as shown in FIG. 3. Next, a line segment h1 defining the mounting surface 11 is drawn in the obtained image. Next, in the image, a portion inside the via conductor 23a that is recognized as an area with a contrast different from that of the via conductor 23a, the terminal electrode 40a, the ceramic layer 21, the cover portion 31, and the internal electrodes 22 (22a, 22b) is determined to be a void. Next, a void to be determined is determined, and a line segment h2 that contacts the void to be determined, is parallel to the line segment h1, and is the shortest distance from the line segment h1; a line segment h3 that contacts the void, is parallel to the line segment h1, and is the longest distance from the line segment h1; and two line segments v1 and v2 that are perpendicular to the line segment h1 and contact the void, and are the longest distance from each other. Then, when the distance between the line segment h2 and the line segment h3 is greater than the distance between the line segment v1 and the line segment v2, the void to be determined is determined to extend in the stacking direction of the laminate 20. Next, in the image, the intersection of the void 231 extending in the stacking direction of the laminate 20 and the line segment h2 is designated as H2, the intersection of the void 231 to be determined and the line segment h3 is designated as H3, and a line segment v3 passing through point H2 and perpendicular to line segment h1, and a line segment v4 passing through point H3 and perpendicular to line segment h1 are drawn. Then, the end of the void 231 to be determined is determined to be blocked by a via conductor when the side of line segment v3 closer to mounting surface 11 than point H2 and the side of line segment v4 farther from the mounting surface than point H3 overlap with via conductor 23a.When drawing the line segment h1, if the mounting surface 11 observed in the image forms a curve or a broken line, the curve or broken line is linearly approximated to form the line segment. Also, although the above procedure is for the vicinity of the via conductor 23a, it goes without saying that it may also be performed for the vicinity of the via conductor 23b, which has a different polarity.

[0029] The voids 231 present inside the via conductors 23 (23a, 23b) and extending in the stacking direction of the laminate 20 preferably have a contact area with the laminate 20 of 30% or less of the total surface area of ​​the voids 231. This ensures a sufficient contact area between the via conductors 23 (23a, 23b) and the internal electrodes 22 (22a, 22b), further reducing the ESR. The area percentage is more preferably 25% or less, even more preferably 20% or less, and particularly preferably 15% or less.

[0030] Here, for a void 231 present inside the via conductor 23 (23a, 23b) and extending in the stacking direction of the laminate 20, the percentage of the contact area with the laminate 20 relative to the total surface area is determined by the following procedure. First, using the same procedure as in the above-mentioned case of determining that a void 231 present inside the via conductor 23 (23a, 23b) and extending in the stacking direction of the laminate 20 exists and that the end of the void is blocked by the via conductor, an image is obtained in which the boundary between the via conductor 23a and the laminate 20, the terminal electrode 40a, the mounting surface 11, and the surface facing thereto are in the same field of view, as shown in Fig. 4, and the void 231 is identified in the obtained image. Next, line segments b1 and b2 that define the boundary with the laminate 20 are drawn on both sides of the via conductor 23a in the image, respectively, and one void 231 that overlaps with either of the line segments is focused on. In the void 231 of interest, the lengths P1, P2, . . . , P n(where n is a natural number) are measured, and the total P is calculated. Next, the length R of the periphery of the void 231 of interest in the image is measured. The length measurement function of image processing software can be used for the measurement. Next, the value (P / R) × 100, which is the percentage of P to R, is calculated, and this value is used as the percentage of the contact area with the laminate 20 to the total surface area of ​​the void 231 of interest. Note that for voids 231 present inside via conductor 23a that do not overlap with the boundary line, the percentage of the contact area with the laminate 20 to the total surface area is determined to be 0% without having to perform the above-mentioned operations.

[0031] It is preferable that the voids 231 present inside the via conductors 23 (23a, 23b) and extending in the stacking direction of the laminate 20 are present only in the peripheral portions of the via conductors 23 (23a, 23b). This makes the multilayer ceramic capacitor 100 less susceptible to damage. This is presumably because stress tends to concentrate more easily in the peripheral portions of the via conductors 23 (23a, 23b) than in the center, and therefore the presence of the voids 231 extending in the stacking direction of the laminate 20 enhances the stress relaxation effect.

[0032] Here, determining whether voids 231 present inside via conductors 23 (23a, 23b) and extending in the stacking direction of laminate 20 are present only at the periphery of via conductors 23 (23a, 23b) is performed using the following procedure: First, using the same procedure as in the above-mentioned case of determining the percentage of the contact area between voids 231 present inside via conductors 23 (23a, 23b) and laminate 20 and extending in the stacking direction of laminate 20 relative to the total surface area, an image is obtained in which the boundary between via conductor 23a and laminate 20, terminal electrode 40a, mounting surface 11, and the surface facing thereto are in the same field of view, as shown in Fig. 5, and voids 231 are identified in the obtained image, and line segments b1 and b2 are drawn. Next, among the internal electrodes 22a in contact with the via conductors 23a in the image, attention is focused on the one located at the outermost position in the lamination direction, and line segments e1 and e2 that define the outer surfaces of the internal electrodes 22a are drawn, and the points where the line segment e1 intersects with the line segments b1 and b2 are respectively designated as E. 11and E 22 Let the points where line segment e2 intersects with line segment b1 and line segment b2 be E 21 and E 22 When drawing the line segments e1 and e2, if the internal electrodes 22a of interest form a curve or a broken line, the curve or the broken line is linearly approximated to form the line segments. 11 and point E 12 The midpoint of the line segment connecting these points is C1, and point E 21 and E 22 The midpoint of the line segment connecting these points is designated as C2, and a line segment c passing through points C1 and C2 is drawn. 11 and point E 12 The distance between and point E 21 and E 22 The distances between the points E and E are measured and compared, and the shortest of the distances is designated as d. 11 and point E 12 The distance between and point E 21 and E 22 and c2 are drawn in the image, each of which is 0.05d away from the line segment c. The area between the line segments c1 and c2 is determined to be the center of the via conductor 23a. Since the void 231 extending in the stacking direction of the laminate 20 is not observed in the center of the via conductor 23a in the image, it is determined that the void 231 extending in the stacking direction of the laminate 20 exists only in the peripheral portion of the via conductor 23a.

[0033] (terminal electrode) The material of the terminal electrodes 40 (40a, 40b) is not limited as long as it is conductive, and examples of the material include metals such as nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), and gold (Au), alloys containing any of these as a main component, and conductive resins.

[0034] The terminal electrodes 40 (40a, 40b) may have an underlying conductor 41 in contact with the element body 10 and a plated conductor 42 formed on the surface of the underlying conductor 41. The terminal electrodes 40 (40a, 40b) having such a structure can improve adhesion to the element body 10 by the underlying conductor 41, and can improve solder wettability by the plated conductor 42 when mounted on a circuit board.

[0035] Ni is an example of the material of the underlying conductor 41. The thickness of the underlying conductor 41 can be set to 0.1 μm or more and 10 μm or less, and preferably 0.5 μm or more and 5 μm or less.

[0036] The plated conductor 42 may be formed of a single layer or multiple layers. When the plated conductor 42 is formed of multiple layers, the number of layers is preferably two to four. An example of the material and structure of the plated conductor 42 is one formed of Cu, Ni, and Sn in this order. The thickness of the plated conductor 42 can be 1 μm to 20 μm, and preferably 3 μm to 10 μm.

[0037] <Second embodiment> In another embodiment (second embodiment) of the multilayer ceramic capacitor according to the first aspect of the present invention, the cross section of the via conductors 23 (23a, 23b) parallel to the stacking direction is trapezoidal. In this case, if the cross section of the via conductors 23 (23a, 23b) perpendicular to the stacking direction is circular or elliptical, the via conductors will have a tapered shape. FIG. 6 shows an example of a multilayer ceramic capacitor 200 according to the second embodiment. In the multilayer ceramic capacitor 200, the interfaces between the via conductors 23 (23a, 23b) and the internal electrodes 22 (22a, 22b) are less likely to peel off, thereby suppressing a decrease in capacitance. This is presumably due to an increase in the contact area between the via conductors 23 (23a, 23b) and the laminate 20 and the contact area between the via conductors 23 (23a, 23b) and the cover portion 31. The size relationship between the upper and lower bases of the trapezoid formed by the cross section of the via conductors 23 (23a, 23b) parallel to the lamination direction is not limited, but when only one end of the via conductors 23 (23a, 23b) contacts the terminal electrodes 40 (40a, 40b) and the other end is present inside the cover part 31, as in the multilayer ceramic capacitor 200 shown in FIG. 6 , it is preferable that the dimension of the side in contact with the terminal electrodes 40 (40a, 40b) is larger than the dimension of the side present inside the cover part 31. In this case, the contact area between the via conductors 23 (23a, 23b) and the terminal electrodes 40 (40a, 40b) is increased, thereby reducing the ESR. In addition, the shrinkage behavior of the via conductors 23 (23a, 23b) during firing in manufacturing approaches that of the terminal electrodes 40 (40a, 40b), thereby significantly suppressing peeling at the interfaces between the via conductors 23 (23a, 23b) and the internal electrodes 22 (22a, 22b).

[0038] <Third embodiment> In another embodiment (third embodiment) of the multilayer ceramic capacitor according to the first aspect of the present invention, the internal electrodes are drawn out to a surface perpendicular to the mounting surface, and external electrodes are disposed on the surfaces (drawn-out surfaces) to which the internal electrodes are drawn out, and the internal electrodes are also electrically connected via the external electrodes. An example of a multilayer ceramic capacitor 300 according to the third embodiment is shown in FIG. 7. Note that FIG. 7 shows an example in which two opposing surfaces are drawn out as drawn-out surfaces 12, but the number of drawn-out surfaces is not limited to this. Also, FIG. 7 shows an example in which terminal electrodes 40 (40a, 40b) extending to the drawn-out surfaces 12 form external electrodes 50 (50a, 50b), but the external electrodes 50 (50a, 50b) may be formed separately from the terminal electrodes 40 (40a, 40b). In the multilayer ceramic capacitor 300, the current flowing through the internal electrodes 22 (22a, 22b) is divided between the via conductors 23 (23a, 23b) and the external electrodes 50 (50a, 50b), thereby reducing the current flowing through each of the via conductors 23 (23a, 23b) and the external electrodes 50 (50a, 50b). This reduces heat generation during operation.

[0039] <Fourth embodiment> In another embodiment (fourth embodiment) of the multilayer ceramic capacitor according to the first aspect of the present invention, the number of terminal electrodes arranged on the mounting surface is four or more, and each of the terminal electrodes has a polarity opposite to that of the nearest terminal electrode on the mounting surface. An example of a multilayer ceramic capacitor 400 according to the fourth embodiment is shown in FIG. 8. Note that FIG. 8 shows an example in which the number of terminal electrodes 40 arranged on the mounting surface 11 is four, but the number of terminal electrodes arranged on the mounting surface is not limited to this. In the multilayer ceramic capacitor 400, the directions of currents flowing through via conductors (not shown) electrically connected to each terminal electrode 40 (40a, 40b) are opposite to those of the nearest conductors, so that magnetic fields generated by the currents cancel each other out, thereby reducing the equivalent series inductance (ESL). The above-mentioned effects are remarkable when the multilayer ceramic capacitor 400 has two pairs of surfaces that are parallel to the stacking direction of the laminate and face each other, and when the distance between one pair, i.e., the L-direction dimension, is L μm and the distance between the other pair, i.e., the W-direction dimension, is W μm (where L≧W), and when the value of W / L, which is the ratio of W to L, is 0.8 or more and 1 or less, i.e., when the mounting surface 11 has a shape that is close to a square.

[0040] [Manufacturing method for multilayer ceramic electronic components] The multilayer ceramic capacitor according to the first aspect of the present invention can be manufactured by the procedure described below.

[0041] (A) Preparation of ceramic powder First, ceramic powder is prepared. Commercially available ceramic powders can be used as appropriate. When producing ceramic powder in-house, various raw material powders containing the constituent elements are mixed in a predetermined ratio and pre-fired (calcined). When mixing the various raw material powders in a predetermined ratio, various additives such as the above-mentioned additive elements and sintering aids may be further added, or these various additives may be further added to the powder after calcination.

[0042] (B) Preparation of raw sheets Next, the ceramic powder is mixed with a binder and a dispersion medium to prepare a slurry, and the slurry is formed into a sheet to obtain a green sheet.

[0043] The binder used should be one that can maintain the shape of the green sheet and volatilizes without leaving behind carbon or other residues during the binder removal process prior to firing. Examples of binders that can be used include polyvinyl alcohol, polyvinyl butyral, cellulose, urethane, and vinyl acetate. There are no particular restrictions on the amount of binder used, but since it will be removed in a later process, it is preferable to use as little as possible within the range that achieves the desired formability and shape retention, in order to reduce raw material costs.

[0044] The dispersion medium used is one that does not cause aggregation of the calcined powder and binder and can be easily removed by volatilization or the like after forming into a green sheet, as described below. Examples of the dispersion medium that can be used include water and alcohol-based solvents.

[0045] Components for adjusting the properties of the slurry, such as dispersants, plasticizers, and thickeners, may be added to the slurry.

[0046] The method for mixing the mixed powder with the binder and the dispersion medium is not particularly limited as long as the components are mixed uniformly while preventing the inclusion of impurities. One example is ball mill mixing.

[0047] The prepared slurry can be formed into a sheet to obtain a green sheet by a commonly used method such as a doctor blade method or a die coating method.

[0048] ((C) Formation of internal electrode pattern) Next, an internal electrode pattern containing metal is formed on the green sheet. The internal electrode pattern can be formed by printing or applying an internal electrode paste in a predetermined pattern, or by forming a metal film in a predetermined pattern by vapor deposition or sputtering. The internal electrode pattern is formed with a sufficient margin to ensure electrical insulation with via conductor patterns that will be formed later and that will not come into contact with the via conductor patterns. This margin forms the internal electrode portion facing portion in the element body obtained after firing, which will be described later.

[0049] When forming an internal electrode pattern using an internal electrode paste, the internal electrode paste used is obtained by mixing metal particles and a vehicle in a triple roll mill. The internal electrode paste may contain glass frit and ceramic powder in addition to the above-mentioned components.

[0050] The type and amount of binder and solvent contained in the vehicle used are not limited, and may be selected appropriately taking into consideration the viscosity of the internal electrode paste, ease of handling, compatibility with the green sheet, and the like.

[0051] The internal electrode paste can be printed on the green sheet using, for example, a screen mask on which a predetermined internal electrode pattern is formed. When printing, a space may be left to become a margin when the multilayer ceramic capacitor is completed.

[0052] (D) Preparation of green laminate Next, a predetermined number of green sheets on which the internal electrode patterns have been formed are stacked and the green sheets are pressure-bonded together to obtain a green laminate. The stacking and pressure-bonding can be performed by a conventional method, such as pressing the stacked green sheets together in the stacking direction while heating them, and thermo-compression bonding by the action of a binder.

[0053] During lamination and compression bonding, a green sheet that will become a cover when the multilayer ceramic capacitor is completed may be added to the end portion in the lamination direction. In this case, the green sheet to be added may have the same composition as the green sheet on which the internal electrode pattern is printed, or a different composition. From the viewpoint of making the shrinkage rate during firing uniform, it is preferable that the composition of the green sheet to be added is the same as or similar to the green sheet on which the above-mentioned internal electrode precursor is arranged.

[0054] (E) Formation of holes for via conductors Next, holes for via conductors are formed in the green laminate. The formed holes may penetrate the green laminate or may have one end located within the green laminate. Conventional methods such as drilling or lasers can be used to form the holes. Among these, the use of a laser is preferred because it can form a smooth processed surface.

[0055] ((F) Formation of via conductor pattern) Next, the holes for the via conductors are filled with a conductive paste to form a via conductor pattern. The conductive paste used contains resin beads that volatilize at the heating temperature during firing, which will be described later. By using two types of conductive paste with different resin bead contents, voids extending in the stacking direction of the laminate and whose ends are blocked by the via conductors can be formed inside the via conductors. A specific filling procedure, as shown in FIG. 9 , involves injecting a first conductive paste 2301 with a low resin bead content (high conductive material content) along the wall surface of the hole and drying it. Then, injecting a second paste 2302 with a high resin bead content (low conductive material content) along the wall surface of the first conductive paste and drying it. Finally, filling the first paste 2301 to block the voids in the hole. Commonly used methods, such as squeegee printing using a metal mask or syringe printing, can be used to inject the conductive paste into the hole. Among these, squeegee printing using a metal mask is preferred due to its excellent filling ability into small-diameter holes. The components of the conductive paste other than the resin beads can be the same as those of the internal electrode paste described above, and the amount of each component to be added can be determined taking into consideration the injection properties into the holes.

[0056] ((G) Formation of terminal electrode pattern) Next, a terminal electrode pattern is formed on at least one of the surfaces (mounting surface) perpendicular to the lamination direction of the green laminate. A green sheet, which will serve as a cover when the laminate is completed, may be crimped onto the surface on which the terminal electrode pattern is not formed, so as to cover the via conductor pattern. The terminal electrode pattern can be formed by printing or applying a terminal electrode paste, or by forming a metal film by vapor deposition or sputtering. The terminal electrode pattern can be formed using a mask with a predetermined pattern, or by forming a paste film or metal film on the entire mounting surface of the green laminate and then removing the area other than the terminal electrode pattern. Face milling, barrel polishing, or other methods can be used to remove the area other than the terminal electrode pattern. When using a terminal electrode paste to form the terminal electrode pattern, the components can be the same as those of the internal electrode paste described above. The blending amounts of each component can be determined to obtain a uniform pattern with a predetermined thickness.

[0057] (H) Preparation of pre-fired chips Next, the green laminate is divided into individual pieces to obtain pre-fired chips. For the division, a commonly used means such as a dicing saw or a laser cutting machine can be used. After dividing the green laminate into individual pieces to form surfaces on which the internal electrode precursors are exposed, the surfaces may be coated with a material for forming margins to obtain pre-fired chips.

[0058] (I) Removal of binder Next, the resulting pre-fired chips are heated to volatilize and remove the binder. The heating conditions can be set appropriately taking into account the volatilization temperature and content of the binder. For example, the chips are held in a nitrogen (N2) atmosphere at a temperature of 200 to 500°C for 5 to 20 hours.

[0059] (J) Firing of pre-fired chips Next, the pre-fired chip from which the binder has been removed is heated to a predetermined temperature and fired. During firing, the resin beads in the via conductor pattern volatilize, creating voids. These voids then rearrange as other materials sinter, forming voids extending in the stacking direction. When determining firing conditions, it is preferable to consider the volatilization temperature of the resin beads, the sinterability of the ceramic powder, and the heat resistance and oxidation resistance of the metals contained in the internal electrode pattern, via conductor pattern, and terminal electrode pattern. Examples of firing conditions include holding the chip in a reducing atmosphere containing a mixture of nitrogen (N), hydrogen (H), and water vapor (H2O) at a temperature of 1100°C to 1400°C for 10 minutes to 2 hours. After firing, a reoxidation treatment may be performed in a nitrogen (N2) gas atmosphere or a low-oxygen atmosphere at a temperature of 600°C to 1000°C.

[0060] The sintered body thus obtained may be used as a multilayer ceramic capacitor as it is, or may be used as a multilayer ceramic capacitor after forming a conductive layer on the surface of the terminal electrode pattern by plating.

[0061] [Circuit board] A circuit board according to a second aspect of the present invention is equipped with the multilayer ceramic capacitor according to the first embodiment. This circuit board is highly reliable and can be installed in a small space because the multilayer ceramic capacitor is a thin type that suppresses the reduction in capacitance.

[0062] This specification also discloses the following techniques.

[0063] (Appendix 1) a laminate in which ceramic layers formed of ceramic and internal electrodes mainly composed of metal are alternately stacked; a protective portion covering the surface of the laminate; and a plurality of via conductors arranged to penetrate the ceramic layers in the stacking direction of the laminate, at least one end of which reaches the surface of the protective portion and is electrically connected to the internal electrodes; A rectangular parallelepiped element having the following structure: a plurality of terminal electrodes disposed on the surface of the element body and electrically connected to ends of the via conductors that reach the surface of the protection portion; Equipped with The via conductor includes a void extending in the stacking direction of the laminate, and the void has an end blocked by the via conductor. Multilayer ceramic capacitor.

[0064] (Appendix 2) The multilayer ceramic capacitor according to (Supplementary Note 1), wherein the contact area of ​​the void with the laminate is 30% or less of the total surface area of ​​the void.

[0065] (Appendix 3) The multilayer ceramic capacitor according to (Supplementary Note 1) or (Supplementary Note 2), wherein the voids are present only in the periphery of the via conductors.

[0066] (Appendix 4) The multilayer ceramic capacitor according to any one of (Appendix 1) to (Appendix 3), wherein the dimension in the lamination direction is 100 μm or less.

[0067] (Appendix 5) A circuit board on which the multilayer ceramic capacitor according to any one of (Appendix 1) to (Appendix 4) is mounted. [Industrial Applicability]

[0068] According to the present invention, it is possible to provide a thin multilayer ceramic capacitor that is resistant to breakage and has an ESR that is suppressed from increasing. Such a multilayer ceramic capacitor is not only highly reliable and high-performance, but also useful in that it can be placed in a small space, thereby reducing restrictions on the design of a circuit board. [Explanation of symbols]

[0069] 100, 200, 300, 400 Multilayer ceramic capacitors 10 Base 11 Mounting surface 12 Drawer surface 20 laminate 21 ceramic layer 22(22a, 22b) Internal electrode 23(23a, 23b) Via conductor 231 Voids extending in the stacking direction of the laminate 30 Protection Department 31 Cover 32 Margin 40(40a, 40b) terminal electrode 41 Undercoat conductor 42 Plated conductor 50(50a, 50b) External electrode 2301 First Paste 2302 Second Paste

Claims

1. a laminate in which ceramic layers formed of ceramic and internal electrodes mainly composed of metal are alternately stacked; a protective portion covering the surface of the laminate; and a plurality of via conductors arranged to penetrate the ceramic layers in the stacking direction of the laminate, at least one end of which reaches the surface of the protective portion and is electrically connected to the internal electrodes; A rectangular parallelepiped element having the following structure: a plurality of terminal electrodes disposed on the surface of the element body and electrically connected to ends of the via conductors that reach the surface of the protection portion; Equipped with The via conductor includes a void extending in the stacking direction of the laminate, and the void has an end blocked by the via conductor. Multilayer ceramic capacitor.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein the contact area of ​​the void with the laminate is 30% or less of the total surface area of ​​the void.

3. The multilayer ceramic capacitor according to claim 1 , wherein the voids are present only around the periphery of the via conductor.

4. 2. The multilayer ceramic capacitor according to claim 1, wherein the dimension in the lamination direction is 100 μm or less.

5. A circuit board having the multilayer ceramic capacitor according to any one of claims 1 to 4 mounted thereon.

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