Semiconductor package

Abstract

To provide a semiconductor package in which the size is reduced, the performance is enhanced, and an integrated circuit function is improved.SOLUTION: A semiconductor package includes a first substrate 10, a first semiconductor structure 20, a second substrate 30, and a filling layer 40. A first surface 101 of the first substrate includes a first signal transmission region 11 and a second signal transmission region 12. The first semiconductor structure exists on the first surface of the first substrate and is electrically connected to the first signal transmission region. The second substrate exists on the first substrate. The second substrate includes a base 33 and a first mutual connection surface 301 existing on the base. The first mutual connection surface faces a side of the first substrate opposite to the first surface, includes a first mutual connection region 31 and a second mutual connection region 32. The filling layer seals the first semiconductor structure, the second substrate, and the first surface of the first substrate. The first mutual connection region is not sealed with the filling layer and the second mutual connection region is sealed with the filling layer. Between an upper surface of the filling layer on the second mutual connection region and the first mutual connection region, a predetermined height h exists.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application is based on a Chinese patent application filed with the China Patent Office on July 8, 2022, bearing application number 202210806565.3 and entitled "Semiconductor Package," and claims priority to that Chinese patent application, the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to the field of semiconductor technology, and more particularly to semiconductor packages. [Background technology]

[0003] Across all sectors, industries, and regions, the electronics industry is demanding lighter, faster, smaller, more versatile, reliable, and cost-effective products. To meet these increasing demands from a variety of different consumers, more and more circuitry must be integrated to provide the necessary functionality. In most applications, there is also an increasing demand for reduced size, increased performance, and improved integrated circuit functionality. Summary of the Invention

[0004] In view of this, an embodiment of the present invention provides a semiconductor package.

[0005] According to a first aspect of an embodiment of the present invention, there is provided a semiconductor package, the semiconductor package comprising: a first substrate having a first surface, the first surface including a first signal transmission region and a second signal transmission region; a first semiconductor structure located on a first surface of the first substrate and electrically connected to the first signal transmission region; a second substrate located on the first substrate, the second substrate having a base and a first interconnection surface located on the base, the first interconnection surface of the second substrate facing opposite to the first surface of the first substrate, the first interconnection surface including a first interconnection region and a second interconnection region coupled to each other, the first interconnection region and the second signal transmission region being electrically connected; a filler layer sealing the first semiconductor structure, the second substrate, and a first surface of the first substrate, wherein the first interconnect region is not sealed by the filler layer, the second interconnect region is sealed by the filler layer, and a predetermined height exists between the top surface of the filler layer on the second interconnect region and the first interconnect region.

[0006] In some embodiments, the first surface of the first substrate further includes a third signal transmission region located between the first signal transmission region and the second signal transmission region, and the first semiconductor structure is located on the third signal transmission region.

[0007] In some embodiments, the first surface of the first substrate further includes a fourth signal transmission region, the second substrate is positioned on the fourth signal transmission region, and the second signal transmission region and the fourth signal transmission region are electrically connected.

[0008] In some embodiments, the second substrate is located on the first semiconductor structure, the first interconnection region is electrically connected to the second signal transmission region via the second interconnection region, the third signal transmission region includes a first sub-signal region and a second sub-signal region, the first sub-signal region is interconnected with the first signal transmission region and is located in an adjacent region of the first signal transmission region, and the second sub-signal region is interconnected with the second signal transmission region and is located in an adjacent region of the second signal transmission region.

[0009] In some embodiments, the fourth signal transmission region and the first interconnection region are electrically connected.

[0010] In some embodiments, the first signal transmission region and the second signal transmission region are located on opposite sides of the first substrate, the first semiconductor structure has a first connection terminal, the first connection terminal is located on the same side as the first signal transmission region, and the first connection terminal and the first signal transmission region are interconnected by a lead wire, and the second interconnection region is located on the same side as the second signal transmission region, and the second interconnection region and the second signal transmission region are interconnected by a lead wire.

[0011] In some embodiments, the first semiconductor structure and the first signal transmission region are interconnected in a direction perpendicular to the first substrate.

[0012] In some embodiments, the first semiconductor structure and the third signal transmission region are interconnected in a direction perpendicular to the first substrate, and the first signal transmission region is interconnected with the third signal transmission region.

[0013] In some embodiments, the second substrate further has a second interconnection surface located on another side of the base, the base having a channel connecting the first interconnection region and the second interconnection surface, and the first interconnection region is interconnected with the second signal transmission region in a direction perpendicular to the first substrate via the channel.

[0014] In some embodiments, the base of the second substrate comprises an electromagnetic shielding layer.

[0015] In some embodiments, an electromagnetic shielding structure is provided between the first sub-signal region and the second sub-signal region of the first substrate.

[0016] In some embodiments, the first substrate has a second surface facing the opposite side to the first surface, a circuit channel is present between the first surface and the second surface, and a plurality of first connection pads are provided on the second surface of the first substrate; The first interconnection region of the second substrate is provided with a plurality of second connection pads, and the area of ​​the second connection pads is equal to or greater than the area of ​​the first connection pads.

[0017] In some embodiments, the second interconnection region of the second substrate is provided with a plurality of third connection pads, and the area of ​​the third connection pads is smaller than the area of ​​the second connection pads.

[0018] In some embodiments, a plurality of fourth connection pads are provided in the first signal transmission region of the first substrate, and the area of ​​the fourth connection pads is equal to or smaller than the area of ​​the first connection pads.

[0019] In some embodiments, the number of the third connection pads is greater than the number of the second connection pads.

[0020] In some embodiments, the first substrate has a first thickness in a direction perpendicular to the first substrate, and the second substrate has a second thickness in a direction perpendicular to the second substrate, and the first thickness is smaller than the second thickness.

[0021] In some embodiments, the semiconductor package further comprises a second package having a contact surface, the second package interconnected with the first interconnect region via the contact surface.

[0022] In some embodiments, a first contact structure is provided on the contact surface of the second package, and the first contact structure has a first height protruding from the contact surface in a direction perpendicular to the contact surface, and the first height is greater than the predetermined height.

[0023] In some embodiments, the first connection pad of the first substrate is provided with a second contact structure protruding from the first substrate, the second contact structure having a second height protruding from the first substrate in a direction perpendicular to the first substrate, and the second height being less than or equal to the first height.

[0024] In some embodiments, the second package comprises a second semiconductor structure, the type of the second semiconductor structure being the same as or different from the type of the first semiconductor structure. [Effects of the Invention]

[0025] In an embodiment of the present invention, by disposing the second substrate, other semiconductor structures can be subsequently connected to the first semiconductor structure and the first substrate through the first interconnection region on the second substrate, thereby realizing interconnections between semiconductor structures of different types or specifications, thereby providing greater flexibility in combining different semiconductor structures. Meanwhile, since the first semiconductor structure and other semiconductor structures subsequently connected to the first semiconductor structure are individually packaged, testing and failure analysis are also facilitated. Furthermore, because there is a predetermined height between the first interconnection region of the second substrate and the upper surface of the fill layer, other semiconductor structures can be disposed within the region of the first interconnection region surrounded by the fill layer, thereby reducing the height and size of the entire structure. [Brief explanation of the drawings]

[0026] [Figure 1] 1 is a schematic diagram of a semiconductor package structure according to an embodiment of the present invention; [Figure 2] 2 is a schematic diagram of a structure of a first substrate according to an embodiment of the present invention; [Figure 3] 3 is a schematic diagram of a structure of a second substrate according to an embodiment of the present invention; [Figure 4] 1 is another example of a semiconductor package according to an embodiment of the present invention. [Figure 5] 1 is another example of a semiconductor package according to an embodiment of the present invention. [Figure 6] 1 is another example of a semiconductor package according to an embodiment of the present invention. [Figure 7] 2 is an exemplary flowchart of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 8a] 1A and 1B are schematic diagrams of a semiconductor package structure according to an embodiment of the present invention during manufacturing process; [Figure 8b] 1A and 1B are schematic diagrams of a semiconductor package structure according to an embodiment of the present invention during manufacturing process; [Figure 8c] 1A and 1B are schematic diagrams of a semiconductor package structure according to an embodiment of the present invention during manufacturing process; [Figure 8d] 1A and 1B are schematic diagrams of a semiconductor package structure according to an embodiment of the present invention during manufacturing process; [Figure 8e] 1A and 1B are schematic diagrams of a semiconductor package structure according to an embodiment of the present invention during manufacturing process; [Figure 8f] 1A and 1B are schematic diagrams of a semiconductor package structure according to an embodiment of the present invention during manufacturing process; [Figure 8g] 1A and 1B are schematic diagrams of a semiconductor package structure according to an embodiment of the present invention during manufacturing process; DETAILED DESCRIPTION OF THE INVENTION

[0027] In order to more clearly explain the embodiments of the present invention or the technical solutions in the prior art, the drawings required in the embodiments are briefly introduced above. Obviously, the above drawings are only some embodiments of the present invention, and those skilled in the art can obtain other drawings according to these drawings without creative efforts.

[0028]

[0023] Exemplary embodiments disclosed herein will now be described in more detail with reference to the drawings. While the drawings illustrate exemplary embodiments of the present invention, it should be understood that the present invention may be embodied in various forms and is not limited to the specific embodiments set forth herein. Rather, these embodiments are provided to provide a more complete understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0029] In the following description, numerous specific details are provided to provide a more complete understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without one or more of these details. In other instances, some technical features well known in the art are not described to avoid confusion with the present invention. That is, this specification does not describe all features of actual embodiments, and well-known functions and structures are not described in detail.

[0030] In the drawings, the sizes and relative sizes of layers, regions and elements may be exaggerated for clarity. Like numbers represent like elements throughout.

[0031] As will be understood, when an element or layer is "located on," "adjacent to," "connected to," or "bonded to" another element or layer, the element or layer may be directly located, adjacent, connected, or bonded to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is "located directly on," "directly adjacent to," "directly connected to," or "directly bonded to" another element or layer, there are no intervening elements or layers. As will be understood, although terms such as first, second, and third may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions are not limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of the present invention. When a second element, component, region, layer, or portion is discussed, it does not imply that the first element, component, region, layer, or portion is necessarily present in the present invention.

[0032] Spatial relationship terms such as "below," "below," "below," "below," "above," "above" and the like may be used herein for convenience of description to describe the relationship between one illustrated element or feature and another illustrated element or feature. As will be understood, the spatial relationship terms are intended to encompass different orientations of the device in use and operation, in addition to the orientation depicted in the figures. For example, if a device in the figures is inverted, an element or feature described as "located below" or "below" or "below" another element or feature would be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "below" can encompass both orientations of above and below. The device may be otherwise oriented (rotated 90 degrees or otherwise oriented), and the spatial description terms used herein should be interpreted accordingly.

[0033] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the present invention. As used herein, the singular forms "a," "one," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Furthermore, the terms "comprising" and / or "comprising," when used herein, mean the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations. The term "and / or," as used herein, includes any and all combinations of the associated items.

[0034] In order to make the present invention thoroughly understood, the following describes the technical solutions of the present invention by taking detailed steps and detailed structures as examples. The following describes the preferred embodiments of the present invention in detail, but the present invention can have other embodiments in addition to these detailed descriptions.

[0035] Current semiconductor packaging technology typically employs discrete or multi-chip packaging (UMCP: UFS Multi Chip Package). The discrete approach involves distributing DRAM chips and NAND chips in separate packages. The multi-chip package involves packaging memory chips and control chips in the same package structure. Discrete packaging requires a relatively large area on the PCB, while multi-chip packaging makes testing and fault analysis more difficult, controllers struggle to dissipate heat, and chips with different capacities cannot be flexibly combined.

[0036] Based on this, an embodiment of the present invention provides a semiconductor package. Figure 1 is a schematic diagram of the structure of a semiconductor package according to an embodiment of the present invention.

[0037] Referring to FIG. 1, the semiconductor package includes: a first substrate 10 having a first surface 101, the first surface 101 including a first signal transmission region 11 and a second signal transmission region 12; a first semiconductor structure 20 located on the first surface 101 of the first substrate 10 and electrically connected to the first signal transmission region 11; a second substrate 30 located on the first substrate 10, the second substrate 30 including a base 33 and a first interconnection surface 301 located on the base 33, the first interconnection surface 301 of the second substrate 30 facing the opposite side to the first surface 101 of the first substrate 10, the first interconnection surface 301 including a first interconnection region 31 and a second interconnection region 32 that are coupled to each other, and the first interconnection region 31 and the second signal transmission region 12 being electrically connected; and a filling layer 40 that seals the first semiconductor structure 20, the second substrate 30, and the first surface 101 of the first substrate 10, wherein the first interconnection region 31 is not sealed by the filling layer 40, the second interconnection region 32 is sealed by the filling layer 40, and a predetermined height h exists between the upper surface of the filling layer 40 above the second interconnection region 32 and the first interconnection region 31.

[0038] By disposing the second substrate, other semiconductor structures can be subsequently connected to the first semiconductor structure and the first substrate through the first interconnection region on the second substrate, thereby realizing interconnections between semiconductor structures of different types or specifications, thereby providing greater flexibility in combining different semiconductor structures. Meanwhile, since the first semiconductor structure and other semiconductor structures subsequently connected to the first semiconductor structure are individually packaged, testing and failure analysis are also facilitated. Furthermore, because there is a predetermined height between the first interconnection region of the second substrate and the upper surface of the fill layer, other semiconductor structures can be disposed within the region of the first interconnection region surrounded by the fill layer, thereby reducing the height and size of the entire structure.

[0039] FIG. 2 is a schematic diagram of a structure of a first substrate according to an embodiment of the present invention.

[0040] In some embodiments, the first substrate 10 may be a printed circuit board (PCB) or a redistribution board.

[0041] As shown in FIG. 2, the first substrate 10 includes a first base 15, and a first upper insulating dielectric layer 16 and a first lower insulating dielectric layer 17 located on the upper and lower surfaces of the first base 15, respectively.

[0042] The first base 15 may be a silicon base, a germanium base, a silicon germanium base, a silicon carbide base, a silicon on insulator (SOI) base, or a germanium on insulator (GOI) base, or may be a base containing other elemental semiconductors or compound semiconductors such as a glass base or a III-V compound base (e.g., gallium nitride base or gallium arsenide base), or may be a stacked structure such as Si / SiGe, or may be another epitaxial structure such as silicon germanium on insulator (SGOI).

[0043] The first upper insulating dielectric layer 16 and the first lower insulating dielectric layer 17 may be solder resist layers, for example, the material of the first upper insulating dielectric layer 16 and the first lower insulating dielectric layer 17 may be green paint.

[0044] In one embodiment, the first substrate 10 has a second surface 102 facing opposite to the first surface 101, a circuit channel 151 exists between the first surface 101 and the second surface 102, and a plurality of first connection pads 171 are provided on the second surface 102 of the first substrate 10.

[0045] A plurality of sixth connection pads 161 are provided on the first surface of the first substrate 10 , and the circuit channel 151 connects the sixth connection pads 161 and the first connection pads 171 .

[0046] In one embodiment, the first signal transmission region 11 of the first substrate 10 is provided with a plurality of fourth connection pads 111, and the area of ​​the fourth connection pads 111 is equal to or smaller than the area of ​​the first connection pads 171. In this embodiment, the area of ​​the fourth connection pads 111 is designed to be smaller than the area of ​​the first connection pads 171, thereby improving the signal transmission efficiency between the first semiconductor structure 20 and the first signal transmission region 11 of the first substrate 10 and reducing the chip area; further, the area of ​​the first connection pads 171 is designed to be larger than the fourth connection pads 111, thereby improving the electrical conductivity and thermal conductivity between the first semiconductor structure 20 and the first substrate 10 and improving the electrical connection passage between the first signal transmission region and the second surface of the first substrate 10.

[0047] The first connection pads 171 of the first substrate 10 are provided with second contact structures 18 that protrude from the first substrate 10 .

[0048] The second contact structure 18 can electrically connect the semiconductor package to an external device and can receive at least one of control signals, power signals and ground signals from the external device to operate the first semiconductor structure, or can receive data signals to be stored in the first semiconductor structure from the external device or provide data in the first semiconductor structure to the external device.

[0049] The second contact structures 18 include a conductive material. In an embodiment of the present invention, the second contact structures 18 are solder balls. It should be understood that the shape of the second contact structures according to an embodiment of the present invention is merely one possible specific embodiment of the present invention and does not constitute a limitation on the present invention, and the second contact structures may have other shapes. The number, spacing, and positions of the second contact structures are not limited to any particular arrangement and can be varied.

[0050] The first surface 101 of the first substrate 10 includes a first signal transmission region 11 and a second signal transmission region 12. The first signal transmission region 11 and the first semiconductor structure 20 are electrically connected, and the second signal transmission region 12 and the second substrate 30 are electrically connected.

[0051] In one embodiment, the first signal transmission region 11 and the second signal transmission region 12 are not interconnected.

[0052] In one embodiment, the first surface 101 of the first substrate 10 further includes a third signal transmission region 13 located between the first signal transmission region 11 and the second signal transmission region 12, and the first semiconductor structure 20 is located on the third signal transmission region 13. In this embodiment, by arranging the first semiconductor structure 20 directly above the third signal transmission region 13, the first signal transmission region 11 is located outside the first semiconductor structure 20, thereby improving the connection stability between the first signal transmission region 11 and the first semiconductor structure 20.

[0053] In one embodiment, the area of ​​the distribution area of ​​the first signal transmission area 11 on the first substrate 10 is made less than the area of ​​the distribution area of ​​the third signal transmission area 13 on the first substrate 10, thereby reducing the lateral size of the first package and improving the degree of integration.

[0054] The first semiconductor structure 20 includes a plurality of first semiconductor chips 21 stacked in a direction perpendicular to the first substrate 10. In this embodiment, stacking the first semiconductor chips from bottom to top can reduce the horizontal area of ​​the semiconductor package. The first semiconductor chips may be DRAM chips.

[0055] In one embodiment, as shown in Figures 1 and 2, the second substrate 30 is located on the first semiconductor structure 20, the first interconnection region 31 is electrically connected to the second signal transmission region 12 via the second interconnection region 32, the third signal transmission region 13 includes a first sub-signal region 131 and a second sub-signal region 132, the first sub-signal region 131 is interconnected with the first signal transmission region 11 and is located in an adjacent region of the first signal transmission region 11, and the second sub-signal region 132 is interconnected with the second signal transmission region 12 and is located in an adjacent region of the second signal transmission region 12.

[0056] In one embodiment, the first sub-signal region 131 and the second sub-signal region 132 are not interconnected.

[0057] In one embodiment, an electromagnetic shielding structure (not shown) is provided between the first sub-signal region 131 and the second sub-signal region 132 of the first substrate 10.

[0058] The first sub-signal region 131 is interconnected with the first signal transmission region 11, and the second sub-signal region 132 is interconnected with the second signal transmission region. Since the first signal transmission region is interconnected with the first semiconductor structure, the second signal transmission region is indirectly interconnected with the second package by being interconnected with the second substrate. Therefore, by arranging an electromagnetic shielding structure between the first sub-signal region and the second sub-signal region, signal interference between the first semiconductor structure and the second package can be prevented.

[0059] FIG. 3 is a schematic diagram of a structure of a second substrate according to an embodiment of the present invention.

[0060] As shown in FIG. 3, the second substrate 30 includes a base 33, an upper insulating dielectric layer 34, and a lower insulating dielectric layer 35 located on the upper and lower surfaces of the base 33, respectively.

[0061] The base 33 may be a silicon base, a germanium base, a silicon germanium base, a silicon carbide base, a silicon on insulator (SOI) base, a germanium on insulator (GOI) base, or the like, or may be a base containing other elemental semiconductors or compound semiconductors such as a glass base or a III-V compound base (e.g., gallium nitride base or gallium arsenide base), or may be a stacked structure such as Si / SiGe, or may be other epitaxial structures such as silicon germanium on insulator (SGOI).

[0062] The upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 may be solder resist layers, and for example, the material of the upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 may be green paint.

[0063] The first interconnection region 31 of the second substrate 30 is provided with a plurality of second connection pads 311 , and the area of ​​the second connection pads 311 is equal to or greater than the area of ​​the first connection pads 171 .

[0064] By setting the area of ​​the second connection pad 311 relatively large, the contact area when the second package and the second connection pad 311 come into contact can be increased; if the contact area is relatively small, it becomes difficult to disassemble after welding; therefore, by increasing the contact area, subsequent disassembly and reassembly becomes easier.

[0065] In one embodiment, the second interconnection region 32 of the second substrate 30 is provided with a plurality of third connection pads 321 , and the area of ​​the third connection pads 321 is smaller than the area of ​​the second connection pads 311 .

[0066] The number of the third connection pads 321 is greater than the number of the second connection pads 311 .

[0067] The layout design of the second connection pads is relatively fixed because they need to be subsequently matched and interconnected with the second package. However, the layout design of the third connection pads is more flexible because they are responsible for interconnecting the second package and the first substrate. By increasing the number of third connection pads and designing their area to be smaller, it is possible to improve signal transmission efficiency and increase the integration density of the first package.

[0068] In one embodiment, the base 33 of the second substrate 30 includes an electromagnetic shielding layer (not shown). By disposing the electromagnetic shielding layer on the base of the second substrate, it is possible to prevent information interference between the second package and the first semiconductor structure from affecting the operation of the device.

[0069] FIG. 4 is a schematic diagram of a structure of a semiconductor package according to another embodiment of the present invention.

[0070] As shown in FIG. 4, in this embodiment, the second substrate 30 is not located above the first semiconductor structure 20 but is located directly on the first substrate 10 .

[0071] In one embodiment, the first surface 101 of the first substrate 10 further includes a fourth signal transmission region 14, the second substrate 30 is located on the fourth signal transmission region 14, and the second signal transmission region 12 and the fourth signal transmission region 14 are electrically connected.

[0072] In one embodiment, the fourth signal transmission region 14 and the first interconnection region 31 are electrically connected.

[0073] In one embodiment, the fourth signal transmission region 14 and the first signal transmission region 11 are not interconnected.

[0074] Specifically, the first interconnection region 31 is electrically connected to the second signal transmission region 12 via the second interconnection region 32, and the second signal transmission region 12 is electrically connected to the fourth signal transmission region 14, so that the fourth signal transmission region 14 is electrically connected to the first interconnection region via the second signal transmission region 12 and the second interconnection region 32.

[0075] In the embodiment of the present invention, the electrical connection method between the first semiconductor structure 20 and the second substrate 30 and the first substrate 10 includes a wire bonding method and a through silicon via (TSV) interconnection method.

[0076] Referring to FIG. 1, the first semiconductor structure 20 and the second substrate 30 are electrically connected to the first substrate 10 by wire bonding.

[0077] The first signal transmission region 11 and the second signal transmission region 12 are located on opposite sides of the first substrate 10, the first semiconductor structure 20 has a first connection terminal 201, the first connection terminal 201 is located on the same side as the first signal transmission region 11, and the first connection terminal 201 and the first signal transmission region 11 are interconnected by a lead wire 50, and the second interconnection region 32 is located on the same side as the second signal transmission region 12, and the second interconnection region 32 and the second signal transmission region 12 are interconnected by a lead wire 50.

[0078] The method of electrically connecting the first semiconductor structure 20 and the first substrate 10 by wire bonding includes an overhang method and a film on wire (FOW) method.

[0079] 1, wire bonding is performed using an overhang method. Two adjacent first semiconductor chips 21 are connected by an adhesive film 60, which does not cover the first connection terminals 201 and lead wires 50 of the underlying first semiconductor chip 21, and is positioned offset from the underlying first semiconductor chip 21.

[0080] In some other embodiments, wire bonding is performed using a film-on-wire method (not shown), where a plurality of the first semiconductor chips are aligned along a direction perpendicular to the first substrate, and an adhesive film between two adjacent first semiconductor chips covers the first connection terminals and lead wires of the underlying first semiconductor chip.

[0081] In another embodiment, referring to FIGS. 5 and 6, the first semiconductor structure 20 and the first substrate 10 are electrically connected by a through silicon via (TSV) interconnection scheme.

[0082] 5, the first semiconductor chip 21 includes first chip connection pads 212 and second chip connection pads 213 located on the top and bottom surfaces, respectively, and first channels 211 that penetrate the first semiconductor chip 21 and connect the first chip connection pads 212 and the second chip connection pads 213. The first channels 211 include through-silicon electrodes.

[0083] Two adjacent first semiconductor chips 21, and the first semiconductor structure 20 and the first substrate 10 are electrically connected via the first chip connection pads 212, the second chip connection pads 213, the first channels 211 and the first solder balls 214.

[0084] The first semiconductor structure 20 and the first signal transmission region 11 are interconnected in a direction perpendicular to the first substrate 10 .

[0085] The first semiconductor structure 20 and the third signal transmission region 13 are interconnected in a direction perpendicular to the first substrate 10 , and the first signal transmission region 11 is interconnected with the third signal transmission region 13 .

[0086] In this embodiment, the first semiconductor structure and the first substrate are electrically connected by a through-silicon via interconnection method, so wire bonding is not required, and therefore the first signal transmission region and the third signal transmission region can be integrated into one region.

[0087] As shown in FIG. 6, the second substrate 30 further includes a second interconnection surface 302 located on the other side of the base 33, and the base 33 has a channel 36 connecting the first interconnection region 31 and the second interconnection surface 302, and the first interconnection region 31 is interconnected with the second signal transmission region 12 in a direction perpendicular to the first substrate 10 via the channel 36.

[0088] The second substrate 30 includes second connection pads 311 located in the first interconnection region 31, fifth connection pads 37 located on the second interconnection surface 302 of the second substrate 30, and channels 36 that pass through the base 33 and connect the second connection pads 311 and the fifth connection pads 37. The channels 36 include through-silicon vias. Second solder balls 38 are further provided between the second substrate 30 and the first substrate 10.

[0089] The second substrate 30 and the first substrate 10 are electrically connected via the second connection pads 311 , the channels 36 , the fifth connection pads 37 and the second solder balls 38 .

[0090] In this embodiment, the second substrate and the first substrate are electrically connected by a silicon through-electrode interconnection method, so wire bonding is not required, and therefore the second signal transmission region and the fourth signal transmission region can be integrated into one region.

[0091] In one embodiment, the first substrate 10 has a first thickness in a direction perpendicular to the first substrate 10, and the second substrate 30 has a second thickness in a direction perpendicular to the second substrate 30, the first thickness being smaller than the second thickness. With this configuration, when the filling layer seals the first substrate and the second substrate, warping of the second substrate 30 due to the size difference between the first substrate 10 and the second substrate 30 can be prevented from affecting the sealing effect.

[0092] In one embodiment, the semiconductor package further includes a second package 70, the second package 70 having a contact surface 701, and the second package 70 is interconnected with the first interconnection region 31 via the contact surface 701.

[0093] A first contact structure 71 is provided on the contact surface 701 of the second package 70, and the first contact structure 71 has a first height H protruding from the contact surface 701 in a direction perpendicular to the contact surface 701, and the first height H is greater than the predetermined height h.

[0094] In an embodiment of the present invention, the first height is set to be greater than a predetermined height, so that the second package can be closely connected to the second substrate, and after the second package is connected to the second substrate, a gap can exist between the second package and the filling layer, thereby improving the heat dissipation efficiency of the controller and reducing the impact of heat dissipation on the chip.

[0095] 2, in one embodiment, the first connection pad 171 of the first substrate 10 is provided with a second contact structure 18 protruding from the first substrate 10, and the second contact structure 18 has a second height protruding from the first substrate 10 in a direction perpendicular to the first substrate 10, the second height being equal to or less than the first height. With this configuration, a more stable bonding effect can be achieved between the second package supported by the first contact structure 71 and the first package.

[0096] In one embodiment, the second package 70 comprises a second semiconductor structure (not shown), the type of which may be the same as or different from the type of the first semiconductor structure 20 .

[0097] For example, the second semiconductor structure may be a Universal Flash Storage (UFS) chip.

[0098] In the semiconductor package according to the present invention, the second semiconductor structure in the second package 70 is interconnected with the second signal transmission region on the first substrate 10 via the second substrate 30, and the first semiconductor structure 20 is interconnected with the first signal transmission region on the first substrate 10. In this way, by distributing the transmission paths of the first semiconductor structure and the second semiconductor structure to different regions of the first substrate, mutual interference between the first semiconductor structure and the second semiconductor structure can be prevented and the stability of signal transmission can be improved.

[0099] A semiconductor package according to an embodiment of the present invention can be applied to a multi-chip package (UMCP: UFS Multi Chip Package) having a package on package (PoP) structure.

[0100] An embodiment of the present invention further provides a method for manufacturing a semiconductor package, details of which are shown in Figure 7. As shown in the figure, the method includes the following steps:

[0101] In step 701, a first substrate is provided, the first substrate having a first surface, the first surface including a first signal transmission region and a second signal transmission region.

[0102] In step 702, a first semiconductor structure is formed on a first surface of the first substrate, and the first semiconductor structure and the first signal transmission region are electrically connected.

[0103] In step 703, a second substrate is formed on the first substrate, the second substrate including a base and a first interconnection surface located on the base, the first interconnection surface of the second substrate facing opposite to the first surface of the first substrate, the first interconnection surface including a first interconnection region and a second interconnection region coupled to each other, and the first interconnection region and the second signal transmission region being electrically connected.

[0104] In step 704, a fill layer is formed, the fill layer sealing the first semiconductor structure, the second substrate, and the first surface of the first substrate, wherein the first interconnect region is not sealed by the fill layer, the second interconnect region is sealed by the fill layer, and a predetermined height exists between the top surface of the fill layer above the second interconnect region and the first interconnect region.

[0105] Hereinafter, a method for manufacturing a semiconductor package according to an embodiment of the present invention will be described in more detail with reference to a specific embodiment.

[0106] 8a to 8g are schematic diagrams of the structure of a semiconductor package according to an embodiment of the present invention during the manufacturing process.

[0107] First, referring to FIG. 8a, step 701 is performed to provide a first substrate 10, the first substrate 10 having a first surface 101, and the first surface 101 including a first signal transmission region 11 and a second signal transmission region 12.

[0108] The first substrate 10 includes a first base 15, and a first upper insulating dielectric layer 16 and a first lower insulating dielectric layer 17 located on the upper and lower surfaces of the first base 15, respectively.

[0109] The first base 15 may be a silicon base, a germanium base, a silicon germanium base, a silicon carbide base, a silicon on insulator (SOI) base, or a germanium on insulator (GOI) base, or may be a base containing other elemental semiconductors or compound semiconductors such as a glass base or a III-V compound base (e.g., gallium nitride base or gallium arsenide base), or may be a stacked structure such as Si / SiGe, or may be another epitaxial structure such as silicon germanium on insulator (SGOI).

[0110] The first upper insulating dielectric layer 16 and the first lower insulating dielectric layer 17 may be solder resist layers, for example, the material of the first upper insulating dielectric layer 16 and the first lower insulating dielectric layer 17 may be green paint.

[0111] The first substrate 10 has a second surface 102 facing the opposite side to the first surface 101, a circuit channel 151 exists between the first surface 101 and the second surface 102, and a plurality of first connection pads 171 are provided on the second surface 102 of the first substrate 10.

[0112] A plurality of sixth connection pads 161 are provided on the first surface of the first substrate 10 , and the circuit channel 151 connects the sixth connection pads 161 and the first connection pads 171 .

[0113] In one embodiment, the first signal transmission region 11 of the first substrate 10 is provided with a plurality of fourth connection pads 111, and the area of ​​the fourth connection pads 111 is equal to or smaller than the area of ​​the first connection pads 171.

[0114] The first surface 101 of the first substrate 10 includes a first signal transmission region 11 and a second signal transmission region 12. The first signal transmission region 11 is electrically connected to a first semiconductor structure 20 to be formed subsequently, and the second signal transmission region 12 is electrically connected to the second substrate 30 to be formed subsequently.

[0115] In one embodiment, the first surface 101 of the first substrate 10 further includes a third signal transmission region 13 located between the first signal transmission region 11 and the second signal transmission region 12, and the subsequently formed first semiconductor structure 20 is located on the third signal transmission region 13.

[0116] In some other embodiments, for example, as shown in FIG. 4, the first substrate 10 further includes a fourth signal transmission region 14, and the subsequently formed second substrate 30 is located on the fourth signal transmission region 14, and the second signal transmission region 12 and the fourth signal transmission region 14 are electrically connected.

[0117] Next, referring to FIG. 8b, step 702 is performed to form a first semiconductor structure 20 on the first surface 101 of the first substrate 10, and the first semiconductor structure 20 and the first signal transmission region 11 are electrically connected.

[0118] The first semiconductor structure 20 includes a plurality of first semiconductor chips 21 stacked in sequence along a direction perpendicular to the first substrate 10 .

[0119] The two adjacent first semiconductor chips 21 are connected by an adhesive film 60 , and the first semiconductor structure 20 and the first substrate 10 are also connected by an adhesive film 60 .

[0120] Next, referring to Figures 8c and 8d, step 703 is performed to form a second substrate 30 on the first substrate 10, the second substrate 30 including a base 33 and a first interconnection surface 301 located on the base 33, the first interconnection surface 301 of the second substrate 30 facing the opposite side to the first surface 101 of the first substrate 10, the first interconnection surface 301 having a first interconnection region 31 and a second interconnection region 32 connected to each other, and the first interconnection region 31 and the second signal transmission region 12 being electrically connected.

[0121] Specifically, first, referring to FIG. 8c, a carrier tape 2 is attached to a ring 1, then an adhesive film 60 is attached to the carrier tape 2, and then a second substrate is attached to the adhesive film 60, where the second substrate is in the form of a strip, and the second substrate is cut to form individual cells as shown in FIG. 8c.

[0122] Next, referring to FIG. 8 d , a second substrate 30 is formed on the first semiconductor structure 20 .

[0123] Specifically, an adhesive layer 60 is formed on the first semiconductor structure 20, and then a second substrate formed in FIG. 8c is attached to the first semiconductor structure 20.

[0124] In some other embodiments, instead of forming the second substrate 30 on the first semiconductor structure 20, the second substrate 30 is formed directly on the first substrate 10, for example as shown in FIG.

[0125] Referring to FIG. 3, the second substrate 30 includes a base 33, and an upper insulating dielectric layer 34 and a lower insulating dielectric layer 35 located on the upper and lower surfaces of the base 33, respectively.

[0126] The base 33 may be a silicon base, a germanium base, a silicon germanium base, a silicon carbide base, a silicon on insulator (SOI) base, a germanium on insulator (GOI) base, or the like, or may be a base containing other elemental semiconductors or compound semiconductors such as a glass base or a III-V compound base (e.g., gallium nitride base or gallium arsenide base), or may be a stacked structure such as Si / SiGe, or may be other epitaxial structures such as silicon germanium on insulator (SGOI).

[0127] The upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 may be solder resist layers, and for example, the material of the upper insulating dielectric layer 34 and the lower insulating dielectric layer 35 may be green paint.

[0128] The first interconnection region 31 of the second substrate 30 is provided with a plurality of second connection pads 311 , and the area of ​​the second connection pads 311 is equal to or greater than the area of ​​the first connection pads 171 .

[0129] By setting the area of ​​the second connection pad 311 relatively large, the contact area when the second package and the second connection pad 311 come into contact can be increased; if the contact area is relatively small, it becomes difficult to disassemble after welding; therefore, by increasing the contact area, subsequent disassembly and reassembly becomes easier.

[0130] In one embodiment, the second interconnection region 32 of the second substrate 30 is provided with a plurality of third connection pads 321 , and the area of ​​the third connection pads 321 is smaller than the area of ​​the second connection pads 311 .

[0131] The number of the third connection pads 321 is greater than the number of the second connection pads 311 .

[0132] The layout design of the second connection pads is relatively fixed because they need to be subsequently matched and interconnected with the second package. However, the layout design of the third connection pads is more flexible because they are responsible for interconnecting the second package and the first substrate. By increasing the number of third connection pads and designing their area to be smaller, the signal transmission efficiency can be improved.

[0133] In one embodiment, the base 33 of the second substrate 30 includes an electromagnetic shielding layer (not shown). By disposing the electromagnetic shielding layer on the base of the second substrate, it is possible to prevent information interference between the second package and the first semiconductor structure from affecting the operation of the device.

[0134] Still referring to FIG. 8d, after forming the second substrate 30, the first semiconductor structure 20 and the second substrate 30 are electrically connected to the first substrate 10 by wire bonding.

[0135] The first signal transmission region 11 and the second signal transmission region 12 are located on opposite sides of the first substrate 10, the first semiconductor structure 20 has a first connection terminal 201, the first connection terminal 201 is located on the same side as the first signal transmission region 11, and the first connection terminal 201 and the first signal transmission region 11 are interconnected by a lead wire 50, and the second interconnection region 32 is located on the same side as the second signal transmission region 12, and the second interconnection region 32 and the second signal transmission region 12 are interconnected by a lead wire 50.

[0136] In some other embodiments, the first semiconductor structure 20 and the second substrate 30 are electrically connected to the first substrate 10 by a through silicon via (TSV) interconnection scheme.

[0137] 5, the first semiconductor chip 21 includes first chip connection pads 212 and second chip connection pads 213 located on the top and bottom surfaces, respectively, and first channels 211 that penetrate the first semiconductor chip 21 and connect the first chip connection pads 212 and the second chip connection pads 213. The first channels 211 include through-silicon electrodes.

[0138] Two adjacent first semiconductor chips 21, and the first semiconductor structure 20 and the first substrate 10 are electrically connected via the first chip connection pads 212, the second chip connection pads 213, the first channels 211 and the first solder balls 214.

[0139] As shown in FIG. 6, the second substrate 30 further includes a second interconnection surface 302 located on the other side of the base 33, and the base 33 has a channel 36 connecting the first interconnection region 31 and the second interconnection surface 302, and the first interconnection region 31 is interconnected with the second signal transmission region 12 in a direction perpendicular to the first substrate 10 via the channel 36.

[0140] The second substrate 30 includes second connection pads 311 located in the first interconnection region 31, fifth connection pads 37 located on the second interconnection surface 302 of the second substrate 30, and channels 36 that pass through the base 33 and connect the second connection pads 311 and the fifth connection pads 37. The channels 36 include through-silicon vias. Second solder balls 38 are further provided between the second substrate 30 and the first substrate 10.

[0141] The second substrate 30 and the first substrate 10 are electrically connected via the second connection pads 311 , the channels 36 , the fifth connection pads 37 and the second solder balls 38 .

[0142] Next, referring to Figures 8e and 8f, step 704 is performed to form a filling layer 40, which seals the first semiconductor structure 20, the second substrate 30 and the first surface 101 of the first substrate 10, wherein the first interconnect region 31 is not sealed by the filling layer 40, the second interconnect region 32 is sealed by the filling layer 40, and there is a predetermined height h between the upper surface of the filling layer 40 on the second interconnect region 32 and the first interconnect region 31.

[0143] Specifically, referring to Figure 8e, a first package mold 91 is formed, and the first package mold 91 has a first portion 911, a second portion 912 located on both sides of the first portion 911, and a third portion 913 connecting the first portion 911 and the second portion 912, wherein the surface of the second portion 912 is higher than the surface of the first portion 911, and both the surface of the second portion 912 and the surface of the first portion 911 are parallel to the surface of the substrate 10, and the first portion 911 is located in the first interconnection region 31 of the second substrate 30.

[0144] The method further includes forming a second package mold 92 , the second package mold 92 being located below the first substrate 10 and parallel to a surface of the first substrate 10 .

[0145] Next, referring to FIG. 8f, a filling layer 40 is formed using the first package mold 91 and the second package mold 92 as a mask, and after forming the filling layer 40, the method further includes removing the first package mold 91 and the second package mold 92 to expose the first interconnect region 31 covered by the first portion 911.

[0146] Continuing to refer to FIG. 8f, after forming the filling layer 40, a second contact structure 18 protruding from the first substrate 10 is formed on the first connection pad 171 of the first substrate 10, and the second contact structure 18 comprises a conductive material.

[0147] Next, referring to FIG. 8g, a second package 70 is formed, the second package 70 having a contact surface 701, and the second package 70 is interconnected with the first interconnection region 31 via the contact surface 701.

[0148] A first contact structure 71 is provided on the contact surface 701 of the second package 70, and the first contact structure 71 has a first height H protruding from the contact surface 701 in a direction perpendicular to the contact surface 701, and the first height H is greater than the predetermined height h.

[0149] In one embodiment, the second contact structure 18 on the first substrate 10 has a second height protruding from the first substrate 10 in a direction perpendicular to the first substrate 10, the second height being less than or equal to the first height.

[0150] In one embodiment, the second package 70 comprises a second semiconductor structure (not shown), the type of which may be the same as or different from the type of the first semiconductor structure 20 .

[0151] The above are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should all be included in the protection scope of the present invention. [Industrial Applicability]

[0152] In an embodiment of the present invention, by disposing the second substrate, other semiconductor structures can be subsequently connected to the first semiconductor structure and the first substrate through the first interconnection region on the second substrate, thereby realizing interconnections between semiconductor structures of different types or specifications, thereby providing greater flexibility in combining different semiconductor structures. Meanwhile, since the first semiconductor structure and other semiconductor structures subsequently connected to the first semiconductor structure are individually packaged, testing and failure analysis are also facilitated. Furthermore, because there is a predetermined height between the first interconnection region of the second substrate and the upper surface of the fill layer, other semiconductor structures can be disposed within the region of the first interconnection region surrounded by the fill layer, thereby reducing the height and size of the entire structure. [Explanation of symbols]

[0153] 1 ring 2 Carrier tape 10 First board 101 Page 1 102 Side 2 11 First signal transmission area 12 Second signal transmission area 13 Third signal transmission area 131 First Sub-Signal Area 132 Second Sub-Signal Area 14 Fourth signal transmission area 15 First Base 16 First upper insulating dielectric layer 17 First lower insulating dielectric layer 18 Second contact structure 111 4th connection pad 151 circuit channels 161 6th connection pad 171 First connection pad 20 First semiconductor structure 21 First semiconductor chip 201 First connection terminal 211 Channel 1 212 First chip connection pad 213 Second chip connection pad 214 First solder ball 30 Second board 31 First Interconnection Area 32 Second Interconnection Area 33 Base 34 Upper insulating dielectric layer 35 Lower insulating dielectric layer 36 channels 37 5th connection pad 38 Second solder ball 301 First interconnection surface 302 Second Interconnection Surface 311 Second connection pad 321 Third connection pad 40 Filled bed 50 lead wires 60 adhesive film 70 2nd Package 71 First contact structure 701 Contact surface 91 First package mold 911 Part 1 912 Part 2 913 Part 3 92 Second package mold

Claims

1. A semiconductor package comprising: a first substrate having a first surface and a second surface facing opposite the first surface, a circuit channel existing between the first surface and the second surface, the first surface including a first signal transmission region and a second signal transmission region that are not interconnected, and a plurality of first connection pads provided on the second surface of the first substrate; a first semiconductor structure located on the first surface of the first substrate and electrically connected to the first signal transmission region; a second substrate located on the first substrate, the second substrate having a base and a first interconnection surface located on the base, the first interconnection surface of the second substrate facing opposite to the first surface of the first substrate, the first interconnection surface including a first interconnection region and a second interconnection region coupled to each other, the first interconnection region and the second signal transmission region being electrically connected; a filler layer sealing the first semiconductor structure, the second substrate, and a first surface of the first substrate, wherein the first interconnect region is not sealed by the filler layer, the second interconnect region is sealed by the filler layer, and a predetermined height exists between an upper surface of the filler layer on the second interconnect region and the first interconnect region; a plurality of second connection pads are provided in the first interconnection region of the second substrate, the area of ​​the second connection pads being equal to or greater than the area of ​​the first connection pads; a plurality of third connection pads are provided in the second interconnection region of the second substrate, the area of ​​the third connection pads being smaller than the area of ​​the second connection pads, and the number of the third connection pads is greater than the number of the second connection pads.

2. The semiconductor package further includes a second package having a contact surface, the second package interconnected with the first interconnect region through the contact surface, and a gap existing between the second package and the fill layer. The semiconductor package of claim 1 .

3. a first contact structure is provided on the contact surface of the second package, the first contact structure having a first height protruding from the contact surface in a direction perpendicular to the contact surface, the first height being greater than the predetermined height; The semiconductor package according to claim 2 .

4. the first signal transmission region and the second signal transmission region are located on opposite sides of the first substrate, the first semiconductor structure has a first connection terminal, the first connection terminal is located on the same side as the first signal transmission region, interconnection between the first semiconductor structure and the first substrate by a lead wire is only interconnection between the first connection terminal and the first signal transmission region by a lead wire, the second interconnection region is located on the same side as the second signal transmission region, and interconnection between the second substrate and the first substrate by a lead wire is only interconnection between the second interconnection region and the second signal transmission region by a lead wire. The semiconductor package according to any one of claims 1 to 3.

5. the first surface of the first substrate further includes a third signal transmission region located between the first signal transmission region and the second signal transmission region, and the first semiconductor structure is located on the third signal transmission region; The semiconductor package according to any one of claims 1 to 3.

6. the second substrate is located directly on the first substrate and not on the first semiconductor structure, the first surface of the first substrate further includes a fourth signal transmission region, the second substrate is located on the fourth signal transmission region, and the second signal transmission region and the fourth signal transmission region are electrically connected; The semiconductor package according to claim 5 .

7. the second substrate further includes a second interconnection surface located on the other side of the base, the base having a channel connecting the first interconnection region and the second interconnection surface, and the first interconnection region is interconnected with the second signal transmission region via the channel in a direction perpendicular to the first substrate; The semiconductor package according to claim 6 .

8. the second substrate is located on the first semiconductor structure, the first interconnection region is electrically connected to the second signal transmission region through the second interconnection region, the third signal transmission region includes a first sub-signal region and a second sub-signal region, the first sub-signal region is interconnected with the first signal transmission region and is located in an adjacent region of the first signal transmission region, the second sub-signal region is interconnected with the second signal transmission region and is located in an adjacent region of the second signal transmission region; an electromagnetic shielding structure is provided between the first sub-signal region and the second sub-signal region of the first substrate; The semiconductor package according to claim 5 .

9. an area of ​​a distribution region of the first signal transmission region on the first substrate is smaller than an area of ​​a distribution region of the third signal transmission region on the first substrate; The semiconductor package according to claim 5 .

10. the base of the second substrate has an electromagnetic shielding layer; The semiconductor package according to any one of claims 1 to 3.

11. the first semiconductor structure and the first signal transmission region are interconnected in a direction perpendicular to the first substrate; the first semiconductor structure and the third signal transmission region are interconnected in a direction perpendicular to the first substrate, and the first signal transmission region is interconnected with the third signal transmission region; The semiconductor package according to claim 5 .

12. a plurality of fourth connection pads are provided in the first signal transmission region of the first substrate, and the area of ​​the fourth connection pads is equal to or smaller than the area of ​​the first connection pads; The semiconductor package according to any one of claims 1 to 3.

13. the first substrate has a first thickness in a direction perpendicular to the first substrate, and the second substrate has a second thickness in a direction perpendicular to the second substrate, the first thickness being smaller than the second thickness; The semiconductor package according to any one of claims 1 to 3.

14. a second contact structure protruding from the first substrate is provided on the first connection pad of the first substrate, the second contact structure having a second height protruding from the first substrate in a direction perpendicular to the first substrate, the second height being equal to or less than the first height; The semiconductor package according to claim 3 .

15. A semiconductor package comprising: a first substrate having a first surface, the first surface including a first signal transmission region, a second signal transmission region, and a third signal transmission region located between the first signal transmission region and the second signal transmission region, the first signal transmission region and the second signal transmission region not being interconnected; a first semiconductor structure located on the third signal transmission region and electrically connected to the first signal transmission region; a second substrate located directly on the first substrate and not located above the first semiconductor structure, the second substrate having a base and a first interconnection surface located at the base, the first interconnection surface of the second substrate facing opposite to the first surface of the first substrate, the first interconnection surface including a first interconnection region and a second interconnection region coupled to each other, the first interconnection region and the second signal transmission region being electrically connected; a filler layer sealing the first semiconductor structure, the second substrate, and a first surface of the first substrate, wherein the first interconnect region is not sealed by the filler layer, the second interconnect region is sealed by the filler layer, and a predetermined height exists between an upper surface of the filler layer on the second interconnect region and the first interconnect region; A semiconductor package, wherein the first surface of the first substrate further includes a fourth signal transmission region, the second substrate is positioned on the fourth signal transmission region, and the second signal transmission region and the fourth signal transmission region are electrically connected.

16. the second substrate further includes a second interconnection surface located on the other side of the base, the base having a channel connecting the first interconnection region and the second interconnection surface, and the first interconnection region is interconnected with the second signal transmission region via the channel in a direction perpendicular to the first substrate; 16. The semiconductor package of claim 15.

17. The semiconductor package further includes a second package having a contact surface, the second package interconnected with the first interconnect region through the contact surface, and a gap existing between the second package and the fill layer.

17. The semiconductor package according to claim 15 or 16.

18. a first contact structure is provided on the contact surface of the second package, the first contact structure having a first height protruding from the contact surface in a direction perpendicular to the contact surface, the first height being greater than the predetermined height; 18. The semiconductor package of claim 17.

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