Voltage detection circuit

Abstract

To detect a disconnection in a voltage detection circuit having an AD converter.SOLUTION: A voltage detection circuit includes: a modulation signal generator that generates a modulation signal; an AD converter that converts a voltage applied between first input wiring and second input wiring into a digital value; a current source that supplies a first current which changes based on the modulation signal to the first input wiring, and supplies a second current which changes based on the modulation signal to the second input wiring; a differentiator that outputs a value obtained by differentiating an output value of the AD converter; a multiplier that multiplies an output value of the differentiator by a value that changes positively and negatively based on the modulation signal; and an integrator that integrates an output value of the multiplier.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a voltage detection circuit.

[0002] The voltage detection circuit disclosed in Patent Document 1 includes an AD converter and a frequency signal generation circuit. The frequency signal generation circuit is connected to the input terminal of the AD converter via a resistor. The frequency signal generation circuit generates a pulse voltage of a reference frequency. If the input terminal of the AD converter is disconnected from the device to be detected, the potential of the input terminal of the AD converter fluctuates at the reference frequency. This voltage detection circuit detects a disconnection by detecting a fluctuating potential synchronized with the reference frequency in the output value of the AD converter. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,852,360 Summary of the Invention [Problem to be solved by the invention]

[0004] In the technology of Patent Document 1, a wire break is detected when the amplitude of the fluctuating potential output by the AD converter (i.e., the fluctuating potential synchronized with the reference frequency) exceeds a reference value, so a pulse voltage with a large amplitude must be generated by a frequency voltage generation circuit. When such a pulse voltage with a large amplitude is applied to the input terminal of the AD converter, the offset voltage increases and the voltage detection accuracy decreases. This specification proposes a technology for more suitably detecting a wire break in a voltage detection circuit having an AD converter. [Means for solving the problem]

[0005] The voltage detection circuit disclosed in this specification includes a modulation signal generator that generates a modulation signal, an AD converter that converts a voltage applied between a first input wiring and a second input wiring into a digital value, a current source that supplies a first current that changes in accordance with the modulation signal to the first input wiring and a second current that changes in accordance with the modulation signal to the second input wiring, a differentiator that outputs a value obtained by differentiating the output value of the AD converter, a multiplier that multiplies a value that changes positively and negatively in accordance with the modulation signal by the output value of the differentiator, and an integrator that integrates the output value of the multiplier.

[0006] In this voltage detection circuit, a first input wiring and a second input wiring are connected to an external circuit including a device whose voltage is to be detected, and a current source supplies a first current that varies in response to a modulation signal to the first input wiring and a second current that varies in response to the modulation signal to the second input wiring.

[0007] If there is no break in the first input wire and the second input wire, the first current and the second current flow to the external circuit. In this case, the voltage generated between the first input wire and the second input wire due to the first current and the second current is small. In other words, the voltage between the first input wire and the second input wire contains almost no voltage component synchronized with the modulation signal. In this case, the output value of the differentiator (i.e., the value obtained by differentiating the output value of the AD converter) contains almost no voltage component synchronized with the modulation signal, and the output value of the differentiator has a relatively flat waveform. Therefore, the output value of the multiplier (i.e., the value obtained by multiplying the output value of the differentiator by a value that changes positively or negatively according to the modulation signal) changes positively or negatively. Therefore, the output value of the integrator (i.e., the value obtained by integrating the output value of the multiplier) is maintained at a low value.

[0008] If a break occurs in either the first input wiring or the second input wiring, the broken input wiring is charged by the first current or the second current, causing the potential of the broken input wiring to rise. At this time, the potential of the broken input wiring rises in a step-like manner in synchronization with the modulation signal. In this case, the output value of the differentiator (i.e., the value obtained by differentiating the output value of the AD converter) fluctuates in synchronization with the modulation signal. Therefore, when the multiplier multiplies the output value of the differentiator by a value that changes positively or negatively according to the modulation signal, the output value of the multiplier becomes a signal that fluctuates biased toward positive or negative values ​​(e.g., a signal that fluctuates between zero and positive values ​​or a signal that fluctuates between zero and negative values). Therefore, the absolute value of the output value of the integrator (i.e., the value obtained by integrating the output value of the multiplier) increases over time.

[0009] As described above, the output value of the integrator changes depending on whether or not there is a wire break. Therefore, the presence or absence of a wire break can be detected based on the output value of the integrator. Furthermore, in this voltage detection circuit, a first current flows through the first input wiring and a second current flows through the second input wiring, so the offset voltage caused by the first and second currents is small, allowing for accurate voltage detection. Furthermore, in the event of a wire break, the integrator integrates the amount of change in potential caused by the wire break, making it possible to detect a wire break even if the voltage generated between the input wiring is not very large. In this way, this voltage detection circuit can detect voltage with high detection accuracy and can effectively detect a wire break. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a circuit diagram of a voltage detection circuit according to the first embodiment. [Figure 2] Graph showing normal operation in Example 1. [Figure 3] 10 is a graph showing the state when a wire is broken in Example 1. [Figure 4] FIG. 10 is a circuit diagram of a voltage detection circuit according to a second embodiment. [Figure 5] Graph showing normal operation in Example 2. [Figure 6] Graph showing the state when a wire is broken in Example 2. [Figure 7]FIG. 10 is a circuit diagram of a voltage detection circuit according to a third embodiment. [Figure 8] FIG. 10 is a circuit diagram of a voltage detection circuit according to a fourth embodiment. [Figure 9] 10 is a graph showing the state when a wire is broken in Example 4. [Figure 10] FIG. 10 is a circuit diagram of a voltage detection circuit according to a fifth embodiment. [Figure 11] FIG. 13 is a circuit diagram of a voltage detection circuit according to a sixth embodiment. [Figure 12] FIG. 13 is a circuit diagram of a modulation signal generator according to a seventh embodiment. [Figure 13] FIG. 10 is a circuit diagram of a modified example of a disconnection detection circuit. [Figure 14] FIG. 10 is a circuit diagram of a modified example of a disconnection detection circuit. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0011] A voltage detection circuit 100 according to the first embodiment shown in FIG. 1 is connected to a shunt resistor 12. The shunt resistor 12 is connected to an external circuit (not shown). A current Is flows through the shunt resistor 12 via the external circuit. The voltage detection circuit 100 detects the current Is by detecting a voltage Vs generated across the shunt resistor 12.

[0012] The voltage detection circuit 100 has a first input wiring 20a, a second input wiring 20b, and an anti-aliasing filter 24 (hereinafter referred to as AAF 24). The first input wiring 20a and the second input wiring 20b are connected to a shunt resistor 12 via the AAF 24. The AAF 24 has a first resistor 24a, a second resistor 24b, and a capacitor 24c. The first input wiring 20a is connected to one terminal 12a of the shunt resistor 12 via the first resistor 24a. The second input wiring 20b is connected to the other terminal 12b of the shunt resistor 12 via the second resistor 24b. Therefore, the shunt resistor 12 is connected between the first input wiring 20a and the second input wiring 20b via the first resistor 24a and the second resistor 24b. The electrical resistance R1 of the first resistor 24a is approximately equal to the electrical resistance R2 of the second resistor 24b. The electrical resistance of the shunt resistor 12 is much smaller than the electrical resistances R1 and R2. The capacitor 24c is connected between the first input wiring 20a and the second input wiring 20b.

[0013] The voltage detection circuit 100 has a modulation signal generator 60 and a synchronizer 62. The modulation signal generator 60 outputs a pulse signal Sig1. As shown in FIG. 2, the signal Sig1 is a pulse signal that changes between a value of HIGH and a value of LOW at a frequency fc. The signal Sig1 is input to the synchronizer 62. The synchronizer 62 outputs a pulse signal Sig1a synchronized with the pulse signal Sig1. The pulse signal Sig1a is a digital signal that is 1 when the pulse signal Sig1 is HIGH and is -1 when the pulse signal Sig1 is LOW. In other words, the pulse signal Sig1a is a pulse signal with the same waveform as the pulse signal Sig1.

[0014] The voltage detection circuit 100 includes a current source 30. The current source 30 includes a first constant current source 30a, a second constant current source 30b, a switch circuit 40a, and a switch circuit 40b.

[0015] The first constant current source 30a generates a constant DC current I1. The first constant current source 30a is connected to the first input wiring 20a via a switch circuit 40a. When the switch circuit 40a is turned on, the first constant current source 30a supplies the current I1 to the first input wiring 20a. When the switch circuit 40a is turned off, the supply of the current I1 from the first constant current source 30a to the first input wiring 20a is stopped. A signal Sig1 is input to the switch circuit 40a. The switch circuit 40a turns on and off in synchronization with the signal Sig1. Therefore, as shown in FIG. 2, the current Iwod1 flowing through the first input wiring 20a becomes a pulse current synchronized with the signal Sig1. As shown in FIG. 1, the current Iwod1 flows to an external circuit via a first resistor 24a.

[0016] The second constant current source 30b generates a constant DC current I2. The current I2 is equal to the current I1. The second constant current source 30b is connected to the second input wiring 20b via a switch circuit 40b. When the switch circuit 40b is turned on, the second constant current source 30b supplies the current I2 to the second input wiring 20b. When the switch circuit 40b is turned off, the supply of the current I2 from the second constant current source 30b to the second input wiring 20b is stopped. A signal Sig1 is input to the switch circuit 40b. The switch circuit 40b turns on and off in response to the signal Sig1. Therefore, as shown in FIG. 2, the current Iwod2 flowing through the second input wiring 20b is a pulse current synchronized with the signal Sig1. In other words, the waveform of the current Iwod2 matches the waveform of the current Iwod1. As shown in FIG. 1, the current Iwod2 flows to an external circuit via a second resistor 24b.

[0017] Because a current Iwod1 flows through the first resistor 24a, the potential of the first input wiring 20a is higher than the potential of the terminal 12a of the shunt resistor 12 by a voltage Va (= R1 · Iwod1). Furthermore, because a current Iwod2 flows through the second resistor 24b, the potential of the second input wiring 20b is higher than the potential of the terminal 12b of the shunt resistor 12 by a voltage Vb (= R2 · Iwod2). If the electrical resistance R1 is equal to the electrical resistance R2 and the current Iwod1 is equal to the current Iwod2, then Va = Vb. However, in reality, there is an error between the electrical resistances R1 and R2, and an error between the currents Iwod1 and Iwod2, so the voltages Va and Vb do not match. Therefore, a voltage V1 is applied between the first input wiring 20a and the second input wiring 20b, such that V1 = Vs + ΔV (note that ΔV = Va - Vb). That is, the voltage V1 is shifted by a voltage ΔV from the voltage Vs to be detected. Hereinafter, the voltage ΔV will be referred to as an offset voltage ΔV.

[0018] The voltage detection circuit 100 has an AD converter 50 (hereinafter referred to as ADC50). The ADC50 is connected to a first input wiring 20a and a second input wiring 20b. The ADC50 outputs a signal obtained by converting a voltage V1 between the first input wiring 20a and the second input wiring 20b into a digital value. Hereinafter, the voltage indicated by the digital signal output by the ADC50 will be referred to as voltage V2. The voltage V2 is used as a detection value of the voltage Vs. For example, the digital signal output by the ADC50 is input to a control circuit (not shown) via a digital low-pass filter or the like, and the control circuit performs control in accordance with the voltage V2.

[0019] The voltage detection circuit 100 includes a differentiator 52, a multiplier 54, an integrator 56, and a comparator 58 as a disconnection detection circuit.

[0020] The differentiator 52 time-differentiates the voltage V2 output by the ADC 50. Therefore, the voltage V3 indicated by the output signal of the differentiator 52 indicates the rate of change of the voltage V2 (i.e., the amount of change per unit time).

[0021] Multiplier 54 multiplies voltage V3 output by differentiator 52 by signal Sig1a output by synchronizer 62. Therefore, voltage V4 output by multiplier 54 matches voltage V3 when signal Sig1a is 1, and matches a voltage obtained by inverting voltage V3 when signal Sig1a is −1.

[0022] The integrator 56 integrates the voltage V4 output by the multiplier 54 over time.

[0023] Comparator 58 determines whether voltage V5 output by integrator 56 is within a range lower than threshold Vth and higher than threshold −Vth. The range between threshold Vth and threshold −Vth is the range that voltage V5 can take when there is no break in the input wiring (i.e., the normal range of voltage V5). Therefore, output signal Sig2 of comparator 58 indicates whether there is a break in the input wiring.

[0024] FIG. 2 shows the changes in each value during normal operation of the voltage detection circuit 100. As described above, signals Sig1 and Sig1a are pulse signals that fluctuate at a constant frequency fc. Because a common signal Sig1 is input to switch circuits 40a and 40b, currents Iwod1 and Iwod2 are both pulse signals with the same waveform as signal Sig1. Current Iwod1 fluctuates between I1 and 0, and current Iwod2 fluctuates between I2 and 0. Furthermore, voltage Vs to be detected fluctuates at a frequency much lower than the frequency fc of signal Sig1. As described above, voltage V1 between the first input wiring 20a and the second input wiring 20b satisfies the relationship V1 = Vs + ΔV. Because the offset voltage ΔV is small, voltage V1 in FIG. 2 is approximately equal to voltage Vs. Voltage V2 output by the ADC 50 is approximately equal to voltage V1. The differentiator 52 differentiates the voltage V2 with respect to time, and the output voltage V3 from the differentiator 52 represents the rate of change of the voltage V2. The multiplier 54 multiplies the voltage V3 by the signal Sig1a, which fluctuates between 1 and -1 at a frequency fc, and outputs the resulting value as the voltage V4. As shown in FIG. 2, when the signal Sig1a is 1, the voltage V4 is equal to the voltage V3, and when the signal Sig1a is -1, the voltage V4 is equal to the voltage obtained by inverting the positive and negative values ​​of the voltage V3. Therefore, the voltage V4 periodically fluctuates between positive and negative. The integrator 56 integrates the voltage V4 output from the multiplier 54 and outputs the resulting value as the voltage V5. Because the voltage V4 periodically fluctuates between positive and negative, the voltage V5 periodically increases and decreases. Therefore, the voltage V5 is maintained at a value near 0. Therefore, the voltage V5 is maintained at a value lower than the threshold Vth and higher than the threshold −Vth. Therefore, the comparator 58 outputs a value indicating that the voltage V5 is within the normal range.

[0025] FIG. 3 shows the changes in each value when a break occurs at point X in FIG. 1 (i.e., when the first input wiring 20a is disconnected from the terminal 12a). In this case, voltage Vs is not applied between the first input wiring 20a and the second input wiring 20b. Furthermore, current Iwod1 no longer flows from the first input wiring 20a to the terminal 12a. Therefore, current Iwod1 charges the first input wiring 20a, and voltage V1 rises independently of voltage Vs, as shown in FIG. 3. For example, current Iwod1 charges capacitor 24c, causing voltage V1 to rise. Voltage V2 rises in the same manner as voltage V1. Voltage V3 output by differentiator 52 represents the rate of change of voltage V2. Voltages V1 and V2 rise during the period when current Iwod1 flows, but do not rise during the period when current Iwod1 is zero. Therefore, voltage V3 output by differentiator 52 has the same waveform as current Iwod1. That is, voltage V3 fluctuates between positive and zero values ​​at frequency fc. Multiplier 54 multiplies voltage V3 by signal Sig1a and outputs the result as voltage V4. When signal Sig1a is 1, voltage V3 is positive, so voltage V4 is also positive. When signal Sig1a is -1, voltage V3 is 0, so voltage V4 is also 0. Therefore, voltage V4 fluctuates between positive and zero values ​​at frequency fc, just like voltage V3. Integrator 56 integrates voltage V4. Because voltage V4 fluctuates between positive and zero values, voltage V5 output by integrator 56 increases in a step-like manner over time. Therefore, voltage V5 exceeds threshold Vth at a predetermined timing. When this occurs, comparator 58 outputs a signal indicating that voltage V5 is an abnormal value. Therefore, a disconnection can be detected based on the output value of comparator 58.

[0026] If a break occurs in the second input wiring 20b, the second input wiring 20b is charged by the current Iwod2, and the potential of the second input wiring 20b rises. As a result, voltages V1 and V2 decrease over time, and voltages V3 and V4 fluctuate between negative and zero. In this case, voltage V5 decreases over time and falls below threshold value -Vth at a predetermined timing. Therefore, comparator 58 outputs a signal indicating that voltage V5 is an abnormal value. Therefore, a break can be detected by the output value of comparator 58.

[0027] As described above, in the voltage detection circuit 100 of the first embodiment, the voltage V5 output by the integrator 56 changes depending on whether or not there is a wire break, so that a wire break can be detected based on the voltage V5 output by the integrator 56. Furthermore, in the voltage detection circuit of the first embodiment, the currents Iwod1 and Iwod2, which are synchronized with each other, flow through the first input wiring 20a and the second input wiring 20b, so the offset voltage ΔV is small. Therefore, the voltage Vs can be accurately detected during normal operation.

[0028] In the voltage detection circuit 100 of the first embodiment, the voltage V2 rises or falls when a disconnection occurs, so it is also possible to detect a disconnection when the voltage V2 falls outside its normal range. However, because the normal range of the voltage V2 is wide, it takes time for the voltage V2 to change to a value outside the normal range. In contrast, the voltage detection circuit 100 of the first embodiment can extract a fluctuation component synchronized with the signal Sig1 from the voltage V2 as the voltage V4, so that the disconnection can be detected in a short time by integrating the voltage V4.

[0029] Furthermore, in the voltage detection circuit 100 of the first embodiment, the integrator 56 detects a wire break by integrating the voltage V4 over multiple periods of the signal Sig1 having the frequency fc. Therefore, even if the voltage Vs itself oscillates for a short period of time at a frequency close to the frequency fc due to noise or the like, the oscillation of the voltage Vs is prevented from being erroneously detected as a wire break. Thus, the voltage detection circuit 100 of the first embodiment is less likely to erroneously detect a wire break. [Example]

[0030] 4, the voltage detection circuit 200 of the second embodiment differs from that of the first embodiment in the configurations of the current source 30 and the modulation signal generator 60. The other configurations of the voltage detection circuit 200 of the fourth embodiment are the same as those of the first embodiment.

[0031] In the second embodiment, as shown in Fig. 5, the signal Sig1 output by the modulation signal generator 60 changes between the value HIGH, the value LOW, and an intermediate value MID between them. The signal Sig1 output by the modulation signal generator 60 is a pulse signal in which a pulse signal of frequency fa and a pulse signal of frequency fb are superimposed. Furthermore, when the signal Sig1 has the value MID, the synchronizer 62 sets the signal Sig1a to 0. That is, the signal Sig1a changes in three stages: 1, 0, and -1.

[0032] In the second embodiment, the current source 30 does not include switch circuits 40a and 40b. Specifically, the first constant current source 30a is directly connected to the first input wiring 20a, and the second constant current source 30b is directly connected to the second input wiring 20b. Specifically, in the second embodiment, the current output from the first constant current source 30a flows to the first input wiring 20a as current Iwod1, and the current output from the second constant current source 30b flows to the second input wiring 20b as current Iwod2. Furthermore, in the second embodiment, a signal Sig1 is input to the first constant current source 30a and the second constant current source 30b. The first constant current source 30a and the second constant current source 30b change the magnitude of their output currents in synchronization with the signal Sig1. 5, the first constant current source 30a outputs a pulse current synchronized with the signal Sig1 as the current Iwod1, and the second constant current source 30b outputs a pulse current synchronized with the signal Sig1 as the current Iwod2. More specifically, when the signal Sig1 is at a HIGH value, the currents Iwod1 and Iwod2 are high currents IH, when the signal Sig1 is at a MID value, the currents Iwod1 and Iwod2 are intermediate-level currents IM, and when the signal Sig1 is at a LOW value, the currents Iwod1 and Iwod2 are zero.

[0033] In the second embodiment, during normal operation, as shown in FIG. 5, when the signal Sig1a is 1, the voltage V4 is equal to the voltage V3; when the signal Sig1a is 0, the voltage V4 is 0; and when the signal Sig1a is −1, the voltage V4 is equal to the inverted value of the voltage V3. Therefore, the voltage V4 periodically changes between positive and negative, and the voltage V5, which is the integrated value of the voltage V4, is maintained at a value close to 0 V. Therefore, the voltage V5 is maintained within the normal range.

[0034] When a disconnection occurs in the first input wiring 20a, as shown in FIG. 6, the first input wiring 20a is charged by the current Iwod1, causing the voltages V1 and V2 to increase. Therefore, the voltage V3 has a waveform substantially identical to that of the current Iwod1. Therefore, when the signal Sig1a is 1, the voltage V4 is positive, and when the signal Sig1a is 0, the voltage V4 is zero. Furthermore, when the signal Sig1a is -1, the voltage V3 is zero, so the voltage V4 is zero. That is, the voltage V4 fluctuates between positive and zero values. Therefore, the voltage V5, which is the integrated value of the voltage V4, increases over time. Therefore, the voltage V5 exceeds the threshold Vth, and the comparator 58 outputs a signal indicating a disconnection. When a disconnection occurs in the second input wiring 20b, the voltage V5 falls below the threshold −Vth, causing the comparator 58 to output a signal indicating a disconnection.

[0035] As described above, in Example 2, the voltage V5 falls outside the normal range when a disconnection occurs, so that the disconnection can be detected. Furthermore, in Example 2, the signal Sig1 has multiple frequency components, so that false detection of a disconnection due to the oscillation of the voltage Vs can be more effectively suppressed. [Example]

[0036] 7, the voltage detection circuit 300 of the third embodiment differs from that of the second embodiment in the configuration of the current source 30. The other configurations of the voltage detection circuit 300 of the third embodiment are the same as those of the second embodiment.

[0037] In the third embodiment, the current source 30 has a first DA converter 31a (hereinafter referred to as the first DAC31a) instead of the first constant current source 30a, and a second DA converter 31b (hereinafter referred to as the second DAC31b) instead of the second constant current source 30b. A signal Sig1 is input to the first DAC31a and the second DAC31b. The first DAC31a outputs a current Iwod1 (i.e., a current Iwod1 that changes in three stages: current IH, current I M, and 0) similar to that of the second embodiment in synchronization with the signal Sig1. The second DAC31b outputs a current Iwod2 (i.e., a current Iwod2 that changes in three stages: current IH, current I M, and 0) similar to that of the second embodiment in synchronization with the signal Sig1. Therefore, in the third embodiment as well, it is possible to detect a disconnection, similar to that of the second embodiment. [Example]

[0038] 8 includes a current generating circuit 70. The current generating circuit 70 includes a third constant current source 34a, a fourth constant current source 34b, a switch circuit 44a, and a switch circuit 44b. Other configurations of the fourth embodiment are the same as those of the first embodiment.

[0039] The third constant current source 34a generates a constant DC current I3. The third constant current source 34a is connected to the first input wiring 20a via a switch circuit 44a. When the switch circuit 44a is turned on, the current I3 flows from the first input wiring 20a to the third constant current source 34a. That is, the current I3 is extracted from the first input wiring 20a. When the switch circuit 44a is turned off, the current I3 stops. The current Iwod1 flowing through the first input wiring 20a is the current I1 minus the current I3. An inverted signal of the signal Sig1 (hereinafter referred to as an inverted signal) is input to the switch circuit 44a. The switch circuit 44a turns on and off in synchronization with the inverted signal. Therefore, when the current I1 stops, the current I3 flows, and when the current I1 is flowing, the current I3 stops. Therefore, the current Iwod1 becomes a pulse current that fluctuates between a positive value I1 and a negative value I3, as shown in FIG. 9. The currents I1 and I3 are set so that the average value of the current Iwod1 is approximately 0. In Fig. 9, the on-duty of the current Iwod1 is 50% or less, so the current I1 is larger than the current I3.

[0040] The fourth constant current source 34b generates a constant DC current I4. The fourth constant current source 34b is connected to the second input wiring 20b via a switch circuit 44b. When the switch circuit 44b is turned on, the current I4 flows from the second input wiring 20b to the fourth constant current source 34b. In other words, the current I4 is extracted from the second input wiring 20b. When the switch circuit 44b is turned off, the current I4 stops. The current Iwod2 flowing through the second input wiring 20b is the current I2 minus the current I4. An inverted signal obtained by inverting the signal Sig1 is input to the switch circuit 44b. The switch circuit 44b turns on and off in synchronization with the inverted signal. Therefore, when the current I2 stops, the current I4 flows, and when the current I2 is flowing, the current I4 stops. Therefore, the current Iwod2 becomes a pulse current that fluctuates between a positive value I2 and a negative value I4, as shown in FIG. 9. The currents I2 and I4 are set so that the average value of the current Iwod2 is approximately zero.

[0041] Even in normal operation of Example 4, current Iwod1 and current Iwod2 are approximately equal, so voltages Vs, V1, V2, V3, V4, and V5 change in the same manner as in Example 1 (i.e., FIG. 2). Therefore, voltage Vs can be detected even in normal operation of Example 4. In particular, in Example 4, the average value of current Iwod1 and the average value of current Iwod2 are approximately zero, so the offset voltage ΔV is very small. Therefore, voltage Vs can be detected more accurately.

[0042] Furthermore, in the fourth embodiment, when the first input wiring 20a is broken, the first input wiring 20a is charged during the period when the current I1 flows, while the second input wiring 20b is discharged during the period when the current I3 flows. Therefore, as shown in FIG. 9, the voltages V1 and V2 are substantially constant. Furthermore, the voltage V3 has the same waveform as the current Iwod1. That is, the voltage V3 is positive during the period when the current I1 flows, and negative during the period when the current I3 flows. That is, the voltage V3 is positive during the period when the signal Sig1a is 1, and negative during the period when the signal Sig1a is -1. Therefore, the voltage V4 output by the multiplier 54 is always positive. Therefore, the voltage V5 output by the integrator 56 rises and exceeds the threshold Vth, and the comparator 58 detects the break. Although not shown, when the second input wiring 20b is broken in the fourth embodiment, the voltage V4 is always negative. As a result, the voltage V5 drops below the threshold value −Vth, and the comparator 58 detects a disconnection. As described above, the fourth embodiment can also detect a disconnection in an appropriate manner. [Example]

[0043] 10, the voltage detection circuit 500 of the fifth embodiment differs from that of the first embodiment in the configuration of the current source 30. The other configurations of the voltage detection circuit 500 of the fifth embodiment are the same as those of the first embodiment.

[0044] In the fifth embodiment, the current source 30 includes a chopper circuit 32. The chopper circuit 32 is connected to a first constant current source 30a, a second constant current source 30b, a switch circuit 40a, and a switch circuit 40b. The chopper circuit 32 alternately switches the mutual connection states of the first constant current source 30a, the second constant current source 30b, the switch circuit 40a, and the switch circuit 40b between a first connection state and a second connection state at a predetermined frequency. In the first connection state, the first constant current source 30a is connected to the switch circuit 40a, and the second constant current source 30b is connected to the switch circuit 40b. In the first connection state, the current Iwod1 fluctuates between I1 and 0, and the current Iwod2 fluctuates between I2 and 0. In the second connection state, the first constant current source 30a is connected to the switch circuit 40b, and the second constant current source 30b is connected to the switch circuit 40a. In the second connection state, the current Iwod1 fluctuates between the current I2 and 0, and the current Iwod2 fluctuates between the current I1 and 0. By alternately switching the paths of the currents I1 and I2 in this manner, the offset voltage ΔV caused by the difference between the currents Iwod1 and Iwod2 can be suppressed. Therefore, the voltage detection circuit 500 can detect the voltage Vs more accurately. [Example]

[0045] 11, the voltage detection circuit 600 of the sixth embodiment differs from that of the first embodiment in the configuration of the current source 30. The other configurations of the voltage detection circuit 600 of the sixth embodiment are the same as those of the first embodiment.

[0046] In the sixth embodiment, the current source 30 includes six constant current sources 30a to 30f and a DEM (Dynamic Element Matching) 36. The constant current sources 30a to 30f generate currents equal to each other. However, there may be an error between the currents generated by the constant current sources 30a to 30f. The DEM 36 is connected to the constant current sources 30a to 30f, a switch circuit 40a, and a switch circuit 40b. The DEM 36 connects three constant current sources selected from the constant current sources 30a to 30f (hereinafter referred to as a first group of constant current sources) to the switch circuit 40a, and connects the remaining three constant current sources (hereinafter referred to as a second group of constant current sources) to the switch circuit 40b. Therefore, when the switch circuit 40a is turned on, the current supplied from the three constant current sources in the first group flows as the current Iwod1 to the first input wiring 20a, and when the switch circuit 40b is turned on, the current supplied from the three constant current sources in the second group flows as the current Iwod2 to the second input wiring 20b. The DEM 36 repeatedly changes the combination of the constant current sources in the first group and the combination of the constant current sources in the second group at a predetermined frequency. In this way, by periodically changing the combination of the constant current sources that supply the current Iwod1 and the combination of the constant current sources that supply the current Iwod2, the offset voltage caused by the difference between the currents Iwod1 and Iwod2 can be suppressed. Therefore, the voltage detection circuit 600 can detect the voltage Vs more accurately. [Example]

[0047] In the above-described first to sixth embodiments, the signal Sig1 has one or more frequency components. In contrast, in the seventh embodiment, the modulation signal generator 60 outputs a pulse signal that changes with a random period as the signal Sig1. In the seventh embodiment, the modulation signal generator 60 is configured with a linear feedback shift register 80 (hereinafter referred to as an LFSR 80) shown in FIG. 12. The LFSR 80 is configured with six flip-flop circuits (hereinafter referred to as FF circuits) connected in series and an XOR circuit. The output value of the first-stage FF circuit and the output value of the sixth-stage FF circuit are input to the XOR circuit. The output value of the XOR circuit is input to the first-stage FF circuit. The LFSR 80 outputs the output value of the sixth-stage FF circuit as the signal Sig1. With this configuration, a pulse signal with a random period can be output as the signal Sig1. Even if a random signal is used as the signal Sig1, a wire break can be appropriately detected. Furthermore, when the signal Sig1 is a random signal, false wire break detection can be more effectively suppressed when the voltage Vs oscillates.

[0048] In any of the embodiments, as shown in FIG. 13, a low-pass filter (hereinafter referred to as LPF) 90 may be provided between the differentiator 52 and the multiplier 54. In this case, the signal Sig1a may be input to the multiplier 54 via a delay device 92. The delay device 92 delays and outputs the signal Sig1a. The amount of signal delay in the delay device 92 is set to match the amount of delay of the signals generated by the ADC 50, the differentiator 52, and the LPF 90. This allows the two signals input to the multiplier 54 to be accurately synchronized, allowing the voltage detection circuit to operate appropriately.

[0049] 14, the signal Sig1a may be input to the multiplier 54 via an LPF 94. The LPF 94 has filter characteristics that match the filter characteristics of the ADC 50, the differentiator 52, and the LPF 90. This configuration can suppress errors due to differences in filter characteristics.

[0050] The frequency fc is an example of a reference frequency. The frequencies fa and fb are examples of frequency components of a modulation signal. The chopper circuit 32 and the DEM 36 are examples of a selection circuit.

[0051] (Configuration 1) A voltage detection circuit, a modulation signal generator for generating a modulation signal; an AD converter that converts a voltage applied between the first input wiring and the second input wiring into a digital value; a current source that supplies a first current that varies in response to the modulation signal to the first input wiring and a second current that varies in response to the modulation signal to the second input wiring; a differentiator that outputs a value obtained by differentiating an output value of the AD converter; a multiplier that multiplies an output value of the differentiator by a value that changes positively or negatively according to the modulation signal; an integrator that integrates the output value of the multiplier; a comparator that compares the output value of the integrator with a threshold value; A voltage detection circuit having (Configuration 2) 2. The voltage detection circuit of claim 1, wherein the modulation signal varies at a reference frequency. (Configuration 3) 2. The voltage detection circuit of claim 1, wherein the modulated signal has a plurality of frequency components. (Configuration 4) The current source a first DA converter that converts the modulated signal into the first current; a second DA converter that converts the modulated signal into the second current; 4. The voltage detection circuit according to any one of configurations 1 to 3, comprising: (Configuration 5) The voltage detection circuit according to any one of configurations 1 to 4, further comprising a current generating circuit that draws current from the first input wiring during a period when the supply of the first current is stopped and draws current from the second input wiring during a period when the supply of the second current is stopped. (Configuration 6) The current source a first constant current source; a second constant current source; a chopper circuit (32) that switches a connection state between a first connection state in which the current supplied from the first constant current source is supplied to the first input wiring as the first current and the current supplied from the second constant current source is supplied to the second input wiring as the second current, and a second connection state in which the current supplied from the second constant current source is supplied to the first input wiring as the first current and the current supplied from the first constant current source is supplied to the second input wiring as the second current; and a frequency at which the chopper circuit switches the connection state is an integer multiple of a sampling frequency of the AD converter; 6. The voltage detection circuit according to any one of configurations 1 to 5. (Configuration 7) The current source a plurality of constant current sources; a selection circuit that selects at least one first constant current source and at least one second constant current source from the plurality of constant current sources; a first current generating circuit that generates the first current from a current supplied from the first constant current source; a second current generating circuit that generates the second current from a current supplied from the second constant current source; and the selection circuit changes over time a combination of the first constant current source and the second constant current source selected from the plurality of constant current sources; 6. The voltage detection circuit according to any one of configurations 1 to 5.

[0052] According to configurations 5 to 7, the offset voltage can be reduced.

[0053] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0054] 20a: first input wiring, 20b: second input wiring, 30: current source, 50: AD converter, 52: differentiator, 54: multiplier, 56: integrator, 58: comparator, 60: modulation signal generator

Claims

1. A voltage detection circuit, a modulation signal generator (60) for generating a modulation signal (Sig1); an AD converter (50) that converts a voltage applied between the first input wiring (20a) and the second input wiring (20b) into a digital value; a current source (30) that supplies a first current (Iwod1) that varies in response to the modulation signal to the first input wiring and a second current (Iwod2) that varies in response to the modulation signal to the second input wiring; a differentiator (52) that outputs a value obtained by differentiating the output value of the AD converter; a multiplier (54) that multiplies a value (Sig1a) that changes positively or negatively according to the modulation signal by an output value of the differentiator; an integrator (56) for integrating the output value of the multiplier; A voltage detection circuit having

2. 2. The voltage detection circuit of claim 1, wherein the modulation signal varies at a reference frequency (fc).

3. 2. The voltage detection circuit of claim 1, wherein the modulated signal has a plurality of frequency components (fa, fb).

4. The current source a first DA converter (31a) that converts the modulated signal into the first current; a second DA converter (31b) for converting the modulated signal into the second current; The voltage detection circuit according to any one of claims 1 to 3, comprising:

5. The voltage detection circuit according to any one of claims 1 to 3, further comprising a current generating circuit (70) that draws current from the first input wiring during a period when the supply of the first current is stopped and draws current from the second input wiring during a period when the supply of the second current is stopped.

6. The current source a first constant current source; a second constant current source; a chopper circuit (32) that switches a connection state between a first connection state in which the current supplied from the first constant current source is supplied to the first input wiring as the first current and the current supplied from the second constant current source is supplied to the second input wiring as the second current, and a second connection state in which the current supplied from the second constant current source is supplied to the first input wiring as the first current and the current supplied from the first constant current source is supplied to the second input wiring as the second current; and a frequency at which the chopper circuit switches the connection state is an integer multiple of a sampling frequency of the AD converter; The voltage detection circuit according to any one of claims 1 to 3.

7. The current source a plurality of constant current sources; a selection circuit (32, 36) for selecting at least one first constant current source and at least one second constant current source from the plurality of constant current sources; a first current generating circuit (40a) that generates the first current from a current supplied from the first constant current source; a second current generating circuit (40b) that generates the second current from the current supplied from the second constant current source; and the selection circuit changes over time a combination of the first constant current source and the second constant current source selected from the plurality of constant current sources; The voltage detection circuit according to any one of claims 1 to 3.

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