Memory device and manufacturing method thereof

Abstract

PROBLEM TO BE SOLVED BY THE INVENTION: To improve the operating performance of a memory device.SOLUTION: A memory device includes a semiconductor substrate, a floating gate, and an erase gate. The floating gate and the erase gate are disposed above the semiconductor substrate, and the erase gate includes a main portion and a first branch portion. The main portion extends in a first horizontal direction, and the first branch portion extends in a second horizontal direction and is connected to the main portion. A first portion of the floating gate is disposed vertically below the first branch portion.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to memory devices and methods of fabricating the same, and more particularly to memory devices including erase gates and methods of fabricating the same. [Background technology]

[0002] Semiconductor memory devices are used in the computer and electronics industries as a means for storing digital information or data. Generally, semiconductor memory devices are classified into volatile and nonvolatile memory devices. Nonvolatile memory devices, which can retain data even when power is interrupted, are widely used. As computer microprocessors become increasingly powerful, the demand for memory (e.g., embedded memory) is also increasing. However, the manufacturing methods and structures of such embedded memory are susceptible to the influence of other devices formed on the chip, and their designs must be appropriately integrated. Therefore, how to improve the operational performance of memory devices through design changes to the structure and / or manufacturing methods has always been a goal in related industries. Summary of the Invention

[0003] The present disclosure provides a memory device and a method for fabricating the same. To improve the performance of the memory device, an erase gate including a branch is used.

[0004] According to one embodiment of the present invention, a memory device is provided. The memory device includes a semiconductor substrate, a floating gate, and an erase gate. The floating gate and the erase gate are disposed above the semiconductor substrate, and the erase gate includes a main portion and a first branch portion. The main portion extends in a first horizontal direction, and the first branch portion extends in a second horizontal direction and is connected to the main portion. A first portion of the floating gate is disposed vertically below the first branch portion.

[0005] According to one embodiment of the present invention, there is provided a method for manufacturing a memory device. The method includes the following steps: a semiconductor substrate is provided; and a floating gate and an erase gate are formed above the semiconductor substrate. The erase gate includes a main portion and a first branch portion. The main portion extends in a first horizontal direction, and the first branch portion extends in a second horizontal direction and is connected to the main portion. A first portion of the floating gate is located vertically below the first branch portion.

[0006] These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various drawing figures. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic diagram showing a memory device according to a first embodiment of the present invention; [Figure 2] 1 is a schematic cross-sectional view showing a memory device according to a first embodiment of the present invention. [Figure 3] 3 is another schematic cross-sectional view showing the memory device according to the first embodiment of the present invention. FIG. [Figure 4] 4 is yet another schematic cross-sectional view showing the memory device according to the first embodiment of the present invention. FIG. [Figure 5] 1 is a partially enlarged schematic view showing a memory device according to a first embodiment of the present invention. [Figure 6] 1A to 1C are schematic diagrams illustrating a method for manufacturing a memory device according to an embodiment of the present invention. [Figure 7] 7A and 7B are schematic diagrams (top schematic views corresponding to FIG. 6) showing a method for manufacturing a memory device according to an embodiment of the present invention. [Figure 8] 7 is a schematic diagram showing a method for manufacturing a memory device according to an embodiment of the present invention (a schematic diagram of the next step in FIG. 6). [Figure 9] 9 is a schematic diagram showing a method for manufacturing a memory device according to an embodiment of the present invention (a schematic diagram of a step subsequent to that of FIG. 8); [Figure 10] 10 is a schematic diagram showing a method for manufacturing a memory device according to an embodiment of the present invention (a schematic diagram of a step subsequent to that of FIG. 9); [Figure 11] 11 is a schematic diagram showing a method for manufacturing a memory device according to an embodiment of the present invention (a schematic diagram of the next step of FIG. 10). [Figure 12] 12 is a schematic diagram showing a method for manufacturing a memory device according to an embodiment of the present invention (a schematic diagram of the next step of FIG. 11). [Figure 13] FIG. 4 is a schematic diagram illustrating a memory device according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] The present invention has been shown and described with respect to particular embodiments and its specific features. The embodiments described herein below should be construed as illustrative and not limiting. It will be apparent to those skilled in the art that various changes and modifications in form and detail can be made therein without departing from the spirit and scope of the invention.

[0009] Before further describing the preferred embodiment, the following definitions are provided for terms used throughout the text.

[0010] The terms "on," "above," and "over" as used herein should be interpreted in the broadest manner, such that "on" not only means "directly on" something, but also includes the meaning "on" something with an intervening object or layer, and "above" or "over" not only means "on" or "on" something, but also means "on" or "on" something without an intervening object or layer (i.e., directly on top of something).

[0011] As used in this specification and claims, ordinal numbers such as "first," "second," etc. are used to modify elements of a claim, and as such, unless specifically stated, do not imply or represent that the claim has any preceding ordinal number, nor do they represent the order of one element in a claim relative to another, nor do they represent an order in a manufacturing process. The use of these ordinal numbers is used solely to distinguish a claimed element with a certain name from another claimed element with the same name.

[0012] The term "etching" is used herein to describe a process of patterning a material layer such that at least a portion of the material layer is retained after etching. When a material layer is "etched," at least a portion of the material layer is retained after processing is completed. In contrast, when a material layer is "removed," substantially all of the material layer is removed in the process. However, in some embodiments, "removal" may be considered a broad term and may include etching.

[0013] The terms "forming" or "depositing" are used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any possible layer formation technique, including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0014] Please refer to FIGS. 1 to 5. FIG. 1 is a schematic diagram showing a memory device 101 according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view showing the memory device according to this embodiment. FIG. 3 is another schematic cross-sectional view showing the memory device according to this embodiment. FIG. 4 is yet another schematic cross-sectional view showing the memory device according to this embodiment. FIG. 5 is a partially enlarged schematic view showing the memory device according to this embodiment. FIGS. 1 and 5 are schematic top views of the memory device. FIG. 2 can be considered a cross-sectional view taken along line A-A' in FIG. 1, FIG. 3 can be considered a cross-sectional view taken along line B-B' in FIG. 1, and FIG. 4 can be considered a cross-sectional view taken along line C-C' in FIG. 1. However, in order to more clearly show structural features in the plan views, some components corresponding to those shown in the cross-sectional views are not shown in the plan views. As shown in FIGS. 1 to 5, the memory device 101 includes a semiconductor substrate 10, a floating gate FG, and an erase gate EG. The floating gate FG and the erase gate EG are disposed above the semiconductor substrate 10, and the erase gate EG has a main portion MP and a branch portion BP (e.g., a first branch portion BP1). The main portion MP extends in a first horizontal direction D1, and the first branch portion BP1 extends in a second horizontal direction D2 and is connected to the main portion MP. A first portion F1 of the floating gate FG is located below the first branch portion BP1 in the vertical direction D3. The design of the erase gate EG, including the branch portion BP, can increase the area between the edge of the floating gate FG and the edge of the erase gate EG for electrical coupling and / or Fowler-Nordheim tunneling (FN tunneling) to occur, thereby improving the programming and erasing speeds of the memory device 101 and / or improving the operating window of the memory device 101 by relatively reducing the operating voltage of the memory device 101.

[0015] In some embodiments, the memory device 101 includes a plurality of floating gates FG spaced apart from one another, and an erase gate EG includes a plurality of branches BP, each of which extends in the second horizontal direction D2 and is directly connected to a main portion MP. Portions of the floating gates FG are located on opposing sides of the erase gate EG in the second horizontal direction D2, and portions of the branches BP are located on opposing sides of the main portion MP in the second horizontal direction D2. The erase gate EG has a fishbone shape in a plan view of the memory device 101, and the first horizontal direction D1 is substantially perpendicular to the second horizontal direction D2, but is not limited thereto. In the plan view of the memory device 101, each floating gate FG is arranged corresponding to two branches BP and partially overlaps these two branches BP in the vertical direction D3. The two branches BP arranged corresponding to the same floating gate FG can be considered as a first branch BP1 and a second branch BP2, respectively. The erase gate EG therefore includes a second branch part BP2 extending in a second horizontal direction D2 and connected to the main part MP, and a second part F2 of the floating gate FG is arranged below the second branch part BP2 in the vertical direction D3.

[0016] Specifically, the vertical direction D3 can be considered the thickness direction of the semiconductor substrate 10. The semiconductor substrate 10 has a top surface and a bottom surface 10BS opposite the top surface in the vertical direction D3. The floating gate FG and erase gate EG may be disposed on the top surface. A horizontal direction substantially perpendicular to the vertical direction D3 (e.g., a first horizontal direction D1 and / or a second horizontal direction D2) is substantially parallel to the top surface and / or bottom surface 10BS of the semiconductor substrate 10, but is not limited thereto. Here, the distance between the bottom surface 10BS of the semiconductor substrate 10 and a relatively high position and / or a relatively high portion in the vertical direction D3 is greater than the distance between the bottom surface 10BS of the semiconductor substrate 10 and a relatively low position and / or a relatively low portion in the vertical direction D3. The lower end or bottom of each component may be closer to the bottom surface 10BS of the semiconductor substrate 10 in the vertical direction D3 than the upper end or top of the component. A component arranged above a certain component can be considered to be relatively far from the bottom surface 10BS of the semiconductor substrate 10 in the vertical direction D3, and a component arranged below a certain component can be considered to be relatively close to the bottom surface 10BS of the semiconductor substrate 10 in the vertical direction D3, but this is not limited to this. It should be noted that, in this specification, the top surface of a certain component may include the uppermost surface of this component in the vertical direction D3, and the bottom surface of a certain component may include the lowermost surface of this component in the vertical direction D3, but is not limited to this. Furthermore, in this specification, the term "arranged between two other components in a certain direction" may include, but is not limited to, the term "sandwiched between the other two components in that direction."

[0017] In some embodiments, the memory device 101 further includes a patterned mask layer HM disposed above the semiconductor substrate 10, with the floating gate FG being partially disposed between the patterned mask layer HM and the semiconductor substrate 10 in the vertical direction D3, and the patterned mask layer HM including a first portion H1 and a second portion H2. The first portion H1 extends in the first horizontal direction D1, and the second portion H2 extends in the second horizontal direction D2 and is connected to the first portion H1 of the patterned mask layer HM. In some embodiments, the memory device 101 includes two patterned mask layers HM disposed on either side of the erase gate EG in the second horizontal direction D2, with each patterned mask layer HM including multiple second portions H2 connected to the first portion H1, and each second portion H2 extending from an edge of the first portion H1 in the second horizontal direction D2 toward the main portion MP of the erase gate EG. In a plan view of the memory device 101, each of the first portions H1 is arranged to correspond to and partially overlap one of the multiple floating gates FG in the vertical direction D3, and each of the second portions H2 is arranged to correspond to and partially overlap one of the multiple floating gates FG in the vertical direction D3, and each of the second portions H2 may be located between two branches BP (e.g., the first branch BP1 and the second branch BP2) of the erase gate EG in the first horizontal direction D1.

[0018] In some embodiments, a portion of the floating gate FG may be defined by the patterned mask layer HM and spacers (not shown in FIGS. 1-5) on the sidewalls of the patterned mask layer HM, and the areas of the first and second portions F1 and F2 of the floating gate FG are appropriately affected by the position of the second portion H2 of the patterned mask layer HM. For example, in a plan view of the memory device 101, when the center line of the second portion H2 in the first horizontal direction D1 overlaps with the center line of the corresponding floating gate FG in the first horizontal direction D1, the length L11 of the first portion F1 of the floating gate FG in the first horizontal direction D1 is substantially the same as the length L12 of the second portion F2 of the floating gate FG in the first horizontal direction D1. In contrast, when an alignment shift occurs in the process of forming the patterned mask layer HM, the length L11 of the first portion F1 of the floating gate FG in the first horizontal direction D1 differs from the length L12 of the second portion F2 of the floating gate FG in the first horizontal direction D1. Furthermore, the length L2 in the first horizontal direction D1 of the second portion H2 of the patterned mask layer HM is shorter than the length L1 in the first horizontal direction D1 of the floating gate FG, and the third portion F3 of the floating gate FG is disposed below the main portion MP of the erase gate EG in the vertical direction D3, and the length L13 in the first horizontal direction D1 of the third portion F3 of the floating gate FG is substantially the same as the length L1 in the first horizontal direction D1 of the floating gate FG. Therefore, the length L13 in the first horizontal direction D1 of the third portion F3 of the floating gate FG is greater than the length L11 in the first horizontal direction D1 of the first portion F1 of the floating gate FG, the length L12 in the first horizontal direction D1 of the second portion F2 of the floating gate FG, and the length L2 in the first horizontal direction D1 of the second portion H2 of the patterned mask layer HM.

[0019] In some embodiments, the semiconductor substrate 10 may include a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a semiconductor substrate made of other suitable semiconductor materials and / or other suitable structures. The memory device 101 may also include an isolation structure 12 disposed within the semiconductor substrate 10 and defining an active region 10A within the semiconductor substrate 10. The active region 10A may be a portion of the semiconductor substrate 10, and accordingly, the material composition of the active region 10A may be the same as the material composition of the semiconductor substrate 10. The isolation structure 12 may include, but is not limited to, a single layer or multiple layers of insulating material, such as an insulating liner layer and an insulating gap-fill material disposed on the insulating liner layer. In some embodiments, the active region 10A includes a first portion extending in a first horizontal direction D1 and multiple second portions intersecting the first portion and extending in a second horizontal direction D2. A floating gate FG is disposed over a second portion of the active area 10A, and an erase gate EG is disposed over the active area 10A and the isolation structure 12. In some embodiments, the floating gate FG and the erase gate EG may be made of polycrystalline silicon or other suitable conductive material, the floating gate FG may be electrically floating without being directly connected to other conductive materials, and the patterned mask layer HM may include a nitride insulating material (e.g., silicon nitride) or other suitable insulating material. In some embodiments, the top surface TS1 of the erase gate EG and the top surface TS2 of the patterned mask layer HM may be substantially coplanar, and the erase gate EG including the branch portion BP replaces the control gate for programming operations (e.g., using the portion of the erase gate EG that overlaps with the floating gate FG in the vertical direction D3 to generate electrical coupling), so that no control gate is additionally disposed in the memory device 101, including, but not limited to, the embodiments described above.

[0020] In some embodiments, the memory device 101 may further include source line regions SL, bit line regions BL, word line structures WL, dielectric layer 14, dielectric layer 18, dielectric layer 26, dielectric layer 30, dielectric layer 32, dielectric layer 34, dielectric layer 36, dielectric layer 38, dielectric layer 40, and multiple contact structures (such as contact structure CT1, contact structure CT2, and contact structure CT3). The source line regions SL and the bit line regions BL are disposed in the semiconductor substrate 10, and the source line regions SL may be disposed corresponding to the erase gate EG in the vertical direction D3. The source line regions SL and the bit line regions BL may each be a doped region, for example, a heavily n-type doped region, formed in the semiconductor substrate 10. The dielectric layers 14, 18, 26, 30, 32, 34, and 36 may each include an oxide dielectric material or another suitable dielectric material. A portion of dielectric layer 14 may be located between floating gate FG and semiconductor substrate 10 in vertical direction D3, dielectric layer 18 may be located between patterned mask layer HM and floating gate FG in vertical direction D3, dielectric layer 30 may be located between erase gate EG and source line region SL, and dielectric layer 32 may be located partially between erase gate EG and floating gate FG and partially between erase gate EG and patterned mask layer HM. Word line structures WL and dielectric layer 26 may be located on dielectric layer 14, and dielectric layer 26 may be located partially between word line structures WL and floating gate FG or partially between word line structures WL and patterned mask layer HM. Dielectric layer 36 may cover word line structures WL, dielectric layer 26, patterned mask layer HM, and erase gate EG, dielectric layer 38 may cover sidewalls of bit line regions BL and word line structures WL, and dielectric layer 34 may be located between dielectric layer 38 and word line structures WL. Dielectric layer 40 may cover dielectric layer 36 and dielectric layer 38 .Contact structure CT1, contact structure CT2, and contact structure CT3 may be electrically connected to erase gate EG, word line structure WL, and bit line region BL, respectively, through corresponding dielectric layers. Dielectric layer 38 may include a nitride dielectric material or other suitable dielectric material, and dielectric layer 40 may include one or more layers of a dielectric material, such as an oxide dielectric material, a nitride dielectric material, an oxynitride dielectric material, or other suitable dielectric material. Word line structure WL includes polycrystalline silicon or other suitable conductive material, and each of the contact structures includes a barrier layer and a low-resistivity material disposed on the barrier layer. The low-resistivity material includes a material with a relatively low electrical resistivity, such as copper, aluminum, or tungsten, and the barrier layer includes, but is not limited to, titanium nitride, tantalum nitride, or other suitable conductive barrier material.

[0021] In some embodiments, the memory device 101 may include two patterned mask layers HM, two word line structures WL, and two bit line regions BL, each disposed on either side of the erase gate EG in the second horizontal direction D2. The floating gate FG may be disposed on either side of the erase gate EG in the second horizontal direction D2. One of the floating gate FG and the erase gate EG, the word line structure WL disposed corresponding to the floating gate FG, the source line region SL, the bit line region BL, the dielectric layer 26, the dielectric layer 30, and the dielectric layer 32 may constitute a memory cell. The erase gate EG may be shared by, but is not limited to, memory cells adjacent to each other in the first horizontal direction D1 and / or memory cells adjacent to each other in the second horizontal direction D2. In some embodiments, the memory device 101 may be considered an embedded flash memory (flash) structure. Eliminating a control gate in the memory device 101 may improve, but is not limited to, integration of the manufacturing process between the memory device 101 and other units formed on the semiconductor substrate 10. The erase gate EG including the branch portion BP of the present invention may also be applied to other types of memory devices depending on design considerations.

[0022] Please refer to FIGS. 6 to 12 and FIGS. 1 to 5. FIGS. 6 to 12 are schematic diagrams illustrating a method for manufacturing a memory device according to an embodiment of the present invention. FIG. 7 is a schematic top view corresponding to FIG. 6. FIG. 8 is a schematic diagram of a step subsequent to FIG. 6. FIG. 9 is a schematic diagram of a step subsequent to FIG. 8. FIG. 10 is a schematic diagram of a step subsequent to FIG. 9. FIG. 11 is a schematic diagram of a step subsequent to FIG. 10. FIG. 12 is a schematic diagram of a step subsequent to FIG. 11. In some embodiments, FIG. 3 can be considered as a schematic diagram of a step subsequent to FIG. 12, but is not limited thereto. Also, in order to more clearly show the structural features of the plan view (FIG. 7), some components in FIG. 6 are not shown corresponding to the plan view. As shown in FIGS. 1 to 5, the manufacturing method of this embodiment includes the following steps: A semiconductor substrate 10 is provided, and a floating gate FG and an erase gate EG are formed above the semiconductor substrate 10. The erase gate EG includes a main portion MP and a first branch portion BP1. The main part MP extends in a first horizontal direction D1, and the first branch part BP1 extends in a second horizontal direction D2 and is connected to the main part MP. A first part F1 of the floating gate FG is located below the first branch part BP1 in the vertical direction D3.

[0023] Specifically, the manufacturing method of the present invention may include, but is not limited to, the following steps. As shown in FIGS. 6 and 7 , a dielectric layer 14, a patterned material layer 16, and a dielectric layer 18 may be formed above the semiconductor substrate 10, and a patterned mask layer HM and a dielectric layer 20 may be formed above the semiconductor substrate 10 after the patterned material layer 16 is formed. In some embodiments, an isolation structure 12 is formed in the semiconductor substrate 10 to define an active region 10A within the semiconductor substrate 10, and the isolation structure 12 is formed by forming a trench in the semiconductor substrate 10 and filling the trench with an insulating material. Furthermore, the dielectric layer 14, the dielectric layer 18, and the material layer sandwiched between the dielectric layer 14 and the dielectric layer 18 may be patterned together by the trench-forming process described above. Therefore, the material layer sandwiched between the dielectric layer 14 and the dielectric layer 18 may be patterned into a patterned material layer 16, which may be, but is not limited to, arranged substantially corresponding to the active region 10A in the vertical direction D3. Furthermore, patterned mask layer HM may include the above-described first portion H1 and second portion H2, where second portion H2 may be formed on active region 10A and patterned material layer 16 in vertical direction D3, and first portion H1 may be formed above isolation structure 12 and patterned material layer 16. Thus, patterned mask layer HM may be partially formed above patterned material layer 16 in vertical direction D3, and may be partially formed above isolation structure 12 in vertical direction D3.

[0024] As shown in FIGS. 6 and 8 , spacers 22 are formed on the sidewalls of the patterned mask layer HM, and the spacers 22 comprise an oxide dielectric material or other suitable dielectric material. In some embodiments, portions of the dielectric layer 20 and the dielectric layer 18 may be removed by an etching process (e.g., but not limited to, a dry etching process) to form the spacers 22, and portions of the patterned material layer 16 may be exposed accordingly. Subsequently, as shown in FIGS. 8 and 9 , a removal process 91 may be performed to remove portions of the spacers 22, and other portions of the spacers 22 may remain on the sidewalls of the second portion H2 of the patterned mask layer HM after the removal process 91. In some embodiments, before the removal process 91, a patterned mask layer 24 may be formed on the semiconductor substrate 10, and the patterned mask layer 24 may cover the spacers 22 and at least a portion of the patterned mask layer HM located on the sidewalls of the second portion H2 of the patterned mask layer HM. In some embodiments, the removal process 91 may include an etching process (such as, but not limited to, a wet cleaning process), and the patterned mask layer 24 can be used as an etching mask in the etching process, where the patterned mask layer 24 can include patterned photoresist or other suitable mask material. As shown in FIGS. 9 and 10 , after the removal process 91, the patterned mask layer 24 is removed, and an etching process 92 is performed on the patterned material layer 16 using the patterned mask layer HM and the spacers 22 (e.g., the spacers 22 located on the sidewalls of the second portion H2 of the patterned mask layer HM) as a mask, and at least a portion of the patterned material layer 16 is etched by the etching process 92 to become the floating gate FG. That is, the removal process 91 is performed before the etching process 92, and the projection pattern of the floating gate FG in the vertical direction D3 is affected by the shapes of the patterned mask layer HM and the spacers 22 and the positions where the patterned mask layer HM and the spacers 22 are formed.It should be noted that the method for forming the floating gate FG in the present invention may include, but is not limited to, the steps shown in Figures 6 to 10 above, and the floating gate FG may be formed by other suitable techniques according to some design considerations.

[0025] As shown in FIG. 11 , after forming floating gate FG, dielectric layer 26 may be formed on the sidewalls of patterned mask layer HM and floating gate FG, and dielectric layer 26 may be considered a spacer formed on the sidewall. In some embodiments, dielectric layer 26 may be formed by forming a dielectric material and performing an etch-back process on the dielectric material, and dielectric layer 28 may be formed on patterned mask layer HM. As shown in FIGS. 11 and 12 , the spacers, portions of dielectric layer 26, portions of dielectric layer 28, and portions of dielectric layer 14 remaining on the sidewalls of second portion H2 of patterned mask layer HM may be removed to expose portions of active region 10A. Subsequently, as shown in FIGS. 3 and 1 , the erase gate EG, source line region SL, bit line region BL, word line structure WL, dielectric layer 30, dielectric layer 32, dielectric layer 34, dielectric layer 36, dielectric layer 38, dielectric layer 40, and contact structure described above may be formed to form memory device 101. That is, after the etching process 92 shown in FIG. 10 , the spacers 22 remaining on the sidewalls of the second portion H2 of the patterned mask layer HM may be removed before forming the erase gate EG. In some embodiments, the method of forming the erase gate EG and the word line structures WL may include performing a planarization process (e.g., but not limited to, a chemical-mechanical polishing process) on a conductive material (e.g., but not limited to, polycrystalline silicon) formed on the semiconductor substrate 10. This planarization process may remove the dielectric layer 28, a portion of the patterned mask layer HM, and a portion of the dielectric layer 26 shown in FIG. 12 , so that the top surface TS of the erase gate EG, the top surface TS2 of the patterned mask layer HM, and the top surfaces of the word line structures WL are substantially coplanar.

[0026] The following description will explain different embodiments of the present invention in detail. For ease of explanation, the same components in the following embodiments are denoted by the same reference numerals. To facilitate understanding of the differences between the embodiments, the following description will explain the differences between the different embodiments in detail, without redundantly explaining the commonalities.

[0027] Please refer to FIG. 13. FIG. 13 is a schematic diagram illustrating a memory device 102 according to a second embodiment of the present invention. As shown in FIG. 13, in the memory device 102, the length L11 in the first horizontal direction D1 of the first portion F1 of the floating gate FG may be different from the length L12 in the first horizontal direction D1 of the second portion F2 of the floating gate FG. For example, if the position where the patterned mask layer HM is formed shifts in the first horizontal direction D1 toward the bottom of FIG. 13, the length L11 in the first horizontal direction D1 of the first portion F1 shown in FIG. 13 may be greater than the length L12 in the first horizontal direction D1 of the second portion F2 shown in FIG. 13, but is not limited thereto. Furthermore, the floating gate FG may be affected by the position where the patterned mask layer HM is formed. The length L1 in the first horizontal direction D1 of the floating gate FG is considered to be the maximum length in the first horizontal direction D1 of the floating gate FG, and the length L13 in the first horizontal direction D1 of the third portion F3 of the floating gate FG may be less than the length L1, but is not limited thereto.

[0028] In summary, the memory device and method of the present invention may use an erase gate including a branch to increase the area between the edge of the floating gate and the edge of the erase gate for electrical coupling and / or FN tunneling, thereby improving the programming and erasing speeds of the memory device and / or relatively reducing the operating voltage of the memory device to improve the operating window of the memory device.

[0029] Those skilled in the art will recognize that numerous modifications and variations of the apparatus and method may be made while retaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. a semiconductor substrate; a floating gate disposed above the semiconductor substrate; an erase gate disposed above the semiconductor substrate, a main portion extending in a first horizontal direction; an erase gate having a first branch extending in a second horizontal direction and coupled to the main portion, the first branch having a first portion of the floating gate disposed vertically below the first branch; A memory device having:

2. 2. The memory device of claim 1, wherein the erase gate further includes a second branch extending in the second horizontal direction and connected to the main portion, the second branch being disposed below the second branch in the vertical direction with a second portion of the floating gate.

3. 3. The memory device of claim 2, wherein the first horizontal length of the first portion of the floating gate is different from the first horizontal length of the second portion of the floating gate.

4. a patterned mask layer disposed above the semiconductor substrate, the floating gate being vertically disposed partially between the patterned mask layer and the semiconductor substrate; a first portion extending in the first horizontal direction; a second portion extending in the second horizontal direction and connected to the first portion of the patterned mask layer, the second portion of the patterned mask layer being sandwiched in the first horizontal direction between the first branch of the erase gate and the second branch of the erase gate. The memory device of claim 2 further comprising said patterned mask layer.

5. 5. The memory device of claim 4, wherein the first horizontal extent of the second portion of the patterned mask layer is less than the first horizontal extent of the floating gate.

6. 5. The memory device of claim 4, wherein a third portion of the floating gate is disposed vertically below the main portion of the erase gate.

7. 7. The memory device of claim 6, wherein the first horizontal length of the third portion of the floating gate is greater than the first horizontal length of the first portion of the floating gate and the first horizontal length of the second portion of the floating gate.

8. 7. The memory device of claim 6, wherein the first horizontal extent of the third portion of the floating gate is greater than the first horizontal extent of the second portion of the patterned mask layer.

9. 5. The memory device of claim 4, wherein a top surface of the erase gate and a top surface of the patterned mask layer are coplanar.

10. The memory device of claim 1 , wherein the first horizontal direction is orthogonal to the second horizontal direction.

11. Providing a semiconductor substrate; forming a floating gate above the semiconductor substrate; forming an erase gate disposed above the semiconductor substrate, the erase gate comprising: a main portion extending in a first horizontal direction; a first branch extending in a second horizontal direction and coupled to the main portion, the first portion of the floating gate having the first branch disposed vertically below the first branch; A method for manufacturing a memory device.

12. The method for forming the floating gate includes: forming a patterned layer of material over the semiconductor substrate; forming a patterned mask layer over the semiconductor substrate after the patterned material layer is formed, the patterned mask layer being partially formed vertically above the patterned material layer; forming spacers on sidewalls of the patterned mask layer; performing an etching process on the patterned material layer using the patterned mask layer and the spacers as a mask, wherein the etching process etches at least a portion of the patterned material layer into the floating gate. The method for manufacturing a memory device according to claim 11 .

13. The patterned mask layer comprises: a first portion extending in the first horizontal direction; a second portion extending in the second horizontal direction and connected to the first portion of the patterned mask layer. The method for manufacturing a memory device according to claim 12.

14. 14. The method of claim 13, wherein the method of forming the floating gate further comprises performing a removal process to remove a portion of the spacer before the etching process, wherein after the removal process, another portion of the spacer remains on a sidewall of the second portion of the patterned mask layer.

15. 15. The method of claim 14, further comprising removing the other portions of the spacers remaining on the sidewalls of the second portions of the patterned mask layer after the etching process and before forming the erase gate.

16. 14. The method of claim 13, wherein the first horizontal length of the second portion of the patterned mask layer is less than the first horizontal length of the floating gate.

17. 14. The method of claim 13, wherein the erase gate further comprises a second branch extending in the second horizontal direction and connected to the main portion, the second portion of the floating gate being disposed below the second branch in the vertical direction.

18. 20. The method of claim 17, wherein the second portion of the patterned mask layer is sandwiched between the first branch of the erase gate and the second branch of the erase gate in the first horizontal direction.

19. 20. The method of claim 17, wherein the first horizontal length of the first portion of the floating gate is different from the first horizontal length of the second portion of the floating gate.

20. 12. The method of claim 11, wherein the first horizontal direction is perpendicular to the second horizontal direction.

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