Solid-state imaging apparatus

Abstract

To provide a solid-state imaging apparatus capable of suppressing a motion artifact and more accurately measuring a distance up to a subject.SOLUTION: The solid-state imaging apparatus includes: a pixel 100 having a photoelectric conversion part 110 for generating an electric charge by photoelectrically converting light, a plurality of charge accumulation parts 211 to 214 for accumulating the electric charge, and a plurality of transfer control parts 221 to 224 for controlling transfer of the electric charge from the photoelectric conversion part to each charge accumulation part; a converter 140 for generating a digital value corresponding to the amount of the electric charge accumulated in the charge accumulation part; an adder 140 for adding the generated digital value to a digital value previously held in memories 151 to 154; and a drive part for controlling the plurality of transfer control parts so that the digital value corresponding to the amount of the electric charge accumulated in one charge accumulation part in a specific sub-frame and the digital value corresponding to the amount of the electric charge accumulated in another charge accumulation part in the next sub-frame are added to each other and the added value of the digital values is held in the memory.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a solid-state imaging device. [Background technology]

[0002] There is a growing demand for TOF (Time Of Flight) technology in the fields of 3D measurement and object recognition.

[0003] The TOF technology uses a multi-tap image sensor having pixels with multiple charge storage portions (for example, see Patent Document 1). The multi-tap image sensor makes it possible to measure the distance to a subject with high accuracy. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2015 / 118884 Summary of the Invention [Problem to be solved by the invention]

[0005] In a multi-tap image sensor, the multiple charge storage sections provided in each pixel must all have the same characteristics.

[0006] However, due to the characteristics of semiconductor manufacturing technology, it is difficult to manufacture all charge storage units identically, and there are variations in the characteristics of multiple charge storage units. As a result, in general multi-tap image sensors, there is a problem of reduced measurement accuracy due to variations in tap characteristics.

[0007] Furthermore, in a typical multi-tap image sensor, pixel signals are read out row by row for each subframe obtained by time-dividing one frame, which results in a long readout time, and therefore the typical multi-tap image sensor may undesirably produce motion artifacts.

[0008] The present invention has been made in view of the above-mentioned problems, and therefore an object of the present invention is to provide a solid-state imaging device that can suppress motion artifacts and measure the distance to a subject with higher accuracy. [Means for solving the problem]

[0009] The above object of the present invention can be achieved by the following means.

[0010] (1) A solid-state imaging device comprising: pixels each having a photoelectric conversion unit that photoelectrically converts light to generate an electric charge; a plurality of charge accumulation units that accumulate the electric charge generated by the photoelectric conversion unit; and a plurality of transfer control units that control the transfer of the electric charge from the photoelectric conversion unit to each of the charge accumulation units; a converter that is provided in common to one pixel or a predetermined number of pixels and generates a digital value corresponding to the amount of electric charge accumulated in the charge accumulation unit; a memory that is provided in common to one pixel or a predetermined number of pixels and stores the digital value; an adder that is provided in common to one pixel or a predetermined number of pixels and adds the digital value generated by the converter to a digital value previously stored in the memory; and a drive unit that controls the operation of the plurality of transfer control units so that a digital value corresponding to the amount of electric charge accumulated in one of the charge accumulation units in a specific subframe is added to a digital value corresponding to the amount of electric charge accumulated in another of the charge accumulation units in a next subframe, and the added value of the digital values ​​is stored in the memory.

[0011] (2) The solid-state imaging device according to (1), wherein each of the transfer control units is turned on at a different phase timing for each of a plurality of consecutive subframes.

[0012] (3) The solid-state imaging device according to (1) or (2), wherein the plurality of transfer control units are turned on in a different order for each of a plurality of consecutive subframes.

[0013] (4) A solid-state imaging device as described in (1) or (2) above, wherein the memory holds the sum of multiple digital values ​​corresponding to the amount of charge stored in each of multiple different charge storage sections in multiple consecutive subframes.

[0014] (5) A solid-state imaging device as described in (1) or (2) above, wherein the memory holds the sum of multiple digital values ​​corresponding to the amount of charge stored in each of multiple different charge storage sections at the same phase timing in multiple consecutive subframes.

[0015] (6) A solid-state imaging device as described in (1) or (2) above, wherein the memory holds a differential value between the sum of multiple digital values ​​corresponding to the amount of charge stored in each of multiple different charge storage units at one phase timing in multiple consecutive subframes, and the sum of multiple digital values ​​corresponding to the amount of charge stored in each of multiple different charge storage units at another phase timing.

[0016] (7) The solid-state imaging device according to (1) or (2) above, further comprising a charge memory disposed between the charge storage section and the transfer control section, for holding the charges generated by the photoelectric conversion section.

[0017] (8) The solid-state imaging device according to (1) or (2), wherein at least one of the converter, the memory, and the adder is provided in common to a predetermined number of pixels.

[0018] (9) The solid-state imaging device according to (1) or (2) above, wherein the converter and the adder are integrally configured.

[0019] (10) The solid-state imaging device according to (1) or (2), wherein the adder includes a ripple counter.

[0020] (11) The solid-state imaging device according to (1) or (2), wherein a plurality of the memories are provided for each pixel.

[0021] (12) The solid-state imaging device according to (1) or (2), wherein the memory includes an SRAM or a DRAM.

[0022] (13) The solid-state imaging device according to (1) or (2), wherein the pixel has two of the photoelectric conversion units.

[0023] (14) The solid-state imaging device according to (1) or (2) above, wherein a first layer in which the photoelectric conversion section is provided and a second layer in which the memory is provided are stacked. [Effects of the Invention]

[0024] According to the solid-state imaging device of the present invention, it is possible to suppress motion artifacts and measure the distance to the subject with higher accuracy. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a diagram showing a schematic configuration of a TOF system to which a solid-state imaging device is applied. [Figure 2] 1 is a circuit diagram showing a schematic configuration of a pixel of a solid-state imaging device according to a first embodiment. [Figure 3] FIG. 2 is a diagram for explaining the operation of a pixel of the solid-state imaging device. [Figure 4] 10A and 10B are diagrams for explaining the effects of the solid-state imaging device; [Figure 5] 10A and 10B are diagrams for explaining the effects of a solid-state imaging device having a general column ADC. [Figure 6] FIG. 1 is a diagram showing a schematic configuration of a solid-state imaging device having a general column ADC. [Figure 7] FIG. 10 is a circuit diagram showing a schematic configuration of a pixel of a solid-state imaging device according to a second embodiment. [Figure 8] FIG. 2 is a diagram for explaining the operation of a pixel of the solid-state imaging device. [Figure 9] FIG. 10 is a circuit diagram showing a schematic configuration of a pixel of a solid-state imaging device according to a third embodiment. [Figure 10]FIG. 2 is a diagram for explaining the operation of a pixel of the solid-state imaging device. [Figure 11] FIG. 10 is a circuit diagram showing a schematic configuration of a pixel of a solid-state imaging device according to a fourth embodiment. [Figure 12] FIG. 10 is a diagram showing a schematic configuration of a solid-state imaging device according to a modified example. [Figure 13] FIG. 10 is a diagram showing a schematic configuration of a solid-state imaging device according to a modified example. [Figure 14] FIG. 10 is a diagram showing a schematic configuration of a solid-state imaging device according to a modified example. [Figure 15] FIG. 10 is a diagram showing a schematic configuration of a solid-state imaging device according to a modified example. [Figure 16] FIG. 10 is a diagram showing a schematic configuration of a solid-state imaging device according to a modified example. [Figure 17] FIG. 10 is a circuit diagram showing a schematic configuration of a pixel of a solid-state imaging device according to a fifth embodiment. [Figure 18] FIG. 10 is a diagram showing a schematic configuration of a solid-state imaging device according to a modified example. [Figure 19] FIG. 10 is a diagram showing a schematic configuration of a solid-state imaging device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience. Meanwhile, the embodiments described below are merely examples, and various modifications are possible from such embodiments.

[0027] Hereinafter, the terms "upper" and "above" may include not only what is directly above in contact with something, but also what is above without contact. Similarly, the terms "lower" and "below" may include not only what is directly below in contact with something, but also what is below without contact.

[0028] The singular expression includes the plural expression unless the context clearly dictates otherwise. Furthermore, when a part "includes," "comprises," or "has" a certain element, it does not mean that it excludes other elements, but that it may further include other elements, unless otherwise specified to the contrary.

[0029] Unless explicitly stated or stated to the contrary, steps constituting a method may be performed in any suitable order, and are not necessarily limited to the order of the steps described. The use of any examples or exemplary terms is merely for the purpose of illustrating the technical idea, and the scope of the invention is not limited by the claims, and should not be construed as being limited by said examples or exemplary terms.

[0030] In the following description, when ordinal numbers such as "first" and "second" are used, unless otherwise specified, they are used for convenience and do not stipulate any particular order.

[0031] (First embodiment) A solid-state imaging device according to a first embodiment of the present invention will be described below with reference to Fig. 1 to Fig. 6. Fig. 1 is a diagram showing a schematic configuration of a TOF system 1 to which a solid-state imaging device 20 according to the first embodiment is applied. As shown in Fig. 1, the TOF system 1 includes a light source device 10 and a solid-state imaging device 20.

[0032] The light source device 10 irradiates light L1 onto the subject 50. The light source device 10 is, for example, a semiconductor laser, and irradiates pulsed light in the near-infrared wavelength band onto the subject 50. The light source device 10 may include an optical element (not shown).

[0033] The solid-state imaging device 20 receives reflected light L2 from the subject 50 and measures a distance Dt to the subject 50. The solid-state imaging device 20 includes a pixel array 21, a drive unit 22, and a calculation unit 23. The pixel array 21 includes a plurality of pixels 100 arranged in an array. Each pixel 100 receives pulsed light reflected by the subject 50 and outputs a pixel signal corresponding to the received reflected light. The drive unit 22 is driven in synchronization with the light source device 10 and controls the operation of the transistors in the pixels 100. The calculation unit 23 calculates a distance Dt to the subject 50 from the pixel signal. The solid-state imaging device 20 may include optical elements (not shown). Note that, although the calculation unit 23 is provided within the solid-state imaging device 20 in FIG. 1, the calculation unit 23 may be provided outside the solid-state imaging device 20, for example, in an ISP (Image Signal Processor).

[0034] Next, the pixel 100 of the solid-state imaging device 20 will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing a schematic configuration of the pixel 100 of the solid-state imaging device 20. The pixel 100 of this embodiment has four taps A to D.

[0035] As shown in FIG. 2, the pixel 100 includes a photodiode (PD) 110, a charge discharging transistor 120, first to fourth signal generating units 131 to 134, an ADC (Analog to Digital Converter) integrator 140, first to fourth memories 151 to 154, and first to fourth memory selecting transistors 161 to 164.

[0036] The PD 110, as a photoelectric conversion unit, photoelectrically converts incident light to generate electric charges. The charge drain transistor 120 controls the draining of electric charges accumulated in the PD 110. The first to fourth signal generation units 131 to 134 output voltages having magnitudes corresponding to the amounts of electric charges generated by the PD 110. The ADC integrator 140 is an integrated configuration of a converter and an adder, and as a converter, converts the voltages output from the first to fourth signal generation units 131 to 134 into digital values. The ADC integrator 140 also functions as an adder, adding the converted digital values ​​to digital values ​​previously stored in the first to fourth memories 151 to 154. The first to fourth memories 151 to 154 store the digital values. The first to fourth memory selection transistors 161 to 164 switch the first to fourth memories 151 to 154 connected to the ADC integrator 140. The first to fourth memories 151 to 154 correspond to the four taps A to D.

[0037] The first to fourth signal generation units 131 to 134 have first to fourth floating diffusions (FD) 211 to 214, first to fourth transfer transistors 221 to 224, first to fourth source follower (SF) transistors 231 to 234, first to fourth reset transistors 241 to 244, and first to fourth signal selection transistors 251 to 254.

[0038] The first to fourth FDs 211 to 214 function as charge storage units and store charges generated by the PD 110. The first to fourth transfer transistors 221 to 224 function as transfer control units and control the transfer of charges from the PD 110 to the first to fourth FDs 211 to 214. The first to fourth SF transistors 231 to 234 output voltages of magnitudes corresponding to the amounts of charges stored in the FDs 211 to 214. The first to fourth reset transistors 241 to 244 perform control to reset the charges in the first to fourth FDs 211 to 214. The first to fourth signal selection transistors 251 to 254 switch the four SF transistors 231 to 234 connected to the ADC integrator 140.

[0039] The pixel 100 of this embodiment has a two-layer structure, with the PD 110, the charge discharging transistor 120, and the first to fourth signal generation units 131 to 134 (excluding the first to fourth signal selection transistors 251 to 254) being provided in a first layer, while the first to fourth signal selection transistors 251 to 254, the ADC integrator 140, the first to fourth memories 151 to 154, and the first to fourth memory selection transistors 161 to 164 being provided in a second layer.

[0040] In the pixel 100 of this embodiment configured as described above, the charge generated by the PD 110 is accumulated in the first to fourth FDs 211 to 214. Then, the ADC integrator 140 generates a digital value (for example, 0 to 127) according to the amount of charge accumulated in the first to fourth FDs 211 to 214, and adds the generated digital value to the digital values ​​previously stored in the first to fourth memories 151 to 154. Hereinafter, the operation of the solid-state imaging device 20 will be described in detail with reference to FIG. 3.

[0041] FIG. 3 is a diagram illustrating the operation of the pixel 100 of the solid-state imaging device 20. Note that the following description will be given taking as an example a case where one frame is composed of four sub-frames. Each sub-frame includes an exposure period and a readout period. In FIG. 3, "Laser" indicates the drive signal of the light source device 10, and "TG1" to "TG4" indicate the drive signals of the first to fourth transfer transistors 221 to 224, respectively. "SW1" to "SW4" indicate the drive signals of the first to fourth signal selection transistors 251 to 254, and "SWA" to "SWD" indicate the drive signals of the first to fourth memory selection transistors 161 to 164.

[0042] (1) First subframe (1-1) Exposure period During the exposure period of the first sub-frame, at the first phase timing t1, the light source device 10 is turned on and emits light. Also, at the first phase timing t1, the first transfer transistor 221 is turned on and the charge generated by the PD 110 is accumulated in the first FD 211 (first exposure operation).

[0043] Subsequently, at the second phase timing t2, the second transfer transistor 222 is turned on, and the charge generated by the PD 110 is accumulated in the second FD 212 (second exposure operation).

[0044] Subsequently, at the third phase timing t3, the third transfer transistor 223 is turned on, and the charge generated by the PD 110 is accumulated in the third FD 213 (third exposure operation).

[0045] Subsequently, at the fourth phase timing t4, the fourth transfer transistor 224 is turned on, and the charge generated by the PD 110 is accumulated in the fourth FD 214 (fourth exposure operation).

[0046] In the exposure period of the first sub-frame, the first to fourth exposure operations are regarded as one operation cycle MC, and the operation cycle MC is repeated a predetermined number of times.

[0047] (1-2) Readout period During the readout period of the first subframe, the first signal selection transistor 251 and the first memory selection transistor 161 are turned on (first readout operation: tap A). ​​As a result, a digital value according to the amount of charge accumulated in the first FD 211 is generated, and the generated digital value is added to the digital value held in the first memory 151.

[0048] Furthermore, the second signal selection transistor 252 and the second memory selection transistor 162 are turned on (second read operation: tap B). As a result, a digital value according to the amount of charge accumulated in the second FD 212 is generated, and the generated digital value is added to the digital value held in the second memory 152.

[0049] Furthermore, the third signal selection transistor 253 and the third memory selection transistor 163 are turned on (third read operation: tap C). As a result, a digital value according to the amount of charge accumulated in the third FD 213 is generated, and the generated digital value is added to the digital value held in the third memory 153.

[0050] Furthermore, the fourth signal selection transistor 254 and the fourth memory selection transistor 164 are turned on (fourth read operation: tap D). As a result, a digital value according to the amount of charge accumulated in the fourth FD 214 is generated, and the generated digital value is added to the digital value held in the fourth memory 154.

[0051] In the readout period of the first subframe, the order of the first to fourth readout operations can be changed.

[0052] (2) Second subframe (2-1) Exposure period During the exposure period of the second sub-frame, at the first phase timing t1 when the light source device 10 is turned on, the fourth transfer transistor 224 is turned on, and the charge generated by the PD 110 is accumulated in the fourth FD 214 (first exposure operation).

[0053] Subsequently, at the second phase timing t2, the first transfer transistor 221 is turned on, and the charge generated by the PD 110 is accumulated in the first FD 211 (second exposure operation).

[0054] Subsequently, at the third phase timing t3, the second transfer transistor 222 is turned on, and the charge generated by the PD 110 is accumulated in the second FD 212 (third exposure operation).

[0055] Subsequently, at the fourth phase timing t4, the third transfer transistor 223 is turned on, and the charge generated by the PD 110 is accumulated in the third FD 213 (fourth exposure operation).

[0056] In the exposure period of the second sub-frame, the first to fourth exposure operations are regarded as one operation cycle MC, and the operation cycle MC is repeated a predetermined number of times.

[0057] (2-2) Readout period During the readout period of the second subframe, the fourth signal selection transistor 254 and the first memory selection transistor 161 are turned on (first readout operation: tap A). ​​As a result, a digital value according to the amount of charge accumulated in the fourth FD 214 is generated, and the generated digital value is added to the digital value held in the first memory 151.

[0058] Furthermore, the first signal selection transistor 251 and the second memory selection transistor 162 are turned on (second read operation: tap B). As a result, a digital value according to the amount of charge accumulated in the first FD 211 is generated, and the generated digital value is added to the digital value held in the second memory 152.

[0059] Furthermore, the second signal selection transistor 252 and the third memory selection transistor 163 are turned on (third read operation: tap C). As a result, a digital value according to the amount of charge accumulated in the second FD 212 is generated, and the generated digital value is added to the digital value held in the third memory 153.

[0060] Furthermore, the third signal selection transistor 253 and the fourth memory selection transistor 164 are turned on (fourth read operation: tap D). As a result, a digital value according to the amount of charge accumulated in the third FD 213 is generated, and the generated digital value is added to the digital value held in the fourth memory 154.

[0061] In the readout period of the second subframe, the order of the first to fourth readout operations can be changed.

[0062] (3) Third subframe (3-1) Exposure period During the exposure period of the third sub-frame, at the first phase timing t1 when the light source device 10 is turned on, the third transfer transistor 223 is turned on, and the charge generated by the PD 110 is accumulated in the third FD 213 (first exposure operation).

[0063] Subsequently, at the second phase timing t2, the fourth transfer transistor 224 is turned on, and the charge generated by the PD 110 is accumulated in the fourth FD 214 (second exposure operation).

[0064] Subsequently, at the third phase timing t3, the first transfer transistor 221 is turned on, and the charge generated by the PD 110 is accumulated in the first FD 211 (third exposure operation).

[0065] Subsequently, at the fourth phase timing t4, the second transfer transistor 222 is turned on, and the charge generated by the PD 110 is accumulated in the second FD 212 (fourth exposure operation).

[0066] In the exposure period of the third sub-frame, the first to fourth exposure operations are defined as one operation cycle MC, and the operation cycle MC is repeated a predetermined number of times.

[0067] (3-2) Readout period During the readout period of the third subframe, the third signal selection transistor 253 and the first memory selection transistor 161 are turned on (first readout operation: tap A). ​​As a result, a digital value according to the amount of charge accumulated in the third FD 213 is generated, and the generated digital value is added to the digital value held in the first memory 151.

[0068] Furthermore, the fourth signal selection transistor 254 and the second memory selection transistor 162 are turned on (second read operation: tap B). As a result, a digital value according to the amount of charge accumulated in the fourth FD 214 is generated, and the generated digital value is added to the digital value held in the second memory 152.

[0069] Furthermore, the first signal selection transistor 251 and the third memory selection transistor 163 are turned on (third read operation: tap C). As a result, a digital value according to the amount of charge accumulated in the first FD 211 is generated, and the generated digital value is added to the digital value held in the third memory 153.

[0070] Furthermore, the second signal selection transistor 252 and the fourth memory selection transistor 164 are turned on (fourth read operation: tap D). As a result, a digital value according to the amount of charge accumulated in the second FD 212 is generated, and the generated digital value is added to the digital value held in the fourth memory 154.

[0071] In the readout period of the third subframe, the order of the first to fourth readout operations can be changed.

[0072] (4) Fourth subframe (4-1) Exposure period During the exposure period of the fourth sub-frame, at the first phase timing t1 when the light source device 10 is turned on, the second transfer transistor 222 is turned on, and the charge generated by the PD 110 is accumulated in the second FD 212 (first exposure operation).

[0073] Subsequently, at the second phase timing t2, the third transfer transistor 223 is turned on, and the charge generated by the PD 110 is accumulated in the third FD 213 (second exposure operation).

[0074] Subsequently, at the third phase timing t3, the fourth transfer transistor 224 is turned on, and the charge generated by the PD 110 is accumulated in the fourth FD 214 (third exposure operation).

[0075] Subsequently, at the fourth phase timing t4, the first transfer transistor 221 is turned on, and the charge generated by the PD 110 is accumulated in the first FD 211 (fourth exposure operation).

[0076] In the exposure period of the fourth sub-frame, the first to fourth exposure operations are regarded as one operation cycle MC, and the operation cycle MC is repeated a predetermined number of times.

[0077] (4-2) Readout period During the readout period of the fourth subframe, the second signal selection transistor 252 and the first memory selection transistor 161 are turned on (first readout operation: tap A). ​​As a result, a digital value according to the amount of charge accumulated in the second FD 212 is generated, and the generated digital value is added to the digital value held in the first memory 151.

[0078] Furthermore, the third signal selection transistor 253 and the second memory selection transistor 162 are turned on (second read operation: tap B). As a result, a digital value according to the amount of charge accumulated in the third FD 213 is generated, and the generated digital value is added to the digital value held in the second memory 152.

[0079] Furthermore, the fourth signal selection transistor 254 and the third memory selection transistor 163 are turned on (third read operation: tap C). As a result, a digital value according to the amount of charge accumulated in the fourth FD 214 is generated, and the generated digital value is added to the digital value held in the third memory 153.

[0080] Furthermore, the first signal selection transistor 251 and the fourth memory selection transistor 164 are turned on (fourth read operation: tap D). As a result, a digital value according to the amount of charge accumulated in the first FD 211 is generated, and the generated digital value is added to the digital value held in the fourth memory 154.

[0081] In the readout period of the fourth subframe, the order of the first to fourth readout operations can be changed.

[0082] As described above, according to the solid-state imaging device 20 of this embodiment, in each subframe, the amount of charge accumulated in the four FDs 211 to 214 is converted into a digital value and output. Then, in four consecutive subframes, the digital value indicating the amount of charge in the four FDs 211 to 214 is added to the digital value stored in the memories 151 to 154, which differ for each subframe.

[0083] Specifically, in the first subframe, a digital value indicating the amount of charge in the first FD 211 is added to the first memory 151 (tap A), and in the second subframe, a digital value indicating the amount of charge in the fourth FD 214 is added. Then, in the third subframe, a digital value indicating the amount of charge in the third FD 213 is added, and in the fourth subframe, a digital value indicating the amount of charge in the second FD 212 is added. As a result, the first memory 151 stores the sum (addition value) of four digital values ​​corresponding to the amounts of charge in the four different FDs 211 to 214. Note that these four digital values ​​indicate the amounts of charge accumulated in the FDs 211 to 214 at the same phase timing (first phase timing) in each subframe.

[0084] Similarly, in the second memory 152 (tap B), a digital value indicating the amount of charge in the second FD 212 is added in the first subframe, and a digital value indicating the amount of charge in the first FD 211 is added in the second subframe. Then, in the third subframe, a digital value indicating the amount of charge in the fourth FD 214 is added, and in the fourth subframe, a digital value indicating the amount of charge in the third FD 213 is added. As a result, the second memory 152 stores the sum (addition value) of four digital values ​​corresponding to the amounts of charge in the four different FDs 211 to 214. Note that these four digital values ​​indicate the amounts of charge accumulated in the FDs 211 to 214 at the same phase timing (second phase timing) in each subframe. The same applies to the third memory 153 and the fourth memory 154.

[0085] According to this configuration, the variations in the characteristics of the four FDs 211 to 214 are averaged in each of the taps A to D, thereby canceling the variations between the taps. Therefore, according to the solid-state imaging device 20 of this embodiment, it is possible to measure the distance to the subject with higher accuracy.

[0086] Next, the effects of the solid-state imaging device 20 will be described in more detail with reference to Figs. 4 to 6. Fig. 4 is a diagram for explaining the effects of the solid-state imaging device 20 according to this embodiment. Fig. 5 is a diagram showing the effects of a solid-state imaging device having a general column ADC as a comparative example. Fig. 6 is a diagram showing a solid-state imaging device having a general column ADC.

[0087] As shown in Figure 5, in a typical solid-state imaging device, the four transfer transistors that control the transfer of charges to the four FDs 1 to 4 are always turned on in the same order (TG1 → TG2 → TG3 → TG4). Therefore, in a typical solid-state imaging device, one FD is assigned to one tap, and variations in the characteristics of FDs 1 to 4 result in variations between the taps. As a result, a typical solid-state imaging device suffers from a problem of reduced measurement accuracy. In addition, a typical solid-state imaging device reads out pixel signals for n rows in units of pixel rows for each subframe, which increases the readout time and may result in motion artifacts.

[0088] On the other hand, in the solid-state imaging device 20 of this embodiment, the four transfer transistors 221-224 that control the transfer of charges to the four FDs 211-214 are turned on in a different order for each subframe. Therefore, the memories 151-154 corresponding to each tap store the sum (addition value) of digital values ​​corresponding to the amounts of charge accumulated in the four different FDs 211-214, averaging out variations in the characteristics of the four FDs 211-214. Therefore, in the solid-state imaging device 20 of this embodiment, variations between taps are canceled out, enabling more accurate measurement of the distance to the subject. Additionally, in the solid-state imaging device 20 of this embodiment, pixel signals are read out pixel by pixel using the memories 151-154 provided in the pixel 100, shortening the readout time and suppressing motion artifacts.

[0089] According to the solid-state imaging device 20 of this embodiment, the amount of charge accumulated in the four FDs 211 to 214 is converted into digital values ​​and added, thereby reducing the memory area. Furthermore, according to the solid-state imaging device 20 of this embodiment, the period of each subframe is shortened, thereby suppressing saturation of pixel signals caused by background light.

[0090] (Second embodiment) Next, a solid-state imaging device according to a second embodiment of the present invention will be described with reference to Figures 7 and 8. The solid-state imaging device according to the second embodiment differs from the solid-state imaging device according to the first embodiment in that each pixel has two PDs. Note that the same components as those in the first embodiment are denoted by the same reference numerals and their description will be omitted.

[0091] 7 is a circuit diagram showing a schematic configuration of a pixel 100 of a solid-state imaging device 20 according to this embodiment. As shown in FIG. 7, the pixel 100 includes first and second PDs 111 and 112, first and second charge discharging transistors 121 and 122, first to fourth signal generating units 131 to 134, an ADC integrator 140, first to fourth memories 151 to 154, and first to fourth memory selecting transistors 161 to 164. The first and second signal generating units 131 and 132 are connected to the first PD 111, and the third and fourth signal generating units 133 and 134 are connected to the second PD 112.

[0092] 8 is a diagram illustrating the operation of the pixel 100 of the solid-state imaging device 20. In this embodiment, one frame is composed of four subframes, and each subframe includes an exposure period and a readout period. The pulse signals indicating the phase timing are input with a shift of half a pulse.

[0093] (1) First subframe (1-1) Exposure period During the exposure period of the first sub-frame, at the first phase timing t1 when the light source device 10 is turned on, the first transfer transistor 221 is turned on, and the charge generated by the first PD 111 is accumulated in the first FD 211 (first exposure operation).

[0094] Subsequently, at the second phase timing t2, the third transfer transistor 223 is turned on, and the charge generated by the second PD 112 is accumulated in the third FD 213 (second exposure operation).

[0095] Subsequently, at the third phase timing t3, the second transfer transistor 222 is turned on, and the charge generated by the first PD 111 is accumulated in the second FD 212 (third exposure operation).

[0096] Subsequently, at the fourth phase timing t4, the fourth transfer transistor 224 is turned on, and the charge generated by the second PD 112 is accumulated in the fourth FD 214 (fourth exposure operation).

[0097] In the exposure period of the first sub-frame, the first to fourth exposure operations are regarded as one operation cycle, and this operation cycle is repeated a predetermined number of times.

[0098] (1-2) Readout period During the readout period of the first subframe, the first signal selection transistor 251 and the first memory selection transistor 161 are turned on (first readout operation: tap A). ​​As a result, a digital value according to the amount of charge accumulated in the first FD 211 is generated, and the generated digital value is added to the digital value held in the first memory 151.

[0099] Furthermore, the second signal selection transistor 252 and the second memory selection transistor 162 are turned on (second read operation: tap B). As a result, a digital value according to the amount of charge accumulated in the second FD 212 is generated, and the generated digital value is added to the digital value held in the second memory 152.

[0100] Furthermore, the third signal selection transistor 253 and the third memory selection transistor 163 are turned on (third read operation: tap C). As a result, a digital value according to the amount of charge accumulated in the third FD 213 is generated, and the generated digital value is added to the digital value held in the third memory 153.

[0101] Furthermore, the fourth signal selection transistor 254 and the fourth memory selection transistor 164 are turned on (fourth read operation: tap D). As a result, a digital value according to the amount of charge accumulated in the fourth FD 214 is generated, and the generated digital value is added to the digital value held in the fourth memory 154.

[0102] In the readout period of the first subframe, the order of the first to fourth readout operations can be changed.

[0103] (2) Second subframe (2-1) Exposure period During the exposure period of the second sub-frame, at the first phase timing t1 when the light source device 10 is turned on, the second transfer transistor 222 is turned on, and the charge generated by the first PD 111 is accumulated in the second FD 212 (first exposure operation).

[0104] Subsequently, at the second phase timing t2, the fourth transfer transistor 224 is turned on, and the charge generated by the second PD 112 is accumulated in the fourth FD 214 (second exposure operation).

[0105] Subsequently, at the third phase timing t3, the first transfer transistor 221 is turned on, and the charge generated by the first PD 111 is accumulated in the first FD 211 (third exposure operation).

[0106] Subsequently, at the fourth phase timing t4, the third transfer transistor 223 is turned on, and the charge generated by the second PD 112 is accumulated in the third FD 213 (fourth exposure operation).

[0107] In the exposure period of the second sub-frame, the first to fourth exposure operations are regarded as one operation cycle, and the operation cycle is repeated a predetermined number of times.

[0108] (2-2) Readout period During the readout period of the second subframe, the second signal selection transistor 252 and the first memory selection transistor 161 are turned on (first readout operation: tap A). ​​As a result, a digital value according to the amount of charge accumulated in the second FD 212 is generated, and the generated digital value is added to the digital value held in the first memory 151.

[0109] Furthermore, the first signal selection transistor 251 and the second memory selection transistor 162 are turned on (second read operation: tap B). As a result, a digital value according to the amount of charge accumulated in the first FD 211 is generated, and the generated digital value is added to the digital value held in the second memory 152.

[0110] Furthermore, the fourth signal selection transistor 254 and the third memory selection transistor 163 are turned on (third read operation: tap C). As a result, a digital value according to the amount of charge accumulated in the fourth FD 214 is generated, and the generated digital value is added to the digital value held in the third memory 153.

[0111] Furthermore, the third signal selection transistor 253 and the fourth memory selection transistor 164 are turned on (fourth read operation: tap D). As a result, a digital value according to the amount of charge accumulated in the third FD 213 is generated, and the generated digital value is added to the digital value held in the fourth memory 154.

[0112] In the readout period of the second subframe, the order of the first to fourth readout operations can be changed.

[0113] (3) Third subframe (3-1) Exposure period During the exposure period of the third sub-frame, at the first phase timing t1 when the light source device 10 is turned on, the third transfer transistor 223 is turned on, and the charge generated by the second PD 112 is accumulated in the third FD 213 (first exposure operation).

[0114] Subsequently, at the second phase timing t2, the second transfer transistor 222 is turned on, and the charge generated by the first PD 111 is accumulated in the second FD 212 (second exposure operation).

[0115] Subsequently, at the third phase timing t3, the fourth transfer transistor 224 is turned on, and the charge generated by the second PD 112 is accumulated in the fourth FD 214 (third exposure operation).

[0116] Subsequently, at the fourth phase timing t4, the first transfer transistor 221 is turned on, and the charge generated by the first PD 111 is accumulated in the first FD 211 (fourth exposure operation).

[0117] In the exposure period of the third sub-frame, the first to fourth exposure operations are regarded as one operation cycle, and this operation cycle is repeated a predetermined number of times.

[0118] (3-2) Readout period During the readout period of the third subframe, the third signal selection transistor 253 and the first memory selection transistor 161 are turned on (first readout operation: tap A). ​​As a result, a digital value according to the amount of charge accumulated in the third FD 213 is generated, and the generated digital value is added to the digital value held in the first memory 151.

[0119] Furthermore, the fourth signal selection transistor 254 and the second memory selection transistor 162 are turned on (second read operation: tap B). As a result, a digital value according to the amount of charge accumulated in the fourth FD 214 is generated, and the generated digital value is added to the digital value held in the second memory 152.

[0120] Furthermore, the second signal selection transistor 252 and the third memory selection transistor 163 are turned on (third read operation: tap C). As a result, a digital value according to the amount of charge accumulated in the second FD 212 is generated, and the generated digital value is added to the digital value held in the third memory 153.

[0121] Furthermore, the first signal selection transistor 251 and the fourth memory selection transistor 164 are turned on (fourth read operation: tap D). As a result, a digital value according to the amount of charge accumulated in the first FD 211 is generated, and the generated digital value is added to the digital value held in the fourth memory 154.

[0122] In the readout period of the third subframe, the order of the first to fourth readout operations can be changed.

[0123] (4) Fourth subframe (4-1) Exposure period During the exposure period of the fourth sub-frame, at the first phase timing t1 when the light source device 10 is turned on, the fourth transfer transistor 224 is turned on, and the charge generated by the second PD 112 is accumulated in the fourth FD 214 (first exposure operation).

[0124] Subsequently, at the second phase timing t2, the first transfer transistor 221 is turned on, and the charge generated by the first PD 111 is accumulated in the first FD 211 (second exposure operation).

[0125] Subsequently, at the third phase timing t3, the third transfer transistor 223 is turned on, and the charge generated by the second PD 112 is accumulated in the third FD 213 (third exposure operation).

[0126] Subsequently, at the fourth phase timing t4, the second transfer transistor 222 is turned on, and the charge generated by the first PD 111 is accumulated in the second FD 212 (fourth exposure operation).

[0127] In the exposure period of the fourth sub-frame, the first to fourth exposure operations are regarded as one operation cycle, and the operation cycle is repeated a predetermined number of times.

[0128] (4-2) Readout period During the readout period of the fourth subframe, the fourth signal selection transistor 254 and the first memory selection transistor 161 are turned on (first readout operation: tap A). ​​As a result, a digital value according to the amount of charge accumulated in the fourth FD 214 is generated, and the generated digital value is added to the digital value held in the first memory 151.

[0129] Furthermore, the third signal selection transistor 253 and the second memory selection transistor 162 are turned on (second read operation: tap B). As a result, a digital value according to the amount of charge accumulated in the third FD 213 is generated, and the generated digital value is added to the digital value held in the second memory 152.

[0130] Furthermore, the first signal selection transistor 251 and the third memory selection transistor 163 are turned on (third read operation: tap C). As a result, a digital value according to the amount of charge accumulated in the first FD 211 is generated, and the generated digital value is added to the digital value held in the third memory 153.

[0131] Furthermore, the second signal selection transistor 252 and the fourth memory selection transistor 164 are turned on (fourth read operation: tap D). As a result, a digital value according to the amount of charge accumulated in the second FD 212 is generated, and the generated digital value is added to the digital value held in the fourth memory 154.

[0132] In the readout period of the fourth subframe, the order of the first to fourth readout operations can be changed.

[0133] As described above, according to the solid-state imaging device 20 of this embodiment, in each subframe, the amount of charge accumulated in the four FDs 211-214 is converted into a digital value and output. Then, in four consecutive subframes, the digital value indicating the amount of charge in the four FDs 211-214 is added to the digital value stored in the memories 151-154, which differ for each subframe. With this configuration, variations in the characteristics of the four FDs 211-214 are averaged out, making it possible to measure the distance to the subject with greater accuracy.

[0134] In addition, according to the solid-state imaging device 20 of this embodiment, the pixel 100 is constructed using two units, each consisting of one PD and two signal generating units, so it is possible to create the signal generating units with higher accuracy compared to when a pixel is constructed using four signal generating units as one unit.

[0135] (Third embodiment) Next, a solid-state imaging device according to a third embodiment of the present invention will be described with reference to Figures 9 and 10. In this embodiment, charges generated by a PD are temporarily stored in a charge memory. Note that components similar to those in the first and second embodiments are designated by the same reference numerals and will not be described again.

[0136] 9 is a circuit diagram showing a schematic configuration of a pixel 100 of a solid-state imaging device 20 according to this embodiment. As shown in FIG. 9, the pixel 100 includes first and second PDs 111 and 112, first and second charge discharging transistors 121 and 122, first and second signal generating units 131 and 132, an ADC integrator 140, first to fourth memories 151 to 154, and first to fourth memory selecting transistors 161 to 164. The first signal generating unit 131 is connected to the first PD 111, and the second signal generating unit 132 is connected to the second PD 112.

[0137] The first and second signal generation units 131, 132 have first and second FDs 211, 212, first to fourth transfer transistors 221-224, first to fourth charge memories 261-264, first to fourth memory transistors 271-274, first and second SF transistors 231, 232, first and second reset transistors 241, 242, and first and second signal selection transistors 251, 252.

[0138] The first to fourth charge memories 261 to 264 are arranged between the first to fourth transfer transistors 221 to 224 and the FDs 211 and 212, and temporarily store charges. The first to fourth memory transistors 271 to 274 are arranged between the first to fourth charge memories 261 to 264 and the FDs 211 and 212, and control the transfer of charges from the charge memories 261 to 264.

[0139] According to the solid-state imaging device 20 of this embodiment configured as described above, the charges generated by the PDs 111 and 112 are temporarily stored in the charge memories 261 to 264. This suppresses reset noise (KTC noise) that occurs when the charges of the FDs 211 and 212 are reset.

[0140] 10 is a diagram illustrating the operation of the pixel 100 of the solid-state imaging device 20. In this embodiment, one frame is composed of four subframes, and each subframe includes an exposure period and a readout period. The pulse signals indicating the phase timing are input with a shift of half a pulse.

[0141] (1) First subframe (1-1) Exposure period During the exposure period of the first subframe, at the first phase timing t1 when the light source device 10 is turned on, the first transfer transistor 221 is turned on, and the charge generated by the first PD 111 is stored in the first charge memory 261 (first exposure operation).

[0142] Subsequently, at the second phase timing t2, the third transfer transistor 223 is turned on, and the charge generated by the second PD 112 is stored in the third charge memory 263 (second exposure operation).

[0143] Subsequently, at the third phase timing t3, the second transfer transistor 222 is turned on, and the charge generated by the first PD 111 is stored in the second charge memory 262 (third exposure operation).

[0144] Subsequently, at the fourth phase timing t4, the fourth transfer transistor 224 is turned on, and the charge generated by the second PD 112 is stored in the fourth charge memory 264 (fourth exposure operation).

[0145] In the exposure period of the first sub-frame, the first to fourth exposure operations are regarded as one operation cycle, and this operation cycle is repeated a predetermined number of times.

[0146] (1-2) Readout period During the readout period of the first subframe, the first signal selection transistor 251 and the first memory selection transistor 161 are turned on (first readout operation: tap A). ​​Then, the first reset transistor 241 is temporarily turned on, and then the first memory transistor 271 is turned on, causing the charge in the first charge memory 261 to be accumulated in the first FD 211. Then, a digital value according to the amount of accumulated charge is generated, and the generated digital value is added to the digital value held in the first memory 151.

[0147] Furthermore, the first signal selection transistor 251 and the second memory selection transistor 162 are turned on (second read operation: tap B). Then, after the first reset transistor 241 is temporarily turned on, the second memory transistor 272 is turned on, causing the charge in the second charge memory 262 to be accumulated in the first FD 211. Then, a digital value according to the amount of accumulated charge is generated, and the generated digital value is added to the digital value held in the second memory 152.

[0148] Furthermore, the second signal selection transistor 252 and the third memory selection transistor 163 are turned on (third read operation: tap C). Then, after the second reset transistor 242 is temporarily turned on, the third memory transistor 273 is turned on, causing the charge in the third charge memory 263 to be accumulated in the second FD 212. Then, a digital value according to the amount of accumulated charge is generated, and the generated digital value is added to the digital value held in the third memory 153.

[0149] Furthermore, the second signal selection transistor 252 and the fourth memory selection transistor 164 are turned on (fourth read operation: tap D). Then, after the second reset transistor 242 is temporarily turned on, the fourth memory transistor 274 is turned on, causing the charge in the fourth charge memory 264 to be accumulated in the second FD 212. Then, a digital value according to the amount of accumulated charge is generated, and the generated digital value is added to the digital value held in the fourth memory 154.

[0150] In the readout period of the first subframe, the order of the first to fourth readout operations can be changed.

[0151] (2) Second subframe (2-1) Exposure period During the exposure period of the second sub-frame, at the first phase timing t1 when the light source device 10 is turned on, the second transfer transistor 222 is turned on, and the charge generated by the first PD 111 is stored in the second charge memory 262 (first exposure operation).

[0152] Subsequently, at the second phase timing t2, the fourth transfer transistor 224 is turned on, and the charge generated by the second PD 112 is stored in the fourth charge memory 264 (second exposure operation).

[0153] Subsequently, at the third phase timing t3, the first transfer transistor 221 is turned on, and the charge generated by the first PD 111 is stored in the first charge memory 261 (third exposure operation).

[0154] Subsequently, at the fourth phase timing t4, the third transfer transistor 223 is turned on, and the charge generated by the second PD 112 is stored in the third charge memory 263 (fourth exposure operation).

[0155] In the exposure period of the second sub-frame, the first to fourth exposure operations are regarded as one operation cycle, and the operation cycle is repeated a predetermined number of times.

[0156] (2-2) Readout period During the readout period of the second subframe, the first signal selection transistor 251 and the first memory selection transistor 161 are turned on (first readout operation: tap A). ​​Then, the first reset transistor 241 is temporarily turned on, and then the second memory transistor 272 is turned on, causing the charge in the second charge memory 262 to be accumulated in the first FD 211. Then, a digital value according to the amount of accumulated charge is generated, and the generated digital value is added to the digital value held in the first memory 151.

[0157] Furthermore, the first signal selection transistor 251 and the second memory selection transistor 162 are turned on (second read operation: tap B). Then, after the first reset transistor 241 is temporarily turned on, the first memory transistor 271 is turned on, causing the charge in the first charge memory 261 to be accumulated in the first FD 211. Then, a digital value according to the amount of accumulated charge is generated, and the generated digital value is added to the digital value held in the second memory 152.

[0158] Furthermore, the second signal selection transistor 252 and the third memory selection transistor 163 are turned on (third read operation: tap C). Then, after the second reset transistor 242 is temporarily turned on, the fourth memory transistor 274 is turned on, causing the charge in the fourth charge memory 264 to be accumulated in the second FD 212. Then, a digital value according to the amount of accumulated charge is generated, and the generated digital value is added to the digital value held in the third memory 153.

[0159] Furthermore, the second signal selection transistor 252 and the fourth memory selection transistor 164 are turned on (fourth read operation: tap D). Then, after the second reset transistor 242 is temporarily turned on, the third memory transistor 273 is turned on, causing the charge in the third charge memory 263 to be accumulated in the second FD 212. Then, a digital value according to the amount of accumulated charge is generated, and the generated digital value is added to the digital value held in the fourth memory 154.

[0160] In the readout period of the second subframe, the order of the first to fourth readout operations can be changed.

[0161] (3) Third subframe (3-1) Exposure period During the exposure period of the third subframe, at the first phase timing t1 when the light source device 10 is turned on, the third transfer transistor 223 is turned on, and the charge generated by the second PD 112 is stored in the third charge memory 263 (first exposure operation).

[0162] Subsequently, at the second phase timing t2, the second transfer transistor 222 is turned on, and the charge generated by the first PD 111 is stored in the second charge memory 262 (second exposure operation).

[0163] Subsequently, at the third phase timing t3, the fourth transfer transistor 224 is turned on, and the charge generated by the second PD 112 is stored in the fourth charge memory 264 (third exposure operation).

[0164] Subsequently, at the fourth phase timing t4, the first transfer transistor 221 is turned on, and the charge generated by the first PD 111 is stored in the first charge memory 261 (fourth exposure operation).

[0165] In the exposure period of the third sub-frame, the first to fourth exposure operations are regarded as one operation cycle, and this operation cycle is repeated a predetermined number of times.

[0166] (3-2) Readout period During the readout period of the third subframe, the second signal selection transistor 252 and the first memory selection transistor 161 are turned on (first readout operation: tap A). ​​Then, the second reset transistor 242 is temporarily turned on, and then the third memory transistor 273 is turned on, causing the charge in the third charge memory 263 to be accumulated in the second FD 212. Then, a digital value according to the amount of accumulated charge is generated, and the generated digital value is added to the digital value held in the first memory 151.

[0167] Furthermore, the second signal selection transistor 252 and the second memory selection transistor 162 are turned on (second read operation: tap B). Then, after the second reset transistor 242 is temporarily turned on, the fourth memory transistor 274 is turned on, causing the charge in the fourth charge memory 264 to be accumulated in the second FD 212. Then, a digital value according to the amount of accumulated charge is generated, and the generated digital value is added to the digital value held in the second memory 152.

[0168] Furthermore, the first signal selection transistor 251 and the third memory selection transistor 163 are turned on (third read operation: tap C). Then, after the first reset transistor 241 is temporarily turned on, the second memory transistor 272 is turned on, causing the charge in the second charge memory 262 to be accumulated in the first FD 211. Then, a digital value according to the amount of accumulated charge is generated, and the generated digital value is added to the digital value held in the third memory 153.

[0169] Furthermore, the first signal selection transistor 251 and the fourth memory selection transistor 164 are turned on (fourth read operation: tap D). Then, after the first reset transistor 241 is temporarily turned on, the first memory transistor 271 is turned on, causing the charge in the first charge memory 261 to be accumulated in the first FD 211. Then, a digital value according to the amount of accumulated charge is generated, and the generated digital value is added to the digital value held in the fourth memory 154.

[0170] In the readout period of the third subframe, the order of the first to fourth readout operations can be changed.

[0171] (4) Fourth subframe (4-1) Exposure period During the exposure period of the fourth subframe, at the first phase timing t1 when the light source device 10 is turned on, the fourth transfer transistor 224 is turned on, and the charge generated by the second PD 112 is stored in the fourth charge memory 264 (first exposure operation).

[0172] Subsequently, at the second phase timing t2, the first transfer transistor 221 is turned on, and the charge generated by the first PD 111 is stored in the first charge memory 261 (second exposure operation).

[0173] Subsequently, at the third phase timing t3, the third transfer transistor 223 is turned on, and the charge generated by the second PD 112 is stored in the third charge memory 263 (third exposure operation).

[0174] Subsequently, at the fourth phase timing t4, the second transfer transistor 222 is turned on, and the charge generated by the first PD 111 is stored in the second charge memory 262 (fourth exposure operation).

[0175] In the exposure period of the fourth sub-frame, the first to fourth exposure operations are regarded as one operation cycle, and the operation cycle is repeated a predetermined number of times.

[0176] (4-2) Readout period During the readout period of the fourth subframe, the second signal selection transistor 252 and the first memory selection transistor 161 are turned on (first readout operation: tap A). ​​Then, the second reset transistor 242 is temporarily turned on, and then the fourth memory transistor 274 is turned on, causing the charge in the fourth charge memory 264 to be accumulated in the second FD 212. Then, a digital value according to the amount of accumulated charge is generated, and the generated digital value is added to the digital value held in the first memory 151.

[0177] Furthermore, the second signal selection transistor 252 and the second memory selection transistor 162 are turned on (second read operation: tap B). Then, after the second reset transistor 242 is temporarily turned on, the third memory transistor 273 is turned on, causing the charge in the third charge memory 263 to be accumulated in the second FD 212. Then, a digital value according to the amount of accumulated charge is generated, and the generated digital value is added to the digital value held in the second memory 152.

[0178] Furthermore, the first signal selection transistor 251 and the third memory selection transistor 163 are turned on (third read operation: tap C). Then, after the first reset transistor 241 is temporarily turned on, the first memory transistor 271 is turned on, causing the charge in the first charge memory 261 to be accumulated in the first FD 211. Then, a digital value according to the amount of accumulated charge is generated, and the generated digital value is added to the digital value held in the third memory 153.

[0179] Furthermore, the first signal selection transistor 251 and the fourth memory selection transistor 164 are turned on (fourth read operation: tap D). Then, after the first reset transistor 241 is temporarily turned on, the second memory transistor 272 is turned on, causing the charge in the second charge memory 262 to be accumulated in the first FD 211. Then, a digital value according to the amount of accumulated charge is generated, and the generated digital value is added to the digital value held in the fourth memory 154.

[0180] In the readout period of the fourth subframe, the order of the first to fourth readout operations can be changed.

[0181] As described above, according to the solid-state imaging device 20 of this embodiment, in each subframe, the amount of charge accumulated in the two FDs 211, 212 is converted into a digital value and output. Then, in four consecutive subframes, the digital value indicating the amount of charge in the two FDs 211, 212 is added to the digital value stored in the memories 151 to 154, which differ for each subframe. With this configuration, variations in the characteristics of the two FDs 211, 212 are averaged out, making it possible to measure the distance to the subject with greater accuracy.

[0182] In addition, according to the solid-state imaging device 20 of this embodiment, the charges generated by the PDs 111 and 112 are temporarily stored in the charge memories 261 to 264, and correlated double sampling is performed, thereby suppressing reset noise. As a result, it becomes possible to measure the distance to the subject with even greater accuracy.

[0183] In the above-described embodiment, the pixel 100 has been described as having two FDs 211 and 212. However, similar to the first and second embodiments, the pixel 100 may have four FDs 211 to 214. Also, similar to the first embodiment, the pixel 100 may have a single PD 110.

[0184] (Fourth embodiment) In the first to third embodiments described above, the converter (ADC) and the adder are configured integrally, but the converter and the adder may be configured separately.

[0185] 11 is a circuit diagram showing a schematic configuration of a pixel 100 of a solid-state imaging device 20 according to the fourth embodiment of the present invention. As shown in FIG. 11, the pixel 100 includes a PD 110, a charge discharging transistor 120, first to fourth signal generating units 131 to 134, an ADC 310, a ripple counter 320, and an SRAM (Static Random Access Memory) 330.

[0186] The ADC 310 serves as a converter and converts the voltages output from the first to fourth signal generating units 131 to 134 into digital values. The ripple counter 320 serves as an adder and adds the digital values ​​converted by the ADC 310 to digital values ​​previously stored in the SRAM 330. The SRAM 330 serves as a memory and stores the digital values.

[0187] According to the solid-state imaging device 20 of the present embodiment configured as described above, the ripple counter 320 reads out digital values ​​stored in memory areas of the SRAM 330 corresponding to the four taps. The ripple counter 320 then adds the digital value output from the ADC 310 to the read digital value, and stores the digital value after the addition in the memory area of ​​the SRAM 330.

[0188] (Variation) The SRAM 330 may be provided in common to a predetermined number of pixels 100. For example, as shown in Fig. 12, the SRAM 330 is provided in common to four pixels 100. Alternatively, as shown in Fig. 13, the SRAM 330 is provided in common to eight pixels 100. Such a configuration reduces the circuit area.

[0189] Furthermore, not only the SRAM 330 but also the ripple counter 320 may be provided in common to a predetermined number of pixels 100. As shown in Fig. 14, the SRAM 330 is provided in common to four pixels 100, and the ripple counter 320 is provided in common to two pixels 100. Alternatively, as shown in Fig. 15, the SRAM 330 is provided in common to eight pixels 100, and the ripple counter 320 is provided in common to two pixels 100. Alternatively, as shown in Fig. 16, the SRAM 330 is provided in common to eight pixels 100, and the ripple counter 320 is provided in common to four pixels 100.

[0190] It should be noted that not only the SRAM 330 and the ripple counter 320 but also the ADC 310 may be provided in common to a predetermined number of pixels.

[0191] (Fifth embodiment) Finally, a fifth embodiment of the present invention will be described with reference to Figures 17 to 19. This embodiment is an embodiment in which the difference value of the digital value is held.

[0192] 17 is a diagram showing a schematic configuration of a pixel 100 of a solid-state imaging device 20 according to this embodiment. As shown in FIG. 17, the pixel 100 includes a PD 110, a charge discharging transistor 120, first to fourth signal generating units 131 to 134, an ADC 310, a ripple up / down counter 325, and an SRAM 330.

[0193] The ripple up / down counter 325 adds together a difference value (AC) between the digital value of tap A and the digital value of tap C, and a difference value (BD) between the digital value of tap B and the digital value of tap D. The ripple up / down counter 325 counts the digital value of tap A and the digital value of tap B using an up counter, while counting the digital value of tap C and the digital value of tap D using a down counter, thereby adding up the difference values. The SRAM 330 holds the sum of the difference values ​​(AC) and the sum of the difference values ​​(BD). In other words, the SRAM 330 holds the difference value between the sum of the digital value of tap A and the sum of the digital value of tap C, and the difference value (BD) between the sum of the digital value of tap B and the sum of the digital value of tap D.

[0194] This configuration allows the distance to the subject to be calculated in a shorter time because the difference value used in the distance calculation is calculated in advance. In addition, memory space is reduced compared to when storing digital values ​​for four taps.

[0195] (Variation) The ripple up / down counter 325 and the SRAM 330 may also be provided in common to a predetermined number of pixels 100. For example, as shown in Fig. 18, the SRAM 330 is provided in common to four pixels 100. Alternatively, as shown in Fig. 19, the SRAM 330 is provided in common to eight pixels 100.

[0196] The present invention is not limited to the above-described embodiments, but can be modified in various ways within the scope of the claims.

[0197] For example, in the above-described embodiments, a single pixel has two or four FDs. However, the number of charge storage units that store the charges generated by the PDs is not limited to the above-described embodiments. For example, a single pixel may have three FDs.

[0198] In the above-described embodiment, the memory that stores the digital values ​​is an SRAM. However, the memory that stores the digital values ​​may be a DRAM (Dynamic Random Access Memory).

[0199] In the above-described embodiment, an example has been described in which one ADC integrator or ADC is provided for each pixel. However, a plurality of ADC integrators or ADCs may be provided for each pixel. For example, the same number of ADC integrators or ADCs as the number of FDs may be provided for each pixel. [Explanation of symbols]

[0200] 1 TOF system, 10 light source device, 20 solid-state imaging device, 21 pixel array, 22 drive unit, 23 arithmetic section, 50 subjects, 100 pixels, 110, 111, 112 Photodiode (photoelectric conversion unit), 120,121,122 Charge drain transistor, 131, 132, 133, 134 signal generation unit; 140 ADC integrator (converter, adder), 151,152,153,154 memory, 161,162,163,164 memory select transistor; 211,212,213,214 Floating diffusion (charge storage section), 221, 222, 213, 224 transfer transistor (transfer control section), 231,232,233,234 Source follower transistor, 241,242,243,244 Reset transistor, 251, 252, 253, 254 signal selection transistors; 261,262,263,264 Charge memory, 271,272,273,274 Memory transistors, 310 ADC (converter), 320 ripple counter (adder), 325 ripple up / down counter (adder), 330 SRAM (memory).

Claims

1. a pixel including a photoelectric conversion unit that photoelectrically converts light to generate electric charges, a plurality of charge accumulation units that accumulate the electric charges generated by the photoelectric conversion unit, and a plurality of transfer control units that control transfer of electric charges from the photoelectric conversion unit to each of the charge accumulation units; a converter provided in common for one pixel or a predetermined number of pixels, which generates a digital value corresponding to the amount of charge accumulated in the charge accumulation unit; a memory provided in common to one pixel or a predetermined number of pixels and storing a digital value; an adder provided in common for one pixel or a predetermined number of pixels, which adds the digital value generated by the converter to a digital value previously stored in the memory; a drive unit that controls the operation of the plurality of transfer control units so that a digital value corresponding to the amount of charge accumulated in one of the charge accumulation units in a specific subframe is added to a digital value corresponding to the amount of charge accumulated in another of the charge accumulation units in a next subframe, and the added value of the digital values ​​is stored in the memory; A solid-state imaging device comprising:

2. The solid-state imaging device according to claim 1 , wherein each of the transfer control units is turned on at a different phase timing for each of a plurality of consecutive subframes.

3. The solid-state imaging device according to claim 1 , wherein the plurality of transfer control units are turned on in a different order for each of a plurality of consecutive subframes.

4. 3. The solid-state imaging device according to claim 1, wherein the memory holds an added value of the plurality of digital values ​​corresponding to the amounts of charge stored in the plurality of different charge storage sections in a plurality of consecutive subframes.

5. 3. The solid-state imaging device according to claim 1, wherein the memory holds an added value of the plurality of digital values ​​corresponding to the amounts of charge stored in the plurality of different charge storage sections at the same phase timing in a plurality of consecutive subframes.

6. 3. The solid-state imaging device according to claim 1, wherein the memory holds a differential value between a sum of a plurality of the digital values ​​corresponding to the amounts of charge stored in a plurality of the charge storage sections that are different from one another at one phase timing in a plurality of consecutive subframes and a sum of a plurality of the digital values ​​corresponding to the amounts of charge stored in a plurality of the charge storage sections that are different from one another at another phase timing.

7. 3. The solid-state imaging device according to claim 1, further comprising a charge memory disposed between the charge storage section and the transfer control section, for holding the charges generated by the photoelectric conversion section.

8. 3. The solid-state imaging device according to claim 1, wherein at least one of said converter, said memory, and said adder is provided in common to a predetermined number of pixels.

9. 3. The solid-state imaging device according to claim 1, wherein the converter and the adder are integrally configured.

10. 3. The solid-state imaging device according to claim 1, wherein the adder includes a ripple counter.

11. 3. The solid-state imaging device according to claim 1, wherein a plurality of said memories are provided for each said pixel.

12. 3. The solid-state imaging device according to claim 1, wherein the memory includes an SRAM or a DRAM.

13. The solid-state imaging device according to claim 1 , wherein the pixel includes two of the photoelectric conversion units.

14. 3. The solid-state imaging device according to claim 1, wherein a first layer in which the photoelectric conversion section is provided and a second layer in which the memory is provided are stacked.

Images