Light-emitting element

Abstract

To provide a light-emitting element.SOLUTION: A light-emitting element comprises: a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer located between the first and second semiconductor layers; a surrounding part located on the semiconductor structure and / or surrounding the semiconductor structure, and exposing the surface of the first semiconductor layer; a first insulating structure located on the semiconductor structure, and including a plurality of protrusions covering a part of the surface of the first semiconductor layer and a plurality of recessed parts exposing the other part of the surface of the first semiconductor layer; a first contact part formed in the surrounding part and contacting the other part of the surface of the first semiconductor layer through the plurality of recessed parts; a first solder pad formed on the semiconductor structure; and a second solder pad formed on the semiconductor structure.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD OF THE INVENTION This application relates to light emitting device structures, and more particularly to light emitting devices that include semiconductor structures and solder pads located on the semiconductor structures. [Background technology]

[0002] Light-emitting diodes (LEDs) are solid-state semiconductor light-emitting devices with the advantages of low power consumption, low heat generation, long operating life, shock resistance, small volume, fast response, and excellent photoelectric properties, such as a stable emission wavelength. Therefore, LEDs are widely used in home appliances, equipment indicators, and photoelectric products. Summary of the Invention [Problem to be solved by the invention]

[0003] A light emitting device is provided that includes a semiconductor structure and a solder pad located on the semiconductor structure. [Means for solving the problem]

[0004] The light-emitting element includes a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer located between the first and second semiconductor layers; an enclosure located on the semiconductor structure and / or surrounding the semiconductor structure to expose a surface of the first semiconductor layer; a first insulating structure located on the semiconductor structure and including a plurality of protrusions covering a portion of the surface of the first semiconductor layer and a plurality of recesses exposing other portions of the surface of the first semiconductor layer; a first contact portion formed on the enclosure and in contact with the other portions of the surface of the first semiconductor layer by the plurality of recesses; a first solder pad formed on the semiconductor structure; and a second solder pad formed on the semiconductor structure. [Brief explanation of the drawings]

[0005] [Figure 1] 1 is a top view of a light-emitting element 2 disclosed in an embodiment of the present application. [Figure 2]2 is a cross-sectional view of the light-emitting element 2 taken along line BB' in FIG. [Figure 3] 2 is a cross-sectional view of the light-emitting element 2 taken along line CC' in FIG. [Figure 4] 2 is a top view of each layer of the light-emitting element 2 disclosed in FIG. [Figure 5] 1 is a top view of a burnt-out region of a light-emitting element 2 disclosed in an embodiment of the present application. [Figure 6] FIG. 10 is a top view of a burnt-out region of a conventional light-emitting element 3. [Figure 7] FIG. 1 is a voltage waveform diagram of a surge in an electrical overstress (EOS) measurement. [Figure 8] This is a table showing the maximum applied voltage of a surge and the forward voltage (Vf) at which it can be turned on. [Figure 9] This is a table of maximum applied surge voltage and reverse current (Ir). [Figure 10] 1 is a schematic diagram of a light emitting device 30 according to one embodiment of the present application. [Figure 11] 1 is a schematic diagram of a light emitting device 4 according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0006] To fully and in detail disclose the present application, the following description will be based on examples and will be given with reference to the drawings. However, the following examples are intended to illustrate the light-emitting device of the present application, and the present application is not limited to these examples. Furthermore, unless otherwise specified, the size, material, shape, relative position, etc. of components described in the examples of this specification are merely illustrative, and the scope of the present application is not limited thereto. Furthermore, the size or positional relationship of components shown in each drawing may be enlarged for clarity. Furthermore, in the following description, components that are identical or have the same properties will be designated by the same names and symbols in order to appropriately omit detailed description.

[0007] As shown in Figures 1 to 4, Figure 1 is a top view of a light-emitting device 2 disclosed in an embodiment of the present application. Figure 2 is a cross-sectional view of the light-emitting device 2 taken along line B-B' in Figure 1. Figure 3 is a cross-sectional view of the light-emitting device 2 taken along line C-C' in Figure 1. Figure 4 is a process diagram for manufacturing the light-emitting device 2 shown in Figure 1.

[0008] The light-emitting element 2 includes a substrate 11b, one or more semiconductor structures 1000b disposed on the substrate 11b, and a surrounding portion 111b disposed on and / or surrounding the one or more semiconductor structures 1000b. A first insulating structure 20b is disposed on the semiconductor structures 1000b and is formed along the surrounding portion 111b. A transparent conductive layer 30b is disposed on the one or more semiconductor structures 1000b. The reflective structure includes a reflective layer 40b and a barrier layer 41b disposed on the transparent conductive layer 30b, and a second insulating structure 50b covers the reflective layer 40b and the barrier layer 41b. A contact layer 60b is disposed on the second insulating structure 50b, and a third insulating structure 70b is disposed on the contact layer 60b. Furthermore, a first solder pad 80b and a second solder pad 90b are disposed on the contact layer 60b.

[0009] 1 to 4, in the manufacturing process of the light emitting device 2, a semiconductor stack 10b is first formed on a substrate 11b. The substrate 11b may be, but is not limited to, a sapphire substrate. In one embodiment, the substrate 11b includes a patterned surface. The patterned surface includes a plurality of patterns. The shape of the patterns may include a cone, a pyramid, or a hemisphere.

[0010] In one embodiment of the present application, the substrate 11b is a growth substrate used for epitaxial growth of the semiconductor stack 10b, and includes a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), or a sapphire (Al2O3) wafer, a gallium nitride (GaN) wafer, or a silicon carbide (SiC) wafer for growing indium gallium nitride (InGaN).

[0011] In one embodiment of the present application, the substrate 11b includes a patterned surface located between the semiconductor structure 1000b and the substrate 11b to enhance the light extraction efficiency of the light-emitting device. The exposed surface of the substrate 11b may include a patterned surface (not shown). The patterned surface may have various patterns, such as an irregular pattern, a micromirror, a microarray, a scattering region, or other types of optical regions. For example, the patterned surface may include a plurality of protrusions, each of which has a height of 0.5 to 2.5 μm, a width of 1 to 3.5 μm, and a pitch of 1 to 3.5 μm between the protrusions.

[0012] In one embodiment of the present application, the substrate 11b includes sidewalls with flat and / or rough surfaces to enhance the light extraction efficiency of the light emitting device. In one embodiment of the present application, the sidewalls of the substrate 11b are inclined relative to the substrate 11b, and the surface adjacent to the semiconductor structure 1000b adjusts the light field distribution of the light emitting device.

[0013] In one embodiment of the present application, the semiconductor stack 10b has optical properties, such as an emission angle or wavelength distribution, and electrical properties, such as a forward voltage or a reverse current, and is formed on the substrate 11b by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), physical vapor deposition (PVD), or ion electroplating, where physical vapor deposition includes sputtering or evaporation.

[0014] Each of the one or more semiconductor structures 1000b includes a semiconductor stack 10b, which includes a first semiconductor layer 101b, a second semiconductor layer 102b, and an active layer 103b located between the first semiconductor layer 101b and the second semiconductor layer 102b. The semiconductor structure 1000b further includes one or more through-holes 100b that penetrate the second semiconductor layer 102b and the active layer 103b to expose the first semiconductor layer 101b. The first semiconductor layer 101b and the second semiconductor layer 102b may each be composed of a single layer or multiple sublayers. The active layer 103b may have a single quantum well structure or a multiple quantum well structure. The semiconductor stack 10b may be formed by forming a Group III nitride compound semiconductor layer on a substrate 11b by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or physical vapor deposition (PVD).

[0015] In one embodiment of the present application, a buffer structure (not shown) may be formed on the substrate 11b before forming the semiconductor stack 10b to accommodate the crystal lattice mismatch between the substrate 11b and the semiconductor stack 10b. The buffer structure may be composed of a gallium nitride (GaN)-based material, such as gallium nitride and aluminum gallium nitride, or an aluminum nitride (AlN)-based material. The buffer structure may be single-layer or multi-layer. The buffer structure may be formed by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or physical vapor deposition (PVD). Physical vapor deposition (PVD) includes sputtering techniques, such as reactive sputtering, or evaporation techniques, such as electron beam evaporation and thermal evaporation. In one embodiment, the buffer structure includes an aluminum nitride (AlN) buffer layer formed by sputtering. The aluminum nitride (AlN) buffer layer is formed on a growth substrate having a patterned surface. An aluminum nitride (AlN) buffer layer may be conformally grown on the patterned surface of substrate 11b, as sputtering can form a dense buffer layer with high uniformity.

[0016] In one embodiment of the present application, the first semiconductor layer 101b and the second semiconductor layer 102b may be cladding layers, which have different conductivity types, electrical properties, or polarities, or may provide electrons or holes by doping elements. For example, the first semiconductor layer 101b is an n-type semiconductor layer, and the second semiconductor layer 102b is a p-type semiconductor layer. The active layer 103b is formed between the first semiconductor layer 101b and the second semiconductor layer 102b. Electrons and holes are combined in the active layer 103b by current driving, and the electrical energy is converted into light energy to emit light. The wavelength of the light emitted by the light-emitting device 2 can be adjusted by changing the physical and chemical composition of one or more layers of the semiconductor stack 10b. The material of the semiconductor stack 10b includes III-V semiconductor materials, such as Al. x In y Ga (1-x-y) N or Al x In y Ga (1-x-y) P, and 0≦x, y≦1, (x+y)≦1. Depending on the material of the active layer 103b, if the material of the semiconductor stack 10b is AlInGaP-based, the active layer 103b can emit red light with a wavelength between 610 nm and 650 nm or yellow light with a wavelength between 530 nm and 570 nm. If the material of the semiconductor stack 10b is InGaN-based, the active layer 103b can emit blue light, deep blue light with a wavelength between 400 nm and 490 nm, or green light with a wavelength between 490 nm and 550 nm. If the material of the semiconductor stack 10b is AlGaN-based, the active layer 103b can emit ultraviolet light with a wavelength between 250 nm and 400 nm. The active layer 103b may be a single heterostructure (SH), a double heterostructure (DH), a double-sided double heterostructure (DDH), or a multi-quantum well (MQW) structure. The material of the active layer 103b may be a neutral, p-type, or n-type semiconductor.

[0017] After forming the semiconductor stack 10b on the substrate 11b, the semiconductor stack 10b is patterned by photolithography and etching to form a plurality of through-holes 100b and an enclosing portion 111b. By photolithography and etching, portions of the second semiconductor layer 102b and the active layer 103b are removed to form a plurality of through-holes 100b, and the second surfaces 1012b of the first semiconductor layers 101b corresponding to the through-holes 100b are exposed. Here, the through-holes 100b are defined by an inner wall 1002b and a second surface 1012b. One end of the inner wall 1002b is connected to the second surface 1012b of the first semiconductor layer 101b, and the other end of the inner wall 1002b is connected to the surface 102sb of the second semiconductor layer 102b.

[0018] By the same or another photolithography and etching process, the second semiconductor layer 102b and the active layer 103b surrounding the semiconductor structure 1000b are removed to form an enclosure 111b, and the enclosure 111b exposes the first surface 1011b of the first semiconductor layer 101b. In another embodiment, in the photolithography and etching process, a portion of the first semiconductor layer 101b is further etched to a deeper etching depth to expose the second surface 1012b and the first surface 1011b. Specifically, the enclosure 111b includes a first outer wall 1003b and a second outer wall 1001b, which are defined by the exposed surface of the substrate 11b, the first surface 1011b on which the first semiconductor layer 101b is exposed, and the side surfaces on which the second semiconductor layer 102b, the active layer 103b, and the first semiconductor layer 101b are exposed. One end of the first surface 1011b is connected to the first outer wall 1003b, and the other end of the first surface 1011b is connected to the second outer wall 1001b. The first outer wall 1003b and the second outer wall 1001b are inclined relative to the first surface 1011b. The enclosure 111b is formed along the periphery of the semiconductor structure 1000b and is positioned around and / or surrounds one or more semiconductor structures 1000b. In one embodiment, the first outer wall 1003b is inclined relative to the exposed surface (not shown) of the substrate 11b. There is an acute angle between the first outer wall 1003b and the exposed surface of the substrate 11b. In one embodiment, there is an obtuse angle between the first outer wall 1003b and the exposed surface of the substrate 11b.

[0019] After forming the semiconductor structure 1000b, a first insulating structure 20b is formed on the semiconductor stack 10b, covering a portion of the surface 102sb of the second semiconductor layer 102b and extending to the second outer wall 1001b to cover the first surface 1011b. In other words, the first insulating structure 20b covers portions of the surrounding portion 111b. The first insulating structure 20b protects the sidewalls of the semiconductor structure 1000b and prevents the active layer 103b from being damaged in subsequent processes. As shown in FIG. 4 , in a top view, the first insulating structure 20b includes a surrounding insulating portion 201b and a plurality of annular covering areas 203b. Here, in a top view, the surrounding insulating portion 201b includes a plurality of protrusions 2011b and a plurality of recesses 2012b. The plurality of annular covering areas 203b are surrounded by the surrounding insulating portion 201b, and the plurality of annular covering areas 203b are respectively formed within the plurality of through holes 100b and correspond to the plurality of through holes 100b. Each of the plurality of annular covering areas 203b has an opening (not shown in the drawing) exposing the second surface 1012b of the first semiconductor layer 101b. In one embodiment, the surrounding insulating portion 201b of the first insulating structure 20b is disposed along the first surface 1011b of the first semiconductor layer 101b and surrounds the semiconductor structure 1000b. In this embodiment, the plurality of protrusions 2011b and the plurality of recesses 2012b of the surrounding insulating portion 201b are alternately arranged along the surrounding portion 111b, and the positions of the plurality of annular covering areas 203b correspond to the positions of the plurality of through holes 100b, but the present application is not limited thereto. In one embodiment, the region located between the two protrusions 2011b forms a recess 2012b. In another embodiment, the surrounding insulating portion 201b further includes sub-protrusions extending from the protrusions 2011b and / or sub-recesses recessed from the recess 2012b. In this embodiment, the multiple protrusions 2011b extend from the upper surface 102sb of the second semiconductor layer 102b and directly contact and cover multiple portions of the first surface 1011b of the first semiconductor layer 101b and multiple corners of the first surface 1011b of the second semiconductor layer 102b. The multiple recesses 2012b expose other portions of the first surface 1011b of the first semiconductor layer 101b that are not covered by the multiple protrusions 2011b.In one embodiment, the plurality of recesses 2012b expose the first surface 1011b located on multiple sides of the semiconductor structure 1000b. As shown in FIG. 2, in the cross-sectional view, the recesses 2012b of the first insulating structure 20b expose a portion of the first surface 1011b of the first semiconductor layer 101b. As shown in FIG. 3, in the cross-sectional view, the protrusions 2011b of the first insulating structure 20b cover the first surface 1011b of the first semiconductor layer 101b and multiple sidewalls of the semiconductor structure 1000b. In other words, the plurality of protrusions 2011b and the plurality of recesses 2012b alternately cover a portion of the first surface 1011b of the first semiconductor layer 101b and expose another portion of the first surface 1011b of the first semiconductor layer 101b. In this embodiment, the exposed portions of the first surface 1011b are discontinuous, and the total area of ​​the exposed portions of the first surface 1011b is smaller than the total area of ​​the first surface 1011b. Most of the second semiconductor layer 102b is not covered by the first insulating structure 20b. In a top view, the shape of the surrounding insulating portion 201b is annular, for example, rectangular, circular, or polygonal. The shape of one of the plurality of protrusions 2011b or the plurality of recesses 2012b includes a triangular, rectangular, semicircular, circular, or polygonal shape. The material of the first insulating structure 20b includes a non-conductive material. The non-conductive material includes an organic material, an inorganic material, or a dielectric material. Organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyetherimide, or fluorocarbon polymer. Inorganic materials include silicone or glass. Dielectric materials include aluminum oxide (Al2O3), silicon nitride (SiN). x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x) The first insulating structure 20b may include one or more layers. The first insulating structure 20b may protect the sidewalls of the semiconductor structure 1000b and prevent the active layer 103b from being damaged in a subsequent process. When the first insulating structure 20b includes multiple layers, the first insulating structure 20b may be a distributed Bragg reflector (DBR) structure including multiple pairs of film layers, which may protect the sidewalls of the semiconductor structure 1000b and selectively reflect light of a specific wavelength emitted by the active layer 103b to the outside of the light-emitting device 2 to enhance brightness, and each film layer may have a refractive index different from that of its adjacent film layer. Specifically, the first insulating structure 20b may be made of SiO x layer and TiO x The DBR can be formed by stacking alternating layers. By adjusting the refractive index difference between the high and low refractive index of each pair of film layers, the DBR can have high reflectivity for a specific wavelength or within a specific wavelength range. The two layers in each pair of film layers have different thicknesses. The thicknesses of the layers of the same material in each pair of film layers can be the same or different.

[0020] After forming the first insulating structure 20b, a transparent conductive layer 30b is formed on the second semiconductor layer 102b. The transparent conductive layer 30b includes a plurality of openings 301tb, exposing the second surface 1012b of the first semiconductor layer 101b. In this embodiment, in a top view, the shape of the transparent conductive layer 30b corresponds to the shape of the second semiconductor layer 102b, and the positions of the plurality of openings 301tb correspond to the positions of the plurality of annular covering areas 203b and the plurality of through-holes 100b. The transparent conductive layer 30b contacts and covers the second semiconductor layer 102b to diffuse and inject current into the second semiconductor layer 102b. The transparent conductive layer 30b does not contact the first semiconductor layer 101b. In one embodiment, the light-emitting element 2 includes another transparent conductive layer (not shown) that contacts the first semiconductor layer 101b in the surrounding portion 111b. The transparent conductive layer 30b may be made of a transparent material that is transparent to the light emitted from the active layer 103b, such as indium zinc oxide (IZO) or indium tin oxide (ITO). The transparent conductive layer 30b may form a low-resistance contact, such as an ohmic contact, with the second semiconductor layer 102b. The transparent conductive layer 30b may include one or more sublayers. For example, if the transparent conductive layer 30b includes multiple sublayers, the transparent conductive layer 30b may have a distributed Bragg reflector (DBR) structure including multiple pairs of sublayers, each of which may have a refractive index different from that of its adjacent sublayer. Specifically, the transparent conductive layer 30b may have a distributed Bragg reflector (DBR) structure by alternately stacking two sublayers with different refractive indices.

[0021] After forming the transparent conductive layer 30b, a reflective structure including a reflective layer 40b and a barrier layer 41b is formed on the transparent conductive layer 30b. In one embodiment, the reflective structure is aligned with the transparent conductive layer 30b, and the sides of the reflective structure are aligned with the sides of the transparent conductive layer 30b. In one embodiment, the reflective structure is not aligned with the transparent conductive layer 30b, and the sides of the reflective structure are located inside or outside the sides of the transparent conductive layer 30b. In one embodiment, the transparent conductive layer 30b and the reflective structure extend to the first insulating structure 20b.

[0022] The reflective layer 40b and the barrier layer 41b include a plurality of openings 401tb and 411tb, respectively. The plurality of openings 401tb in the reflective layer 40b and the plurality of openings 411tb in the barrier layer 41b expose the plurality of annular covering areas 203b, the plurality of through holes, and the second surface 1012b of the first semiconductor layer 101b. The barrier layer 41b is formed on and covers the reflective layer 40b, and the barrier layer 41b can prevent the transition, diffusion, or oxidation of metal elements in the reflective layer 40b. The shapes of the reflective layer 40b and the barrier layer 41b of the reflective structure correspond to the shapes of the transparent conductive layer 30b. In one embodiment, the shapes of the reflective layer 40b and the barrier layer 41b of the reflective structure are close to rectangular, and the corners of the reflective layer 40b and the barrier layer 41b are arched. The reflective layer 40b may be made of a metal material having a high reflectivity to the light emitted from the active layer 103b, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), or an alloy of the above materials. The barrier layer 41b may be made of a metal material having a high reflectivity to the light emitted from the active layer 103b, such as chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), or zinc (Zn). When the barrier layer 41b has a multi-layer structure, the barrier layer 41b is formed by alternating first and second barrier layers (not shown), such as Cr / Pt, Cr / Ti, Cr / TiW, Cr / W, Cr / Zn, Ti / Pt, Ti / W, Ti / TiW, Ti / Zn, Pt / TiW, Pt / W, Pt / Zn, TiW / W, TiW / Zn, or W / Zn. The reflective structure may further include a distributed Bragg reflector (DBR) formed under the reflective layer 40b. The distributed Bragg reflector (DBR) structure includes multiple pairs of sublayers, each of which has a refractive index different from that of its adjacent sublayer. In one embodiment, SiO x layer and TiO xMultiple pairs of sublayers may be formed by stacking layers alternately. By adjusting the refractive index difference between the high and low refractive index of each pair of sublayers, the distributed Bragg reflector (DBR) can have high reflectivity at a specific wavelength or within a specific wavelength range. The two layers in each pair of sublayers have different thicknesses. The thicknesses of the layers of the same material in each pair of sublayers may be the same or different.

[0023] After forming the reflective structure, a second insulating structure 50b is formed on the reflective structure so as to cover a portion of the upper surface of the reflective structure (the reflective layer 40b or the barrier layer 41b) and to be located in the peripheral region of the second semiconductor layer 102b between the reflective structure and the first insulating structure 20b. The second insulating structure 50b contacts and covers the first insulating structure 20b, so that the first outer wall 1003b and the second outer wall 1001b of the surrounding portion 111b and the portion of the first surface 1011b covered by the first insulating structure 20b are also covered by the second insulating structure 50b. The second insulating structure 50b protects the sidewalls of the semiconductor structure 1000b and can prevent the active layer 103b from being damaged in a subsequent process. Because the second insulating structure 50b covers the first insulating structure 20b, the second insulating structure 50b can prevent the first insulating structure 20b from being etched away in a subsequent process. As shown in FIG. 4, the second insulating structure 50b includes a plurality of openings 501b and 503b. Here, the second insulating structure 50b includes an outer periphery 505b having a plurality of protrusions 5051b and a plurality of recesses 5052b. The openings 503b expose a portion of the reflective layer 40b or the barrier layer 41b of the reflective structure, and the plurality of openings 501b expose the second surface 1012b of the first semiconductor layer 101b. As shown in FIGS. 2 to 4, in this embodiment, the outer periphery 505b of the second insulating structure 50b contacts, covers, and is aligned with the first insulating structure 20b. The positions of the plurality of openings 501b correspond to the positions of the plurality of openings 401tb, 411tb, and 301tb and the plurality of through-holes 100b. Furthermore, the plurality of protrusions 5051b and the plurality of recesses 5052b located on the outer periphery 505b of the second insulating structure 50b are alternately arranged along the surrounding insulating portion 201b or the surrounding portion 111b of the first insulating structure 20b, respectively covering and exposing different portions of the first surface 1011b of the first semiconductor layer 101b. In one embodiment, the area between two protrusions 5051b constitutes the recess 5052b. In another embodiment, the second insulating structure 50b further includes a sub-protrusion extending from the protrusion 5051b and / or a sub-recess recessed from the recess 5052b.In one embodiment, the shape of the outer periphery 505b of the second insulating structure 50b corresponds to the shape of the surrounding insulating portion 201b of the first insulating structure 20b, discontinuously exposing the portion of the first surface 1011b of the first semiconductor layer 101b located in the surrounding portion 111b. In other words, the shapes and positions of the protrusions 5051b and the recesses 5052b correspond to the shapes and positions of the protrusions 2011b and the recesses 2012b of the surrounding insulating portion 201b. The portion of the first surface 1011b exposed by the recesses 2012b is also exposed by the recesses 5052b. The portion of the first surface 1011b covered by the protrusions 2011b is also covered by the protrusions 5051b. When the first surface 1011b is discontinuously exposed by the first insulating structure 20b and the second insulating structure 50b, in one embodiment, the shape or position of the protrusion 5051b and the recess 5052b may be different from the shape or position of the protrusion 2011b and the recess 2012b. In one embodiment, the area of ​​the protrusion 5051b and the recess 5052b may be larger or smaller than the area of ​​the protrusion 2011b and the recess 2012b. The portion of the first surface 1011b exposed at the recess 2012b and the recess 5052b is adjusted by the shape, position, or area of ​​the protrusion 2011b, 5051b and the recess 2012b, 5052b.

[0024] 2, in the cross-sectional view, a portion of the first surface 1011b of the first semiconductor layer 101b is exposed by the plurality of recesses 2012b of the first insulating structure 20b and is also exposed by the plurality of recesses 5052b of the second insulating structure 50b. In other words, the portion of the first surface 1011b of the first semiconductor layer 101b that is not covered by the plurality of protrusions 2011b, 5051b and that is exposed by the plurality of recesses 2012b is exposed by the plurality of recesses 5052b of the second insulating structure 50b. As shown in Figure 3, in the cross-sectional view, the multiple protrusions 5051b cover the multiple protrusions 2011b of the first insulating structure 20b on the first surface 1011b of the first semiconductor layer 101b, and also cover the surrounding insulating portion 201b formed on the first outer wall 1003b and the second outer wall 1001b and the corners of the first surface 1011b of the first semiconductor layer 101b, and the first outer wall 1003b and the second outer wall 1001b are formed by side surfaces to which the second semiconductor layer 102b, the active layer 103b and the first semiconductor layer 101b are exposed. Specifically, in this embodiment, the protrusions 5051b are in direct contact with the protrusions 2011b of the first insulating structure 20b, the recesses 5052b expose the first surface 1011b of the first semiconductor layer 101b, and the protrusions 5051b and the recesses 5052b are arranged alternately to discontinuously expose portions of the first surface 1011b of the first semiconductor layer 101b. In other words, the portions of the first surface 1011b exposed in the recesses 5052b are discontinuous, and the first surface 1011b has a total exposed area that is smaller than the entire area of ​​the first surface 1011b.

[0025] In one embodiment, the shape of one of the plurality of protrusions 5051b includes a triangle, a rectangle, a semicircle, a circle, or a polygon. The material of the second insulating structure 50b includes a non-conductive material. The non-conductive material includes an organic material, an inorganic material, or a dielectric material. The organic material includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyetherimide, or fluorocarbon polymer. The inorganic material includes silicone or glass. The dielectric material includes aluminum oxide (Al2O3), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ) The second insulating structure 50b includes one layer or multiple layers. The second insulating structure 50b protects the sidewalls of the semiconductor structure 1000b, prevents the active layer 103b from being destroyed in a later process, and selectively emits light of a specific wavelength emitted by the active layer 103b to the outside of the light-emitting device 2, thereby increasing brightness. When the second insulating structure 50b includes multiple layers, the second insulating structure 50b may be a distributed Bragg reflector (DBR) structure including multiple pairs of film layers, and each film layer may have a refractive index different from that of its adjacent film layer. In one embodiment, the second insulating structure 50b is made of SiO x layer and TiO x The DBR can be formed by stacking alternating layers. By adjusting the refractive index difference between the high and low refractive index of each pair of film layers, the distributed Bragg reflector (DBR) can have high reflectivity for a specific wavelength or within a specific wavelength range. The two layers in each pair of film layers have different thicknesses. The thicknesses of the layers of the same material in each pair of film layers can be the same or different.

[0026] 1 to 4, the contact layer 60b is located on the second insulating structure 50b and the reflective structure (the reflective layer 40b and the barrier layer 41b) and includes a first contact portion 600b, a second contact portion 601b, and a third contact portion 602b. In one embodiment, in a top view, the second contact portion 601b is located at the geometric center of the semiconductor structure. The first contact portion 600b and the third contact portion 602b are separated from each other. The third contact portion 602b is surrounded by the first contact portion 600b. The first contact portion 600b is electrically connected to the first semiconductor layer 101b, the third contact portion 602b is electrically connected to the second semiconductor layer 102b, and the second contact portion 601b is electrically isolated from the first semiconductor layer 101b and the second semiconductor layer 102b. In one embodiment, the second contact portion 601b is electrically connected to one of the first contact portion 600b and the third contact portion 602b. In one embodiment, the first contact portion 600b contacts the second surface 1012b and the first surface 1011b through the openings 501b and the recesses 5052b of the second insulating structure 50b, and is electrically connected to the first semiconductor layer 101b. In the cross-sectional view of the surrounding portion 111b, the first contact portion 600b has an uneven surface along the periphery 505b of the first insulating structure 20b or the second insulating structure 50b. The first contact portion 600b is formed into a plurality of protrusions 5051b and a plurality of recesses 5052b along the periphery 505b, and the uneven surface is formed corresponding to the protrusions 5051b and the recesses 5052b. The first contact portion 600b is in discontinuous contact with the first surface 1011b via the plurality of recesses 2012b of the surrounding insulating portion 201b and the plurality of recesses 5052b of the second insulating structure 50b. The first contact portion 600b and the first surface 1011b of the first semiconductor layer 101b include a plurality of discontinuous first contact regions (not shown). The first contact portion 600b and the second surface 1012b of the first semiconductor layer 101b include a plurality of first contact regions (not shown).

[0027] In this embodiment, the second contact portion 601b and the third contact portion 602b are surrounded by the first contact portion 600b, and in top view, the shape of the second contact portion 601b includes a geometric shape, such as a rectangle, a circle, or an irregular shape. The third contact portion 602b contacts the reflective structure and is electrically connected to the second semiconductor layer 102b through an opening 503b in the second insulating structure 50b. A second contact region (not shown) is provided between the third contact portion 602b and the reflective structure. In one embodiment, the second contact portion 601b may be connected to the first contact portion 600b or the third contact portion 602b. The contact layer 60b may be composed of a single layer or multiple sublayers. The contact layer 60b includes a metal material, such as aluminum (Al), chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), or zinc (Zn).

[0028] 1 to 4, after forming the contact layer 60b, a third insulating structure 70b is formed on the contact layer 60b to cover the contact layer 60b. The third insulating structure 70b includes a first opening 701b and a second opening 702b. The first opening 701b of the third insulating structure 70b exposes the first contact portion 600b of the contact layer 60b. The second opening 702b exposes the third contact portion 602b of the contact layer 60b. The material of the third insulating structure 70b includes a non-conductive material. The non-conductive material includes an organic material, an inorganic material, or a dielectric material. Organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyetherimide, or fluorocarbon polymer. Inorganic materials include silicone or glass. Dielectric materials include aluminum oxide (Al2O3), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF xThe first insulating structure 20b, the second insulating structure 50b, and the third insulating structure 70b can be formed by screen printing, evaporation, or sputtering.

[0029] After forming the third insulating structure 70b, a first solder pad 80b and a second solder pad 90b are formed on the semiconductor stack 10b to complete the fabrication of the light-emitting element 2. The positions of the first solder pad 80b and the second solder pad 90b correspond to the positions of the first opening 701b and the second opening 702b, respectively, of the third insulating structure 70b. In one embodiment, the positions and shapes of the first solder pad 80b and the second solder pad 90b correspond to the positions and shapes of the first opening 701b and the second opening 702b, respectively, of the third insulating structure 70b. The first solder pad 80b contacts the first contact portion 600b of the contact layer 60b through the first opening 701b of the third insulating structure 70b and is electrically connected to the first semiconductor layer 101b. The second solder pad 90b contacts the third contact portion 602b of the contact layer 60b through the second opening 702b of the third insulating structure 70b and is electrically connected to the second semiconductor layer 102b. In one embodiment, when viewed from the top of the light-emitting device, the first solder pad 80b has the same shape as the second solder pad 90b. For example, the first solder pad 80b and the second solder pad 90b may be comb-shaped, but it is clear that the present invention is not limited thereto. In one embodiment, the shape or size of the first solder pad 80b may be different from the shape or size of the second solder pad 90b. For example, the first solder pad 80b may be rectangular, the second solder pad 90b may be comb-shaped, and the area of ​​the first solder pad 80b may be larger than the area of ​​the second solder pad 90b. In one embodiment, the first solder pad 80b and the second solder pad 90b may have a single-layer or multi-layer structure. The first solder pad 80b and the second solder pad 90b may include a metal material, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or an alloy of the above materials. When the first solder pad 80b and the second solder pad 90b include multiple layers, the first solder pad 80b includes a first upper solder pad and a first lower solder pad, and the second solder pad 90b includes a second upper solder pad and a second lower solder pad. The upper solder pad and the lower solder pad have different functions. The function of the upper solder pad is to be used for soldering and wiring.The light-emitting element 2 is inverted and mounted on the package substrate via the upper solder pads by solder or AuSn eutectic bonding. The upper solder pads include a highly ductile metal material, such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), or osmium (Os). The upper solder pads may be a single layer, multiple layers, or alloys of the above materials. In one embodiment of the present application, the material of the upper solder pads preferably includes nickel (Ni) and / or gold (Au), and the upper solder pads may be a single layer or multiple layers. The function of the lower solder pad is to form a stable interface with the contact layer 60b, the reflective layer 40b, or the barrier layer 41b, for example, to improve the interfacial bonding strength between the first lower solder pad and the contact layer 60b, or between the second lower solder pad and the reflective layer 40b or the barrier layer 41b. Another function of the lower solder pad is to prevent tin (Sn) in the solder or AuSn from diffusing into the reflective structure and damaging the reflectivity of the reflective structure. Therefore, the lower solder pad preferably contains a metal element other than gold (Au) and copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), or osmium (Os). The lower solder pad may be a single layer, a multilayer, or an alloy of the above materials. In one embodiment of the present application, the lower solder pad preferably contains a multilayer film of titanium (Ti) and aluminum (Al), or a multilayer film of chromium (Cr) and aluminum (Al).

[0030] In one embodiment, when the light-emitting element 2 is operated, an external power source is electrically connected to the first solder pad 80b and the second solder pad 90b, respectively. In this case, a current is injected into the light-emitting element 2, and the current is diffused by the first contact portion 600b and the third contact portion 602b, and then injected into the first semiconductor layer 101b and the second semiconductor layer 102b via the first contact region and the second contact region, respectively. To improve the current distribution in the light-emitting element 2, the area and position of the first contact region between the first contact portion 600b and the first surface 1011b of the first semiconductor layer 101b can be adjusted to prevent the current from concentrating in a specific region of the first surface 1011b, such as a corner of the first surface 1011b. In one embodiment, the surrounding insulating portion 201b of the first insulating structure 20b and the outer periphery 505b of the second insulating structure 50b cover a portion of the first surface 1011b of the first semiconductor layer 101b, so that the area and position of the first contact region between the contact layer 60b and the first surface 1011b can be adjusted by the surrounding insulating portion 201b and the second insulating structure 50b. In other words, the area and position of the first contact region are adjusted by the exposed portion of the first surface 1011b exposed in the recesses 2012b, 5052b of the surrounding insulating portion 201b and the second insulating structure 50b. However, when designing the surrounding insulating portion 201b of the first insulating structure 20b and the second insulating structure 50b, the forward voltage (V f ) and current distribution must be considered at the same time. Specifically, the larger the area of ​​the first contact region, the lower the forward voltage of the light-emitting element 2. However, if the area of ​​the first contact region is large, a current crowding effect occurs in the light-emitting element 2. fTo achieve a favorable current distribution, the first contact portion 600b is designed to discontinuously contact the first surface 1011b by a plurality of recesses 2012b, 5052b and to be electrically isolated from portions of the first surface 1011b by a plurality of protrusions 2011b, 5051b. In one embodiment, the first contact portion 600b is designed not to contact the corners of the first surface 1011b of the first semiconductor layer 101b. This allows current to be injected into the first semiconductor layer 101b by the discontinuous first contact region of the first contact portion 600b and not directly into the regions covered by the first insulating structure 20b and the second insulating structure 50b. Therefore, the current is spread by the first contact portion 600b and further spread by the discontinuous first contact region. In other words, the design of the surrounding insulating portion 201b and the outer periphery 505b of the second insulating structure 50b can affect the forward voltage value and change the current path, directing the current into the first surfaces exposed by the plurality of recesses 2012b and the plurality of recesses 5052b, thereby changing the current distribution. In this embodiment, the area of ​​the first contact portion 600b is sufficient to achieve an acceptable forward voltage value, for example, 2.15V to 2.4V, and a desired current distribution can be achieved in this first contact area, as will be described in detail below.

[0031] As shown in Figures 5 and 6, Figure 5 is a top view of the burnt-out region of the light-emitting device 2. Figure 6 is a top view of the burnt-out region of the conventional light-emitting device 3. The difference between the light-emitting device 2 and the conventional light-emitting device 3 is that the first insulating structure 20b' and the second insulating structure 50b' of the conventional light-emitting device 3 do not have the multiple protrusions 2011b, 5051b and the multiple recesses 2012b, 5052b like the light-emitting device 2. In the conventional light-emitting device 3, the entire first surface 1011b of the first semiconductor layer 101b is exposed and in contact with the contact layer 60b, so that the contact layer 60b is in continuous contact with the first surface 1011b of the first semiconductor layer 101b and in direct contact with the corners (not shown) of the first surface 1011b of the first semiconductor layer 101b.

[0032] As shown in FIG. 6, when a surge is applied to the conventional light-emitting element 3, the conventional light-emitting element 3 is unable to withstand the high voltage and effectively dissipate the current, resulting in current concentration at the corners, making the conventional light-emitting element 3 susceptible to damage. Referring to FIG. 6, the surge voltage exceeds the normal operating voltage of the conventional light-emitting element 3, and the surge damages the conventional light-emitting element 3 in multiple failure areas indicated by symbol f3. The current of the conventional light-emitting element 3 tends to concentrate more at the corners than in other areas. When a surge exceeding its tolerance is applied to the light-emitting element 2, the failure area of ​​the light-emitting element 2 is indicated by symbol f2, as shown in FIG. 5. The distribution of the failure area f2 is different from the distribution of the failure area f3 of the conventional light-emitting element 3. The current of the light-emitting element 2 does not concentrate at the corners of the first surface 1011b of the first semiconductor layer 101b. The current distribution of the light-emitting element 2 is more uniform than that of the conventional light-emitting element 3, and the light-emitting element 2 is more able to withstand high-voltage surges.

[0033] In this embodiment, the discontinuous first contact area between the contact layer 60b and the first surface 1011b of the first semiconductor layer 101b is beneficial to current spreading in the light emitting device 2 and can prevent breakdown of the light emitting device 2. Furthermore, the discontinuous first contact area allows the light emitting device 2 to have an acceptable forward voltage, e.g., 2.15V to 2.4V, and a predictable current distribution. In one embodiment, electrical overstress (EOS) measurements were performed on the light emitting device 2 and the conventional light emitting device 3 at different applied voltages. See FIGS. 7, 8, and 9. FIG. 7 is a waveform diagram of surge voltages in the electrical overstress (EOS) measurements. FIG. 8 is a waveform diagram of the maximum applied voltage surge and the conductible forward voltage (V) in the electrical overstress (EOS) measurements on the light emitting device 2 and the conventional light emitting device 3. f ) is a table showing the maximum applied voltage of surge and reverse current (I) in the electrical overstress (EOS) measurement of the light-emitting element 2 and the conventional light-emitting element 3.r ) is a table. To further compare the light emitting device 2 of the present application with the conventional light emitting device 3, as shown in FIG. 8, electrical overstress (EOS) measurements were performed on samples 1 and 2 of the light emitting device 2 and samples 1 and 2 of the conventional light emitting device 3. In the EOS measurements (meeting the IEC 61000-4-5 standard), surges having voltage waveforms as shown in FIG. 7 were applied to the light emitting device 2 and the conventional light emitting device 3, respectively. The voltage of each surge varied over time, and each surge had a maximum applied voltage Va(max). As shown in FIG. 8, different maximum applied voltages Va(max) were applied to multiple samples, for example, 0 V, 20 V, 30 V, 35 V, 40 V, 45 V, 50 V, 55 V, 60 V, and 65 V. For each maximum applied voltage Va(max), five surges were applied at a frequency of once per second, and each surge was approximately 10 V. -4 Each sample measures approximately 38 x 38 mils. 2 After measuring the surge voltage at the maximum applied voltage, each sample was driven at a fixed current of 10 μA, and the forward voltage (V f ) was measured and recorded in the table of FIG. 8. As shown in FIG. 8, EOS measurements were performed on samples 1 and 2 of the light-emitting element 2 at maximum applied surge voltages of 65 V and 60 V, respectively, and the measured forward voltages V f The forward voltage V is less than 2.15 V. EOS measurements were performed on samples 1 and 2 of the conventional light-emitting element 3 with a maximum applied surge voltage of 50 V. fThe forward voltage measured was less than 2.15V. In addition, the allowable forward voltage value was between 2.15V and 2.4V. After a surge of a maximum applied voltage of 60V or less was applied to sample 1 of light emitting device 2, the measured forward voltage was greater than 2.15V and less than 2.4V. That is, sample 1 of light emitting device 2 can operate normally even after the EOS measurement. After a surge of a maximum applied voltage of 55V or less was applied to sample 2 of light emitting device 2, the measured forward voltage was greater than 2.15V and less than 2.4V. That is, sample 2 can operate normally even after the EOS measurement. Compared to conventional light emitting device 3, light emitting device 2 can withstand a surge of a maximum applied voltage of 60V, and therefore light emitting device 2 showed better results in the electrical overstress (EOS) measurement.

[0034] In one example, as in the above example, as shown in FIG. 9, electrical overstress (EOS) measurements were performed using samples 1, 2, 3, and 4 of the light emitting device 2 and samples 1, 2, 3, and 4 of the conventional light emitting device 3. Surge measurements were performed on each sample by applying different maximum voltages of 0V, 60V, 65V, 70V, 75V, and 80V. After measuring the surge after applying the maximum voltage, the samples were driven at a reverse voltage of -5V, and the reverse current (I r ) was measured and the measured values ​​were recorded in the table of FIG. 9. In this example, the allowable reverse current (I r ) is less than 0.3 μA. As shown in FIG. 9, if the light-emitting element is damaged, for example, in the case of breakdown, the reverse current (I r ) occurs, and in this example, a value of 100 μA is measured as shown in FIG. 9. When electrical overstress (EOS) measurements were performed at maximum applied voltage surges of 75 V and 80 V, the reverse current I r(μA) is 100 μA, which is greater than 0.3 μA. In other words, the maximum surge voltage that can be tolerated by the light-emitting element 2 is 75 V or less. When electrical overstress (EOS) measurements were performed with a surge of a maximum applied voltage of 65 V to 80 V, the reverse current I r In other words, the maximum surge voltage that can be tolerated by the light-emitting element 3 is 65 V or less. r ) is less than 0.3 μA, after applying a surge of the maximum applied voltage of 70 V or less, the measurement results for samples 1, 2, 3, and 4 of the light-emitting element 2 show that the reverse current I r The results were zero, that is, samples 1, 2, 3, and 4 of the light emitting device 2 were still operable and passed the electrical overstress (EOS) measurement. Compared to the light emitting device 3, the light emitting device 2 could withstand a maximum applied voltage of 70 V, and therefore the light emitting device 2 showed better results than the conventional light emitting device 3 in the electrical overstress (EOS) measurement.

[0035] As shown in Figures 8 and 9, the light-emitting device 2 has better reliability than the conventional light-emitting device 3 in electrical overstress (EOS) measurements. In the present embodiment, the design of the surrounding insulating portion 201b of the first insulating structure and the outer periphery 505b of the second insulating structure 50b allows the light-emitting device 2 of the present invention to avoid current concentration at the corners. Furthermore, by adjusting the area and position of the first contact region of the contact layer 60b, an acceptable forward voltage can be achieved. This allows a forward voltage between 2.15V and 2.4V to be achieved, improving the current distribution of the light-emitting device 2 and increasing the reliability of the light-emitting device 2.

[0036] FIG. 10 is a schematic diagram of a light-emitting device 30 according to one embodiment of the present application. The light-emitting element 2 in this embodiment is mounted on a first pad 511 and a second pad 512 of a package substrate 51 in a flip-chip format. The first pad 511 and the second pad 512 are electrically insulated from each other by an insulating portion 53 containing an insulating material. In the flip-chip mounting, the growth substrate 11b, which faces the solder pad formation surface, faces upward, and the growth substrate side serves as the main light extraction surface. A reflective structure 54 may be provided around the light-emitting element 2 to enhance the light extraction efficiency of the light-emitting device 30.

[0037] 11 is a schematic diagram of a light emitting device 4 according to one embodiment of the present application. The light emitting device 4 is a light bulb, and includes a light cover 602, a reflector 604, a light emitting module 610, a light base 612, a heat dissipation sheet 614, a connection part 616, and an electrical connection element 618. The light emitting module 610 includes a mounting part 606 and a plurality of light emitting units 608 located on the mounting part 606, and the plurality of light emitting units 608 may be the light emitting element 2 or the light emitting device 30 in the above embodiment.

[0038] The examples illustrated in this application are intended to illustrate the present application and not to limit the scope of the present application, and any obvious modifications or variations thereto are intended to fall within the spirit and scope of the present application. [Explanation of symbols]

[0039] 2 Light-emitting element 3. Conventional light-emitting devices 4. Light-emitting device 10b Semiconductor stack 11b board 20b, 20b' First insulating structure 30 Light-emitting device 30b Transparent conductive layer 40b reflective layer 41b Barrier layer 50b, 50b' Second insulating structure 60b, 60b' contact layer 70b Third insulating structure 80b First solder pad 90b Second solder pad 100b through hole 101b First semiconductor layer 102b second semiconductor layer 102sb surface 103b Active layer 111b Enclosed section 201b Enclosing insulation part 203b Annular coverage area 301tb aperture 401tb aperture 411tb aperture 501b aperture 503b aperture 505b Enclosure 600b First contact part 601b Second contact part 602b Third contact part 701b First opening 702b Second opening 1000b semiconductor structure 1002b Inner wall 1001b Second outer wall 1003b First outer wall 1011b First surface 1012b Second surface 2011b Protrusion 2012b Concavity 5051b Protrusion 5052b Recessed part f2 failure area f3 failure area 51 Package substrate 53 Insulation section 54 Reflective structure 511 First Pad 512 Second Pad 602 Light Cover 604 Reflector 606 Mounting section 608 Lighting Unit 610 Light Emitting Module 612 Light Base 614 Heat dissipation sheet 616 Connection 618 Electrical Connection Elements

Claims

1. A light-emitting element, a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a contact layer overlying the semiconductor structure and including a first contact portion, a second contact portion, and a third contact portion spaced apart from one another; a third insulating structure located on the contact layer and having an opening; a first solder pad in contact with the first contact portion of the contact layer; a second solder pad in contact with the third contact portion of the contact layer; the second contact portion is formed at the geometric center of the semiconductor structure, and the second contact portion is electrically insulated from the first semiconductor layer and the second semiconductor layer; The shape of the first contact portion corresponds to the shape of the opening.

2. The light-emitting element of claim 1 , wherein the shape of the second contact portion comprises a rectangle, a circle, or an irregular shape.

3. The light-emitting device of claim 1 , wherein the second contact portion comprises a metallic material.

4. further comprising a first insulating structure located on the semiconductor structure; 10. The light-emitting element of claim 1, wherein in a top view of the light-emitting element, the first insulating structure includes a plurality of protrusions covering a first surface of the first semiconductor layer, a plurality of recesses exposing the first surface of the first semiconductor layer, and a second insulating structure positioned between the second contact portion and the semiconductor structure.

5. further comprising a second insulating structure located on the first insulating structure; The light emitting device of claim 4 , wherein in the top view, the second insulating structure comprises a plurality of second protrusions and a plurality of second recesses.

6. the positions of the plurality of first protrusions correspond to the positions of the plurality of second protrusions; The light-emitting device according to claim 5 , wherein the positions of the plurality of first recesses correspond to the positions of the plurality of second recesses.

7. The light-emitting device according to claim 6 , wherein the area of ​​the second protrusion is smaller than the area of ​​the first protrusion.

8. The light-emitting element according to claim 1 , wherein the shape of the first solder pad comprises a comb shape.

9. The light emitting device of claim 1 , wherein the first solder pad has a different area or shape from the second solder pad.

10. The light-emitting device of claim 4 , wherein the second insulating structure comprises a distributed Bragg reflector (DBR).

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