CTAT current generation circuit and bgr circuit

Abstract

To achieve a more compact CTAT current generation circuit by reducing an area occupied by resistors.SOLUTION: A CTAT current generation circuit 11 comprises: a current mirror circuit 111; N (where N≥2) transistors MD1 to MDN connected in series in one current path; a transistor M1 connected in the other current path; and transistors M2 and a resistor R1' connected in series to an output line. A gate G of the transistor M1 is connected to a connection point between the transistor M2 and resistor R1'. The gate G of the transistor M2 is connected to a connection point between the current mirror circuit 111 and transistor M1. An output voltage VBE1 corresponding to a bandgap voltage from the PTAT current generation circuit 10 is applied to the gate G of transistor MD1.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a CTAT current generating circuit and a BGR circuit that mainly operate with low power consumption. [Background technology]

[0002] In semiconductor integrated circuits (LSI: Large Scale Integration), the reference voltage source circuit is an essential circuit block for analog signal processing. Generally, LSIs are required to have an output voltage that does not change with changes in the manufacturing process, power supply voltage, and operating temperature. The changes in each item are called PVT variations, and the reference voltage source circuit in particular is required to have high PVT variation tolerance.

[0003] A well-known reference voltage source circuit is the bandgap reference (BGR) circuit, which generates a voltage based on the silicon bandgap voltage (1.2 V). BGR circuits have high PVT tolerance and are widely used as on-chip reference voltage source circuits.

[0004] BGR circuits with various architectures have been proposed. Among them, Non-Patent Document 1 proposes a low-voltage BGR circuit that can change the output voltage depending on the resistor ratio used. This low-voltage BGR circuit can operate at a low voltage of 1 volt or less, consumes low power, and allows the reference voltage to be set arbitrarily. Because the temperature dependence of the operating current can be controlled, it can also be used as a reference current source, which has attracted attention. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] H. Banba et al., “A CMOS bandgap reference circuit with sub-1-V operation,” in IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 670-674, May 1999, doi: 10.1109 / 4.760378. Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the low-voltage BGR circuit described in Non-Patent Document 1, if the current flowing through it is set to the order of nanoamperes in order to reduce power consumption, it is necessary to use extremely large resistors. Such an increase in resistance value leads to an increase in the area of ​​the resistors mounted on the LSI chip, which also leads to an increase in costs.

[0007] These issues will be explained in more detail below. First, the device characteristics of bipolar transistors and MOSFETs operating in the subthreshold region, which are necessary for explaining low-voltage BGR circuits, will be explained, and then the operation of the low-voltage BGR circuit described in Non-Patent Document 1 will be explained with reference to Figures 1 and 2.

[0008] <A.1> Overview of device characteristics <A.1.1> Bipolar transistor characteristics Base-emitter voltage V of a bipolar transistor BE is the current flowing I B Then, it is expressed by the following equation.

[0009]

number

[0010] where I S is the saturation current, V T is the thermal voltage (V T =K B T / q), K Bis the Boltzmann constant, T is the absolute temperature, and q is the elementary charge. BE has a negative temperature characteristic with respect to absolute temperature, so I B When the temperature characteristic of is small, it can be approximated as in Equation 2.

[0011]

number

[0012] where V BGR is the bandgap voltage of silicon (~1.2V), and γ is the temperature coefficient.

[0013] <A.1.2> MOSFET subthreshold characteristics MOSFET gate-source current V GS is the threshold voltage V TH When the subthreshold current I D When the drain-source voltage is 0.1V or more, I D can be approximated by an exponential function and is expressed as Equation 3.

[0014]

number

[0015] where I0 is the pre-factor of the subthreshold current, and η is a device-dependent constant due to the gate oxide capacitance and depletion layer capacitance.

[0016] <A.2> Low voltage BGR circuit <A.2.1> Low-voltage BGR circuit operating principle Figure 1 shows a conventional low-voltage BGR circuit proposed in Non-Patent Document 1. The size ratio of bipolar transistors Q1 and Q2 is set to 1:M, and R2 is connected in series to Q2. Resistor R1 is also connected in parallel to these. An operational amplifier is used to a and V b The voltages are at the same potential (V a =V b), the current I flows through the pair of PMOS transistors that make up the current mirror. REF This current I REF is applied to resistor R3 via a current mirror, and a reference voltage V REF The circuit operation will be explained in detail below.

[0017] The base-emitter voltages of bipolar transistors Q1 and Q2 are V BE1 and V BE2 Then, the current I flowing through resistor R2 R2 is expressed by the following equation 4.

[0018]

number

[0019] On the other hand, the current I flowing through resistor R1 R1 is the number 5.

[0020]

number

[0021] Therefore, the current flowing through the circuit I REF is the number 6.

[0022]

number

[0023] Here, the gate-source voltage and drain-source voltage of the two PMOS transistors that supply current to bipolar transistors Q1 and Q2 are equal, so the current flowing through each current path is equal. a =V b Therefore, the currents flowing through the resistor R1 are equal, so the currents flowing through the bipolar transistors Q1 and Q2 are equal (I Q1 =I Q2 ) The current I flowing through resistor R2 R2 is expressed by the formula 7.

[0024]

number

[0025] Therefore, I REF is the number 8.

[0026]

number

[0027] Here, I in number 8 REF The first term on the right side of the equation has a negative temperature dependency (CTAT: Complementary To Absolute Temperature), and the second term has a positive temperature dependency (PTAT: Proportional To Absolute Temperature). In other words, the low-voltage BGR circuit shown in Figure 1 has a current I REF The temperature dependence of the

[0028] Generated current I REF By supplying this to resistor R3, a voltage V that depends on the BGR voltage is generated. REF can be generated, i.e., the number 9.

[0029]

number

[0030] Furthermore, V in Math 2 BE1 =V BGR Considering −γT, Equation 9 can be expressed as Equation 10.

[0031]

number

[0032] Therefore, as in equation 11, the term related to temperature T is set to 0.

[0033]

number

[0034] As a result, by designing resistors R1, R2, R3, and M to satisfy equation 11, the temperature-compensated reference voltage V REF can be obtained as shown in Equation 12.

[0035]

number

[0036] The resistor ratio R3 / R1 determines the BGR voltage V BGR Any of the following voltages can be generated:

[0037] <A.2.2> Issues with low-voltage BGR circuits To achieve long-term continuous operation of battery-powered devices, it is necessary to reduce the power consumption of the circuit. This can be achieved by setting the current flowing through the low-voltage BGR circuit to a minute current on the order of nanoamperes. However, reducing the power consumption of a low-voltage BGR circuit that uses resistors poses the problem of increasing the amount of resistors used.

[0038] Figure 2 shows the current I used in the low-voltage BGR circuit of Figure 1. R1 This is a circuit that generates a current I R1 is the base-emitter voltage V of bipolar transistor Q1 BE1 It is generated by connecting a resistor R1 in parallel to V. BE1 The voltage is set to 400mV, and the current I is set to 10nA. R1 When the resistor R1 is calculated as shown in Equation 13,

[0039]

number

[0040] From equation 13, a resistor of R1 = 40 MW is required. Assuming a 0.18-μm CMOS process, consider the case where a polysilicon resistor with a high resistance value (sheet resistance: 1.037 kW / square) is used. The width W of the basic polysilicon resistor R1 and length L R1 W R1 L = 2 μm R1 = 757 μm, 100 basic polysilicon resistors must be connected in series, resulting in an area of ​​230 × 760 μm, which occupies an extremely large chip area to implement a single resistor on-chip.

[0041] The present invention has been made in view of the above, and has as its object to provide a CTAT current generating circuit and a BGR circuit that are compact by reducing the area occupied by resistors. [Means for solving the problem]

[0042] The CTAT current generating circuit according to the present invention includes a current mirror circuit having left and right current paths, N (N≧2) transistors connected in series to one of the current paths, a first transistor connected to the other current path, and a second transistor and a resistor connected in series to an output line, and a voltage V BE1 is applied, and the potential of the control terminal of the first transistor and the connection point between the second transistor and the resistor is V BE1 / N.

[0043] According to the present invention, the voltage applied between N transistors connected in series is divided by N. The output voltage V corresponding to a predetermined or reference voltage, for example, a bandgap voltage, is output from an external circuit. BE1 is input to the control terminal of the first-stage transistor connected to the current mirror circuit among the N transistors, a current I1 is supplied to the first transistor interposed in the other current path of the current mirror circuit, and this current I1 generates a gate-source voltage V GS1is generated, which causes a current to flow through the resistor. Therefore, the voltage across the resistor is equivalent to V BE1 / N, and the resistor R1' is increased by N times compared to the conventional resistor. This reduces the amount of resistance used that equivalently changes the current and voltage by 1 / N, resulting in a more compact design.

[0044] In addition, the CTAT current generation circuit according to the present invention comprises a current mirror circuit having left and right current paths, N (N≧2) transistors connected in series to one of the current paths, a first transistor connected to the other current path, and a second transistor and a resistor connected in series to an output line, wherein the control terminal of the first transistor is connected to the connection point between the second transistor and the resistor, and the control terminal of the second transistor is connected to the connection point between the current mirror circuit and the first transistor, and an output voltage corresponding to the bandgap voltage from the PTAT current generation circuit is applied to the control terminal of the transistor connected to the current mirror circuit among the N transistors.

[0045] According to the present invention, the voltage applied across N series-connected transistors is divided by N. The output voltage V corresponding to the bandgap voltage from the PTAT current generating circuit is BE1 is input to the control terminal of the first-stage transistor connected to the current mirror circuit among the N transistors, a current I1 is supplied to the first transistor interposed in the other current path of the current mirror circuit, and this current I1 generates a gate-source voltage V GS1 is generated, which causes a current to flow through the resistor. Therefore, the voltage across the resistor is equivalent to V BE1 / N, and the resistor R1' is increased by N times compared to the conventional resistor. This reduces the amount of resistance used that equivalently changes the current and voltage by 1 / N, resulting in a more compact design.

[0046] The bandgap voltage is the bandgap voltage of silicon. With this configuration, it is possible to generate a reference voltage that is set to the bandgap voltage of silicon, 1.2V, using a predetermined resistance ratio or the like.

[0047] Furthermore, by using MOS transistors for each transistor, a circuit suitable for low power consumption is constructed.

[0048] In addition, the BGR circuit of the present invention comprises a PTAT current generating circuit having left and right current paths, a CTAT current generating circuit according to any one of claims 1 to 3, and an adding circuit that outputs the currents flowing through each current path of the PTAT current generating circuit and the CTAT current generating circuit via a current mirror circuit and adds them up.

[0049] According to the present invention, in addition to making the CTAT current generating circuit more compact, the PTAT current generating circuit also does not need two resistors R1, so the entire BGR circuit can also be made more compact.

[0050] The adder circuit is also provided with a resistor that converts the added output into a voltage and outputs it. This configuration makes it possible to provide a voltage source circuit in addition to a current source circuit.

[0051] The present invention also includes a startup circuit that generates a startup signal and outputs it to the PTAT current generation circuit when it detects that the output of the adder circuit is 0. This configuration makes it possible to ensure the startup of the PTAT current generation circuit. [Effects of the Invention]

[0052] According to the present invention, it is possible to provide a CTAT current generating circuit and a BGR circuit that are compact and have a reduced area occupied by resistors. [Brief explanation of the drawings]

[0053] [Figure 1] This is a conventional low-voltage BGR circuit proposed in Non-Patent Document 1. [Figure 2] This is a circuit for generating the current IR1 used in the low-voltage BGR circuit of Figure 1. [Figure 3] 1 is a circuit diagram showing an embodiment of a CTAT current generating circuit according to the present invention. [Figure 4] 4 is a circuit diagram showing an embodiment of a BGR current source circuit using the CTAT current generation circuit of FIG. 3. [Figure 5] 4 is a circuit diagram showing an embodiment of a BGR voltage source circuit using the CTAT current generation circuit of FIG. 3. [Figure 6] FIG. 2 is a diagram illustrating a startup circuit. [Figure 7] 1 shows a circuit in which a PTAT current generating circuit and a bias voltage generating circuit are connected. [Figure 8] FIG. 10 is a diagram illustrating a BGR current source circuit when N=3. [Figure 9] FIG. 10 is a diagram showing the temperature characteristics of a current IREF in the range of −20 to 100° C. [Figure 10] FIG. 10 is a diagram showing a histogram of the average value (μ) of the current IREF by Monte Carlo simulation (number of trials: 1000). [Figure 11] FIG. 10 is a diagram showing layout diagrams (estimated: wiring area excluded) of a comparative example (N=0) and an example (N=3) when IREF=100 nA. [Figure 12] FIG. 10 is a diagram showing layout diagrams (estimated: wiring area excluded) of a comparative example (N=0) and an example (N=0) when IREF=10 nA. [Figure 13] FIG. 10 is a diagram illustrating a BGR voltage source circuit when N=4. [Figure 14] This shows the BGR voltage source circuit when N=6. [Figure 15] FIG. 10 is a diagram showing the temperature characteristics of a voltage VREF in the range of −20 to 100° C. [Figure 16] FIG. 10 is a diagram showing a histogram of the average value (μ) of the voltage VREF obtained by Monte Carlo simulation (number of trials: 1000). [Figure 17]FIG. 10 is a diagram showing layout diagrams (excluding wiring areas) of a comparative example (N=0) and examples (N=4, 6). [Figure 18] This is a diagram for eight chips showing the temperature characteristics of the current IREF at −20 to 100° C. [Figure 19] FIG. 10 is a diagram for eight chips showing the power supply voltage dependency of the current IREF. DETAILED DESCRIPTION OF THE INVENTION

[0054] The CTAT current generating circuit and the BGR circuit according to the present invention will be described below item by item with reference to FIGS.

[0055] [1] Reducing the area of ​​BGR circuits that operate with low power consumption When aiming to reduce the power consumption of conventional BGR circuits, it is necessary to use an extremely large resistor to generate the CTAT current, which increases the area occupied by the resistor on the LSI chip and leads to increased costs. Therefore, below we propose a technology to reduce the area of ​​the CTAT current generation circuit.

[0056] [1.1] Reduction of area of ​​CTAT current generation circuit 3 is a circuit diagram showing an embodiment of a CTAT current generating circuit 11 according to the present invention. The CTAT current generating circuit 11 generates a base-emitter voltage V BE1 The CTAT current I R1’ Output.

[0057] The CTAT current generation circuit 11 includes a PMOS current mirror circuit 111 made up of a group of PMOS transistors, and causes an equal current I1 to flow through the left and right current paths. BE1 The current path on one side (left side) to which is input has N (N≧2) transistors of the same size, for example, NMOS transistors M D1 ,··M DN The base-emitter voltage V of the bipolar transistor Q1 (Figure 4) is BE1 is the first stage NMOS transistor M D1This is input to the gate of the NMOS transistor M D1 ,··M DN The current I1 is generated by dividing it into N equal parts using the formula (14).

[0058]

number

[0059] The generated current I1 is input to the NMOS transistor M1 via the other (right) current path from the PMOS current mirror circuit 111. The gate of the NMOS transistor M1 is connected to the output line. This output line is formed by connecting the NMOS transistor M2 and a resistor R1' in series. The gate G of the NMOS transistor M1 is connected to the connection point between the source S of the NMOS transistor M2 and the resistor R1'. The gate G of the NMOS transistor M2 is connected to the drain D of the NMOS transistor M1. With this circuit configuration, the output level is set by the NMOS transistor M1, and the output current I R1’ is generated.

[0060] At this time, a current I1 flows through the NMOS transistor M1, and the gate-source voltage V GS1 becomes the number 15.

[0061]

number

[0062] The voltage applied to resistor R1' is V GS1 and the output current I from the NMOS transistor M2 R1’ is expressed as in equation 16.

[0063]

number

[0064] This makes it possible to generate a CTAT current that exhibits negative temperature dependency. Moreover, as can be seen from Equation 16, the resistance value can be equivalently increased by N times compared to the CTAT current shown in Non-Patent Document 1, and in addition, it is possible to eliminate the need for resistor R1, which requires a large chip area as in Non-Patent Document 1.

[0065] [1.2] BGR circuit using CTAT current generation circuit 11 Next, a BGR circuit using the CTAT current generation circuit 11 will be described. Fig. 4 is a circuit diagram showing an embodiment of a BGR current source circuit 1 using the CTAT current generation circuit 11. Fig. 5 is a circuit diagram showing an embodiment of a BGR voltage source circuit 2 using the CTAT current generation circuit 11. Fig. 6 is a diagram showing a startup circuit 21, and Fig. 7 is a diagram showing the PTAT current generation circuit 10 and a bias voltage generation circuit 22.

[0066] [1.2.1]BGR current source circuit 1 As shown in FIG. 4, the BGR current source circuit 1 includes a PTAT current generating circuit 10, a CTAT current generating circuit 11, and a current adding circuit 12.

[0067] The PTAT current generator 10 sets the size ratio of bipolar transistors Q1 and Q2 to 1:M, and connects resistor R2 in series with bipolar transistor Q2. The PMOS current mirror circuit 101 equalizes the currents flowing through the left and right current paths of the PTAT current generator 10, and the NMOS transistor pair BE1 and V in Q2 BE2 The voltage across resistor R2 is set equal to the current I R2 is expressed as in Equation 17. The PTAT current generating circuit 10 differs from the conventional circuit configuration of Fig. 1 in that it does not require the resistor R1 connected in parallel with the bipolar transistor pair Q1, Q2.

[0068]

number

[0069] As explained in FIG. 3, the CTAT current generating circuit 11 generates a current I R1 ' is generated.

[0070]

number

[0071] The current adder circuit 12 calculates the PTAT current I R2 and CTAT current I R1 ' and ' are generated through the respective current mirror circuits and added together to obtain the reference current I REF That is, the reference current I REF is expressed as in Equation 19.

[0072]

number

[0073] Therefore, by designing the values ​​of resistors R1', R2 and size ratio M so that the number 20 is satisfied, the temperature-independent current I REF can be generated.

[0074]

number

[0075] Then, the resistors R1', R2, and the size ratio M are designed to satisfy the number 20, so that the temperature-independent current I REF can be generated.

[0076] [1.2.2] BGR voltage source circuit 2 As shown in FIG. 5, the BGR voltage source circuit 2 includes a PTAT current generating circuit 10, a CTAT current generating circuit 11, a current adding circuit 12, and a voltage generating circuit 13.

[0077] The BGR voltage source circuit 2 is configured by adding a voltage generation circuit 13 to the BGR current source circuit 1 shown in Figure 4. The voltage generation circuit 13 is configured with a resistor R3. The resistor R3 has a current I REF flows, the output voltage V REF becomes the number 21.

[0078]

number

[0079] Here, by designing the values ​​of resistors R1', R2 and size ratio M so that equation 22 is satisfied, a temperature-independent voltage V REF can be generated.

[0080]

number

[0081] Also, the voltage V REF is expressed as in equation 23.

[0082]

number

[0083] By changing the number of divisions N and the resistors R1' and R3, an arbitrary voltage V REF can be generated.

[0084] [1.2.3] Start-up circuit 21 The PTAT current generator circuit 10 is self-biased, so in addition to the desired operating point, the current I R2 = 0 (A). In other words, in addition to the desired voltage and current, the circuit can also operate when the current flowing through the two current paths is 0 (A). However, I R2= 0 (A) is an undesirable operating point, and this operating point must be avoided. The start-up circuit is provided to avoid this undesirable operating point. The start-up circuit operates when the PTAT current generating circuit 10 (see FIGS. 4 and 5) is not operating (I R2 =0(A)) to ensure that the output current is 0(A) (I REF =0(A)) and forcibly injects current into the PTAT current generating circuit 10 to operate the circuit at a desired operating point.

[0085] FIG. 6 shows the startup circuit 21. MS1 to MS9 are MOS transistors. When the PTAT current generating circuit 10 is not operating at a desired operating point, I REF =0A, so V REF becomes 0V. The startup circuit 21 detects this using an inverter consisting of MS3 and MS4 and outputs a High signal, which is an inverted signal. At this time, the startup circuit 21 uses diode-connected MS1, MS2, and MS5 to adjust the inversion point of the inverter and also suppress through current.

[0086] The startup circuit 21 then further inverts the output signal using an inverter consisting of MS6 and MS7, and again makes it swing to full swing, generating a low-level signal. ST , and starts the PTAT current generating circuit 10. When the PTAT current generating circuit 10 is started and starts operating, V REF will generate the desired voltage. V REF When the desired voltage is generated, the inverter consisting of MS3 and MS4 outputs a low signal as an inverted signal, and the inverter consisting of MS6 and MS7 outputs a high signal, so the current flowing through MS8 and MS9 is turned off, and the startup circuit 21 completes its operation.

[0087] [1.2.4] Bias voltage generation circuit 22 The PTAT current generator circuit 10 shown in Figures 4 and 5 uses a cascode current mirror consisting of an NMOS transistor pair on the lower side of the PMOS current mirror circuit 101. Cascode current mirrors have the problem of requiring a high minimum operating voltage. Therefore, a low-voltage cascode current mirror is used to reduce the minimum operating voltage.

[0088] 7 shows a circuit in which the PTAT current generating circuit 10 and the bias voltage generating circuit 22 are connected. The bias voltage generating circuit 22 receives a current via a PMOS current mirror circuit 101 of the PTAT current generating circuit 10, and outputs a voltage to an NMOS transistor M B , and further includes a bipolar transistor Q1' in series. The bias voltage generating circuit 22 has a two-stage series configuration of PMOS transistors to improve accuracy. The NMOS transistor M B By properly designing V BIAS can be generated.

[0089] [2] Simulation evaluation Next, the effectiveness of the CTAT current generator was tested using SPICE simulation (Simulation Program with Integrated Circuit Emphasis). REF Two types of current source circuits were evaluated: 10 and 100 nA. REF = 600mV, and two types of voltage source circuits with N = 4 and 6 were evaluated.

[0090] [2.1] Simulation evaluation of BGR current source circuit Figure 8 shows the BGR current source circuit (test circuit) with the division number N=3 (MD1, MD2, MD3). Current I REF The parameters were adjusted to be =10,100 nA.

[0091] Figure 9 shows the current I REF The temperature characteristics of I REFThe temperature coefficients at =100 and 10nA were 66.0 and 35.8 ppm / °C, respectively.

[0092] Figure 10 shows the current I REF The histogram of the mean value (μ) of I is shown (number of trials: 1000). REF The variance (σ) at = 100 and 10 nA was 5.21 and 0.512 nA, respectively, and the coefficient of variation was 5.21 and 5.12%.

[0093] To confirm the area reduction effect, we designed a test circuit layout. REF The figures show layout diagrams (excluding wiring area) of a comparative example (N=0) which is a conventional circuit and a test circuit (N=3) according to the embodiment when the current is set to 100 nA. In the embodiment, it was confirmed that the area of ​​resistor R1' was reduced to one-third of that of R1 in the conventional example (R1=9.88, R1'=3.23 MΩ). Note that the area of ​​the NMOS transistors MD1-3 and M1 increased, so the total area only decreased slightly. This was because the device size and the number of parallel connections of the MOS transistors were increased to eliminate transistor performance variations. Because the size of the resistors used was clearly reduced, optimizing the transistor size is expected to reduce the overall area.

[0094] Figure 12 shows I REF The layout diagrams (excluding wiring area) of the comparative example (N=0) and the test circuit according to the embodiment (N=3) when I = 10 nA are shown. As mentioned above, it was confirmed that the area of ​​the test circuit resistor R1' can be reduced to one-third of that of the comparative example R1 (R1=95.5, R1'=31.5 MΩ). REF As in the case of =100 nA, the area increased by the area of ​​the NMOS transistors MD1 to MD3 and M1. However, because the area of ​​the resistor R1 in the comparative example became extremely large, the total area was successfully reduced to about one-third of that of the comparative example.

[0095] Tables 1 and 2 are REFThis figure summarizes the simulation results for BGR current sources of 100 and 10nA. Here, we compared the PVT variation tolerance of the example (N=3) and the comparative example (N=0). It was found that there was no significant difference in performance in terms of the coefficient of variation of process variation (σ / μ), temperature dependence (TC), or power supply voltage dependence (LS).

[0096] Also, I REF At I = 100nA, the area occupied by the transistor circuit was relatively large, but the resistor area could be reduced, so the total area reduction effect was about 7%, as shown in the bottom row of Table 1. To achieve a larger reduction effect, optimization of the transistor circuit is necessary. REF At 10nA, the effect of reducing the resistor area was significant, and as shown in the bottom row of Table 2, it was confirmed that the area could be reduced to about one-third.

[0097] [Table 1]

[0098] [Table 2]

[0099] [2.2] Simulation evaluation of BGR voltage source circuit 13 and 14 are diagrams showing BGR voltage source circuits with the division number N=4, 6. The startup circuit 21 and bias voltage generating circuit 22 are included in FIGS. 13 and 14. Also, in FIGS. 13 and 14, compared to FIG. 8, a voltage generating circuit 13 consisting of a resistor R3 is connected to the output terminal, and functions as a voltage source circuit. The voltage V REF The circuit was designed to have a voltage of 600mV and a current consumption of less than 100nA.

[0100] Figure 15 shows the voltage V REF The temperature coefficients for N=4 and N=6 are 21.9 and 27.8 ppm / °C, respectively.

[0101] Figure 16 shows the voltage V REF The histogram of the average value (μ) of (number of trials: 1000) is shown. The variance (σ) for N=4 and N=6 was 4.7 and 4.6 mV, respectively, and the coefficient of variation was 0.79 and 0.77%. Note that the values ​​indicated in Figures 15 and 16 show better values ​​than those for the current source circuit in Figure 8, due to the inclusion of resistor R3.

[0102] FIG. 17 shows the layout diagrams (excluding wiring area) of the BGR circuits of a comparative example (N=0) of the conventional circuit and examples (N=4, 6) of the proposed circuit. Comparing the layout of resistor R1, we confirmed that the resistance value was reduced to approximately 1 / 4 or 1 / 6 depending on the division number N=4 or 6. However, as with the current source circuit (FIG. 8), the area of ​​NMOS transistors MD1-MD3 and M1 increased. Based on this, we found that the area of ​​the BGR circuit with N=4 was reduced to approximately 1 / 2 compared to the comparative example. With N=6, resistor R1 was reduced to 1 / 6, but the area of ​​NMOS transistors MD5 and MD6 increased, resulting in a total area similar to that of the BGR circuit with N=4. This is because although resistor R1 was reduced, the area of ​​resistor R3 dominates.

[0103] [Table 3]

[0104] Table 3 summarizes the simulation results. The PVT variation tolerance of the example and the comparative example (N=0) is compared. It was found that there was no substantial difference in performance in terms of process variation (σ / μ) and temperature dependency (TC). However, in terms of power supply voltage dependency (LS), the power supply voltage dependency deteriorated as the number of divisions N increased. This is thought to be due to the drain dependency of MD1 of the MOSFET in the CTAT current generation circuit. The mounting areas for the number of divisions N=4 and N=6 were approximately the same, but it was confirmed that by adopting the example, the area could be reduced by approximately 50% compared to when the example was not adopted.

[0105] [3] Measurement results We fabricated eight chips of the proposed BGR current source circuit using a 0.18-μm CMOS process. The CTAT current generator has a division number of N=3, and the output current is I REF =100nA.

[0106] Figure 18 shows the current I REF The temperature characteristics of the chips are shown below (8 chips). REF The standard deviation σ of the current I was 1.16 nA, and the coefficient of variation was 1.16%. REF This figure shows the power supply voltage dependency of I for eight chips. As shown in Figure 19, the characteristics of the eight chips are similar. The power supply voltage dependency was 0.93% / V. Also, when the power supply voltage was 1.3V or higher, I REF Table 4 shows a summary of the measurement results of the prototype chip fabricated using the 0.18-μm CMOS process and the SPICE simulation results in Table 1.

[0107] [Table 4]

[0108] In this way, among the measurement results of the BGR current source circuit prototyped on a chip, I REF The standard deviation (σ), coefficient of variation (σ / μ), and power supply voltage dependency (LS) of the were comparable to the SPICE simulation results. [Explanation of symbols]

[0109] 1 BGR current source circuit (BGR circuit) 2 BGR voltage source circuit (BGR circuit) 10 PTAT current generation circuit 11 CTAT current generation circuit 12 Current summing circuit 13 Voltage generation circuit 21 Start-up circuit 22 Bias voltage generation circuit 111 PMOS current mirror circuit MD1~MD N NMOS transistor M1, M2 NMOS transistors R1' resistor

Claims

1. a current mirror circuit having left and right current paths; N (N≧2) transistors connected in series to one current path; a first transistor connected to the other current path; a second transistor and a resistor connected in series to the output line; A voltage V is applied to the control terminal of the transistor connected to the current mirror circuit among the N transistors. ＢＥ１ is applied, The potential of the control terminal of the first transistor and the connection point between the second transistor and the resistor is V ＢＥ１ / N, a CTAT current generating circuit.

2. a current mirror circuit having left and right current paths; N (N≧2) transistors connected in series to one current path; a first transistor connected to the other current path; a second transistor and a resistor connected in series to the output line; a control terminal of the first transistor is connected to a connection point between the second transistor and the resistor; a control terminal of the second transistor is connected to a connection point between the current mirror circuit and the first transistor; a PTAT current generating circuit in which an output voltage corresponding to the bandgap voltage from a PTAT current generating circuit is applied to a control terminal of a transistor connected to the current mirror circuit among the N transistors;

3. 2. The CTAT current generating circuit of claim 1, wherein the bandgap voltage is the bandgap voltage of silicon.

4. 2. The CTAT current generating circuit of claim 1, wherein each of said transistors is a MOS transistor.

5. a PTAT current generating circuit having left and right current paths; a CTAT current generating circuit according to any one of claims 2 to 4; a BGR circuit including an adder circuit that outputs the currents flowing through the current paths of the PTAT current generating circuit and the CTAT current generating circuit via a current mirror circuit and adds them together.

6. 6. The BGR circuit according to claim 5, wherein the adder circuit includes a resistor that converts the added output into a voltage and outputs the voltage.

7. 6. The BGR circuit according to claim 5, further comprising a startup circuit that generates a startup signal and outputs it to the PTAT current generating circuit when the output of the adding circuit detects 0.

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