Communication device, processing method for communication device, and program

Abstract

To hold a time at which a packet has been received or a time at which a packet is transmitted with a small error.SOLUTION: A communication device includes: detection means 602, 604 for detecting a write or read of a predetermined packet based on a signal on a channel for writing a packet received from the outside to a memory unit or a signal on a channel for transmitting a packet read from the memory unit to the outside; and time holding means 606 for holding a current time of a clock unit as a time of write holding or a time of read holding if a write or read of the predetermined packet is detected.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to a communication device, a processing method for a communication device, and a program. [Background technology]

[0002] Recently, technology for synchronizing time between multiple devices connected via a network has been used in a wide range of fields. Precision Time Protocol (PTP) is a widely used technology for synchronizing time between multiple devices.

[0003] In PTP, the time synchronization source and destination terminals each acquire the current time (timestamp) when they send or receive a specified PTP packet, and use the timestamp to calculate the network delay time (one-way transmission time) between the terminals.The destination terminal then calculates the time difference with the time synchronization source terminal based on the network delay time, corrects its own clock, and synchronizes with the time synchronization source.

[0004] Patent Document 1 discloses a technique for acquiring a time stamp during wireless communication and performing time synchronization. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-111654 Summary of the Invention [Problem to be solved by the invention]

[0006] In time synchronization using PTP, it is known that the closer the timestamp is acquired to the lower network layers, such as the PHY layer or MAC (Media Access Control) layer, the more accurate the time synchronization can be.

[0007] When the acquisition timing is at a higher layer, the timestamp includes not only fluctuations in the transmission time when packets flow over the network, but also fluctuations in memory access within the terminal and fluctuations due to CPU processing. The greater these fluctuations, the more the time synchronization accuracy deteriorates.

[0008] For this reason, some wireless communication chips and network interface cards (hereafter referred to as NICs) that handle lower layer processing have built-in functionality for acquiring timestamps when packets are sent or received.

[0009] However, if a communications chip or NIC with this function is not available, a timestamp will be obtained when the upper layer detects the start of PTP packet transmission or when it detects the reception of a PTP packet.

[0010] In other words, the timestamp at the time of reception includes the memory access latency from when the packet received from the communications chip or NIC is written to the PTP packet in its own memory area such as DRAM.

[0011] The timestamp at the time of transmission includes the time it takes for the PTP packet in the device's own memory area, such as DRAM, to be passed to the communications chip or NIC. These fluctuations lead to a deterioration in synchronization accuracy.

[0012] An object of the present disclosure is to make it possible to maintain the time when a packet is received or the time when a packet is transmitted with a small error. [Means for solving the problem]

[0013] The communication device has a detection means for detecting the writing or reading of a specified packet based on a signal of a channel for writing a packet received from the outside to a memory unit or a signal of a channel for transmitting a packet read from the memory unit to the outside, and a time holding means for holding the current time of the clock unit as the write holding time or read holding time when the writing or reading of the specified packet is detected. [Effects of the Invention]

[0014] According to the present disclosure, the time when a packet is received or the time when a packet is transmitted can be maintained with a small error. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 illustrates an example of the configuration of a communication system. [Figure 2] FIG. 1 illustrates an example of the configuration of a digital camera. [Figure 3A] FIG. 10 is a diagram illustrating a group of signals in a Valid-Ready protocol. [Figure 3B] FIG. 10 is a diagram illustrating a group of signals in a Valid-Ready protocol. [Figure 4] FIG. 2 is a diagram illustrating channels used for connecting a DMA unit and a system bus. [Figure 5] FIG. 10 is a diagram showing a signal that the time management unit takes in as a monitoring signal. [Figure 6] FIG. 2 illustrates an example of the configuration of a time management unit. [Figure 7] 10 is a flowchart illustrating an operation of a write data channel analysis unit. [Figure 8] 10 is a flowchart illustrating an operation of a read request channel analysis unit. [Figure 9] 10 is a flowchart illustrating an operation of a read response channel analysis unit. [Figure 10] 10 is a flowchart showing the operation of the clock unit. [Figure 11] 10 is a flowchart showing the operation of a time holding unit. [Figure 12] FIG. 1 illustrates an example of the configuration of a digital camera. [Figure 13] FIG. 2 is a diagram illustrating an example of the configuration of a DMA unit. [Figure 14] FIG. 10 is a diagram illustrating a PTP time synchronization process. DETAILED DESCRIPTION OF THE INVENTION

[0016] (First embodiment) 1 is a diagram showing an example of the configuration of a communication system 100 according to the first embodiment. The communication system 100 includes digital cameras 101a, 101b, and 101c and a wireless LAN network .

[0017] In the following description, it is assumed that digital cameras 101b and 101c are added to a wireless LAN network 102 formed by a digital camera 101a operating as an access point. The digital camera 101a performs time synchronization with the participating digital cameras 101b and 101c using PTP. PTP stands for Precision Time Protocol.

[0018] In this embodiment, the digital camera 101a operates as a time synchronization source (primary terminal) in time synchronization, and the digital cameras 101b and 101c operate as time synchronization destinations (secondary terminals).

[0019] Hereinafter, when there is no need to distinguish between the digital cameras 101a, 101b, and 101c, they will be referred to as digital camera 101, and the alphabet will be omitted.

[0020] The digital cameras 101a to 101c generate timing signals for capturing images based on synchronized times, thereby enabling all the digital cameras 101a to 101c to capture images at the same timing (synchronized capture).

[0021] In the following description of the present embodiment, the device constituting the communication system 100 is a digital camera 101, but the device may be another device such as a smartphone, a PC (personal computer), a video camera, a smart watch, a drone, etc. The digital camera 101 is an example of a communication device.

[0022] Although the number of devices in the communication system 100 is three, it may be two or four or more. The timing signal can also be used for applications other than photography, such as applications in which multiple drone devices operate in cooperation with each other.

[0023] Fig. 2 is a diagram showing an example of the configuration of the digital camera 101 in Fig. 1. The digital camera 101 has a CPU 201, a memory unit 202, a communication IF unit 203, an antenna 204, a DMA unit 205, a time management unit 206, a system bus 209, and a photographing unit 210.

[0024] The CPU 201, memory unit 202, DMA unit 205, and time management unit 206 are connected to a system bus 209. Although each functional unit is shown connected to the system bus 209 via one connection, two or more connections may be used depending on the purpose. For example, the DMA unit 205 has two interfaces for connection to the system bus 209, one for data transfer and the other for accessing a register for controlling the DMA unit 205.

[0025] The CPU 201 is a processing unit that controls the entire digital camera 101, and also performs time synchronization processing (PTP protocol processing) by exchanging PTP packets with other digital cameras 101. When the digital camera 101 operates as a secondary terminal, the CPU 201 corrects the time of the clock in the time management unit 206 during the time synchronization processing to synchronize the time with the clock in the primary terminal.

[0026] The memory unit 202 is a memory that stores programs for the CPU 201, PTP packets to be transmitted and received, etc. Although only one memory unit 202 is shown in Fig. 2, it may be divided into multiple memory units 202 depending on the purpose, and each memory unit 202 may have a different type of memory.

[0027] The communication IF unit 203 is a functional unit that transmits and receives communication packets to and from other digital cameras 101 via an antenna 204 .

[0028] The DMA unit 205 transfers communication packets received from the communication IF unit 203 to the memory unit 202, and reads communication packets to be passed to the communication IF unit 203 from the memory unit 202. An example of a connection IF standard between the DMA unit 205 and the communication IF unit 203 is Peripheral Component Interconnect-Express (hereinafter referred to as PCIe). Alternatively, a connection IF standard such as Secure Digital Input / Output (hereinafter referred to as SDIO) or Universal Serial Bus (USB) may be used.

[0029] The time management unit 206 takes in a part of the signal of the IF connection between the system bus 209 and the DMA unit 205 as a monitor signal 207. When the monitor signal 207 satisfies a predetermined condition, the time management unit 206 holds the time of a clock stored in the time management unit 206 and outputs a notification signal 208 to notify the CPU 201. Details will be described later. The time management unit 206 also has a function of generating a timing signal 211 based on the time of the clock stored in the time management unit 206.

[0030] The photographing unit 210 is a functional unit that photographs when it detects a rising edge or a falling edge of the timing signal 211. The image data photographed by the photographing unit 210 is temporarily stored in the memory unit 202, and then saved by the CPU 201 in an external medium (not shown) such as a memory card. Note that the CPU 201 may be configured to control the transfer of the image data photographed by the photographing unit 210 to another terminal via the communication IF unit 203, rather than to the external medium (not shown).

[0031] The system bus 209 connects each functional block. Here, the basic protocol (Valid-Ready protocol) used for connecting the system bus 209 and each functional block will be explained using Figures 3A and 3B, and the channel used for connecting the DMA unit 205 and the system bus 209 will be explained using Figure 4.

[0032] FIG. 3A illustrates signals used when transferring data from module 301 to module 302, and defines this group of signals as channel 309.

[0033] Channel 309 includes a clk signal 303a, a valid signal 304a, a data signal 305a, a sideband signal 306a, a ready signal 307a, and a last signal 308a.

[0034] Since a clk signal 303a, which is an operating clock, is supplied to both the module 301 and the module 302, no input or output of the clk signal 303a occurs between the module 301 and the module 302, but this is shown in the figure.

[0035] The valid signal 304a, the data signal 305a, the sideband signal 306a, and the last signal 308a are generated by the module 301 and output to the module 302. The ready signal 307a is generated by the module 302 and output to the module 301.

[0036] Each signal will be explained below. When the valid signal 304a is at a high level, it means that there is data to be passed. When the ready signal 307a is at a high level, it means that data can be received. As its name suggests, the data signal 305a represents the data to be passed, and is usually made up of multiple bits, each of which is a multiple of 8 bits.

[0037] The sideband signal 306a is additional information, such as byte enable information, that accompanies the data signal 305a. When the last signal 308a is at a high level, it indicates that the currently output data signal 305 (and the sideband signal 306a) is the last of a set of data that has been transferred over multiple cycles.

[0038] When the valid signal 304a and ready signal 307a output by each of them both become high, the data signal 305a, last signal 308a, and sideband signal 306a indicate that data has been received. Then, in the next clock cycle, the values ​​can be updated. When the valid signal 304a is high but the ready signal 307a is low, the data output side must output the data signal 305a, last signal 308a, and sideband signal 306a with the same values ​​in the next cycle.

[0039] 3A shows the waveform of one data output (input) from module 301 to module 302. Between times T8 and T10, ready signal 307a is at a low level, and therefore the values ​​of data signal 305a, last signal 308a, and sideband signal 306a do not change during that time. Note that multiple sideband signals 306a may be defined depending on the application, or there may be no sideband signal 306a at all.

[0040] Figure 3B also illustrates signals used when transferring data from module 301 to module 302, and defines a bundle of these signals as channel 310. Unlike Figure 3A, Figure 3B does not include the last signal in channel 310. The other signals in Figure 3B are the same as those in Figure 3A, so they are represented by different letters with the same numbers.

[0041] Channel 310 includes a clk signal 303b, a valid signal 304b, a data signal 305b, a sideband signal 306b, and a ready signal 307b.

[0042] 3B shows the waveform of one data output (input) from module 301 to module 302. Between times T4 and T11, ready signal 307b is at a low level, and therefore the values ​​of data signal 305b and sideband signal 306b do not change during that time.

[0043] Hereinafter, when there is no need to distinguish between the valid signal 304, data signal 305, sideband signal 306, ready signal 307, and last signal 308, only the assigned numbers will be described and the letters will be omitted. Channel 310 in Figure 3B is a unit for one piece of data.

[0044] 4 illustrates five channels 401 to 405 for connection between the DMA unit 205 and the system bus 209. Of the five channels 401 to 405, the write address channel 401, the write response channel 403, and the read request channel 404 do not have the last signal 308, similar to the channel 310 described above. The remaining two channels, the write data channel 402 and the read response channel 405, have the last signal 308, similar to the channel 309.

[0045] Of these five channels 401 to 405, the signals used by the write data channel 402, the read request channel 404, and the read response channel 405 are taken in by the time management unit 206 as the monitor signal 207.

[0046] The DMA unit 205 manages data transfer via the system bus 209 using these five channels 401 to 405 as a set of interface signals.

[0047] Channels 401 to 405 are channels between DMA unit 205 and system bus 209. DMA unit 205 is a direct memory access unit.

[0048] The write address channel 401 is used to transmit address information to be written as a data signal 305. The write address channel 401 also specifies the amount of data to be written using a sideband signal 306, and also specifies information indicating whether the access is a cache access or a secure access using another sideband signal 306.

[0049] The write data channel 402 is used to transmit data to be written to an address specified by the write address channel 401 as a data signal 305. The write data channel 402 also specifies the valid area of ​​the data to be written by a sideband signal 306 (byte enable). The number of cycles until the last signal 308 goes high is specified in advance by the sideband signal 306 of the write address channel 401 as the "amount of data to be written."

[0050] The write response channel 403 is used to transmit information indicating whether the information specified by the write address channel 401 and the write data channel 402 has been written correctly.

[0051] The read request channel 404 is used to transmit the address to be read as a data signal 305. The read request channel 404 also specifies the amount of data to be read using a sideband signal 306, and also specifies information indicating whether the access is a cache access or a secure access using another sideband signal 306.

[0052] The read response channel 405 is used to transmit data information of the address specified by the read request channel 404 using the data signal 305, and no byte enable information is present in the sideband signal 306 of the read response channel 405. The number of cycles until the last signal 308 goes high is specified in advance by the "amount of data to be read" in the sideband signal 306 of the read request channel 404.

[0053] When the value of the data signal 305 of the read request channel 404 does not match the alignment of the system bus 209, the data signal 305 received by the read response channel 405 will receive data starting from the aligned area. In other words, when the bus width of the system bus 209 is 8 bytes and a request is made to read data from address 0x15, the read response channel 405 will return the data signal 305 in 8-byte units starting from address 0x8. The functional block that generates the read request determines the valid area of ​​the received data signal 305 based on the requested address.

[0054] As described above, an example of a bus protocol that manages address information and data information on different channels is the Advanced eXtensible Interface (AXI). This embodiment can be applied to the AXI bus protocol, and can also be applied to other bus protocols that manage address information and data information on different channels as long as they meet the specifications described above.

[0055] The DMA unit 205 has two interfaces for connection to the system bus 209, and the DMA unit 205 has a total of 10 channels between the system bus 209 and the DMA unit 205.

[0056] The time management unit 206 detects PTP packets from the signals captured inside, and therefore, a signal used in a channel of an interface used for data transfer is connected as a monitor signal 207 .

[0057] Normally, the data string of a communication packet is handled in network byte endian, so the data signals 305c and 305e in Fig. 5 must be handled in network byte endian among the information captured by the supervisory signal 207. In other words, the lower bits of the data signals 305c and 305e are the information at the beginning of the communication packet.

[0058] FIG. 5 illustrates a signal that the time management unit 206 takes in as the monitor signal 207 .

[0059] The write data channel 402 has five types of supervisory signals 207: a valid signal 304c, a data signal 305c, a sideband signal (byte_enable signal) 306c, a ready signal 307c, and a last signal 308c. The time management unit 206 takes in only the sideband signal (byte_enable signal) 306c, which indicates byte enable, from among the multiple sideband signals 306.

[0060] The monitor signal 207 of the read request channel 404 includes three types: a valid signal 304d, a data signal 305d, and a ready signal 307d.

[0061] The monitor signal 207 of the read response channel 405 includes four types of signals: a valid signal 304e, a data signal 305e, a ready signal 307e, and a last signal 308e.

[0062] Next, the internal block configuration of the time management unit 206 will be explained using Fig. 6. The register unit 601 is connected to the system bus 209, and manages the control information of the time management unit 206 set by the CPU 201 in Fig. 2. The control information includes module start / stop information, conditions for PTP packets detected by the monitoring signal 207, correction information for the clock unit 605, output start time information for the timing signal 211, etc.

[0063] When the CPU 201 reads the timestamp of a transmitted / received packet held in the time management unit 206 from the register unit 601, the write hold time 614 and the read hold time 615 output by the time holding unit 606 can be read.

[0064] These timestamps remain internally unless the CPU 201 issues a discard command via the register unit 601, so the CPU 201 does not necessarily have to start the operation of acquiring the timestamps when it receives the notification signal 208. Even if the timestamps are read when it is detected that a packet has been transmitted or received, the accuracy of the time synchronization will not be degraded.

[0065] When the CPU 201 makes a request to discard the timestamp of a transmitted / received packet held in the time management unit 206, the register unit 601 outputs a write discard request 618 or a read discard request 619 to the time holding unit 606. Note that each functional block in the time management unit 206 can always refer to the control information set in the register unit 601.

[0066] The write data channel analysis unit 602 detects PTP packets using the supervisory signal 207 of the write data channel 402. When the write data channel analysis unit 602 detects a PTP packet, it outputs a write detection notification 608 to the time holding unit 606. The detection conditions will be described later when explaining the operation flow of the write data channel analysis unit 602.

[0067] The read request channel analysis unit 603 calculates the byte enable for the first data of the read response data using the monitor signal 207 of the read request channel 404. The calculated byte enable information is stored in FIFO_A (not shown) inside the read request channel analysis unit 603. If one or more data are stored, this FIFO_A is configured to continue outputting the oldest data until a extraction request is received.

[0068] The output value of FIFO_A is output to the read response channel analysis unit 604 as first byte enable information 609. FIFO_A is updated (the oldest data is deleted and the second oldest data is switched to be output) when a discard request 611 received from the read response channel analysis unit 604 is detected. A detailed operation flow of the read request channel analysis unit 603 will be described later.

[0069] The read response channel analysis unit 604 detects a PTP packet using the first byte enable information 609 and the monitoring signal 207 of the read response channel 405. When the read response channel analysis unit 604 detects a PTP packet, it outputs a write detection notification 608 to the time holding unit 606. The method for detecting a PTP packet is basically the same as the detection method performed by the write data channel analysis unit 602.

[0070] The clock unit 605 has an internal counter that indicates the current time. If the digital camera 101 is a secondary terminal, the CPU 201 corrects the time of the clock in the time management unit 206 during the time synchronization process via the register unit 601. In other words, the CPU 201 changes the counter value of the clock unit 605, instructs the current counter to add or subtract a specified value, or changes the counter increment value. The clock unit 605 constantly outputs the current time 612, which is the counter value, to the time holding unit 606 and the timing signal generation unit 620.

[0071] When the time holding unit 606 detects a write detection notification 608, it stores the value of the current time 612 in FIFO_B (not shown) which it holds internally. When the time holding unit 606 receives a read detection notification 610, it stores the value of the current time 612 in FIFO_C (not shown) which it holds internally.

[0072] Like FIFO_A, FIFO_B and FIFO_C are configured to continue outputting the oldest data when one or more data items are stored therein until a request for extraction is received. The stored data output by FIFO_B is treated as the write retention time 614. The stored data output by FIFO_C is treated as the read retention time 615.

[0073] FIFO_B is updated when a write discard request 618 output by the register unit 601 is detected. FIFO_C is updated when a read discard request 619 output by the register unit 601 is detected.

[0074] The time holding unit 606 stores the value of the current time 612 in FIFO_B or FIFO_C, and at the same time outputs a read notification request 617 or a write notification request 616 to the notification unit 607 .

[0075] When the notification unit 607 receives a read notification request 617 or a write notification request 616, it outputs a notification signal 208. This notification signal 208 is used to notify that the time management unit 206 has internally stored a timestamp indicating the time at which the PTP packet was transmitted or received. The notification signal 208 can be canceled by the register unit 601. Note that the notification unit 607 may be configured not to generate the notification signal 208, but to have status information that notifies the register unit 601 that a timestamp has internally been stored.

[0076] The timing signal generating unit 620 outputs the timing signal 211 when the current time 612 output by the clock unit 605 coincides with the output start time of the timing signal 211 held in the register unit 601 .

[0077] The timing signal 211 may be a signal with a fixed cycle, a signal that outputs 1 until a release instruction is given like an interrupt signal, or a signal that outputs 1 for one to several cycles. The timing signal 211 may also be configured to have inverted polarity (outputting 1 until the output start time arrives, and outputting 0 at the output start time). When the timing signal 211 has a fixed cycle, the cycle is specified in the register unit 601.

[0078] In this embodiment, there is one timing signal 211, but the number of timing signals 211 may be increased depending on the type of corresponding application. In that case, a different timing signal 211 is connected to the processing unit of each application.

[0079] Next, the operational flow of the write data channel analysis unit 602 will be described with reference to Fig. 7. This flow starts in step S701 when the digital camera 101 is turned on and an instruction to start analysis is detected by the CPU 201. Note that the offsets and execution results of the variables used in this flow start from an initialized state.

[0080] The initial value of the offset is 0, and the initial value of the execution result is information indicating "does not match." This flow operates based on the clock signal supplied to the write data channel analysis unit 602, and operates in one cycle from step S702 to return to S702, or from step S702 to proceed to S712. Of course, the processing of this flow may be divided into multiple blocks and pipelined to operate in multiple cycles.

[0081] The write data channel analysis unit 602 inputs the monitor signal 207 of the write data channel 402. The write data channel 402 is a channel for writing packets received from the outside via the communication IF unit 203 to the memory unit 202. The processing method of the digital camera 101 will be described below.

[0082] In step S702, the write data channel analysis unit 602 branches depending on whether it detects the valid signal 304c = 1 and the ready signal 307c = 1. If it detects the valid signal 304c = 1 and the ready signal 307c = 1, it proceeds to step S703, and if not, it proceeds to step S711.

[0083] In step S703, the write data channel analysis unit 602 identifies the valid head data position of the data signal 305c from the sideband signal (byte_enable signal) 306c. For example, if the data width is 64 bits and the sideband signal (byte_enable signal) 306c is 0xF0, the valid head data position is the fourth byte among the zeroth byte (lower bit side) to the seventh byte (higher bit side).

[0084] Here, the valid start data position indicates the start position of valid data. The byte_enable signal is an example of byte enable information.

[0085] In step S704, the write data channel analysis unit 602 branches depending on whether or not one or more bytes of information for identifying a PTP packet are included in the data from the position identified in step S703 to the end of the valid area of ​​the data signal 305c. If one or more bytes of information for identifying a PTP packet are included, the process proceeds to step S705; otherwise, the process proceeds to step S706.

[0086] Here, we will explain the information used to determine PTP packets. When PTP packets flow on a network, there are three main patterns that can be considered for the configuration of the PTP packets.

[0087] The first is when the packet consists of an Ethernet header, a PTP header, and a PTP payload in that order from the beginning (hereinafter referred to as pattern 1).

[0088] The second is when the packet is composed of an Ethernet header, IPv4 header, UDP header, PTP header, and PTP payload in that order (hereinafter referred to as pattern 2). IPv4 stands for Internet Protocol Version 4. UDP stands for User Datagram Protocol.

[0089] The third case is when the packet is composed of an Ethernet header, an IPv6 header, a UDP header, a PTP header, and a PTP payload, in that order from the beginning (hereafter referred to as pattern 3). IPv6 stands for Internet Protocol Version 6.

[0090] Since this embodiment is used for wireless communication, a wireless header specific to the wireless chip vendor is added before the Ethernet header. That is, for example, pattern 1 is configured in the order of wireless header, Ethernet header, PTP header, and PTP payload from the beginning of the packet, and a wireless header area is added to the beginning of the packet.

[0091] The CPU 201 specifies in advance which of these three patterns of packets to detect and what the wireless header length is in the register unit 601. Of course, the time management unit 206 may be implemented to be able to handle all patterns.

[0092] In Pattern 1, the information used to identify a PTP packet consists of at least two header fields: the first is the EtherType field in the Ethernet header, and the second is the messageType field in the PTP header (the information in the lowest 4 bits of the first byte of the PTP header).

[0093] In Pattern 2, the information used to identify a PTP packet is at least four header fields: the EtherType field in the Ethernet header, the Protocol field in the IPv4 header, the Destination Port field in the UDP header, and the messageType field in the PTP header.

[0094] In Pattern 3, the information used to identify a PTP packet is at least four header fields: the first is the EtherType field in the Ethernet header, the second is the Next Header field in the IPv6 header, the third is the Destination Port field in the UDP header, and the fourth is the messageType field in the PTP header.

[0095] In these three patterns, other fields, such as the Destination MAC Address field in the Ethernet header or the Destination Address field in the IPv4 header, may also be used. The more fields used for detection, the lower the probability of false detection. Using these fields makes it possible to add a judgment using the multicast address used in PTP.

[0096] In the above three patterns, the information for determining the PTP packet in step S704 is the value of the area from the beginning of the PTP packet to the messageType area of ​​the PTP header.

[0097] The write data channel analysis unit 602 uses information from the data signal 305c and the sideband signal (byte_enable signal) 306c to determine whether these header areas contain one byte or more. To make this determination, it is necessary to manage the position of the data from the beginning of the current packet that is flowing on the supervisory signal 207 of the write data channel 402, and this is managed by the variable offset initialized in step S701.

[0098] The write data channel analysis unit 602 can determine whether the desired header area has been reached based on the offset value and the amount of data up to the end of the valid area. In other words, an offset of 0 means starting from the beginning of the packet, and an offset of N means starting N bytes from the beginning of the packet.

[0099] The offset calculation is explained in step S706, and the actual value to be determined is explained in step S705. Since the area of ​​each header has a known data size, the write data channel analysis unit 602 can determine whether the area of ​​each header has been reached.

[0100] In step S705, the write data channel analysis unit 602 performs pattern matching on the information for determining the PTP packet in step S704 using the determination information set in the register unit 601, stores the result of the pattern matching, and proceeds to step S706. The determination information is the expected values ​​of multiple areas used in the above three patterns. Pattern matching means determining whether the information for determining the PTP packet matches the expected values.

[0101] In pattern 1, the expected value of the EtherType field in the Ethernet header is 0x88F7, and the expected value of the messageType field in the PTP header is one of 0x0 to 0x3. messageType=0x0 means that the PTP packet type is Sync. messageType=0x1 means that the PTP packet type is delay_req. messageType=0x2 means that the PTP packet type is Pdelay_req. messageType=0x3 means that the PTP packet type is Pdelay_resp. These four types require a timestamp in PTP, so they are determined by pattern matching.

[0102] The expected value of the messageType field of the PTP header may be any of 0x0, 0x1, 0x8, and 0x9. messageType=0x0 means that the type of PTP packet is Sync (Fig. 14). messageType=0x1 means that the type of PTP packet is delay_req (Fig. 14). messageType=0x8 means that the type of PTP packet is follow_up (Fig. 14). messageType=0x9 means that the type of PTP packet is delay_resp (Fig. 14).

[0103] In pattern 2, the expected value of the EtherType field in the Ethernet header is 0x0800. The expected value of the Protocol field in the IPv4 header is 0x11. The expected value of the Destination Port field in the UDP header is either 319 or 320. The expected value of the messageType field in the PTP header is either 0x0 to 0x3.

[0104] In pattern 3, the expected value of the EtherType field in the Ethernet header is 0x86DD. The expected value of the Next Header field in the IPv6 header is 0x11. The expected value of the Destination Port field in the UDP header is either 319 or 320. The expected value of the messageType field in the PTP header is either 0x0 to 0x3.

[0105] If there are multiple expected values ​​in one area, it is sufficient to match any one of them. In other words, an OR check is performed as pattern matching of the expected values.

[0106] These determination information (expected values) may be held as fixed values ​​by the time management unit 206, but by configuring them to be changeable by the register unit 601, there is room for flexibility in responding to future specification changes and the like.

[0107] Furthermore, the primary terminal and secondary terminal differ in the channels on which PTP packets requiring timestamps appear. In the primary terminal, PTP Sync packets (FIG. 14) are transmitted, so PTP Sync packets are detected on the read-side channel. This is because the CPU 201 generates Sync packets in the memory unit 202, and the DMA unit 205 transfers them to the communication IF unit 203. On the other hand, the secondary terminal receives PTP Sync packets, so PTP Sync packets are detected on the write-side channel.

[0108] If these areas match the expected values, the write data channel analysis unit 602 changes the implementation result to information indicating "match," and if they do not match, it leaves the implementation result as information indicating "does not match."

[0109] Patterns 1 to 3 require a match with the expected value in multiple areas, and since these areas may be multiple bytes in size, the write data channel analysis unit 602 is configured to manage the implementation results separately for each byte or less. In other words, for pattern 1, a determination is required in two areas, and there is a total of 2 bytes + 4 bits of expected value comparison, so the implementation results are managed in three places (two in the EtherType area and one in the messageType area).

[0110] Even if the data from the position identified in step S703 to the end of the valid area of ​​the data signal 305c includes only one half of the area to be determined, the write data channel analysis unit 602 performs the determination for the area up to the included part. Of course, it is also possible to have an implementation result for each area.

[0111] In step S706, the write data channel analysis unit 602 adds the amount of data from the position identified in step S703 to the end of the valid area of ​​the data signal 305c to the offset, and then proceeds to step S707. By retaining the position in the packet that has been reached as an offset, the write data channel analysis unit 602 can determine the correspondence between the valid start data position of the next data signal 305c and the position in the packet from which the data starts.

[0112] In step S707, the write data channel analysis unit 602 branches depending on whether the last signal 308c is 1. The value 1 of the last signal 308c indicates the end of the data. If the last signal 308c is 1, the process proceeds to step S708; otherwise, the process proceeds to step S702. If the last signal 308c is 1, the time management unit 206 determines that the end data of the packet has been reached.

[0113] In step S708, the write data channel analysis unit 602 checks all conditions for determining that the packet is a PTP packet, and branches depending on whether all the results indicate "match." If all the results indicate "match," the process proceeds to step S709; otherwise, the process proceeds to step S710. For example, in the case of pattern 1, the process checks whether all three results indicate "match."

[0114] In step S709, the write data channel analysis unit 602 functions as a detection unit and detects the writing of a PTP packet, so it outputs a write detection notification 608 to the time holding unit 606 and proceeds to step S711. In other words, the write data channel analysis unit 602 notifies that it has detected a PTP packet. A PTP packet is an example of a predetermined packet.

[0115] In step S710, the write data channel analysis unit 602 initializes the offset and the execution result, and then the process proceeds to step S711.

[0116] In step S711, the write data channel analysis unit 602 branches depending on whether or not an analysis stop instruction has been received from the CPU 201. If an analysis stop instruction has been received, the process proceeds to step S712, where the flow of Fig. 7 ends; otherwise, the process proceeds to step S702.

[0117] As a result, the write data channel analysis unit 602 detects PTP packets from the monitoring signal 207 of the write data channel 402 and notifies the time holding unit 606. If the valid signal 304c=1 and the ready signal 307c=1 continue until the last signal 308c becomes 1, the data signal 305c at that time is determined to be data of the same packet, and when the last signal 308c becomes 1, it is determined that this is the packet break.

[0118] Next, the operational flow of the read request channel analysis unit 603 will be described with reference to Figure 8. This flow starts in step S801 when the digital camera 101 is powered on and an instruction to start analysis is detected by the CPU 201. This flow operates based on a clock signal supplied to the read request channel analysis unit 603, and operates in one cycle from step S802 to returning to S802, or from step S802 to proceeding to S807. Of course, the processing of this flow may be divided into multiple blocks and operated in a pipeline, so as to operate in multiple cycles.

[0119] The read request channel analysis unit 603 receives the monitor signal 207 of the read request channel 404. The read request channel 404 is a channel for transmitting a packet read from the memory unit 202 to the outside via the communication IF unit 203.

[0120] In step S802, the read request channel analysis unit 603 branches depending on whether it detects the valid signal 304d = 1 and the ready signal 307d = 1. If it detects the valid signal 304d = 1 and the ready signal 307d = 1, it proceeds to step S803, and if not, it proceeds to step S804.

[0121] In step S803, the read request channel analysis unit 603 stores the inverted value of the lower bit information of the data signal 305d in FIFO_A inside the read request channel analysis unit 603, and proceeds to step S804. The data signal 305d indicates the address information of the data to be read. For the lower bit information, if the read request channel 404 has a data width of 64 bits, the lower 3 bits of information is used, and if the data width is 128 bits, the lower 4 bits of information is used. In other words, data width (bits) = 8 x 2 下位ビット数 is the value for which

[0122] The information stored in FIFO_A is output to the read response channel analysis unit 604 as leading byte enable information 609 .

[0123] In step S804, the read request channel analysis unit 603 branches depending on whether or not it has received the discard request 611. If it has received the discard request 611, it proceeds to step S805, and if not, it proceeds to step S806.

[0124] In step S805, the read request channel analysis unit 603 extracts the oldest data from FIFO_A stored in the read request channel analysis unit 603, and the process proceeds to step S806.

[0125] In step S806, the read request channel analysis unit 603 branches depending on whether or not an analysis stop instruction has been received from the CPU 201. If an analysis stop instruction has been received, the process proceeds to step S807, where the flow of Fig. 8 ends; otherwise, the process proceeds to step S802.

[0126] As described above, the read request channel analysis unit 603 calculates the first byte enable information 609 of the read data from the monitor signal 207 of the read request channel 404. As described above, the information stored in FIFO_A is output to the read response channel analysis unit 604 as the first byte enable information 609.

[0127] Next, the operation flow of the read response channel analysis unit 604 will be described with reference to Fig. 9. This flow starts in step S901 when the digital camera 101 is powered on and an instruction to start analysis is detected by the CPU 201.

[0128] The offset and execution result variables used in this flow start from an initialized state, similar to the operation flow in Figure 7. The initial value of the offset is 0, and the initial value of the execution result is information indicating "not matched."

[0129] This flow operates based on a clock signal supplied to the write data channel analysis unit 602, and operates in one cycle from step S902 to return to S902, or from step S902 to proceed to S915. Of course, the processing of this flow may be divided into multiple blocks and pipelined to operate in multiple cycles.

[0130] The read response channel analysis unit 604 receives the monitor signal 207 of the read response channel 405. The read response channel 405 is a channel for transmitting a packet read from the memory unit 202 to the outside via the communication IF unit 203.

[0131] In step S902, the read response channel analysis unit 604 branches depending on whether it detects the valid signal 304e = 1 and the ready signal 307e = 1. If it detects the valid signal 304e = 1 and the ready signal 307e = 1, it proceeds to step S903, and if not, it proceeds to step S914.

[0132] In step S903, the read response channel analysis unit 604 branches depending on whether the offset of the variable is 0. If the offset of the variable is 0, the process proceeds to step S904, and if not, the process proceeds to step S905.

[0133] In step S904, the read response channel analysis unit 604 identifies the valid head data position of the data signal 305e from the head byte enable information 609, and proceeds to step S906. For example, if the data width is 64 bits and the head byte enable information 609 is 0xFE, the first byte of the 0th byte (lower bit side) to 7th byte (higher bit side) is the valid head data position.

[0134] In step S905, the read response channel analysis unit 604 determines that all of the data signal 305e is valid data, identifies the valid leading data position, and proceeds to step S906. For example, if the data width is 64 bits, the 0th byte (lower bit side) is the valid leading data position.

[0135] In step S906, the read response channel analysis unit 604 branches depending on whether or not one or more bytes of information for identifying a PTP packet are included in the data from the position identified in step S904 or S905 to the end of the valid area of ​​the data signal 305c. If one or more bytes of information for identifying a PTP packet are included, the process proceeds to step S907; otherwise, the process proceeds to step S908. The method of determination is the same as the method of processing in step S704 of FIG. 7, and therefore will not be described here.

[0136] In step S907, the read response channel analysis unit 604 performs pattern matching on the information for determining the PTP packet in step S906 using the determination information set in the register unit 601, stores the result of the matching, and proceeds to step S908. The determination information, pattern matching, and result of the matching are omitted because they are the same as those in the process of step S705 in Fig. 7.

[0137] In step S908, the read response channel analysis unit 604 adds the amount of data from the position identified in step S904 or S905 to the end of the valid area of ​​the data signal 305e to the offset, and then proceeds to step S909.

[0138] In step S909, the read response channel analysis unit 604 branches depending on whether the last signal 308e is 1. If the last signal 308e is 1, the process proceeds to step S910; otherwise, the process proceeds to step S902. If the last signal 308e is 1, the time management unit 206 determines that the end data of the packet has been reached.

[0139] In step S910, the read response channel analysis unit 604 checks all conditions for determining that the packet is a PTP packet, and branches depending on whether all the results indicate "match." If all the results indicate "match," the process proceeds to step S911; otherwise, the process proceeds to step S913.

[0140] In step S911, the read response channel analysis unit 604 functions as a detection unit and detects the reading of a PTP packet, so it outputs a read detection notification 610 to the time holding unit 606 and proceeds to step S912. That is, the read response channel analysis unit 604 notifies that a PTP packet has been detected. A PTP packet is an example of a predetermined packet.

[0141] In step S912, the read response channel analysis unit 604 outputs the discard request 611 to the read request channel analysis unit 603, and the process proceeds to step S913.

[0142] In step S913, the read response channel analysis unit 604 initializes the variables offset and execution result, and then proceeds to step S914.

[0143] In step S914, the read response channel analysis unit 604 branches depending on whether or not an analysis stop instruction has been received from the CPU 201. If an analysis stop instruction has been received, the process proceeds to step S915, where the flow of Fig. 9 ends; otherwise, the process proceeds to step S902.

[0144] As a result, the read response channel analysis unit 604 detects a PTP packet from the monitoring signal 207 of the read response channel 405 and notifies the time holding unit 606. If the valid signal 304e=1 and the ready signal 307e=1 continue until the last signal 308e becomes 1, the data signal 305e at that time is determined to be data of the same packet, and if the last signal 308c becomes 1, it is determined that this is the packet break.

[0145] Next, the operational flow of the clock unit 605 will be described with reference to Fig. 10. This flow starts in step S1001 when the digital camera 101 is powered on and the CPU 201 detects an instruction to start the clock.

[0146] This flow operates based on a clock signal supplied to the clock unit 605, and operates in one cycle from step S1002 to return to S1002, or from step S1002 to proceed to S1006. Of course, the processing of this flow may be divided into multiple blocks and operated in a pipeline, so as to operate in multiple cycles.

[0147] In step S1002, the clock unit 605 branches depending on whether or not a time correction request has been received from the CPU 201. If a time correction request has been received, the process proceeds to step S1003, and if not, the process proceeds to step S1004.

[0148] In step S1003, the clock unit 605 updates the current time based on the instructed correction information, and the process proceeds to step S1005.

[0149] In step S1004, the clock unit 605 updates the current time using the increment value of the counter set in the register unit 601, and the process proceeds to step S1005.

[0150] In step S1005, the clock unit 605 branches depending on whether or not it has received an instruction to stop the clock from the CPU 201. If it has received an instruction to stop the clock, it proceeds to step S1006, where it ends the flow of Fig. 10, and if not, it proceeds to step S1002.

[0151] As a result, the clock unit 605 either updates the time based on an instruction from the CPU 201 or updates the time using the set increment value. As mentioned above, the clock unit 605 always outputs the time it manages as the current time 612, so the time holding unit 606 and the timing signal generating unit 620 can refer to it at any time.

[0152] Next, the operational flow of the time keeping unit 606 will be described with reference to Fig. 11. This flow starts in step S1101 when the digital camera 101 is powered on and the CPU 201 detects an instruction to start the clock.

[0153] This flow operates based on the clock signal supplied to the time holding unit 606, and operates in one cycle from step S1102 to returning to S1102, or from step S1102 to proceeding to S1113.

[0154] In step S1102, the time holding unit 606 branches depending on whether or not it has received the light detection notification 608. If it has received the light detection notification 608, it proceeds to step S1103, and if not, it proceeds to step S1105.

[0155] In step S1103, the time holding unit 606 holds the current time 612 of the clock unit 605 in FIFO_B (not shown) inside the time holding unit 606, outputs the value of FIFO_B to the register unit 601 as the write hold time 614, and proceeds to step S1104.

[0156] In step S1104, the time holding unit 606 outputs the write notification request 616 to the notification unit 607, and the process proceeds to step S1105.

[0157] In step S1105, the time holding unit 606 branches depending on whether or not it has received the read detection notification 610. If it has received the read detection notification 610, it proceeds to step S1106, and if not, it proceeds to step S1108.

[0158] In step S1106, the time holding unit 606 holds the current time 612 of the clock unit 605 in FIFO_C (not shown) inside the time holding unit 606, outputs the value of FIFO_C to the register unit 601 as the read hold time 615, and proceeds to step S1108.

[0159] In step S1107, the time holding unit 606 outputs the read notification request 617 to the notification unit 607, and the process proceeds to step S1108.

[0160] In step S1108, the time holding unit 606 branches depending on whether or not it has received the write discard request 618. If it has received the write discard request 618, it proceeds to step S1109, and if not, it proceeds to step S1110.

[0161] In step S1109, the time holding unit 606 extracts the oldest data from FIFO_B (not shown) stored inside the time holding unit 606, and the process proceeds to step S1110.

[0162] In step S1110, the time holding unit 606 branches depending on whether or not it has received a read abandon request 619. If it has received a read abandon request 619, it proceeds to step S1111, and if not, it proceeds to step S1112.

[0163] In step S1111, the time holding unit 606 extracts the oldest data from FIFO_C (not shown) stored inside the time holding unit 606, and the process proceeds to step S1112.

[0164] In step S1112, the time keeping unit 606 branches depending on whether or not an instruction to stop the clock has been received from the CPU 201. If an instruction to stop the clock has been received, the process proceeds to step S1113, where the flow of Fig. 11 ends; otherwise, the process proceeds to step S1102.

[0165] As a result, when the time holding unit 606 receives a notification request, it stores the current time 612 in the internal FIFO_B or FIFO_C. These two FIFO_B and FIFO_C continue to output the oldest data until the extraction process is performed, and the values ​​are output to the register unit 601 as the write hold time 614 and the read hold time 615.

[0166] Upon detecting a notification signal 208 generated by a notification unit 607 or upon detecting the completion of DMA transfer of a PTP packet, the CPU 201 reads the write retention time 614 and the read retention time 615 from the register unit 601. After reading, the CPU 201 issues a discard command to the register unit 601 to delete the timestamp that is no longer needed.

[0167] The register unit 601 generates a write discard request 618 or a read discard request 619 based on the discard command, and the oldest data (the read write retention time 614 or read retention time 615) is deleted from FIFO_B or FIFO_C.

[0168] Although this embodiment is based on a wireless communication environment, the same thing can be achieved in a wired communication environment. The difference is that the position from the beginning of the packet to the appearance of the header area for detecting it as a PTP packet changes. The time management unit 206 can specify the wireless header length, and when used in a wired system, switching can be performed by setting the wireless header length to 0.

[0169] Although this embodiment assumes that the Ethernet frame is Ethernet II, it may be in the Ethernet header format specified by IEEE 802.3. In this case, the position of the EtherType field has been changed to the Length field, so the EtherType field should not be compared directly with the expected value. When using the Ethernet header format specified by IEEE 802.3, an LLC header and a SNAP header are added to specify the upper layer protocol. LLC stands for Logical Link Control, and SNAP stands for SubNetwork Access Protocol. Therefore, when using the Ethernet header format specified by IEEE 802.3, the packet is composed of the Ethernet header, LLC header, SNAP header, PTP header, and PTP payload, in that order from the beginning. The SNAP has a PID (Protocol IDentifier) ​​field, which plays the same role as the EtherType field of Ethernet II. The PID value indicates a value equivalent to the EtherType (0x0800 if the upper layer protocol is IPv4), so the expected value does not need to be changed depending on the Ethernet header format. The time management unit 206 may be configured to be able to specify the length from the beginning of the packet until the EtherType field or PID field appears.

[0170] 14 is a diagram showing PTP time synchronization processing. Digital camera 101a operates as a time synchronization source (primary terminal) in time synchronization, and digital camera 101b operates as a time synchronization destination (secondary terminal).

[0171] In step S1401, the digital camera 101a transmits a synchronization packet Sync to the digital camera 101b at regular intervals. When the digital camera 101a transmits the synchronization packet Sync, it holds a transmission timestamp t1 at that time. In this case, in step S911 of FIG. 9, the read response channel analysis unit 604 outputs a read detection notification 610 to the time holding unit 606. In step S1106 of FIG. 11, the time holding unit 606 holds a current time 612 in FIFO_C inside the time holding unit 606, and outputs the value of FIFO_C to the register unit 601 as a read hold time 615. The read hold time 615 corresponds to the transmission timestamp t1 of FIG. 14.

[0172] When the digital camera 101b receives the synchronization packet Sync, it holds the reception timestamp t2 at that time. In this case, in step S709 in Fig. 7, the write data channel analysis unit 602 outputs the write detection notification 608 to the time holding unit 606. In step S1103 in Fig. 11, the time holding unit 606 holds the current time 612 in FIFO_B inside the time holding unit 606, and outputs the value of FIFO_B to the register unit 601 as the write hold time 614. The write hold time 614 corresponds to the reception timestamp t2 in Fig. 14.

[0173] Next, in step S1402, the digital camera 101a transmits the transmission timestamp t1 used to transmit the synchronization packet Sync to the digital camera 101b by incorporating the transmission timestamp t1, which was included in the synchronization packet Sync, into a synchronization packet Follow_Up. Upon receiving the synchronization packet Follow_Up, the digital camera 101b holds the transmission timestamp t1 included in the synchronization packet Follow_Up.

[0174] In the above example, the digital camera 101a transmits the synchronization packet Sync by including the transmission timestamp t1 in the synchronization packet Follow_Up. In addition to this method, the digital camera 101a may transmit the synchronization packet Sync by including the transmission timestamp t1 in the synchronization packet Sync itself, rather than in the synchronization packet Follow_Up.

[0175] Next, in step S1403, the digital camera 101b transmits a synchronization packet "delay_req" to the digital camera 101a. When the digital camera 101b transmits the synchronization packet "delay_req," it holds the transmission timestamp t3 of the delay_req at that time. In this case, in step S911 of FIG. 9, the read response channel analysis unit 604 outputs a read detection notification 610 to the time holding unit 606. In step S1106 of FIG. 11, the time holding unit 606 holds the current time 612 in FIFO_C inside the time holding unit 606, and outputs the value of FIFO_C to the register unit 601 as the read holding time 615. The read holding time 615 corresponds to the transmission timestamp t3 of FIG. 14.

[0176] When the digital camera 101a receives the synchronization packet delay_req, it holds the reception timestamp t4 of the delay_req at that time. In this case, in step S709 in Fig. 7, the write data channel analysis unit 602 outputs the write detection notification 608 to the time holding unit 606. In step S1103 in Fig. 11, the time holding unit 606 holds the current time 612 in FIFO_B inside the time holding unit 606, and outputs the value of FIFO_B to the register unit 601 as the write hold time 614. The write hold time 614 corresponds to the reception timestamp t4 in Fig. 14.

[0177] Next, in step S1404, the digital camera 101a transmits a synchronization packet delay_resp to the digital camera 101b. At this time, the digital camera 101a transmits the reception timestamp t4 of the synchronization packet delay_req to the digital camera 101b via the synchronization packet delay_resp.

[0178] When the digital camera 101b receives the synchronization packet delay_resp, it holds the reception timestamp t4 carried in the synchronization packet delay_resp.

[0179] The CPU 201 of the digital camera 101b calculates the average transmission delay time Td using the following equation based on the timestamps t1 to t4 from the exchange of synchronization packets Sync, follow_up, delay_req, and delay_resp in steps S1401 to S1404. Td={(t2-t1)+(t4-t3)} / 2

[0180] Next, the CPU 201 of the digital camera 101b calculates a correction value Tc using the following equation based on the average transmission delay time Td. Tc=(t2-t1)-td

[0181] The correction value Tc is the amount of deviation between the current time 612 of the clock unit 605 of the digital camera 101a and the current time 612 of the clock unit 605 of the digital camera 101b. The CPU 201 of the digital camera 101b transmits a time correction request for the correction value Tc to the clock unit 605. In step S1003 of Fig. 10 , the clock unit 605 of the digital camera 101b functions as a correction unit and corrects the current time 612, which is the counter value of the clock unit 605, so that the value obtained by subtracting the correction value Tc from the current time 612 becomes the corrected current time 612.

[0182] As a result, the current time 612 of the clock unit 605 of the digital camera 101b becomes the same as the current time 612 of the clock unit 605 of the digital camera 101a. Similarly, the current time 612 of the clock unit 605 of the digital camera 101c becomes the same as the current time 612 of the clock unit 605 of the digital camera 101a.

[0183] 6 generates a timing signal 211 based on the current time 612 of the clock unit 605. The imaging unit 210 in FIG.

[0184] The timing signals 211 of the digital cameras 101a to 101c are generated at the same timing, so that the image capturing sections 210 of the digital cameras 101a to 101c can capture images at the same timing.

[0185] 7 to 11, the time it takes for the PTP packet to travel from the communication IF unit (communication chip or NIC) 203 in Fig. 2 to the memory unit (DRAM, etc.) 202 and the associated processing time of the CPU 201 are not included in the timestamp. Even if the communication IF unit (communication chip or NIC) 203 does not have a timestamp function, the time management unit 206 will acquire a timestamp near the boundary with the lower layer, making it possible to achieve higher synchronization accuracy among multiple digital cameras 101a to 101c.

[0186] (Second embodiment) In the first embodiment, the time management unit 206 is connected to the system bus 209, and detects PTP packets using signals from a connection IF between the system bus 209 and the DMA unit 205. In the second embodiment, a configuration in which the time management unit 206 is incorporated into the DMA unit 205 will be described.

[0187] Fig. 12 shows an example of the configuration of a digital camera 101 according to the second embodiment. The same parts in Fig. 12 and Fig. 2 are given the same reference numerals, and the description thereof will be omitted.

[0188] The digital camera 101 includes a CPU 201, a memory unit 202, a communication IF unit 203, an antenna 204, a system bus 209, a photographing unit 210, and a DMA unit 1201. The DMA unit 1201 includes a time management unit 206.

[0189] In the second embodiment, a time management unit 206 is incorporated into the DMA unit 1201, and detects PTP packets by monitoring internal signals. As in the first embodiment, the time management unit 206 outputs a notification signal 208 to the CPU 201 when it detects a PTP packet and stores a timestamp. In addition, the time management unit 206 outputs a timing signal 211 when the internal clock reaches a specified time. The DMA unit 1201 also has functions equivalent to those of the first embodiment.

[0190] Fig. 13 shows an example of the configuration of the DMA unit 1201 in Fig. 12. The DMA unit 1201 has a DMA register unit 1301, a system transfer unit 1302, an internal memory unit 1303, a communication IF transfer unit 1304, a time management unit 206, and an internal bus 1306.

[0191] The DMA register unit 1301 is connected to the system bus 209 and manages control information for the DMA unit 1201 and the time management unit 206 set by the CPU 201. The control information can be referenced at any time by each internal functional block. In the first embodiment, the register unit 601 exists in the time management unit 206, but it may coexist with the DMA register unit 1301 or may be integrated into one functional block.

[0192] The system transfer unit 1302 is connected to the system bus 209 and the internal bus 1306 , and is responsible for data transfer between the memory unit 202 and the internal memory unit 1303 .

[0193] The internal memory unit 1303 is connected to the internal bus 1306 and is used to temporarily store packets received from the communication IF unit 203 and packets to be passed to the communication IF unit 203 .

[0194] The communication IF transfer unit 1304 is connected to the communication IF unit 203 and the internal bus 1306 , and is responsible for data transfer between the communication IF unit 203 and the internal memory unit 1303 .

[0195] The protocol of the IF connected to the internal bus 1306 may be the same as or different from the protocol of the IF connected to the system bus 209. In the case where they are different, the signal group used in the first embodiment must be able to be mapped to the monitoring signal 1305 input to the time management unit 206.

[0196] (Other embodiments) The present disclosure can also be realized by a process in which a program that realizes one or more functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in the computer of the system or device read and execute the program. The present disclosure can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0197] It should be noted that the above-described embodiments merely illustrate specific examples of implementing the present disclosure, and the technical scope of the present disclosure should not be construed as being limited by these embodiments. In other words, the present disclosure can be implemented in various forms without departing from its technical concept or main features.

[0198] The disclosure of this embodiment includes the following configuration, method, and program. (Configuration 1) a detection means for detecting writing or reading of a predetermined packet based on a signal of a channel for writing a packet received from an external device into the memory unit or a signal of a channel for transmitting a packet read from the memory unit to an external device; time holding means for holding the current time of the clock unit as a write hold time or a read hold time when writing or reading of the predetermined packet is detected; A communication device comprising: (Configuration 2) 2. The communication device according to configuration 1, wherein the predetermined packet is a PTP packet. (Configuration 3) The communication device according to configuration 2, wherein the detection means determines that a PTP packet write or read has been detected when the values ​​of the EtherType field of the Ethernet header and the messageType field of the PTP header match expected values. (Configuration 4) The communication device according to configuration 2, wherein the detection means determines that writing or reading of a PTP packet has been detected when values ​​in the EtherType field of the Ethernet header, the Protocol field of the IPv4 header, the Destination Port field of the UDP header, and the messageType field of the PTP header match expected values. (Configuration 5) The communication device according to configuration 2, wherein the detection means determines that writing or reading of a PTP packet has been detected when the values ​​of the EtherType field of the Ethernet header, the Next Header field of the IPv6 header, the Destination Port field of the UDP header, and the messageType field of the PTP header match expected values. (Configuration 6) 6. The communication device according to any one of configurations 2 to 5, wherein the detection means detects writing or reading of a PTP packet based on a value in an area from the beginning of the PTP packet to a messageType area of ​​the PTP header. (Configuration 7) 7. The communication device according to any one of configurations 1 to 6, wherein the detection means detects writing or reading of a predetermined packet after the signal of the channel reaches a value indicating the end of data. (Configuration 8) the channel for writing the packet received from the outside into the memory unit is a write data channel; The communication device according to any one of configurations 1 to 7, characterized in that the detection means identifies the beginning position of valid data based on byte enable information of the write data channel, and detects the writing of a specified packet based on the valid data. (Configuration 9) a channel for transmitting the packet read from the memory unit to an external device includes a read request channel and a read response channel; The communication device described in any one of configurations 1 to 7, characterized in that the detection means identifies the starting position of valid data in the read response channel based on address information of the read request channel, and detects the reading of a specified packet based on the valid data. (Configuration 10) 10. The communication device according to any one of configurations 1 to 9, wherein the channel is a channel between a DMA unit and a bus. (Configuration 11) 11. The communication device according to configuration 10, wherein the detecting means and the time keeping means are provided inside the DMA unit. (Configuration 12) The detection means a first detecting means for detecting the writing of a PTP packet based on a signal of a channel for writing the packet received from the outside into a memory unit; a second detection means for detecting the reading of a PTP packet based on a signal of a channel for transmitting the packet read from the memory unit to the outside, The time keeping means When the writing of the PTP packet is detected, the current time of the clock unit is held as a write holding time; 7. The communication device according to any one of configurations 2 to 6, wherein when reading of the PTP packet is detected, the current time of the clock unit is held as a read hold time. (Configuration 13) 13. The communication device according to configuration 12, further comprising a correction means for correcting the current time of the clock unit based on the write hold time and the read hold time. (Configuration 14) a timing signal generating means for generating a timing signal based on the current time of the clock unit; 14. The communication device according to configuration 13, further comprising an image capturing means for capturing an image based on the timing signal. (Method 1) a detection step of detecting writing or reading of a predetermined packet based on a signal of a channel for writing a packet received from an external device to a memory unit or a signal of a channel for transmitting a packet read from the memory unit to an external device; a time holding step of holding the current time of the clock unit as a write hold time or a read hold time when writing or reading of the predetermined packet is detected; A processing method for a communication device, comprising: (Program 1) A program for causing a computer to function as the communication device according to any one of the first to fourteenth aspects. [Explanation of symbols]

[0199] 101 digital camera, 102 wireless LAN network, 201 CPU, 202 memory unit, 203 communication IF unit, 204 antenna, 205 DMA unit, 206 time management unit, 209 system bus, 210 photographing unit, 601 register unit, 602 write data channel analysis unit, 603 read request channel analysis unit, 604 read response channel analysis unit, 605 clock unit, 606 time holding unit, 607 notification unit, 620 timing signal generation unit, 1201 DMA unit, 1301 DMA register unit, 1302 system transfer unit, 1303 internal memory unit, 1304 communication IF transfer unit, 1306 internal bus

Claims

1. a detection means for detecting writing or reading of a predetermined packet based on a signal of a channel for writing a packet received from an external device into the memory unit or a signal of a channel for transmitting a packet read from the memory unit to an external device; time holding means for holding the current time of the clock unit as a write hold time or a read hold time when writing or reading of the predetermined packet is detected; A communication device comprising:

2. 2. The communication device according to claim 1, wherein the predetermined packet is a PTP packet.

3. 3. The communication device according to claim 2, wherein the detection means determines that writing or reading of a PTP packet has been detected when the values ​​of the EtherType field of the Ethernet header and the messageType field of the PTP header match expected values.

4. 3. The communication device according to claim 2, wherein the detection means determines that writing or reading of a PTP packet has been detected when values ​​in the EtherType field of the Ethernet header, the Protocol field of the IPv4 header, the Destination Port field of the UDP header, and the messageType field of the PTP header match expected values.

5. 3. The communication device according to claim 2, wherein the detection means determines that writing or reading of a PTP packet has been detected when values ​​in the EtherType field of the Ethernet header, the Next Header field of the IPv6 header, the Destination Port field of the UDP header, and the messageType field of the PTP header match expected values.

6. 3. The communication device according to claim 2, wherein the detection means detects writing or reading of a PTP packet based on a value in an area from the beginning of the PTP packet to a messageType area of ​​the PTP header.

7. 2. The communication device according to claim 1, wherein said detecting means detects writing or reading of a predetermined packet after the signal of said channel reaches a value indicating the end of data.

8. the channel for writing the packet received from the outside into the memory unit is a write data channel; 2. The communication device according to claim 1, wherein the detection means identifies the leading position of valid data based on byte enable information of the write data channel, and detects the writing of a predetermined packet based on the valid data.

9. a channel for transmitting the packet read from the memory unit to an external device includes a read request channel and a read response channel; 2. The communication device according to claim 1, wherein the detection means identifies the leading position of valid data in the read response channel based on address information of the read request channel, and detects the reading of a specified packet based on the valid data.

10. 2. The communication device according to claim 1, wherein the channel is a channel between a DMA unit and a bus.

11. 11. The communication device according to claim 10, wherein the detecting means and the time holding means are provided inside the DMA unit.

12. The detection means a first detecting means for detecting a write of a PTP packet based on a signal of a channel for writing the packet received from the outside into a memory section; a second detecting means for detecting the reading of a PTP packet based on a signal of a channel for transmitting the packet read from the memory unit to an external device, The time keeping means When the writing of the PTP packet is detected, the current time of the clock unit is held as a write holding time; 3. The communication device according to claim 2, wherein when the reading of the PTP packet is detected, the current time of the clock unit is held as a read hold time.

13. 13. The communication device according to claim 12, further comprising a correction unit that corrects the current time of the clock unit based on the write hold time and the read hold time.

14. a timing signal generating means for generating a timing signal based on the current time of the clock unit; 14. The communication device according to claim 13, further comprising an image capturing means for capturing an image based on the timing signal.

15. a detection step of detecting writing or reading of a predetermined packet based on a signal of a channel for writing a packet received from an external device to a memory unit or a signal of a channel for transmitting a packet read from the memory unit to an external device; a time holding step of holding the current time of the clock unit as a write hold time or a read hold time when writing or reading of the predetermined packet is detected; A processing method for a communication device, comprising:

16. A program for causing a computer to function as the communication device according to any one of claims 1 to 14.

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