Semiconductor device

Abstract

To provide a semiconductor device having a memory array that can be miniaturized.SOLUTION: A semiconductor device includes a memory array 10. The memory array 10 includes a memory cell area MCA that is arranged in the central portion and dummy cell areas DCA_U and DCA_L arranged in the peripheral portion when viewed in plain view. In the dummy cell area DCA_L, a dummy cell D2_SS is connected to a word line DWL2_SLFIXRF<L_0>, and the dummy cell D2_SS has a transistor NM2 whose gate terminal is connected to the word line DWL2_SLFIXRF<L_0> and drain terminal is supplied with ground voltage Vss. During a read operation of a memory cell N, the transistor NM2 is turned to a conductive state so that the ground voltage Vss is supplied to source lines CSL<0> to CSL<n>.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, for example, a semiconductor device including a memory array in which a plurality of variable resistance memory cells are arranged in a matrix. [Background technology]

[0002] A resistance change memory cell (hereinafter simply referred to as a memory cell) refers to a memory cell having a memory element whose resistance value changes depending on the information (data) to be stored. An example of an electrically rewritable nonvolatile memory device (hereinafter also referred to as a nonvolatile memory device) configured with such memory cells is a magnetoresistive random access memory (hereinafter also referred to as an MRAM).

[0003] A memory array is formed by arranging multiple memory cells in a matrix, and is used in a nonvolatile memory device. When, for example, data is read from a memory cell, the memory cell is identified in the memory array by an address signal, and data is read from the identified memory cell. In this case, the change in characteristics due to manufacturing variations of memory cells located in the outer periphery of the memory array is greater than the change in characteristics due to manufacturing variations of memory cells located in the center of the memory array. For example, the resistance value of memory cells located in the outer periphery varies relatively greatly due to manufacturing variations, making it difficult to read correct data.

[0004] To ensure that correct data is read, a dummy cell area in which memory cells that are not specified by an address signal (not disclosed to the user) are formed is arranged in the outer periphery of the memory array. For example, Non-Patent Document 1 shows that a dummy cell area is arranged in the outer periphery of the memory array, and the memory cells arranged in the dummy cell area are used as one-time programmable memory (hereinafter also referred to as OTP). [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] “A 16nm 32Mb Emmbedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle With Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity”, ISSCC 2023 / SESSION 33 / NON-VOLATILE MEMORY AND COMPUTE-IN-MEMORY / 33.1, 2023 IEEE International Solid-State Circuit Conference Summary of the Invention [Problem to be solved by the invention]

[0006] Generally, as miniaturization advances and memory cell size shrinks, the variation in characteristics due to manufacturing variations in memory cells located on the periphery of the memory array increases, making it necessary to increase the number of memory cells located in the dummy cell region. In particular, in the case of MRAM, the difference in resistance value of memory cells (the difference between the high resistance value and the low resistance value corresponding to the stored data) is small, and if manufacturing variations in memory cells located on the periphery of the memory array are large, there is a high possibility of read errors, so it is necessary to further increase the number of memory cells located in the dummy cell region.

[0007] As shown in Non-Patent Document 1, if memory cells arranged in the dummy cell region are used as OTPs that store trimming information, it is possible to effectively utilize part of the dummy cell region. However, because trimming information and the like do not require a large capacity, most of the memory cells arranged in the dummy cell region are unused. Furthermore, in memory cells consisting of one memory element and one select transistor, such as MRAM, memory cells that only have a select transistor and no memory element are also arranged in the dummy cell region. Since such memory cells do not have a memory element, they cannot be used as OTPs, so they become unused memory cells, and the number of unused memory cells arranged in the dummy cell region is even greater.

[0008] Even if the memory cell size is shrunk, it is necessary to increase the number of memory cells to be arranged in the dummy cell region, so the dummy cell region increases, the area ratio of the dummy cell region to the memory array becomes higher than before the shrinkage, and the effective memory cell size becomes larger. Therefore, the inventors have thought about making effective use of the dummy cell region to reduce the size of a semiconductor device equipped with a memory array. [Means for solving the problem]

[0009] A brief summary of a representative embodiment of the present invention will be given below.

[0010] That is, a semiconductor device according to one embodiment has a pair of first sides extending in a first direction and a pair of second sides extending in a second direction intersecting the first sides, and has a memory array having a plurality of rows parallel to the first sides and a plurality of columns parallel to the second sides.

[0011] Here, the memory array, when viewed in a plan view, includes a memory cell region disposed between a pair of first sides and a dummy cell region disposed between the memory cell region and the first side. In the memory array, each row disposed in the memory cell region includes a first word line and a plurality of memory cells, each including a first transistor having a gate terminal connected to the first word line and a first storage element. In each row disposed in the dummy cell region, a second word line and a plurality of first dummy cells, each including a second transistor having a gate terminal connected to the second word line and a drain terminal supplied with a predetermined voltage, are disposed. In addition, in the memory array, each column is provided with source lines and bit lines. In each column disposed in the memory cell region, a source terminal of the first transistor of the memory cell is connected to the source line disposed in the column, and a drain terminal of the first transistor of the memory cell is connected to the bit line disposed in the column via the first storage element. In each column disposed in the dummy cell region, a source terminal of the second transistor of the first dummy cell is connected to the source line disposed in the column.

[0012] The plurality of memory cells are arranged in the memory region at a first pitch in a first direction and at a second pitch in a second direction, and the plurality of first dummy cells are arranged in the dummy cell region at the first pitch in the first direction and at the second pitch in the second direction.

[0013] The semiconductor device further includes a row decoder connected to the first word line and configured to select the first word line in accordance with a row address signal during a read operation, and a control circuit connected to the second word line and configured to supply a selection signal that turns on the second transistor of the first dummy cell so that a predetermined voltage is supplied to the source line during a read operation.

[0014] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Effects of the Invention]

[0015] According to one embodiment, it is possible to provide a semiconductor device including a memory array that can be miniaturized. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a block diagram showing the configuration of a nonvolatile memory device built into a semiconductor device according to a first embodiment. [Figure 2] 2A and 2B are circuit diagrams showing the configurations of memory cells and dummy cells according to the first embodiment. [Figure 3] FIG. 3 is a plan view showing the structure of the memory cell according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view showing the structure of the memory cell according to the first embodiment. [Figure 5] FIG. 5 is a circuit diagram showing the configuration of a memory array according to the first embodiment. [Figure 6] FIG. 6 is a block diagram showing a configuration of the semiconductor device according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, various embodiments of the present invention will be described with reference to the drawings. Note that the disclosure is merely an example, and any appropriate modifications that can be easily conceived by a person skilled in the art while maintaining the gist of the invention are naturally included within the scope of the present invention.

[0018] Furthermore, in this specification and each drawing, elements similar to those previously described with respect to the previous drawings are given the same reference numerals, and detailed descriptions thereof may be omitted as appropriate.

[0019] (Embodiment 1) <Configuration of semiconductor device> Fig. 6 is a block diagram showing the configuration of a semiconductor device according to the first embodiment. In Fig. 6, 1000 indicates a semiconductor device. The semiconductor device 1000 includes an internal bus 1001 and a plurality of circuit blocks connected to the internal bus 1001. The internal bus 1001 and the plurality of circuit blocks included in the semiconductor device 1000 are formed on the same semiconductor substrate.

[0020] 6 shows, as an example of the plurality of circuit blocks, a processor 1002, a volatile memory device (RAM) 1003, a nonvolatile memory device 1004, a timer 1005, an analog-to-digital conversion circuit (ADC) 1006, a digital-to-analog conversion circuit (DAC) 1007, a communication interface circuit (communication IF) 1008, and a peripheral circuit 1009. Of course, the circuit blocks shown in FIG. 6 are just an example and are not limited to these.

[0021] For example, the processor 1002 operates in accordance with a program, thereby realizing a predetermined function in the semiconductor device 1000. To realize the predetermined function, the processor 1002 accesses circuit blocks (e.g., the nonvolatile memory device 1004, the peripheral circuit 1009, etc.) connected to the internal bus 1001 via the internal bus 1001. This access causes the processor 1002 to perform an operation of reading data stored in the nonvolatile memory device 1004, for example. In this read operation, the processor 1002 supplies address signals (row address signal and column address signal) and control signals related to reading / writing (hereinafter also referred to as read / write control signals R / W) to the nonvolatile memory device 1004 via the internal bus 1001. When a read operation is instructed by the read / write control signal R / W, the nonvolatile memory device 1004 outputs data of a memory cell identified (selected) in accordance with the supplied address signal to the processor 1002 via the internal bus 1001.

[0022] In the first embodiment, the nonvolatile memory device 1004 is an MRAM, and is described as having a memory array in which MRAM memory cells are arranged in a matrix, but this is not limited to this, and the nonvolatile memory device 1004 may be any memory device having a memory array in which resistance-change memory cells are arranged in a matrix.

[0023] <Configuration of nonvolatile storage device> FIG. 1 is a block diagram showing the configuration of a nonvolatile memory device built into a semiconductor device according to a first embodiment.

[0024] The nonvolatile memory device 1004 according to the first embodiment includes a memory array 10, a row decoder (R-DEC & R-DRV) 11, a column decoder (C-DEC & C-SW) 12, a sense amplifier 13, a write circuit 14, and a control circuit 15.

[0025] When viewed in a plan view, the row decoder 11, column decoder 12, sense amplifier 13, write circuit 14, and control circuit 15 are arranged outside the memory array 10 on the semiconductor substrate. The interior of the memory array 10 is depicted in a schematic manner to match the actual arrangement on the semiconductor substrate.

[0026] When viewed in a plan view, the memory array 10 has a rectangular shape on a semiconductor substrate, which is configured by a pair of first sides 10_1 extending in a first direction DP1 and a pair of second sides 10_2 extending in a second direction DP2 intersecting (orthogonal to) the first direction DP1. The memory array 10 has arranged therein a matrix configured by a plurality of rows parallel to the first sides 10_1 and a plurality of columns parallel to the second sides 10_2. In FIG. 1, a column is indicated by the symbol CLM, and a row is indicated by the symbol RLM.

[0027] The memory array 10 has a memory cell area MCA arranged in the central portion of the memory array 10, and dummy cell areas DCA_U, DCA_L, DCA_R, and DCA_E ​​arranged to surround the memory cell area MCA. In other words, the memory cell area MCA is arranged between a pair of first sides 10_1, a first dummy cell area DCA_U is arranged between one first side 10_1A of the pair of first sides 10_1 and the memory cell area MCA, and a second dummy cell area DCA_L is arranged between the other first side 10_1B of the pair of first sides 10_1 and the memory cell area MCA. Furthermore, dummy cell areas DCA_R and DCA_E ​​are arranged between a pair of second sides 10_2 and the memory cell area MCA.

[0028] In the matrices and columns arranged in the memory array 10, a matrix in which the memory cell area MCA is arranged (a matrix to which the memory cell area MCA is assigned) has a plurality of memory cells N arranged therein, as shown in Fig. 1. Similarly, in the matrices and columns arranged in the memory array 10, a matrix in which the dummy cell areas DCA_U, DCA_L, DCA_R, and DCA_E ​​are arranged (a matrix to which the dummy cell area is assigned) has a plurality of dummy cells D1 and D2 arranged therein, as shown in Fig. 1. An example of the configuration of the memory cell N and the dummy cells D1 and D2 will be described later using Fig. 2, and therefore description thereof will be omitted here.

[0029] When the memory cells and dummy cells are viewed in a plan view, the lengths of the memory cell N and the dummy cells D1 and D2 in the first direction DP1 and the second direction DP2 are equal. That is, the lengths of the memory cell N and the dummy cells D1 and D2 in the first direction DP1 are the same MLL1, and the lengths of the memory cell N and the dummy cells D1 and D2 in the second direction DP2 are the same MLL2. The memory cells N and the dummy cells D1 and D2 are arranged in a matrix within the memory array 10 without any gaps. Therefore, in the first direction DP1, the multiple memory cells N are arranged at intervals of a pitch P1 corresponding to the length MLL1, and in the second direction DP2, they are arranged at intervals of a pitch P2 corresponding to the length MLL2. Similarly, the multiple dummy cells D1 and D2 are arranged at a pitch P1 corresponding to the length MLL1 in the first direction DP1, and at a pitch P2 corresponding to the length MLL2 in the second direction DP2.

[0030] A source line and a bit line are arranged in each column of the matrix constituting the memory array 10. In FIG. 1, the source lines arranged in the columns of the memory cell area MCA and the dummy cell areas DCA_U and DCA_L are denoted by the symbol CSL <0> ~CSL <n>and the bit line is denoted by BL <0> ~BL <m>The source lines arranged in the columns of the dummy cell areas DCA_R and DCA_E ​​are denoted by the symbol CSL <d>and the bit line is denoted by BL <d>is shown.

[0031] In FIG. 1, one source line (e.g., CSL <0> ) is shown as an example, but the present invention is not limited to this. For example, one source line and one bit line may be arranged for each column. However, as shown in FIG. 1, by sharing a source line between adjacent columns, it is possible to achieve miniaturization or to reduce wiring resistance by making the source line wiring thicker.

[0032] A word line is arranged in each row of the matrix that constitutes the memory array 10. In FIG. 1, the word lines arranged in the rows of the memory cell area MCA and in some rows of the dummy cell areas DCA_R and DCA_E ​​are denoted by the symbol WL <0> ~WL <n>The word lines arranged in some rows of the dummy cell areas DCA_R and DCA_E ​​and in the rows of the dummy cell areas DCA_U and DCA_L are denoted by the symbol DWL2<U_0> ~DWL2<U_n> , code DWL1<U_0> ~DWL1<U_n> , code DWL2<L_0> ~DWL2<L_n> , code DWL1<L_0> ~DWL1<L_n> is shown.

[0033] <<Memory cell N and dummy cells D1 and D2>> Here, the memory cell N and the dummy cells D1 and D2 will be described with reference to the drawings. Fig. 2 is a circuit diagram showing the configuration of the memory cell and the dummy cells according to the first embodiment. In the first embodiment, the configuration of the dummy cell D1 is the same as that of the memory cell N. Fig. 2(A) shows the configuration of the memory cell N and the dummy cell D1, and Fig. 2(B) shows the configuration of the dummy cell D2.

[0034] As shown in FIG. 2A, the memory cell N and the dummy cell D1 each include an N-channel field-effect transistor (hereinafter simply referred to as a transistor) NM1 and a storage element MTJ. The gate terminal of the transistor NM1 is connected to a word line WL or DWL1, and the drain terminal TDT is connected to the terminal TMT via the storage element MTJ. In FIG. 2A, the symbol TST denotes the source terminal of the transistor NM1. In the first embodiment, the storage element MTJ is a three-layered element of a magnetic tunneling junction. This three-layered element is an element with a stacked structure of a pinned layer, a tunneling layer, and a free layer, and its resistance value changes according to the written data.

[0035] As shown in Figure 2B, the dummy cell D2 includes a transistor NM2. The gate terminal of the transistor NM2 is connected to a word line WL, DWL1, or DWL2. In Figure 2B, the symbol TDT denotes the drain terminal of the transistor NM2, and the symbol TST denotes the source terminal of the transistor NM2.

[0036] In FIG. 2, the symbols MLL1 and MLL2 schematically indicate the lengths of the memory cell N and the dummy cells D1 and D2 in the first direction DP1 and the second direction DP2.

[0037] Returning to FIG. 1, the description of the nonvolatile storage device 1004 will continue.

[0038] Word line WL <0> ~WL <n>are connected to the row decoder 11. The row decoder 11 includes a decoder circuit 11_D and a word line driver. The decoder circuit 11_D decodes a row address signal (R address) from the processor 1002 (FIG. 6) and generates a selection signal according to the row address signal. The word line driver selects the word line WL <0> ~WL <n>The decoder circuit 11_D has a plurality of switches SSW and NSW corresponding to the selected word lines. The switch SSW or NSW is turned on in accordance with a selection signal generated by the decoder circuit 11_D. When the switch SSW is turned on by the selection signal, a selected word line voltage (power supply voltage) Vpp is supplied to the corresponding word line via the switch SSW. On the other hand, when the switch NSW is turned on by the selection signal, a non-selected word line voltage Vmm (a voltage lower than Vpp, for example, a negative voltage, ground voltage Vss, etc.) is supplied to the corresponding word line via the switch NSW.

[0039] As explained in FIG. 2A, the memory cells N arranged in the matrix of the memory cell area MCA have a gate terminal of the transistor NM1 connected to the word line WL (WL <0> ~WL <n>) and the source terminal TST of the transistor NM1 in the memory cell N is connected to the source line CSL <0> ~CSL <n>The drain terminal of the transistor NM1 is connected to the bit line BL via the memory element MTJ and the terminal TMT. <0> ~BL <m>is connected to.

[0040] Bit line BL <0> ~BL <m>are connected to the column decoder 12. A column address signal (C address) is supplied to the column decoder 12 from the processor 1002 (FIG. 6). The column decoder 12 includes a decoder circuit (C-DEC) and a column switch (C-SW), not shown. The decoder circuit (C-DEC) decodes the column address signal and generates a selection signal. The column switch (C-SW) selects a bit line BL <0> ~BL <m>A bit line designated by a selection signal is selected from the list and connected to a sense amplifier 13 and a write circuit 14 .

[0041] For example, when a row address signal is input to the word line WL <0> and the column address signal is applied to the bit line BL <0> , the word line WL <0> The switch SSW corresponding to the word line WL <0> The transistors NM1 in the memory cells N connected to the bit line BL1 become conductive, and the memory elements MTJ in the memory cells N are connected between the corresponding bit line and source line via the transistors NM1. At this time, the decoder circuit (C-DEC) applies a signal to the bit line BL1 in accordance with the column address signal. <0> A selection signal is generated to select the bit line BL <0> are connected to the sense amplifier 13 and the write circuit 14. At this time, other word lines (for example, WL <n>), the corresponding switch NSW is turned on, and therefore the transistors NM1 in the memory cells N connected to the other word lines are turned off. As a result, the memory elements MTJ in the memory cells N connected to the other word lines are electrically isolated from the corresponding bit lines.

[0042] The sense amplifier 13 is controlled by a read control signal R_CNT, and the write circuit 14 is controlled by a write control signal W_CNT. That is, when a read operation is instructed by the read control signal R_CNT, the sense amplifier 13 amplifies the voltage on the connected bit line (a voltage according to the data of the memory cell N) and supplies it as read data Out to the processor 1002. On the other hand, when a write operation is instructed by the write control signal W_CNT, the write circuit 14 supplies the input data In supplied from the processor 1002 to the connected bit line, and writing to the memory cell N is performed.

[0043] The control circuit 15 outputs a read control signal R_CNT indicating a read operation and a write control signal W_CNT indicating a write operation in accordance with a read / write control signal R / W from the processor 1002.

[0044] The control circuit 15 also controls the word lines DWL2 arranged in the rows of the dummy cell areas DCA_U and DCA_L and in some rows of the dummy cell areas DCA_R and DCA_E.<U_0> ~DWL2<U_n> , DWL1<U_0> ~DWL1<U_n> , DWL2<L_0> ~DWL2<L_n> , DWL1<L_0> ~DWL1<L_n> The control circuit 15 according to the first embodiment is not supplied with address signals (row address signals: R address and column address signals: C address), but supplies predetermined selection signals and non-selection signals to the connected word lines.

[0045] The bit lines BL arranged in each column of the dummy cell areas DCA_R and DCA_E <d>and source line CSL <d>Although not particularly limited, in the first embodiment, the bit lines BL are connected to a common wiring IVL as shown in FIG. <d>and source line CSL <d>1, the wiring IVL is supplied with the ground voltage Vss because it is not used in the read operation or the write operation. The voltage supplied to the wiring IVL is not limited to the ground voltage Vss, but may be a voltage for inhibiting writing or a voltage for easing the breakdown voltage during writing. Alternatively, the wiring IVL may be in a floating state.

[0046] 1, a memory cell area MCA made up of memory cells specified by address signals (R address and C address) is arranged in the central part of the memory array 10, and dummy cell areas DCA_U, DCA_L, DCA_R, and DCA_E ​​made up of dummy cells that are not specified by the address signals and are not disclosed to the user are arranged in the outer periphery of the memory array 10, surrounding the memory cell area MCA. This allows the dummy cell areas to guarantee the characteristics of the memory cell areas.

[0047] 1, in the dummy cell areas DCA_U, DCA_L, DCA_R, and DCA_E, a dummy cell D1 having a configuration similar to that of memory cell N is arranged in the portion (area) adjacent to memory cell area MCA, and a dummy cell D2 having only transistor NM2 is arranged in the portion (area) outside of that. As a result, the characteristics of the transistor and memory element constituting memory cell N are guaranteed by the transistor and memory element of dummy cell D1 having a configuration similar to that of memory cell N, and further, the characteristics of memory cell N and transistor NM1 of dummy cell D1 are guaranteed by transistor NM2 of dummy cell D2.

[0048] <<<Memory cell structure>>> Next, an example of the structure of a memory cell will be described with reference to the drawings. Fig. 3 is a plan view showing the structure of a memory cell according to the first embodiment. Fig. 4 is a cross-sectional view showing the structure of a memory cell according to the first embodiment. Fig. 4 shows a cross section taken along dashed line AA' in Fig. 3. Below, an example of the structure of a memory cell will be described mainly with reference to Figs. 3 and 4.

[0049] A P-type well region 1000_PW is formed on a semiconductor substrate, and a memory cell N is formed in this P-type well region 1000_PW.

[0050] N formed in the P-type well region 1000_PW + The type diffusion layer DFN constitutes the source region (S) and drain region (D) of the transistor NM1 (see FIG. 2A) of the memory cell N. The N + The gate electrode of the transistor NM1 is formed by a polysilicon layer PSG formed on the P-type well region 1000_PW between the type diffusion layers DFN. The polysilicon layer PSG also extends as a word line WL in the first direction DP1 (see FIGS. 1 and 2A).

[0051] The N + The source region (S) and the drain region (D) formed by the diffusion layer DFN are connected to the first metal layer M1. Here, the first metal layer M1 connected to the source region (S) is connected to the source line M1 (CSL: for example, the CSL in FIG. 1). <0> etc.)

[0052] A second metal layer M2 is connected to the first metal layer M1 via a metal V1 filled in a via hole provided in an interlayer insulating film (not shown) on the first metal layer M1, and a third metal layer M3 is connected to the second metal layer M2 via a metal V2 filled in a via hole provided in an interlayer insulating film (not shown) on the second metal layer M2. A memory element MTJ is connected between the third metal layer M3 and the fourth metal layer, and a fifth metal layer M5 is connected to the fourth metal layer M4 via a metal V4 filled in a via hole provided in an interlayer insulating film (not shown). This fifth metal layer M5 forms a bit line M5 (BL: for example, BL in FIG. 1). <0> As a result, in the memory cell N, the memory element MTJ is connected between the drain terminal of the transistor NM1 and the bit line BL. The source line M1 (CSL) and the bit line M5 (BL) extend in a second direction DP2 (see FIGS. 1 and 2A) that intersects (is perpendicular to) the first direction DP1.

[0053] When viewed in a plan view, one memory cell N is formed in an area surrounded by a thin dashed line in Fig. 3, and has a length MLL1 in a first direction DP1 and a length MLL2 in a second direction DP2. In the structure of the memory cell N shown in Fig. 3, one word line WL is composed of two polysilicon layers PSG(G_A) and PSG(G_B) arranged on either side of the drain region (D) and the memory element MTJ.

[0054] Since the dummy cell D1 has the same configuration as the memory cell N, Figures 3 and 4 can also be considered to show the structure of the dummy cell D1. Also, the dummy cell D2 has a structure in which the memory element MTJ is removed from Figures 3 and 4. When viewed in a plan view, the lengths (MLL1, MLL2) and areas of the memory cell N and the dummy cells D1 and D2 are equal to each other.

[0055] 3 and 4 are merely examples and are not intended to be limiting. For example, as explained in FIG. 1, the source line M1 (CSL) is shared by two columns, but it may be shared by no columns or by four or more columns.

[0056] <Memory array configuration> Fig. 5 is a circuit diagram showing the configuration of the memory array 10 according to the first embodiment. Fig. 5 shows only the memory cell area MCA shown in Fig. 1, a dummy cell area (second dummy cell area) DCA_U arranged between the memory cell area MCA and the first side 10_1A (see Fig. 1), and a dummy cell area (first dummy cell area) DCA_L arranged between the memory cell area MCA and the first side 10_1B (see Fig. 1).

[0057] In Figure 5, the memory cells, dummy cells, word lines, bit lines, and source lines shown in the memory cell area MCA and the dummy cell areas DCA_U and DCA_L are drawn schematically to match their actual planar arrangement on the semiconductor substrate.

[0058] When viewed in a plan view, the rows of the memory cell area MCA are connected to word lines (first word lines) WL as shown in FIG. <0> ~WL <n>are arranged, and the word line WL <0> ~WL <n>The gate terminal of the transistor (first transistor) NM1 constituting the memory cell N arranged in the row in which it is arranged is connected to the corresponding source line (e.g., CSL <n>), and the drain terminal TDT (FIG. 2A) is connected to a corresponding bit line (for example, BL <m>)

[0059] The row of the dummy cell area DCA_U is connected to the word line DWL2_EQN<U_0> ~DWL2_EQN<U_3> and word line DWL1_OTP<U_0> ~DWL1_OTP<U_5> Here, the word line DWL2_EQN<U_0> ~DWL2_EQN<U_3> is the word line DWL2 shown in FIG.<U_0> ~DWL2<U_n> and is arranged in the row in which the dummy cell D2 is arranged.<U_0> ~DWL1_OPT<U_5> is the word line DWL1 shown in FIG.<U_0> ~DWL2<U_n> and is placed in the row in which the dummy cell D1 is placed.

[0060] In addition, the word line DWL2_SLFIXRF is connected to the row of the dummy cell area DCA_L.<L_0> ~DWL2_SLFIXRF<L_3> and word line DWL2_NOSL<L_0> ~DWL2_NOSL<L_1> and word line DWL1_OTP<L_0> ~DWL1_OTP<L_5> Here, the word line DWL2_SLFIXRF<L_0> ~DWL2_SLFIXRF<L_3> and word line DWL2_NOSL<L_0> ~DWL2_NOSL<L_1> is the word line DWL2 shown in FIG.<L_0> ~DWL2<L_n> and is arranged in the row in which the dummy cell D2 is arranged.<L_0> ~DWL1_OPT<L_5> is the word line DWL1 shown in FIG.<U_0> ~DWL2<U_n> and is placed in the row in which the dummy cell D1 is placed.

[0061] The dummy cell area DCA_U will be described later in the second embodiment, and therefore will not be described here.

[0062] <<Dummy cell area DCA_L>> 5, when viewed in a plan view, a matrix of 12 rows is arranged in the dummy cell area DCA_L. Of these 12 rows, dummy cells D1 (D1_OT) are arranged in six rows adjacent to the memory cell area MCA, and dummy cells D2 (D2_SS, D2_NS) are arranged in the remaining six rows outside of these. Of course, this number of rows is just an example and is not limited to this number of rows.

[0063] In the row in which the dummy cells (first dummy cells) D2_SS and D2_NS are arranged, as shown in FIG. 5, the word line (second word line) DWL2_SLFIXRF<L_0> ~DWL2_SLFIXRF<L_3> and word line (third word line) DWL2_NOSL<L_0> ~DWL2_NOSL<L_1> The gate terminal of the transistor (second transistor) NM2 constituting the dummy cell D2_SS is connected to the word line DWL2_SLFIXRF arranged in the row in which the dummy cell is arranged.<L_0> ~DWL2_SLFIXRF<L_3> The gate terminal of the transistor NM3 constituting the dummy cell D2_NS is connected to the word line DWL2_NOSL arranged in the row in which the dummy cell is arranged.<L_0> ~DWL2_NOSL<L_1> is connected to.

[0064] The source terminal of the transistor NM2 constituting the dummy cell D2_SS is connected to the source line (for example, CSL <n>), and a predetermined voltage (ground voltage Vss in FIG. 5) is supplied to the drain terminal. Similarly, the source terminal of the transistor NM3 constituting the dummy cell D2_NS is connected to the source line (for example, CSL <n>), and a predetermined voltage (ground voltage Vss in FIG. 5) is supplied to the drain terminal. For convenience of explanation, different reference numerals are used for the transistors constituting the dummy cell D2_SS and the transistors constituting the dummy cell D2_NS, but they have the same size and characteristics.

[0065] The control circuit 15 shown in FIG. 1 controls the word line DWL2_SLFIXRF<L_0> ~DWL2_SLFIXRF<L_3> A selection signal that turns on the transistor NM2 is supplied to the word line DWL2_NOSL<L_0> ~DWL2_NOSL<L_1> 2. A selection signal that turns off the transistor NM3 is supplied to the source line CSL through the transistor NM2 that configures the dummy cell D2_SS. <0> ~CSL <n>A predetermined voltage (ground voltage Vss) is supplied to the source line CSL. <0> ~CSL <n>When the voltage reaches a predetermined value, the bit line BL <0> ~BL <m>This voltage is a voltage according to the state of the storage element MTJ1, with a predetermined voltage as the reference voltage, and is amplified and read by the sense amplifier 13 (FIG. 1).

[0066] Each source line (e.g., CSL <n>During a read operation, a predetermined voltage is supplied to the source line NM1 by multiple transistors NM2 (eight transistors in FIG. 5) in parallel, so that the voltage of the source line can be reliably fixed to a predetermined voltage, thereby reducing the possibility of erroneous data being read.

[0067] In a read operation, the more transistors connected between the source line and a predetermined voltage, the more reliably the voltage of the source line can be fixed, but the more current flows between the source line and the predetermined voltage. Therefore, in FIG. 5, a word line DWL2_NOSL connected to a dummy cell D2_NS having the same configuration as the dummy cell D2_SS is connected.<L_0> ~DWL2_NOSL<L_1> For the dummy cells D2_NS, a selection signal is supplied from the control circuit 15 to turn off the transistor NM3 in the dummy cell D2_NS. This makes it possible to regularly arrange a plurality of dummy cells D2 having the same configuration in the dummy cell area DCA_L, suppress an increase in current consumption, and reduce the possibility of erroneous data being read.

[0068] To further reduce current consumption, the drain terminal of transistor NM3 constituting dummy cell D2_NS may be set to a floating state by not supplying a predetermined voltage, and further, the source terminal of transistor NM3 may also be separated from the source line and set to a floating state.

[0069] In the row in which the dummy cell (second dummy cell) D1_OT is arranged, as shown in FIG. 5, the word line (fourth word line) DWL1_OTP<L_0> ~DWL1_OTP<L_5> The gate terminal of the transistor (third transistor) NM4 constituting the dummy cell D1_OT is connected to the word line DWL1_OTP arranged in the row in which the dummy cell is arranged.<L_0> ~DWL1_OTP<L_5> The source terminal of the transistor NM4 is connected to the source line (for example, CSL <n>), and the drain terminal is connected to a bit line (for example, BL <m>)

[0070] The dummy cell D1_OT is a memory cell for OTP, and trimming information and the like are written in advance. For example, by destroying the memory element MTJ2, data constituting the trimming information and the like is written to the dummy cell D1_OT. Since data is written depending on whether or not the memory element MTJ2 is destroyed, it is possible to increase the difference between the resistance value of the memory element MTJ2 when it is not destroyed and the resistance value after it is destroyed. Furthermore, by configuring the dummy cell D1_OT to read data in a complementary manner, it is possible to further increase the difference in resistance value.

[0071] For example, the source line CSL <n>and word line DWL1_OPT<L_5> Complementary data is written to the two dummy cells D1_OT connected to the bit line BL <m-1>and BL <m>By reading the voltage difference between the dummy cell D1_OT and the dummy cell D2_OT, it is possible to read complementary data. In this way, by increasing the difference in resistance value, it is possible to read correct trimming information, etc. from the dummy cell D1_OT even in memory cells that are arranged outside the memory cell area MCA and have large variations in resistance value during manufacturing.

[0072] As described above, according to the first embodiment, the dummy cell D2_SS arranged in the dummy cell area is used to supply a predetermined voltage to the source line during a read operation, which makes it possible to effectively use the dummy cell area and reduce the possibility of reading erroneous data.In addition, trimming information and the like can be stored in the dummy cell area by using the dummy cell D1_OT, which further makes it possible to effectively use the dummy cell area.

[0073] Furthermore, since the memory element MTJ is not used to supply a predetermined voltage to the source line, it is possible to supply a predetermined voltage to the source line without being affected by variations in the memory element MTJ.

[0074] Since the source line and the predetermined voltage are connected by a plurality of transistors NM2 connected in parallel, it is possible to reliably supply the predetermined voltage to the source line even if there is variation in the characteristics of the transistors NM2. Also, since the dummy cell D2_SS is arranged in the outer periphery of the memory array 10, it is conceivable that the on-resistance of the transistor NM2 will be high. However, since the transistors NM2 connected in parallel as shown in Figure 5 are used, it is possible to connect the predetermined voltage and the source line with low resistance (the combined resistance of the parallel-connected transistors NM2 in the conductive state).

[0075] FIG. 5 shows an example in which dummy cells DS_SS arranged in four rows are used to supply a predetermined voltage to the source line, but this is not limited to this, and one row of dummy cells D2_SS or five or more rows of dummy cells D2_SS may be used.

[0076] Alternatively, instead of or in combination with the dummy cell D2_SS, a dummy cell D1 (e.g., D1_OT) having a memory element MTJ2 may be used as a dummy cell that supplies a predetermined voltage to the source line. In this case, it is desirable to perform a write process or the like on the memory element MTJ2 so that its resistance value is reduced.

[0077] Without using the dummy cell D2_SS, for example, a predetermined voltage (ground voltage Vss) and a source line CSL are connected outside the memory array 10. <0> ~CSL <n>It is also possible to provide a configuration in which multiple transistors are provided to connect between the source line and the transistors. However, in such a configuration, an area is required outside the memory array 10 for forming the transistors, and an area is required for forming wiring connecting the transistors to the source line, resulting in an increase in area. Furthermore, the parasitic capacitance of the wiring connecting the transistors to the source line may increase the parasitic capacitance connected to the source line, and it may take a long time to set the source line to a predetermined voltage.

[0078] According to the first embodiment, such transistors and wiring are not required, which makes it possible to achieve miniaturization and prevent the time required to set the source line to a predetermined voltage from becoming long.

[0079] (Embodiment 2) A memory array 10 according to the second embodiment will be described with reference to FIG.

[0080] In plan view, the dummy cell area DCA_U shown in Figure 5 has 12 rows arranged in a matrix. Of the 12 rows, dummy cells D1 (D1_OT) are arranged in six rows adjacent to the memory cell area MCA, and dummy cells D2 (D2_EQ) are arranged in the remaining six rows outside of those. Of course, this number of rows is just an example and is not limited to this number of rows.

[0081] As shown in FIG. 5, in the row where the dummy cell (first dummy cell) D2_EQ is arranged, the word line (second word line) DWL2_EQN<U_0> ~DWL2_EQN<U_3> The gate terminal of the transistor (second transistor) NM5 constituting the dummy cell D2_EQ is connected to the word line DWL2_EQN arranged in the row in which the dummy cell is arranged.<U_0> ~DWL2_EQN<U_3> is connected to.

[0082] The source terminal of the transistor NM5 constituting the dummy cell D2_EQ is connected to the source line (for example, CSLM) corresponding to the column in which the dummy cell is arranged. <n>), and the drain terminal is connected to a bit line (e.g., BL <m-1>or BL <m>)

[0083] In FIG. 5, the gate terminal is connected to the word line DWL2_EQN<U_0> or DWL2_EQN<U_3> and the source terminal is connected to the source line (CSL <n>) and the drain terminal TDT of the transistor NM5 in a floating state represents the dummy cell D2.

[0084] The dummy cell D2_EQ is used to equalize the bit line and the source line before a read operation of the memory cell N. Before reading data from the memory cell N, the bit line (for example, BL <m>The voltage of the bit line and source line is fixed at a predetermined voltage (for example, ground voltage Vss). When a read operation starts, the voltage transitions from the predetermined voltage to a voltage determined by the resistance of the memory element MTJ1 of the memory cell, and is then amplified by the sense amplifier. In other words, before a read operation, it is necessary to equalize the bit line and source line.

[0085] In the second embodiment, the control circuit 15 shown in FIG. 1 transmits a selection signal to the word line DWL2_EQN to make the transistor NM5 conductive before a read operation for the memory cell N.<U_0> ~DWL2_EQN<U_3> More specifically, before a read operation for memory cell N, the control circuit 15 supplies the above selection signal to word line DWL2_EQN.<U_0> ~DWL2_EQN<U_3> Then, when reading from memory cell N is started, a non-selection signal that turns transistor NM5 into a non-conductive state is supplied to DWL2_EQN.<U_0> ~DWL2_EQN<U_3> As a result, the transistor NM5 is in a conductive state during a part of the period in which the transistor NM2 in the dummy cell D2_SS is in a conductive state, and then the transistor NM5 is in a non-conductive state.

[0086] As a result, transistor NM2 in dummy cell D2_SS performs an equalization operation to reduce the potential difference between the bit line and the source line during a portion of the period during which a predetermined voltage is supplied to the source line, and the above-mentioned equalization operation by dummy cell D2_EQ is completed before the read operation of memory cell N is started, and the voltage on the bit line changes according to the data of memory cell N.

[0087] In the row in which the dummy cell (third dummy cell) D1_OT is arranged, as shown in FIG. 5, the word line (fifth word line) DWL1_OTP<U_0> ~DWL1_OTP<U_5> are arranged. The dummy cells D1_OT are memory cells for OTP, the same as the dummy cells D1_OT described in the dummy cell area DCA_L of the first embodiment. The dummy cells D1_OT have already been described in the first embodiment, so a detailed description thereof will be omitted.

[0088] Although the timing for performing equalization has been described as before the read operation of memory cell N, it is not limited to this. For example, in a read operation, it is desirable to continue equalizing the bit lines deselected by the column decoder 12 (FIG. 1) even during the read operation. For example, when the bit lines BL <m>When selected, the bit line BL <m-1>Even during the read operation, the bit line BL <m-1>The dummy cell D2_EQ connected to the bit line BL <m-1>and source line CSL <n>To achieve this, for example, a column address signal (C address: FIG. 1) is supplied to the control circuit 15, and the control circuit 15 connects the bit line BL <m-1>The word line of the dummy cell D2_EQ connected to<U_0> ) during the read operation of memory cell N.

[0089] By equalizing, the bit line BL <0> ~BL <m>In order to supply a predetermined voltage to the source line CSL <0> ~CSL <n>As described in the first embodiment, a predetermined voltage (ground voltage Vss) is supplied to the source line CSL by the dummy cell (second dummy cell) D2_SS.

[0090] However, without using the dummy cell DS_SS, for example, a predetermined voltage (ground voltage Vss) and a source line CSL are connected outside the memory array 10. <0> ~CSL <n>However, such a configuration requires an area outside the memory array 10 for forming the transistors and an area for forming the wiring connecting the transistors to the source lines, resulting in an increase in area. Furthermore, the parasitic capacitance of the wiring connecting the transistors to the source lines may increase the parasitic capacitance connected to the bit lines and source lines, which may slow down the read operation.

[0091] According to the second embodiment, the dummy cells D2_SS and D2_EQ supply a predetermined voltage to the source line and perform equalization, which makes it possible to achieve a smaller size and to increase the speed of the read operation.

[0092] According to the second embodiment, the dummy cell D2_EQ in the dummy cell region is used to equalize the bit lines, so that the dummy cell region can be used effectively.

[0093] 5, the dummy cell D2_EQ is arranged on the outer periphery of the memory array 10. Therefore, the transistor NM5 constituting the dummy cell D2_EQ may have poor characteristics, for example, a high threshold voltage. However, since the transistor NM5 is used to equalize the bit line and the source line, a high threshold voltage does not pose a problem.

[0094] 5 shows an example in which a dummy cell without a memory element MTJ2 is used for equalization, but equalization may also be performed using a dummy cell D1 (e.g., D1_OT) that has a memory element MTJ2. In this case, during equalization, the source line and bit line are connected via transistor NM4 and memory element MTJ2. That is, the source line and bit line are connected with a relatively high resistance.

[0095] 5 shows an example in which equalization is performed by the dummy cell D2_EQ arranged in the dummy cell area DCA_U and a predetermined voltage is supplied to the source line by the dummy cell D2_SS arranged in the dummy cell area DCA_L, but this is not limiting. For example, a dummy cell D2_EQ that performs equalization and a dummy cell D2_SS that supplies a predetermined voltage may be arranged in each of the dummy cell areas DCA_U and DCA_L.

[0096] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0097] 10 Memory Array 11 Row Decoder 12 Column Decoder 15 Control circuit 1000 Semiconductor device 1002 processor 1004 Non-volatile storage device D1, D1_OT, D2, D2_EQ, D2_NS, D2_SS dummy cells DCA_E, DCA_L, DCA_R, DCA_U dummy cell area N memory cells NM1~NM5 transistors MCA memory cell area MTJ, MTJ1, MTJ2 memory elements< / n> < / n> < / m> < / n> < / m> < / m> < / n> < / m> < / n> < / n> < / m> < / n> < / m> < / n> < / n> < / m> < / n> < / n> < / n> < / n> < / m> < / n> < / n> < / n> < / d> < / d> < / d> < / d> < / n> < / m> < / m> < / m> < / n> < / n> < / n> < / n> < / n> < / d> < / d> < / m> < / n>

Claims

1. A semiconductor device comprising a memory array including a pair of first sides extending in a first direction and a pair of second sides extending in a second direction intersecting the first sides, the memory array including a plurality of rows parallel to the first sides and a plurality of columns parallel to the second sides, When viewed in a plan view, the memory array includes a memory cell region disposed between the pair of first sides, and a dummy cell region disposed between the memory cell region and the first sides, In the memory array, each row arranged in the memory cell region is provided with a first word line, and a plurality of memory cells each including a first transistor having a gate terminal connected to the first word line and a first storage element, and each row arranged in the dummy cell region is provided with a second word line, and a plurality of first dummy cells each including a second transistor having a gate terminal connected to the second word line and a drain terminal to which a predetermined voltage is supplied, In the memory array, a source line and a bit line are arranged in each column, and in each column arranged in the memory cell region, a source terminal of a first transistor of the memory cell is connected to the source line arranged in the column, and a drain terminal of the first transistor of the memory cell is connected to the bit line arranged in the column via the first memory element, and in each column arranged in the dummy cell region, a source terminal of a second transistor of the first dummy cell is connected to the source line arranged in the column, the plurality of memory cells are arranged in the memory cell region at a first pitch in the first direction and at a second pitch in the second direction, and the plurality of first dummy cells are arranged in the dummy cell region at the first pitch in the first direction and at the second pitch in the second direction, The semiconductor device includes: a row decoder connected to the plurality of first word lines and selecting a first word line in accordance with a row address signal during a read operation; a control circuit connected to the second word line, for supplying a selection signal that causes the second transistor of the first dummy cell to be in a conductive state so that the predetermined voltage is supplied to the source line during the read operation; Equipped with Semiconductor device.

2. 2. The semiconductor device according to claim 1, the dummy cell region further includes a row in which a plurality of first dummy cells are arranged and connected to a third word line different from the second word line; the third word line is connected to the control circuit, and the control circuit makes second transistors of the plurality of first dummy cells connected to the third word line non-conductive during the read operation; Semiconductor device.

3. 2. The semiconductor device according to claim 1, The source lines are shared between adjacent columns. Semiconductor device.

4. 3. The semiconductor device according to claim 2, the dummy cell region includes a row in which a plurality of second dummy cells are arranged, the second dummy cells being connected to a fourth word line different from the second word line and the third word line; the second dummy cell comprises a third transistor and a second memory element connected to a drain terminal of the third transistor, the third transistor having a gate terminal connected to the fourth word line, a source terminal connected to the source line, and a drain terminal connected to the bit line via the second memory element; data of the second memory element is set in advance, and when reading out data of the second memory element, the control circuit causes the third transistor to be in a conductive state via the fourth word line; Semiconductor device.

5. 5. The semiconductor device according to claim 4, the first memory element and the second memory element are elements having a three-layer structure in which a fixed layer, a tunnel layer, and a free layer of a magnetic tunnel junction are stacked; Semiconductor device.

6. 6. The semiconductor device according to claim 5, the semiconductor device includes a column decoder connected to the plurality of bit lines in the memory cell region and selecting a bit line in accordance with a column address signal; the row decoder, the column decoder, and the control circuit are arranged outside the memory array; Semiconductor device.

7. A semiconductor device comprising a memory array including a pair of first sides extending in a first direction and a pair of second sides extending in a second direction intersecting the first sides, the memory array including a plurality of rows parallel to the first sides and a plurality of columns parallel to the second sides, When viewed in a plan view, the memory array includes a memory cell region disposed between the pair of first sides, and a dummy cell region disposed between the memory cell region and the first sides, In the memory array, each row arranged in the memory cell region is provided with a first word line, and a plurality of memory cells each including a first transistor having a gate terminal connected to the first word line and a first storage element, and each row arranged in the dummy cell region is provided with a second word line, and a plurality of first dummy cells each including a second transistor having a gate terminal connected to the second word line, In the memory array, a source line and a bit line are arranged in each column, and in each column arranged in the memory cell region, a source terminal of a first transistor of the memory cell is connected to the source line arranged in the column, and a drain terminal of the first transistor of the memory cell is connected to the bit line arranged in the column via the first memory element, and in each column arranged in the dummy cell region, a source terminal of a second transistor of the first dummy cell is connected to the source line arranged in the column, and a drain terminal of the second transistor of the first dummy cell is connected to the bit line arranged in the column, the plurality of memory cells are arranged in the memory cell region at a first pitch in the first direction and at a second pitch in the second direction, and the plurality of first dummy cells are arranged in the dummy cell region at the first pitch in the first direction and at the second pitch in the second direction, The semiconductor device includes: a row decoder connected to the first word line, for selecting the first word line in accordance with a row address signal during a read operation; a control circuit connected to the second word line, the control circuit supplying a selection signal that causes the second transistor to be in a conductive state, thereby reducing a potential difference between the source line and the bit line; Equipped with Semiconductor device.

8. 8. The semiconductor device according to claim 7, The source lines are shared between adjacent columns. Semiconductor device.

9. 9. The semiconductor device according to claim 8, the dummy cell region further includes a row in which a plurality of second dummy cells are arranged and connected to a third word line different from the second word line; the second dummy cell includes a third transistor having a gate terminal connected to the third word line, a source terminal connected to the source line, and a drain terminal to which a predetermined voltage is supplied; the third word line is connected to the control circuit, and the control circuit supplies a selection signal to the third word line, which causes the third transistor to be in a conductive state, so that the predetermined voltage is supplied to the source line during the read operation. Semiconductor device.

10. 10. The semiconductor device according to claim 9, the dummy cell region further comprises a row of second dummy cells connected to a fourth word line different from the second word line and the third word line; the fourth word line is connected to the control circuit, and the control circuit makes the third transistor of the second dummy cell connected to the fourth word line non-conductive during the read operation. Semiconductor device.

11. 11. The semiconductor device according to claim 10, the dummy cell region includes a row in which a plurality of third dummy cells are arranged, the third dummy cells being connected to a fifth word line different from the second word line, the third word line, and the fourth word line; the third dummy cell includes a fourth transistor and a second memory element connected to a drain terminal of the fourth transistor, the fourth transistor having a gate terminal connected to the fifth word line, a source terminal connected to the source line, and a drain terminal connected to the bit line via the second memory element; data of the second memory element is set in advance, and when reading out data of the second memory element, the control circuit causes the fourth transistor to be in a conductive state via the fifth word line; Semiconductor device.

12. 12. The semiconductor device according to claim 11, the first memory element and the second memory element are elements having a three-layer structure in which a fixed layer, a tunnel layer, and a free layer of a magnetic tunnel junction are stacked; Semiconductor device.

13. 13. The semiconductor device according to claim 12, the semiconductor device includes a column decoder connected to the plurality of bit lines in the memory cell region and selecting a bit line in accordance with a column address signal; the row decoder, the column decoder, and the control circuit are arranged outside the memory array; Semiconductor device.

14. 14. The semiconductor device according to claim 13, a row in which a plurality of second dummy cells connected to the third word line are arranged is arranged in a first dummy cell region between one of the pair of first sides and the memory cell region; a row in which a plurality of first dummy cells connected to the second word line are arranged and a row in which a plurality of first dummy cells connected to the fourth word line are arranged are arranged in a second dummy cell region between the other first side of the pair of first sides and the memory cell region; a row in which a plurality of third dummy cells connected to a fourth word line are arranged is arranged in the first dummy cell region and the second dummy cell region; Semiconductor device.

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