Manufacturing method for semiconductor device and semiconductor device

Abstract

To provide a manufacturing method for a semiconductor device and a semiconductor device capable of ensuring reliable write operations to MTJ-OTP memory cells by a user.SOLUTION: A write driver WTD writes one of two binary data to an OTP memory cell MCo using a boost voltage Vcp or a regulator voltage Vrg. An OTP voltage selection register REGoh controls the write driver WTD to select one of two voltages. Trimming registers REGtc and REGtr hold voltage setting values SV1 and SV2, each of which determines the magnitude of the two voltages. An OTP voltage trimming process involves writing one of the two voltage setting values SV1 and SV2 in a plurality of OTP memory cells MCo, one by one, as a trimming target and sequentially changing the voltage setting value to a high voltage direction until consecutive programming with the same voltage setting value is successful in N OTP memory cells MCo.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and relates to, for example, OTP (One Time Programmable) memory technology. [Background technology]

[0002] Non-Patent Document 1 shows a logic NVM cell that uses an anti-fuse programming mechanism to achieve high density and excellent data storage life. Non-Patent Document 2 describes writing trimming data and the like to an MTJ (Magnetoresistive Tunnel Junction)-OTP memory cell before WLCSP (Wafer Level Chip Scale Package). Non-Patent Document 3 describes a method for determining the logic of the cell current of an MTJ-OTP memory cell by using the cell current in a parallel state (I P ) and the cell current under dielectric breakdown condition (I BD ) is set between the [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] “Highly Reliable Anti-Fuse Technology in sub-16nm Technologies for Security Applications”, 2016 IEEE International Conference on Integrated Circuit Design and Technology (ICICDT) [Non-patent document 2] “Design Challenges and Solutions of Emerging Nonvolatile Memory for Embedded Applications”, 2021 IEEE International Electron Devices Meeting (IEDM) [Non-patent document 3] “33.1 A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity”, 2023 IEEE International Solid-State Circuits Conference (ISSCC) Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, there has been a growing demand for semiconductor devices such as MCUs (Micro Controller Units) or SoCs (System on Chips) to write, in addition to trimming data and rescue data, security information, boot information, and the like, into OTPs. In this case, a large capacity OTP of, for example, several tens to several hundreds of kB is required. To realize a large capacity OTP in a small area, it is beneficial to use MTJ-OTP memory cells as shown in Non-Patent Documents 2 and 3, instead of the antifuse-type OTP as shown in Non-Patent Document 1.

[0005] An MTJ-OTP memory cell is realized by using a portion of a memory cell in an STT-MRAM (Spin Torque Transfer Magnetic RAM) and causing dielectric breakdown of the MTJ element in that memory cell. When causing dielectric breakdown of the MTJ element, a voltage higher than that used in normal writing is applied. This can cause reliability issues such as voltage resistance. When using an MTJ-OTP memory cell to write trimming data, etc., writing to the OTP memory cell is performed during the STT-MRAM test process. Therefore, even if a defect occurs due to writing to the OTP memory cell, the defect can be detected during the test process, preventing defective products from being sold to users.

[0006] On the other hand, when using an MTJ-OTP memory cell to write security information, boot information, etc., the writing to the OTP memory cell is performed by the user. Therefore, it is necessary to guarantee that the user can write to the OTP memory cell reliably. Furthermore, it is necessary to guarantee that no defects occur due to the user's writing to the OTP memory cell.

[0007] The embodiments described below have been made in consideration of the above, and other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A semiconductor device manufacturing method according to one embodiment includes a wafer processing step of forming a nonvolatile memory on a semiconductor wafer and a wafer testing step of testing the semiconductor wafer. The wafer testing step includes an OTP voltage trimming step. The nonvolatile memory includes a plurality of word lines, a plurality of bit lines, a plurality of source lines, and a plurality of OTP memory cells, as well as a charge pump circuit, a voltage regulator circuit, a write driver, an OTP voltage selection register, a first trimming register, and a second trimming register. The plurality of OTP memory cells have MTJ elements that store binary data based on the presence or absence of dielectric breakdown. The charge pump circuit generates a boosted voltage by boosting a power supply voltage. The voltage regulator circuit generates a regulator voltage by lowering the power supply voltage. The write driver writes one of the binary data to the OTP memory cells by applying the boosted voltage or the regulator voltage between the bit line and the source line. The OTP voltage selection register causes the write driver to select either the boosted voltage or the regulator voltage. The first trimming register and the second trimming register hold a first voltage setting value that determines the magnitude of the boost voltage and a second voltage setting value that determines the magnitude of the regulator voltage, respectively. The OTP voltage trimming process is a process in which either the first voltage setting value or the second voltage setting value is used as the voltage setting value to be trimmed, and the voltage setting value is written to a plurality of OTP memory cells one by one, and the voltage setting value is sequentially changed toward a higher voltage until writing with the same voltage setting value is successful in N OTP memory cells consecutively. [Effects of the Invention]

[0009] According to the embodiment, it is possible to ensure reliable write operations to the MTJ-OTP memory cells by the user. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic diagram showing a configuration example of a semiconductor device according to an embodiment. [Figure 2]FIG. 2 is a circuit block diagram showing a schematic configuration example of the nonvolatile memory in FIG. [Figure 3] FIG. 3 is a schematic diagram showing an example of the configuration and operation of the memory cell in FIG. [Figure 4] FIG. 4 is a flow diagram showing an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] FIG. 5 is a circuit block diagram showing an example of the configuration of the main part of FIG. 2, focusing on the write operation to the OTP memory area. [Figure 6] FIG. 6 is a flowchart showing an example of detailed processing contents of the OTP voltage trimming step in FIG. [Figure 7] FIG. 7 is a schematic diagram showing a specific example of operation based on the flow shown in FIG. [Figure 8] FIG. 8 is a circuit diagram showing a detailed configuration example of the voltage regulator circuit in FIG. [Figure 9] FIG. 9 is a circuit diagram showing a schematic configuration example of the charge pump circuit in FIG. [Figure 10A] FIG. 10A is a schematic diagram showing an example of the layout configuration of the OTP memory area in FIG. [Figure 10B] FIG. 10B is a schematic diagram showing an example of the layout configuration of the OTP memory area in FIG. [Figure 11] FIG. 11 is a flow chart showing an example of detailed processing contents of the screening step in FIG. [Figure 12] FIG. 12 is a supplementary diagram for explaining part of the processing contents in FIG. [Figure 13] FIG. 13 is a circuit block diagram showing a modified configuration example of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0012] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0013] In the following embodiments, a p-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an n-channel MOSFET will be referred to as a pMOS transistor and an nMOS transistor, respectively. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings used to explain the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations will be omitted.

[0014] <Outline of semiconductor device> Fig. 1 is a schematic diagram showing an example of the configuration of a semiconductor device according to an embodiment. The semiconductor device DEV shown in Fig. 1 is, for example, an MCU or SoC configured on a single semiconductor chip. The semiconductor device DEV includes internal units connected to each other by a bus BS. The internal units include, for example, a processor PRC, a volatile memory RAM, a non-volatile memory NVM, and a peripheral circuit PERI.

[0015] The volatile memory RAM is, for example, SRAM (Static Random Access Memory). The nonvolatile memory NVM is STT-MRAM. The processor PRC includes a CPU (Central Processing Unit) and may also include a DSP (Digital Signal Processor) and a GPU (Graphics Processing Unit). The processor PRC executes a predetermined program stored in the STT-MRAM while using, for example, SRAM as a working memory.

[0016] The peripheral circuits PERI are circuits provided depending on the application of the semiconductor device DEV. Examples of the peripheral circuits PERI include a communication interface, an analog-to-digital converter, a digital-to-analog converter, various timer circuits, various analog circuits, etc. Although not shown, the semiconductor device DEV also includes a power supply circuit that generates an internal power supply from an external power supply, a clock generation circuit that generates an internal clock signal, etc.

[0017] Fig. 2 is a circuit block diagram showing a schematic configuration example of the nonvolatile memory NVM in Fig. 1. Fig. 3 is a schematic diagram showing a configuration example and an operation example of a memory cell in Fig. 2. The nonvolatile memory NVM shown in Fig. 2, specifically, an STT-MRAM, includes a memory array MARY, a word line control circuit WLC, J (=j+1) read / write control circuits RWC[0]-RWC[j], and a memory control circuit MCTL. The memory array MARY includes a plurality of word lines WL, a plurality of bit lines BL, a plurality of source lines SL, and a plurality of memory cells MC.

[0018] A plurality of bit lines BL are arranged intersecting with a plurality of word lines WL. A plurality of source lines SL are arranged parallel to the plurality of bit lines BL. A plurality of memory cells MC are arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL. Here, the memory array MARY includes a normal memory area ARn and an OTP memory area ARo. The normal memory area ARn has normal memory cells MCn, which are a part of the plurality of memory cells MC. The OTP memory area ARo has OTP memory cells MCo, which are another part of the plurality of memory cells MC.

[0019] However, the normal memory cells MCn and the OTP memory cells MCo are basically memory cells MC with the same configuration. As shown in Figure 3, the memory cells MC have a transistor switch TS and an MTJ element ME connected in series between one of a plurality of bit lines BL and one of a plurality of source lines SL. In this example, two bit lines BL share one source line SL.

[0020] The transistor switch TS is composed of, for example, an nMOS transistor. One end of the transistor switch TS is connected to a source line SL, and its on / off state is controlled by one of multiple word lines WL. One end of the MTJ element ME is connected to a bit line BL, and the other end is connected to the transistor switch TS. The MTJ element ME is composed of a free layer FL and a fixed layer PL made of a magnetic material, and an insulating layer ISL provided between the free layer FL and the fixed layer PL, which serves as a tunnel barrier film.

[0021] Here, in the normal memory cell MCn, AP (Anti-Parallel) write or P (Parallel) write is performed as a write operation. In AP write, for example, 2.0 V is applied to the word line WL, 0 V is applied to the bit line BL, and 1.5 V is applied to the source line SL. This causes a write current to flow from the source line SL to the bit line BL, and the magnetization directions of the fixed layer PL and the free layer FL become antiparallel (AP state). As a result, the MTJ element ME becomes a high-resistance state ("1" level state).

[0022] In a P write, for example, 1.6V is applied to the word line WL, 0V is set to the source line SL, and 1.4V is applied to the bit line BL. This causes a write current to flow from the bit line BL to the source line SL, and the magnetization directions of the fixed layer PL and the free layer FL become parallel (P state). As a result, the MTJ element ME becomes a low resistance state ("0" level state). In a read operation, for example, 1.1V is applied to the word line WL, 0V is set to the source line SL, and 0.2V is applied to the bit line BL. A read current of different magnitudes flows through the memory cell MC depending on whether it is in the AP state or the P state. Binary data is determined based on the difference in this read current.

[0023] On the other hand, in the OTP memory cell MCo, i.e., the MTJ-OTP memory cell, OTP writing is performed as a write operation. In OTP writing, for example, with 2.0 V applied to the word line WL, 0 V is applied to the source line SL, and 2.5 V is applied to the bit line BL. This causes a dielectric breakdown in the insulating layer ISL. As a result, the MTJ element ME enters an irreversible dielectric breakdown state (BD state) and an even lower resistance state ("0" level state).

[0024] The MTJ element ME in the OTP memory cell MCo stores binary data depending on whether or not this dielectric breakdown has occurred, i.e., whether it is in the AP state / P state or the BD state. Note that OTP writing requires a larger write current than AP writing or P writing. For this reason, the OTP memory cell MCo, more specifically, can be configured with multiple transistor switches TS connected in parallel, unlike the normal memory cell MCn.

[0025] 2, the memory control circuit MCTL receives a command signal CMD, an address signal ADR, and the like, and controls the entire nonvolatile memory NVM in accordance with the input contents. Specifically, the memory control circuit MCTL controls the memory cell MC designated by the address signal ADR in accordance with the write command signal CMD so that a J-bit data signal DT[0:j] (DTi[0:j]) can be written from the outside to the memory cell MC designated by the address signal ADR. In addition, the memory control circuit MCTL controls the memory cell MC designated by the address signal ADR in accordance with the read command signal CMD so that the J-bit data signal DT[0:j] (DTo[0:j]) can be read out to the outside.

[0026] The word line control circuit WLC controls activation / deactivation of multiple word lines WL. Specifically, the word line control circuit WLC has an address decoder ADEC and a word line driver WLD. The address decoder ADEC selects one of the multiple word lines WL based on an address signal ADR. The word line driver WLD activates the selected word line WL by applying a predetermined voltage, as described in FIG. 3, to the selected word line WL in accordance with the content of the command signal CMD. Note that the word line driver WLD may also apply a negative voltage to unselected word lines WL, as shown in FIG. 3.

[0027] J read / write control circuits RWC[0]-RWC[j] are provided corresponding to the J-bit data signals DT[0]-DT[j], respectively. Each of the read / write control circuits RWC[0]-RWC[j] drives a predetermined number of bit lines BL and source lines SL assigned to it. As a result, each of the read / write control circuits RWC[0]-RWC[j] controls read and write operations for memory cells MC connected to the predetermined number of bit lines BL and source lines SL.

[0028] Each of the read / write control circuits RWC[0]-RWC[j] includes a column selector CSEL, a sense amplifier SA, and a write driver WTD. Here, the read / write control circuit RWC[0] will be described as a representative example. The column selector CSEL selects one of a predetermined number of bit lines BL and source lines SL based on, for example, a signal from the address decoder ADEC, and thus the address signal ADR. The column selector CSEL then connects the selected bit line BL and source line SL to a global bit line GBL and a global source line GSL, respectively.

[0029] When writing the data signal DT[0] (DTi[0]), the write driver WTD applies a predetermined voltage between the selected bit line BL and source line SL via the global bit line GBL and global source line GSL, as described in Fig. 3. More specifically, the write driver WTD has a bit line driver that drives the bit line BL and a source line driver that drives the source line SL.

[0030] During a read operation of the data signal DT[0] (DTo[0]), the sense amplifier SA applies a predetermined voltage, as described in FIG. 3, between the selected bit line BL and source line SL via the global bit line GBL and global source line GSL. This causes a read current corresponding to the binary data to flow between the global bit line GBL and global source line GSL through the memory cell MC to be read. The sense amplifier SA amplifies the difference between the read current and a predetermined reference current, thereby determining the binary data in the data signal DT[0] (DTo[0]).

[0031] 2 shows an example of a configuration in which the normal memory area ARn and the OTP memory area ARo share the bit line BL. However, the nonvolatile memory NVM may have a configuration in which the normal memory area ARn and the OTP memory area ARo share the bit line BL. That is, the nonvolatile memory NVM may have, for example, a plurality of divided memory arrays MARY, and the OTP memory area ARo may be a part of the plurality of memory arrays MARY.

[0032] <Method of manufacturing a semiconductor device> 4 is a flow diagram showing an example of a method for manufacturing a semiconductor device according to an embodiment. The flow includes a wafer process step (step S101), a wafer test step (step S102), a packaging step (step S103), a shipping test step (step S104), a manufacturing step at a primary customer (step S105), a shipping test step (step S106), and a use step at an end customer (step S107). The flow from step S101 to step S104 is a flow by a semiconductor manufacturer. On the other hand, the flow from step S105 to step S107 is a flow by a user.

[0033] The wafer processing step (step S101) is a step of forming a plurality of semiconductor devices DEV, each including a nonvolatile memory NVM as shown in Figures 1 and 2, on a semiconductor wafer using various semiconductor manufacturing equipment. The wafer testing step (step S102) is a step of testing the semiconductor wafer on which the plurality of semiconductor devices DEV are formed, using a probe inspection device. The wafer testing step (step S102) includes an OTP voltage trimming step (step S102a) and a screening step (step S102b), which will be described in detail later.

[0034] The packaging process (step S103) is a process in which a semiconductor wafer is divided into a plurality of semiconductor devices DEV using a dicing device, and the semiconductor devices DEV determined to be non-defective in the wafer test process (step S102) are assembled into packages using an assembly device. The shipping test process (step S104) is a process in which the packaged semiconductor devices DEV are tested using a semiconductor tester. Then, the semiconductor devices DEV determined to be non-defective in the test are shipped to primary customers.

[0035] The manufacturing process at the primary customer (step S105) is a process of manufacturing an intermediate product by mounting the shipped semiconductor device DEV together with other components on a printed circuit board or the like. The shipping test process (step S106) is a process of testing the intermediate product. Then, intermediate products that are determined to be non-defective in the test are shipped to the end customer. The use process at the end customer (step S107) is a process of assembling a final product that includes the intermediate product and then using the final product as appropriate.

[0036] 2 is used to write trimming data, repair data, etc. The repair data is data for replacing a word line WL or a bit line BL determined to be defective in the wafer test process (step S102) with a redundant word line or bit line provided in the redundant area. The writing of the trimming data, repair data, etc. is performed in the wafer test process (step S102).

[0037] In the wafer test process, an arbitrary external power supply voltage Vcc can be applied to the semiconductor device DEV from the probe inspection device. This ensures the high voltage required for writing to the OTP memory area ARo. However, this writing, i.e., the application of a high voltage to the bit line BL, may cause defects, for example, in the normal memory area ARn. However, such defects can be detected in the wafer test process (step S102) or the shipping test process (step S104). This also prevents defective semiconductor devices DEV from being distributed to primary customers.

[0038] Meanwhile, in recent years, there has been a growing demand for writing, for example, security information and boot information in addition to trimming data and rescue data into the OTP memory area ARo. Specifically, the security information includes, for example, an "anti-rollback counter" for preventing rollback attacks that roll back versions of communication protocols, etc. The boot information includes, for example, a first stage boot loader (FSBL), which is the first code executed immediately after startup.

[0039] Such security information, boot information, etc. must be written not only in the wafer test process (step S102) but also in the manufacturing process at the primary customer (step S105) or the use process at the end customer (step S107). This can lead to the following three main problems. The first problem is that (A) unlike semiconductor manufacturers, users, i.e., primary customers or end customers, are not always able to apply an arbitrary external power supply voltage Vcc to the semiconductor device DEV. Therefore, there is a risk that the high voltage required for writing to the OTP memory area ARo cannot be secured. For example, in FIG. 3, if the external power supply voltage Vcc is lower than 2.5 V, the required high voltage cannot be secured.

[0040] As a second problem, assuming that (B) the user writes to the memory area ARo for OTP, the write voltage used at this time may not be appropriate. Therefore, considering manufacturing variations of semiconductor wafers, etc., it is required to determine in advance an appropriate write voltage that is neither too low nor too high. Summarizing (A) and (B), it is necessary for the semiconductor manufacturer to guarantee in advance a reliable write operation to the MTJ-OTP memory cell by the user.

[0041] As a third problem, (C) when the user writes to the OTP memory cell MCo, due to the application of a high voltage to the bit line BL, there is a possibility that a defect may occur in another memory cell MC that shares the OTP memory cell MCo and the bit line BL. For the user, unlike the semiconductor manufacturer, the occurrence of such a defect itself becomes a problem. Therefore, it is necessary for the semiconductor manufacturer to guarantee in advance that such a defect does not occur.

[0042] Regarding supplementary explanations for (A)-(C), first, in the wafer test process (step S102), the write voltage can be arbitrarily determined. Therefore, for example, by using a slightly excessive write voltage, etc., writing can be surely performed to the memory area ARo for OTP. And even if a defect occurs in, for example, the memory area ARn for normal use, etc., due to such a write voltage, it is possible to remedy or exclude it as a defective product. Therefore, as long as the semiconductor manufacturer writes to the memory area ARo for OTP, unlike the user, no particular problem occurs.

[0043] <Regarding the write operation to the memory area for OTP> Fig. 5 is a circuit block diagram showing an example of the configuration of the main parts of Fig. 2, focusing on the write operation to the OTP memory area ARo. Fig. 5 shows the OTP memory area ARo having OTP memory cells MCo, J read / write control circuits RWC[0]-RWC[j] that write to the OTP memory cells MCo, and a memory control circuit MCTL that controls the write operation. In this specification, the J read / write control circuits RWC[0]-RWC[j] are collectively referred to as the read / write control circuit RWC.

[0044] The memory control circuit MCTL includes an input buffer IBF, an OTP voltage selection register REGoh, a write count selection register REGom, a write controller MWC, a voltage regulator circuit VREG and a trimming register REGtr, and a charge pump circuit CP and a trimming register REGtc. The input buffer IBF includes, for example, J flip-flops FFi[0]-FFi[j]. This allows the input buffer IBF to latch a J-bit data signal DTi[0:j] input from the outside.

[0045] The charge pump circuit CP generates a boosted voltage Vcp by boosting the input power supply voltage, here the external power supply voltage Vcc. The trimming register (first trimming register) REGtc holds a voltage setting value (first voltage setting value) SV1 that determines the magnitude of the boosted voltage Vcp. The voltage regulator circuit VREG generates a regulator voltage Vrg by stepping down the external power supply voltage Vcc. The trimming register (second trimming register) REGtr holds a voltage setting value (second voltage setting value) SV2 that determines the magnitude of the regulator voltage Vrg. Details of the OTP voltage selection register REGoh, the write count selection register REGom, and the write controller MWC will be described later.

[0046] The memory area ARo has m+1 word lines WL[0]-WL[m]. The memory area ARo also has n+1 bit lines BL[0]-BL[n] and k+1 (=(n+1) / 2) source lines SL[0]-SL[k] for one read / write control circuit RWC. Accordingly, the memory area ARo has (m+1)*(n+1) OTP memory cells MCo for one read / write control circuit RWC. An example is n=31, k=15.

[0047] The read / write control circuit RWC includes a column selector CSEL, a write driver WTD, and a write logic circuit WLGC. As described in FIG. 2, the column selector CSEL selects one bit line BL from the n+1 bit lines BL[0]-BL[n]. The write driver WTD, here a bit line driver, applies a boost voltage Vcp or a regulator voltage Vrg to the selected bit line BL via the global bit line GBL.

[0048] That is, the write driver WTD applies the boost voltage Vcp or regulator voltage Vrg between the selected bit line BL and the source line SL while a source line driver (not shown) applies 0 V to the source line SL, thereby causing the write driver WTD to write one of the binary data, for example, a “0” level, to the OTP memory cell MCo connected to the selected word line WL and the selected bit line BL.

[0049] The write driver WTD, for example, includes an nMOS transistor MNcl for clamping and two pMOS transistors MPc and MPr for voltage selection. The nMOS transistor MNcl receives an external power supply voltage Vcc at its drain and a regulator voltage Vrg at its gate. This causes the nMOS transistor MNcl to output the regulator voltage Vrg from its source; more specifically, the regulator voltage Vrg that has been reduced by the threshold voltage.

[0050] The pMOS transistor MPc receives the boosted voltage Vcp at its source. The pMOS transistor MPr receives the regulator voltage Vrg from the nMOS transistor MNcl at its source. The pMOS transistors MPc and MPr are controlled to be on and off by enable signals ENc and ENr, respectively. The enable signals ENc and ENr are controlled so that only one of them becomes an "L" pulse signal having a predetermined write pulse width, i.e., an on-pulse signal. Alternatively, the enable signals ENc and ENr are both controlled to maintain an "H" level, i.e., an off level.

[0051] The write logic circuit WLGC has a flip-flop FFw and various logic gates that use the flip-flop FFw's output as input to control the enable signals ENc and ENr. When the flip-flop FFw holds a low level, the write logic circuit WLGC controls both the enable signals ENc and ENr to a high level, i.e., an off level. On the other hand, when the flip-flop FFw holds a high level, the write logic circuit WLGC controls one of the enable signals ENc and ENr to a low level, i.e., an on level, and the other to a high level, i.e., an off level.

[0052] Therefore, by appropriately controlling the value of the flip-flop FFw, the write logic circuit WLGC can control so that only one of the enable signals ENc and ENr becomes an “L” pulse signal. The write controller MWC in the memory control circuit MCTL appropriately controls the value of the flip-flop FFw based on the data signal DTi[0:j] latched in the input buffer IBF.

[0053] As a specific example, when the data signal DTi[0] is at a "0" level, the write controller MWC appropriately controls the value of the flip-flop FFw of the read / write control circuit RWC[0]. As a result, one of the enable signals ENc and ENr becomes an "L" pulse signal. On the other hand, when the data signal DTi[0] is at a "1" level, the write controller MWC writes an "L" level to the flip-flop FFw of the read / write control circuit RWC[0]. As a result, both the enable signals ENc and ENr maintain an "H" level.

[0054] Here, the OTP voltage selection register REGoh in the memory control circuit MCTL holds a selection value HVCC that determines the voltage supply source. The selection value HVCC determines whether the enable signal ENc or ​​ENr is controlled to be an "L" pulse signal. That is, the OTP voltage selection register REGoh causes the write driver WTD to select either the boost voltage Vcp or the regulator voltage Vrg via the write logic circuit WLGC.

[0055] In this example, when the selection value HVCC is at the "H" level, the enable signal ENr becomes a "L" pulse signal via the write logic circuit WLGC. Accordingly, the write driver WTD selects the regulator voltage Vrg. On the other hand, when the selection value HVCC is at the "L" level, the enable signal ENc becomes a "L" pulse signal via the write logic circuit WLGC. Accordingly, the write driver WTD selects the boosted voltage Vcp.

[0056] When the write driver WTD selects the regulator voltage Vrg, it can pass a large write current due to the external power supply voltage Vcc. In this case, the write drivers WTD in the J read / write control circuits RWC can simultaneously write to J OTP memory cells MCo. On the other hand, when the write driver WTD selects the boost voltage Vcp, it can only pass a certain amount of write current due to the current supply capacity of the charge pump circuit CP. In this case, the number of simultaneous writes is K, which is less than J, and can be, for example, K=4 or less.

[0057] However, the current supply capacity of the charge pump circuit CP can vary depending on the magnitude of the external power supply voltage Vcc input to the charge pump circuit CP. For example, when "Vcc < 2.0V", K = 1. On the other hand, when "2.0V < Vcc < 2.5V", for example, K = 2 or K = 4, etc. From the perspective of shortening the time required for writing, it is desirable to have as many simultaneous writes as possible.

[0058] Therefore, in FIG. 5, when the boosted voltage Vcp is selected, a write number selection register REGom is provided for selecting whether the number of simultaneous writes is 1 or K which is 2 or more. The write number selection register REGom holds a selection value MVCC that determines the number of simultaneous writes. For example, when "Vcc < 2.0V", the selection value MVCC is set to the "L" level. On the other hand, when "2.0V < Vcc < 2.5V", the selection value MVCC is set to the "H" level. Note that the OTP voltage selection register REGoh and the write number selection register REGom can also be configured by different bits within one register.

[0059] The selection values HVCC, MVCC are arbitrarily determined by the semiconductor manufacturer or the user. Specifically, in the wafer test process (step S102) shown in FIG. 4, for example, the semiconductor manufacturer can determine the selection values HVCC, MVCC via a probe inspection device and test terminals, etc. On the other hand, in the manufacturing process at the primary customer (step S105) or the usage process at the end customer (step S107), the user can determine the selection values HVCC, MVCC via, for example, a processor PRC and a bus BS.

[0060] At this time, the user may determine the selection values HVCC and MVCC based on the magnitude of the external power supply voltage Vcc to be used. As an example, when the external power supply voltage Vcc is somewhat higher than 2.5V, the user may set the selection value HVCC for the voltage supply source to the "H" level. On the other hand, when "2.0V < Vcc < 2.5V", the user may set the selection value HVCC for the voltage supply source to the "L" level and the selection value MVCC for the simultaneous write count to the "H" level, respectively. Also, when "Vcc < 2.0V", the user may set the selection value HVCC to the "L" level and the selection value MVCC to the "L" level, respectively.

[0061] The write controller MWC controls the simultaneous write count to the memory area ARo for OTP according to the selection values HVCC and MVCC. Specifically, when the selection value HVCC is at the "H" level, the write controller MWC controls, for example, the flip - flops FFw in J read - write control circuits RWC[0] - RWC[j] in parallel based on the J - bit data signal DTi[0:j].

[0062] On the other hand, when the selection value HVCC is at the "L" level, the write controller MWC controls the flip - flops FFw in K read - write control circuits RWC in parallel based on the corresponding K - bit data signal DTi. At this time, the write controller MWC determines the value of K based on the selection value MVCC.

[0063] As described above, in the configuration example of FIG. 5, a write driver WTD is provided that selectively applies a boosted voltage Vcp or a regulator voltage Vrg between the bit line BL and the source line SL. Thereby, (A) even for the user, a high voltage necessary for writing to the memory area ARo for OTP can be ensured. That is, even when it is not possible to ensure an external power supply voltage Vcc corresponding to the required write voltage, the necessary write voltage can be ensured using the charge pump circuit CP.

[0064] Also, by providing the OTP voltage selection register REGoh, the selection of the boost voltage Vcp or the regulator voltage Vrg can be made by user settings. As a specific example, when the user can ensure the desired external power supply voltage Vcc, it is advisable to select the regulator voltage Vrg for the light driver WTD. Thereby, since the number of simultaneous writes can be increased compared to the case of using the boost voltage Vcp, the time required for writing can be shortened. Also, by providing the write count selection register REGom, even when using the boost voltage Vcp, the time required for writing can be shortened as much as possible.

[0065] Furthermore, by providing the trimming registers REGtr and REGtc, (B) when the user writes to the memory area ARo for OTP, an appropriate write voltage required can be determined in advance. More specifically, in the OTP voltage trimming process (step S102a) shown in FIG. 4, as described below, by appropriately operating the trimming registers REGtr and REGtc, an appropriate write voltage is determined.

[0066] <Details of the OTP Voltage Trimming Process> FIG. 6 is a flowchart showing an example of the detailed processing content of the OTP voltage trimming process (step S102a) in FIG. 4. FIG. 7 is a schematic diagram showing a specific operation example based on the flow shown in FIG. 6. In the OTP voltage trimming process (step S102a), at least one of the first voltage setting value SV1 by the trimming register REGtc or the second voltage setting value SV2 by the trimming register REGtr is set as the voltage setting value SV to be trimmed. Also, in the OTP voltage trimming process, writes are performed one by one to a plurality of OTP memory cells MCo.

[0067] Then, as shown in Fig. 7, in N (N is an integer equal to or greater than 2) OTP memory cells MCo included in the plurality of OTP memory cells MCo, the voltage setting value SV is sequentially changed by +1 in the direction toward a higher voltage until consecutive writes with the same voltage setting value SV are successful. Specifically, as shown in Fig. 7, if OTP write fails, the voltage setting value SV is changed. Furthermore, to eliminate the influence of OTP write accumulation, the OTP address Ao, i.e., the OTP memory cell MCo to be written, is also changed.

[0068] On the other hand, if the OTP writing is successful, only the OTP address Ao is changed while the voltage setting value SV remains unchanged. This process is repeated until the OTP writing is successful N times in a row. If the OTP writing is successful N times in a row, a predetermined margin "+M" in the higher voltage direction is added to the current voltage setting value SV to ensure a more reliable success without excessively high voltage. The value of +M may be a small value, such as +1 or +2. The voltage setting value SV with this margin added becomes the trimming result of the first voltage setting value SV1 or the second voltage setting value SV2.

[0069] The flow shown in Fig. 6 is performed using, for example, a probe testing device. In Fig. 6, first, the probe testing device performs initial settings on the nonvolatile memory NVM (step S201). By the initial settings, the nonvolatile memory NVM is set, for example, to a test mode for trimming in which the voltage setting value SV can be arbitrarily changed. Furthermore, in the test mode for trimming, OTP writing is performed bit by bit using an OTP test area provided in the OTP memory area ARo. In this case, the OTP address Ao represents one of a plurality of OTP memory cells MCo, and this one is determined as the target OTP memory cell MCo.

[0070] As a specific example, assume that the region of multiple OTP memory cells MCo connected to word line WL[0] in FIG. 5 is an OTP test region. In this case, the probe testing device sequentially controls the address signals to the column selector CSEL while setting only one bit of data signal DTi[0] among the data signals DTi[0:j] to a "0" level. This allows OTP writing to be performed bit by bit on "n+1" OTP memory cells MCo assigned to the column selector CSEL in the read / write control circuit RWC[0]. After that, the same process can be performed while setting only the data signal DTi[1] to a "0" level.

[0071] 6, after step S201, the probe inspection device sets the voltage setting value SV to an initial value, for example, the minimum value, and sets the OTP address Ao to the initial value (step S202). Subsequently, the probe inspection device causes the nonvolatile memory NVM to perform 1-bit OTP writing (step S203). That is, the nonvolatile memory NVM uses the current voltage setting value SV to write to the target OTP memory cell MCo specified by the OTP address Ao.

[0072] Next, the probe test device causes the nonvolatile memory NVM to perform a read operation on the target OTP memory cell MCo, and then, based on the read data signal DT[0:j], the probe test device determines whether the write operation, i.e., the dielectric breakdown (BD) in the target OTP memory cell MCo has been successful (step S204).

[0073] If the determination result in step S204 is failure ("No"), the probe inspection device clears the number of consecutive successes it has stored (step S205). Then, the probe inspection device changes the voltage setting value SV toward a higher voltage (step S206), changes the OTP address Ao, i.e., the target OTP memory cell MCo, and returns to step S203 (step S207).

[0074] On the other hand, if the determination result in step S204 is success ("Yes"), the probe inspection device counts up the number of consecutive successes it holds (step S208). Then, if the number of consecutive successes does not reach the value of N (step S209: No), the probe inspection device changes the OTP address Ao, i.e., the target OTP memory cell MCo, and returns to step S203. Also, if the number of consecutive successes reaches the value of N (step S209: Yes), the probe inspection device adds a margin in the higher voltage direction to the current voltage setting value SV (step S210).

[0075] As a result, the probe inspection device determines the voltage setting value SV with the margin added as the trimming result of one of the first voltage setting value SV1 or the second voltage setting value SV2. The voltage setting value SV determined as the trimming result is written to a trimming data storage area provided in the OTP memory area ARo. During normal startup, the semiconductor device DEV loads the voltage setting value SV written to the trimming data storage area, i.e., the trimming value, into one of the trimming registers REGtc and REGtr.

[0076] By using the OTP voltage trimming process described above, it becomes possible to determine an appropriate write voltage required for (B) a user to write data to the OTP memory area ARo. That is, it becomes possible to determine an appropriate write voltage that is neither too low nor too high, taking into account manufacturing variations in semiconductor wafers, etc. This allows the semiconductor manufacturer to guarantee in advance that the user will be able to perform a reliable write operation to the MTJ-OTP memory cell. Note that the OTP voltage trimming process may be performed on all semiconductor devices DEV, or may be performed on a single or multiple semiconductor devices DEV defined for each semiconductor wafer.

[0077] <Details of the voltage regulator circuit and charge pump circuit> Fig. 8 is a circuit diagram showing a detailed configuration example of the voltage regulator circuit VREG in Fig. 5. The voltage regulator circuit VREG shown in Fig. 8 includes a reference voltage generation circuit VREFG, a regulator voltage generation circuit VRGG, and a selection circuit SELv2. The reference voltage generation circuit VREFG has a pMOS transistor MP1, a resistive voltage divider circuit RDIV, and an amplifier circuit AMP1.

[0078] The pMOS transistor MP1 and the resistive voltage divider circuit RDIV are connected in series between the external power supply voltage Vcc and the ground power supply voltage GND. The amplifier circuit AMP1 controls the gate voltage of the pMOS transistor MP1 so that the voltage at the fixed voltage node in the resistive voltage divider circuit RDIV matches the bandgap voltage Vbg. As a result, the resistive voltage divider circuit RDIV generates a plurality of reference voltages Vref whose voltage values ​​differ by a fixed step width from a plurality of, here "P+1", resistive voltage divider nodes. <p:0>The selection circuit SELv2 selects one of a plurality of reference voltages Vref based on the voltage setting value SV2 from the trimming register REGtr. <p:0>One of these is output as the reference voltage Vref2.

[0079] The regulator voltage generation circuit VRGG includes an nMOS transistor MNclR, a pMOS transistor MPrR, a current source CS, and an amplifier circuit AMP2. The nMOS transistor MNclR, the pMOS transistor MPrR, and the current source CS are connected in series between the external power supply voltage Vcc and the ground power supply voltage GND. The amplifier circuit AMP2 controls the gate voltage of the nMOS transistor MNclR so that the voltage of the node Ngbl, which serves as the drain of the pMOS transistor MPrR, matches the reference voltage Vref2 from the selection circuit SELv2. At the same time, the amplifier circuit AMP2 outputs this gate voltage as the regulator voltage Vrg.

[0080] The nMOS transistor MNclR and the pMOS transistor MPrR are replica transistors of the nMOS transistor MNcl and the pMOS transistor MPr, respectively, in the write driver WTD shown in Fig. 5. The current value of the current source CS is set to, for example, a write current value required for OTP writing to one OTP memory cell MCo.

[0081] Accordingly, the node Ngbl can be regarded as a replica node of the global bit line GBL. As a result, the amplifier circuit AMP2 outputs, as the regulator voltage Vrg, the gate voltage of the nMOS transistor MNcl required to make the voltage of the global bit line GBL equal to the reference voltage Vref2. Note that the pMOS transistor MPrR may be fixed on, for example.

[0082] 9 is a circuit diagram showing a schematic configuration example of the charge pump circuit CP in FIG. 5. The charge pump circuit CP shown in FIG. 9 includes a selection circuit SELv1, a charge pump control circuit CPCT, and a boost circuit BSTC in addition to the reference voltage generation circuit VREFG similar to that in FIG. 8. The reference voltage generation circuit VREFG generates a plurality of reference voltages Vref <p:0>The reference voltage generating circuit VREFG may be used in common with the voltage regulator circuit VREG shown in FIG.

[0083] The selection circuit SELv1 selects one of a plurality of reference voltages Vref based on the voltage setting value SV1 from the trimming register REGtc. <p:0>One of these is output as the reference voltage Vref1. Here, the trimming register REGtc includes two trimming registers REGtc1 and REGtc2. The trimming register (third trimming register) REGtc1 holds the voltage setting value SV1a when the selection value MVCC is at the "L" level, i.e., when the number of simultaneous writes is one. The trimming register (fourth trimming register) REGtc2 holds the voltage setting value SV1b when the selection value MVCC is at the "H" level, i.e., when the number of simultaneous writes is two or more, K.

[0084] The selection of the two voltage setting values ​​SV1a and SV1b from the two trimming registers REGtc1 and REGtc2 is performed by a selection circuit SELm. That is, the selection circuit SELm selects one of the two voltage setting values ​​SV1a and SV1b based on the selection value MVCC and outputs it as the voltage setting value SV1 to the selection circuit SELv1.

[0085] The boost circuit BSTC has a configuration in which, for example, multiple boost stages, each consisting of a diode and a capacitor, are cascaded. The boost circuit BSTC generates a boosted voltage Vcp by alternately repeating charging of a capacitor and boosting the capacitor. The charge pump control circuit CPCT controls, for example, activation / deactivation of the boost circuit BSTC so that the boosted voltage Vcp, more specifically, the voltage obtained by resistor-dividing the boosted voltage Vcp, matches the reference voltage Vref1 from the selection circuit SELv1.

[0086] To obtain the trimmed value of the voltage setting value SV2 shown in Fig. 8, for example, an external power supply voltage Vcc higher than 2.5 V may be applied, the selection value HVCC may be set to the "H" level, and the flow shown in Fig. 6 may be executed. To obtain the trimmed value of the voltage setting value SV1a shown in Fig. 9, for example, an external power supply voltage Vcc lower than 2.0 V may be applied, the selection value HVCC may be set to the "L" level, and the flow shown in Fig. 6 may be executed.

[0087] On one hand, in order to obtain the trimming value of the voltage setting value SV1b shown in FIG. 9, for example, an external power supply voltage Vcc of "2.0V < Vcc < 2.5V" is applied, and with the selected value HVCC set to the "L" level, a flow similar to the flow shown in FIG. 6 may be executed. In this case, the flow shown in FIG. 6 is executed using a write in units of K bits which is 2 or more, rather than a write in units of 1 bit.

[0088] However, in some cases, it is also possible to obtain any one of the three trimming values in the voltage setting values SV2, SV1a, and SV1b by conversion without executing the flow shown in FIG. 6 or a similar flow three times. That is, if the correlation relationship between the three trimming values is known in advance, for example, the remaining two trimming values can be calculated from one trimming value. The said correlation relationship can be obtained, for example, by using pre-evaluated statistical data or the like.

[0089] <Regarding the memory area for OTP> FIGS. 10A and 10B are schematic diagrams showing an example of the layout configuration of the memory area ARo for OTP in FIG. 5. In the example shown in FIG. 10A, as described in FIG. 2, a plurality of divided memory arrays are provided, and one of the plurality of memory arrays is the memory area ARo for OTP. The plurality of memory arrays are divided by the formation area of the sense amplifier SA or the formation area of the write driver WTD.

[0090] The memory area ARo for OTP includes an OTP user area ARoU and an OTP test area ARoT. The OTP user area ARoU is composed of a part of a plurality of OTP memory cells MCo and is an area that can be freely used by the user. On the other hand, the OTP test area ARoT is composed of another part of the plurality of OTP memory cells MCo and is the area used in the OTP voltage trimming process (step S102a) shown in FIG. 6.

[0091] Here, the OTP test area ARoT is located farther from the write driver WTD than the OTP user area ARoU. That is, the OTP user area ARoU is assigned to the word lines WL closer to the write driver WTD. On the other hand, the OTP test area ARoT is assigned to the word lines WL farther from the write driver WTD.

[0092] By using this arrangement, the write path WPt from the write driver WTD to the OTP test area ARoT is longer than the write path WPu to the OTP user area ARoU. Accordingly, the write voltage required for OTP writing to the OTP test area ARoT is higher than the write voltage required for OTP writing to the OTP user area ARoU. As a result, by using the write voltage determined in the OTP voltage trimming process (step S102a), the write operation to the OTP user area ARoU can be more reliably guaranteed.

[0093] 10A, the layout configuration example shown in FIG. 10B differs from that of FIG. 10A in that a switch SW for connecting the source line SL to the ground power supply voltage GND is provided in the region where the sense amplifier SA is formed. In this case, the write paths WPt and WPu include a path from the OTP memory cell MCo back to the write driver WTD, as in FIG. 10A, and a path from the OTP memory cell MCo toward the sense amplifier SA. Even in this case, the required write voltage is usually determined mainly based on the path from the write driver WTD toward the OTP memory cell MCo, so it is beneficial to use a similar layout.

[0094] In some cases, unused dummy word lines WL are provided in the memory array at the boundary with the write driver WTD and at the boundary with the sense amplifier SA. These dummy word lines WL can be allocated to the OTP test area ARoT. This reduces area overhead. In the example shown in FIGS. 10A and 10B, another of the multiple memory arrays is the normal memory area ARn described in FIG. 2. The normal memory area ARn, together with the OTP user area ARoU, constitutes the user area AR-U that can be freely used by the user.

[0095] <Screening process details> Fig. 11 is a flow diagram showing an example of detailed processing contents of the screening step (step S102b) in Fig. 4. Fig. 12 is a supplementary diagram for explaining part of the processing contents in Fig. 11. The flow shown in Fig. 11 is performed using, for example, a probe inspection device.

[0096] First, the probe testing device stores a voltage setting value SV2, which is the trimming result of the OTP voltage trimming process (step S102a), in the trimming register REGtr of the nonvolatile memory NVM (step S301). Next, based on an instruction from the probe testing device, the nonvolatile memory NVM writes to the OTP memory cells MCo in the OTP test area ARoT so that an OTP voltage based on the voltage setting value SV2, i.e., a write voltage, is applied to all bit lines BL to which the multiple OTP memory cells MCo are connected (step S302).

[0097] Here, Fig. 12 shows a layout configuration example similar to that of Fig. 10A. However, unlike Fig. 10A, here, a manufacturer area ARoM is further added to the OTP memory area ARo. For example, trimming data and the like are written in the manufacturer area ARoM. A voltage setting value SV2, which is the trimming result in the OTP voltage trimming step (step S102a), may be written in the manufacturer area ARoM, for example, before the screening step (step S102b).

[0098] 12, the voltage setting value SV2 resulting from the trimming is written to the area AR1. In this case, the boost voltage Vcp or regulator voltage Vrg determined in the OTP voltage trimming process (step S102a) has already been applied to the bit lines BL included in the area AR1, specifically, the bit lines BL to which the "0" level has been written. Therefore, the OTP memory cells MCo in the OTP test area ARoT to be written in step S302, and ultimately the bit lines BL, may be the OTP memory cells MCo in the area AR2 excluding the bit lines BL included in this area AR1. This allows the test time to be shortened.

[0099] Next, based on an instruction from the probe testing device, the nonvolatile memory NVM performs P write or AP write to the user memory cells MC connected to all bit lines BL to which the OTP memory cells MCo are connected (step S303). The user memory cells MC are the OTP memory cells MCo included in the OTP user area ARoU in FIG. 10A. Also, for example, as shown in FIG. 2, when the bit lines BL are shared between the OTP user area ARoU and the normal memory area ARn, the user memory cells MC also include the normal memory cells MCn in the normal memory area ARn.

[0100] Thereafter, the probe test equipment verifies that P read or AP read is possible by causing the nonvolatile memory NVM to perform a read operation (steps S304 and S305). In the example shown in Fig. 10A, the probe test equipment judges pass / fail regarding the reading of "0" level or "1" level from the OTP memory cell MCo in the OTP user area ARoU (step S305). If the judgment result is fail, the probe test equipment judges the screening result as fail (step S307).

[0101] On the other hand, if the determination result in step S305 is pass, the probe testing device determines the screening result as pass (step S306). By performing the processes in steps S302-S305, (C) it is possible to assure the user that when the user writes to the OTP memory cell MCo, a defect will not occur in other memory cells MC that share the bit line BL with the OTP memory cell MCo due to the application of a high voltage to the bit line BL.

[0102] <About modified examples> Fig. 13 is a circuit block diagram showing a modified configuration example of Fig. 5. In Fig. 13, a memory BIST (Built In Self Test) circuit MBIST is added to the configuration example shown in Fig. 5. The memory BIST circuit MBIST outputs a command signal CMD, an address signal ADR, and a data signal DTi[0:j] to the memory control circuit MCTL in response to, for example, a start signal from a probe testing device, and also inputs a data signal DTo[0:j] from the memory control circuit MCTL to determine pass / fail. Furthermore, the memory BIST circuit MBIST can operate the OTP voltage selection register REGoh, the write count selection register REGom, and the trimming registers REGtr and REGtc.

[0103] As a result, the memory BIST circuit MBIST performs a self-test on the nonvolatile memory NVM in place of the probe testing equipment. As one of the functions, the memory BIST circuit MBIST controls the sequence of the OTP voltage trimming process (step S102a) shown in FIG. 6. This enables each of the multiple semiconductor devices DEV formed on the semiconductor wafer to autonomously obtain its own optimum trimming value. The memory BIST circuit MBIST may also control the sequence of the screening process (step S102b) shown in FIG. 11.

[0104] By providing such a memory BIST circuit MBIST, it is possible to increase the number of semiconductor devices DEV that can be tested simultaneously within the limited resources of the probe testing equipment. As a result, it is possible to reduce test costs. The memory BIST circuit MBIST can be configured, for example, by a command generation circuit, an address generation circuit, a data generation circuit, a data judgment circuit, and a sequencer circuit that controls these circuits.

[0105] <Major effects of each embodiment> As described above, in the method according to the embodiment, either the regulator voltage obtained by stepping down the power supply voltage or the boosted voltage obtained by stepping up the power supply voltage can be selectively used as the write voltage to the MTJ-OTP memory cell. Furthermore, the optimum values ​​of these voltages can be determined by the OTP voltage trimming process performed by the semiconductor manufacturer. This ensures reliable write operations to the OTP memory cells by the user. Furthermore, in the method according to the embodiment, a screening process is provided after the OTP voltage trimming process. This ensures that no defects occur due to write operations to the OTP memory cells by the user.

[0106] The invention made by the inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit of the invention. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0107] ARn Normal memory area Memory area for ARo OTP ARoT OTP Test Area ARoU OTP user area BL bit line CP Charge pump circuit DEV Semiconductor device MCo OTP memory cell NVM Non-volatile memory (MRAM) REGoh OTP voltage selection register REGom Write count selection register SL Source Line SV voltage setting value VREG Voltage regulator circuit Vcp boost voltage Vrg regulator voltage WL Word Line WTD Light Driver

Claims

1. a wafer process step of forming a nonvolatile memory on a semiconductor wafer; a wafer testing step of testing the semiconductor wafer; A method for manufacturing a semiconductor device having The nonvolatile memory includes: a plurality of word lines; a plurality of bit lines arranged to intersect with the plurality of word lines; a plurality of source lines arranged in parallel with the plurality of bit lines; a plurality of OTP (One Time Programmable) memory cells, each of which is disposed at an intersection of the plurality of word lines and the plurality of bit lines, and each of which has a transistor switch whose on / off state is controlled by one of the plurality of word lines and a magnetoresistive tunnel junction (MTJ) element that stores binary data depending on the presence or absence of dielectric breakdown; a charge pump circuit that generates a boosted voltage by boosting a power supply voltage; a voltage regulator circuit that generates a regulator voltage by stepping down the power supply voltage; a write driver that writes one of the binary data into one of the plurality of OTP memory cells by applying the boost voltage or the regulator voltage between one of the plurality of bit lines and one of the plurality of source lines; an OTP voltage selection register that causes the write driver to select either the boosted voltage or the regulator voltage; a first trimming register that holds a first voltage setting value that determines the magnitude of the boosted voltage; a second trimming register that holds a second voltage setting value that determines the magnitude of the regulator voltage; is formed, the wafer test process includes an OTP voltage trimming process, The OTP voltage trimming step is a step of writing one of the first voltage setting value or the second voltage setting value into the plurality of OTP memory cells one by one, using one of the first voltage setting value or the second voltage setting value as a voltage setting value to be trimmed, and sequentially changing the voltage setting value toward a higher voltage until writing with the same voltage setting value is successively successful in N OTP memory cells, which is two or more OTP memory cells included in the plurality of OTP memory cells. A method for manufacturing a semiconductor device.

2. 2. The method for manufacturing a semiconductor device according to claim 1, The OTP voltage trimming process includes: (A) setting the voltage setting value to an initial value and setting one of the plurality of OTP memory cells as a target OTP memory cell; (B) writing to the target OTP memory cell using the voltage setting value; (C) determining whether writing to the target OTP memory cell has been successful; (D1) if the determination result in step (C) is failure, clear the number of consecutive successes, change the voltage setting value toward a higher voltage, change the target OTP memory cell, and return to step (B); (D2) if the determination result in step (C) is successful, count up the number of consecutive successes, and if the number of consecutive successes does not reach N, change the target OTP memory cell and return to step (B); having A method for manufacturing a semiconductor device.

3. 3. The method for manufacturing a semiconductor device according to claim 2, Furthermore, (E) when the number of consecutive successes reaches N in step (D2), adding a margin in the direction of a higher voltage to the current voltage setting value, and determining the voltage setting value to which the margin has been added as a trimming result of either the first voltage setting value or the second voltage setting value. A method for manufacturing a semiconductor device.

4. 3. The method for manufacturing a semiconductor device according to claim 2, A memory BIST (Built In Self Test) circuit that controls the sequence of the OTP voltage trimming process is formed in the nonvolatile memory. A method for manufacturing a semiconductor device.

5. 2. The method for manufacturing a semiconductor device according to claim 1, The nonvolatile memory includes: an OTP user area that is configured as a part of the plurality of OTP memory cells and that is an area that can be freely used by a user; an OTP test area configured by another part of the plurality of OTP memory cells and used in the OTP voltage trimming process; A normal memory area is an area that is made up of normal memory cells that hold binary data in a P (Parallel) state or an AP (Anti-Parallel) state and that can be used freely by the user; is formed, A method for manufacturing a semiconductor device.

6. 6. The method for manufacturing a semiconductor device according to claim 5, the OTP test area is formed at a position farther from the write driver than the OTP user area; A method for manufacturing a semiconductor device.

7. 6. The method for manufacturing a semiconductor device according to claim 5, the wafer testing step further includes a screening step performed after the OTP voltage trimming step, The screening step includes: (F) writing to the OTP memory cells in the OTP test area so that the boost voltage or the regulator voltage determined in the OTP voltage trimming process is applied to all bit lines to which the plurality of OTP memory cells are connected; (G) after the step (F), a step of performing P write or AP write on the plurality of memory cells that are connected to all of the bit lines and are included in the OTP user area or the normal memory area, and verifying that P read or AP read can be performed; having A method for manufacturing a semiconductor device.

8. 8. The method for manufacturing a semiconductor device according to claim 7, In the step (F), the bit lines to which the boost voltage or the regulator voltage determined in the OTP voltage trimming process has been applied before the step (F) are excluded from the write target. A method for manufacturing a semiconductor device.

9. 2. The method for manufacturing a semiconductor device according to claim 1, The OTP voltage trimming process includes: a step of setting the first voltage setting value as the trimming target; a step of setting the second voltage setting value as the trimming target; having A method for manufacturing a semiconductor device.

10. A word line; a plurality of bit lines arranged to intersect the word lines; a plurality of source lines arranged in parallel with the bit lines; a plurality of OTP (One Time Programmable) memory cells each having a transistor switch whose on / off state is controlled by the word line and a magnetoresistive tunnel junction (MTJ) element that stores binary data depending on the presence or absence of dielectric breakdown, the memory cells being arranged at intersections of the word line and the plurality of bit lines; a charge pump circuit that generates a boosted voltage by boosting a power supply voltage; a voltage regulator circuit that generates a regulator voltage by stepping down the power supply voltage; a write driver that writes one of the binary data into one of the plurality of OTP memory cells by applying the boost voltage or the regulator voltage between one of the plurality of bit lines and one of the plurality of source lines; an OTP voltage selection register that causes the write driver to select either the boosted voltage or the regulator voltage; Equipped with Semiconductor device.

11. 11. The semiconductor device according to claim 10, further comprising: a first trimming register that holds a first voltage setting value that determines the magnitude of the boosted voltage; a second trimming register that holds a second voltage setting value that determines the magnitude of the regulator voltage; Equipped with Semiconductor device.

12. 12. The semiconductor device according to claim 11, Further, a write number selection register is provided for selecting whether the number of simultaneous writes to the plurality of OTP memory cells is one or K, which is two or more, when the boost voltage is selected; The first trimming resistor comprises: a third trimming register that holds the first voltage setting value when the number of simultaneous writes is one; a fourth trimming register that holds the first voltage setting value when the number of simultaneous writes is K; Contains, Semiconductor device.

13. 13. The semiconductor device according to claim 12, the write driver simultaneously writes data to J OTP memory cells, which is greater than the K OTP memory cells, when the regulator voltage is selected by the OTP voltage selection register; Semiconductor device.

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