Pulse width modulation circuit and motor drive unit

Abstract

To provide a pulse width modulation circuit which can reduce an influence of glitch noise to be generated in an internal signal by a delay time to be generated in a reference signal from a control object.SOLUTION: A pulse width modulation circuit 10B comprises: an amplifier circuit 11 which generates a first amplification signal Vg1 from a reference signal Vs from a control object; a mask unit 18 which generates a second amplification signal Vg2 obtained by masking a predetermined period T1 of the first amplification signal Vg1; an integration circuit 14 which generates an error signal Verr from the second amplification signal Vg2 and a command signal Vin; and a pulse width modulation signal generation unit 16 which generates a pulse width modulation signal Vp to be supplied to the control object from the error signal Verr and a triangular wave signal Vt.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a pulse width modulation circuit and a motor drive device. [Background technology]

[0002] 2. Description of the Related Art Motor driving devices for driving motors in hard disk drives and the like are known.

[0003] [overview] In a motor drive device, for example, a motor control circuit controls the operation of the motor drive circuit that drives the motor based on a pulse-width modulation signal supplied from a pulse-width modulation circuit. The pulse-width modulation circuit generates a pulse-width modulation signal based on a command signal and a reference signal fed back from the motor drive circuit that is the object of control. Due to the influence of the propagation delay time of the motor control circuit, a delay time occurs between the reference signal of the motor drive circuit and the pulse-width modulation signal of the pulse-width modulation circuit. The delay time of the reference signal causes glitch noise to occur in the internal signal of the pulse-width modulation circuit.

[0004] An object of the present disclosure is to provide a pulse width modulation circuit and a motor drive device that can reduce the influence of glitch noise that occurs in an internal signal due to a delay time that occurs in a reference signal from a controlled object.

[0005] In order to solve the above-mentioned problems, one aspect of the present disclosure is a pulse width modulation circuit including an amplifier circuit, a masking unit, an integrating circuit, and a pulse width modulation signal generating unit. The amplifier circuit generates a first amplified signal from a reference signal from a controlled object. The masking unit generates a second amplified signal by masking a predetermined period of the first amplified signal. The integrating circuit generates an error signal from the second amplified signal and a command signal. The pulse width modulation signal generating unit generates a pulse width modulation signal to be supplied to the controlled object from the error signal and a triangular wave signal.

[0006] Another aspect of the present disclosure is a motor drive device including a motor drive circuit, a motor control circuit, and a pulse-width modulation circuit. The motor drive circuit drives a motor. The motor control circuit controls the motor drive circuit. The pulse-width modulation circuit supplies a pulse-width modulation signal to the motor control circuit. The pulse-width modulation circuit includes an amplifier circuit, a masking unit, an integrating circuit, and a pulse-width modulation signal generating unit. The amplifier circuit generates a first amplified signal from a reference signal from a controlled object. The masking unit generates a second amplified signal by masking a predetermined period of the first amplified signal. The integrating circuit generates an error signal from the second amplified signal and a command signal. The pulse-width modulation signal generating unit generates a pulse-width modulation signal to be supplied to the controlled object from the error signal and a triangular wave signal. The motor control circuit controls the motor drive circuit based on the pulse-width modulation signal supplied from the pulse-width modulation circuit. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a circuit diagram showing an example of the configuration of a motor drive device according to a comparative example and an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a pulse width modulation circuit according to a comparative example. [Figure 3] FIG. 3 is a time chart showing simulation results of the waveforms of the signals when the command signal Vin=0.75 V and the frequency of the triangular wave generator=20 kHz in the pulse width modulation circuit according to the comparative example. [Figure 4] FIG. 4 is a time chart showing simulation results of the waveforms of the signals when the command signal Vin=1.35 V and the frequency of the triangular wave generator=20 kHz in the pulse width modulation circuit according to the comparative example. [Figure 5] FIG. 5 is a circuit diagram showing an example of the configuration of a pulse width modulation circuit according to an embodiment. [Figure 6] FIG. 6 is a time chart showing the relationship between the pulse width modulation signal and the mask signal in the pulse width modulation circuit according to the embodiment. [Figure 7]FIG. 7 is a time chart showing simulation results of the waveforms of the signals when the command signal Vin=0.75 V and the frequency of the triangular wave generator=20 kHz in the pulse width modulation circuit according to the embodiment. [Figure 8] FIG. 8 is a time chart showing simulation results of the waveforms of the signals when the command signal Vin=1.35 V and the frequency of the triangular wave generator=20 kHz in the pulse width modulation circuit according to the embodiment.

[0008] [Detailed explanation] Hereinafter, a pulse width modulation circuit and a motor drive device according to an embodiment will be described in detail with reference to the drawings. However, it should be noted that the drawings are schematic.

[0009] The embodiments described below are comprehensive or specific examples. The numerical values, shapes, materials, components, installation positions, and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the scope of the present disclosure. Furthermore, among the components in the following embodiments, components that are not recited in the independent claims that represent the highest concepts are described as optional components. Furthermore, the dimensional proportions in the drawings are exaggerated for the sake of explanation and may differ from the actual proportions. Furthermore, the following embodiments and their variations may include similar components, and the same reference numerals will be used to denote similar components, and redundant explanations will be omitted.

[0010] (Comparative Example) Before describing a motor drive device 1B and a pulse width modulation circuit 10B according to an embodiment, the configurations of a motor drive device 1A and a pulse width modulation circuit 10A according to a comparative example will be described with reference to Figures 1 and 2. Figure 1 is a circuit diagram showing an example of the configuration of a motor drive device 1A according to the comparative example. Figure 2 is a circuit diagram showing an example of the configuration of a pulse width modulation circuit 10A according to the comparative example.

[0011] 1, a motor drive device 1A according to the comparative example drives a motor M1, such as a three-phase DC motor, in accordance with the value of a command signal Vin. The motor drive device 1A according to the comparative example includes a pulse width modulation circuit 10A according to the comparative example, a motor control circuit 20, and a motor drive circuit 30. The motor control circuit 20 and the motor drive circuit 30 are controlled by the pulse width modulation circuit 10A.

[0012] The pulse width modulation circuit 10A receives a command signal Vin from the variable DC power supply 2 at its VIN terminal, and a current sense signal Vs, which is a reference signal, from the motor drive circuit 30 at its SENSE terminal. The GND terminal of the pulse width modulation circuit 10A is connected to the ground (reference potential). The pulse width modulation circuit 10A outputs a pulse width modulation signal Vp, generated based on the command signal Vin and the current sense signal Vs, to its DIR terminal. The pulse width modulation signal Vp is a pulse-shaped signal whose amplitude is either an L level (e.g., 0 V) ​​or an H level (e.g., 3.3 V) and whose polarity is either low or high.

[0013] The motor control circuit 20 and the motor drive circuit 30 are configured, for example, by a single external semiconductor integrated circuit, and an existing product can be used. Alternatively, the motor control circuit 20 and the motor drive circuit 30 may each be configured by separate semiconductor integrated circuits. The motor control circuit 20 controls the motor drive circuit 30 in response to the pulse-width modulation signal Vp generated by the pulse-width modulation circuit 10A.

[0014] The motor drive circuit 30 includes, for example, a first series circuit 31 of transistors Q1 and Q2, a second series circuit 32 of transistors Q3 and Q4, and a third series circuit 33 of transistors Q5 and Q6. A power supply voltage VCC is input to first main electrodes of transistors Q1, Q3, and Q5. A power supply terminal of motor M1 is connected to a connection point between the second main electrode of transistor Q1 and the first main electrode of transistor Q2, a connection point between the second main electrode of transistor Q3 and the first main electrode of transistor Q4, and a connection point between the second main electrode of transistor Q5 and the first main electrode of transistor Q6. The second main electrodes of transistors Q2, Q4, and Q6 are connected to ground via a current detection resistor Ri. A current sense signal Vs, which is a reference signal corresponding to the current flowing through current detection resistor Ri, is output to a SENSE terminal of the motor drive circuit 30 and fed back to the SENSE terminal of pulse-width modulation circuit 10A. The transistors Q1 to Q6 are configured by power transistors such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), for example.

[0015] As shown in FIG. 2, a pulse width modulation circuit 10A according to the comparative example includes an amplifier circuit 11, an integrating circuit 14, a comparator 16, and a triangular wave generator 17.

[0016] The amplifier circuit 11 includes resistors R1 to R4, a polarity changeover switch 12, and a first operational amplifier 13. Each of the resistors R1 to R4 is a variable resistor, but they do not have to be variable resistors. A DC voltage VCA is input to the power supply terminal of the first operational amplifier 13. An inverting input terminal − of the first operational amplifier 13 is connected to the output terminal of the first operational amplifier 13 via a resistor R4 that serves as a feedback resistor. A non-inverting input terminal + of the first operational amplifier 13 is connected to a first regulated voltage Vref1 via a resistor R3.

[0017] The polarity changeover switch 12 includes a first switch SW1 and a second switch SW2. The connections of the first switch SW1 and the second switch SW2 are switched when the polarity of the pulse-width modulated signal Vp is inverted. That is, when the pulse-width modulated signal Vp is at an L level, the L terminals of the first switch SW1 and the second switch SW2 on the input side of the polarity changeover switch 12 are turned on and the H terminals are turned off. On the other hand, when the pulse-width modulated signal Vp is at an H level, the H terminals of the first switch SW1 and the second switch SW2 on the input side of the polarity changeover switch 12 are turned on and the L terminals are turned off.

[0018] On the input side of the polarity changeover switch 12, the L terminal of the first switch SW1 and the H terminal of the second switch SW2 are connected to the SENSE terminal via a resistor R1, and the H terminal of the first switch SW1 and the L terminal of the second switch SW2 are connected to the GND terminal via a resistor R2. On the output side of the polarity changeover switch 12, the first switch SW1 is connected to the inverting input terminal (-) of a first operational amplifier 13, and the second switch SW2 is connected to the non-inverting input terminal (+) of the first operational amplifier.

[0019] When the pulse-width modulated signal Vp is at L level, the current sense signal Vs is input via resistor R1 to the inverting input terminal - of the first operational amplifier 13. The non-inverting input terminal + of the first operational amplifier 13 is connected to ground via resistor R2 and to a first regulated voltage Vref1 via resistor R3. When the pulse-width modulated signal Vp is at L level, the amplifier circuit 11 operates as an inverting amplifier circuit that inverts and amplifies the current sense signal Vs and shifts it by a predetermined voltage.

[0020] On the other hand, when the pulse-width modulated signal Vp is at H level, the inverting input terminal - of the first operational amplifier 13 is connected to ground via resistor R2. The non-inverting input terminal + of the first operational amplifier 13 is connected to the current sense signal Vs via resistor R1 and to the first regulated voltage Vref1 via resistor R3. When the pulse-width modulated signal Vp is at H level, the amplifier circuit 11 operates as a non-inverting amplifier circuit that non-inverts and amplifies the current sense signal Vs and shifts it by a predetermined voltage.

[0021] Through this operation, the amplifier circuit 11 converts the sawtooth waveform current sense signal Vs into a triangular waveform first amplified signal Vg1. The amplifier circuit 11 also converts the current sense signal Vs into the first amplified signal Vg1 using an amplification factor and a voltage shift amount that are determined according to the resistance values ​​of the resistors R1 to R4 and the first regulated voltage Vref1. Once the desired amplification factor and voltage shift amount are determined, appropriate values ​​for the resistance values ​​of the resistors R1 to R4 and the first regulated voltage Vref1 can be selected in advance through calculation, circuit simulation, or the like.

[0022] The integrator circuit 14 includes a second operational amplifier 15, a capacitor C1 connected between the inverting input terminal and the output terminal of the second operational amplifier 15, and resistors R0 and R5 connected to the inverting input terminal of the second operational amplifier 15. A DC voltage VCA is input to the power supply terminal of the second operational amplifier 15.

[0023] The command signal Vin is input to the inverting input terminal (-) of the second operational amplifier 15 via resistor R0, and the first amplified signal Vg1 output from the amplifier circuit 11 is input to the non-inverting input terminal (+) of the second operational amplifier 15 via resistor R5. The second regulated voltage Vref2 is input to the non-inverting input terminal (+). The integrator circuit 14 integrates the current Ic = (Vin / R0 + Vg1 / R5) flowing from the junction of resistors R0 and R5 to capacitor C1, and outputs an error signal Verr with the DC voltage component shifted by the amount of the second regulated voltage Vref2. The error signal Verr is Verr = -1 / C1 · ∫Icdt + Vref2 = -1 / C1 · ∫(Vin / R0 + Vg1 / R5)dt + Vref2. The integrator circuit 14 converts the triangular waveform of the first amplified signal Vg1 into a parabolic (quadratic function) error signal Verr.

[0024] The error signal Verr is input to the positive input terminal + of the comparator 16. The triangular wave signal Vt generated by the triangular wave generator 17 is input to the negative input terminal − of the comparator 16. The triangular wave signal Vt generated by the triangular wave generator 17 is variable, for example, between 20 and 100 kHz, with a maximum amplitude voltage VH of 1.2 V and a minimum amplitude voltage VL of 0.3 V. The comparator 16 generates a pulse-width modulated signal Vp from the error signal Verr input to the positive input terminal + and the triangular wave signal Vt input to the negative input terminal −. The pulse-width modulated signal Vp generated by the comparator 16 is input to the motor control circuit 20 and the polarity changeover switch 12.

[0025] Next, the operation of a pulse-width modulation circuit 10A according to a comparative example will be described with reference to Figures 3 and 4. Figure 3 is a time chart showing simulation results of the waveforms of each signal in the pulse-width modulation circuit 10A according to the comparative example when the command signal Vin is 0.75 V and the frequency of the triangular wave generator 17 is 20 kHz. Figure 4 is a time chart showing simulation results of the waveforms of each signal in the pulse-width modulation circuit 10A according to the comparative example when the command signal Vin is 1.35 V and the frequency of the triangular wave generator 17 is 20 kHz. Figures 3 and 4 show, from top to bottom, the waveforms of the first amplified signal Vg1, the error signal Verr, the current sense signal Vs, and the pulse-width modulated signal Vp.

[0026] The pulse-width modulated signal Vp generated by the pulse-width modulation circuit 10A is input to the motor control circuit 20, which drives the motor drive circuit 30 in accordance with the pulse-width modulated signal Vp. The motor drive circuit 30 outputs a current sense signal Vs that is synchronized with the pulse-width modulated signal Vp and has an amplitude that corresponds to the drive state of the motor drive circuit 30. This current sense signal Vs is fed back to the SENSE terminal of the pulse-width modulation circuit 10A and input to the amplifier circuit 11.

[0027] In amplifier circuit 11, polarity changeover switch 12 switches the connections between the L terminal and the H terminal of first switch SW1 and second switch SW2 on the input side when the polarity of pulse-width modulated signal Vp is inverted. When pulse-width modulated signal Vp is at L level, first amplified signal Vg1 is a signal obtained by inverting and amplifying current sense signal Vs, and when pulse-width modulated signal Vp is at H level, it is a signal obtained by non-inverting and amplifying current sense signal Vs. Amplifier circuit 11 converts current sense signal Vs, which has a sawtooth waveform, into first amplified signal Vg1, which has a triangular waveform.

[0028] At this time, current sense signal Vs experiences a delay time Δ of approximately 1.2 μs relative to pulse-width modulated signal Vp due to the propagation delay time of motor control circuit 20 and motor drive circuit 30, which are integrated circuits. Therefore, glitch noise occurs in first amplified signal Vg1, the output signal of amplifier circuit 11, during delay time Δ when the polarity of pulse-width modulated signal Vp reverses. Similarly, glitch noise also causes signal disturbance in parabolic error signal Verr, generated by integrator circuit 14 from triangular-wave first amplified signal Vg1, during delay time Δ when the polarity of pulse-width modulated signal Vp reverses. This signal disturbance in error signal Verr also causes disturbance in the pulse width of pulse-width modulated signal Vp.

[0029] For this reason, it is desirable to be able to reduce the influence of glitch noise that occurs in the first amplified signal Vg1, which is the output signal of the amplifier circuit 11.

[0030] (Embodiment) Next, the configurations of a motor drive device 1B and a pulse width modulation circuit 10B according to an embodiment will be described with reference to Figures 1, 5, and 6. Figure 1 is a circuit diagram showing an example of the configuration of a motor drive device 1B according to an embodiment. Figure 5 is a circuit diagram showing an example of the configuration of a pulse width modulation circuit 10B according to an embodiment. Figure 6 is a time chart showing the relationship between a pulse width modulation signal Vp and a mask signal Vm in the pulse width modulation circuit 10B according to an embodiment.

[0031] 1, the motor drive device 1B according to the embodiment differs from the motor drive device 1A according to the comparative example only in that the pulse width modulation circuit 10A according to the comparative example is replaced with the pulse width modulation circuit 10B according to the embodiment, and the other parts are the same. Therefore, a detailed description of the configuration of the motor drive device 1B according to the embodiment will be omitted.

[0032] 5, the pulse width modulation circuit 10B according to the embodiment differs from the pulse width modulation circuit 10A according to the comparative example only in that a switch 18 serving as a masking unit is provided between the amplifier circuit 11 and the integrating circuit 14. The configuration of other parts is common between the pulse width modulation circuit 10B according to the embodiment and the pulse width modulation circuit 10A according to the comparative example. Therefore, a description of the circuit configuration of the amplifier circuit 11 and the integrating circuit 14 and a description of the operation up to the point where the amplifier circuit 11 outputs the first amplified signal Vg1 as an output signal will be omitted.

[0033] The first amplified signal Vg1 from the amplifier circuit 11 is input to the switch 18. The switch 18 is turned on when the mask signal Vm is at H level, and turned off when the mask signal Vm is at L level. As a result, the switch 18 outputs a second amplified signal Vg2 in which the first amplified signal Vg1 is masked only during the period when the mask signal Vm is at L level.

[0034] 6, the mask signal Vm goes low for a mask period T1 after the polarity of the pulse-width modulated signal Vp is inverted, turning the switch 18 off, and goes high for the rest of the period, turning the switch 18 on. For example, when the delay time Δ is approximately 1.2 μs, the mask period T1 may be set to a period slightly longer than the delay time Δ, for example, 1.5 μs. With this configuration, the switch 18 outputs the second amplified signal Vg2, which is a signal obtained by masking the first amplified signal Vg1 during the mask period T1 after the polarity of the pulse-width modulated signal Vp is inverted.

[0035] The inverting input terminal (-) of the second operational amplifier 15 of the integrator circuit 14 is connected to the command signal Vin via resistor R0 and to the second amplified signal Vg2 output from the switch 18 via resistor R5. The non-inverting input terminal (+) of the second operational amplifier 15 is connected to the second regulated voltage Vref2. The integrator circuit 14 integrates the current Ic = (Vin / R0 + Vg2 / R5) flowing from the junction of resistors R0 and R5 to capacitor C1 and outputs the resulting error signal Verr, with the DC voltage component shifted by the amount of the second regulated voltage Vref2. The error signal Verr is Verr = -1 / C1 · ∫Icdt + Vref2 = -1 / C1 · ∫(Vin / R0 + Vg2 / R5)dt + Vref2. The integrator circuit 14 converts the triangular waveform of the second amplified signal Vg2 into a parabolic (quadratic function) error signal Verr.

[0036] The error signal Verr is input to the positive input terminal + of the comparator 16. The triangular wave signal Vt generated by the triangular wave generator 17 is input to the negative input terminal − of the comparator 16. The triangular wave signal Vt generated by the triangular wave generator 17 is variable, for example, between 20 and 100 kHz, with a maximum amplitude voltage VH of 1.2 V and a minimum amplitude voltage VL of 0.3 V. The comparator 16 generates a pulse-width modulated signal Vp from the error signal Verr input to the positive input terminal + and the triangular wave signal Vt input to the negative input terminal −. The pulse-width modulated signal Vp generated by the comparator 16 is input to the motor control circuit 20 and the polarity changeover switch 12.

[0037] Next, the operation of the pulse width modulation circuit 10B according to this embodiment will be described with reference to Figures 7 and 8. Figure 7 is a time chart showing the simulation results of the waveforms of the signals in the pulse width modulation circuit 10B when the command signal Vin is 0.75 V and the frequency of the triangular wave generator 17 is 20 kHz. Figure 8 is a time chart showing the simulation results of the waveforms of the signals in the pulse width modulation circuit 10B when the command signal Vin is 1.35 V and the frequency of the triangular wave generator 17 is 20 kHz. Figures 7 and 8 show, from top to bottom, the waveforms of the second amplified signal Vg2, the error signal Verr, the current sense signal Vs, the pulse width modulation signal Vp, and the mask signal Vm.

[0038] 7 and 8, the second amplified signal Vg2 is a signal masked in synchronization with the mask signal Vm going to L level for a mask period T1 at the timing after the polarity of the pulse-width modulation signal Vp is inverted, compared to the first amplified signal Vg1 shown in Figures 3 and 4. In other words, the second amplified signal Vg2 is a signal in which only the area around where the glitch noise occurs is masked, compared to the first amplified signal Vg1 shown in Figures 3 and 4.

[0039] 7 and 8, the error signal Verr has reduced signal disturbances caused by glitch noise at the timing after the polarity of pulse-width modulated signal Vp is inverted, compared to the error signal Verr shown in Figures 3 and 4. Furthermore, by reducing the signal disturbances caused in error signal Verr, the pulse width disturbances of pulse-width modulated signal Vp are also reduced.

[0040] According to the motor drive device 1B and pulse width modulation circuit 10B of the embodiment, the influence of glitch noise that occurs in the internal signal of the pulse width modulation circuit 10B due to the delay time Δ that occurs in the current sense signal Vs, which is a reference signal from the motor drive circuit 30, can be reduced.

[0041] Although the present disclosure has been described in detail above, it is clear to those skilled in the art that the present disclosure is not limited to the embodiments described herein. The present disclosure can be implemented in modified and altered forms without departing from the spirit and scope of the present disclosure as defined by the claims. Therefore, the description of the present disclosure is intended to be illustrative and does not have any limiting meaning on the present disclosure.

[0042] (Addendum) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0043] (Appendix 1) The pulse width modulation circuit 10B includes an amplifier circuit 11, a masking unit 18, an integrating circuit 14, and a pulse width modulation signal generating unit 16. The amplifier circuit 11 generates a first amplified signal Vg1 from a reference signal Vs from the controlled object. The masking unit 18 generates a second amplified signal Vg2 by masking a predetermined period T1 of the first amplified signal Vg1. The integrating circuit 14 generates an error signal Verr from the second amplified signal Vg2 and the command signal Vin. The pulse width modulation signal generating unit 16 generates a pulse width modulation signal Vp, which is supplied to the controlled object, from the error signal Verr and the triangular wave signal Vt.

[0044] According to the pulse width modulation circuit 10B described in Supplementary Note 1, it is possible to reduce the influence of glitch noise that occurs in an internal signal due to the delay time Δ that occurs in the reference signal Vs from the controlled object.

[0045] (Appendix 2) In the pulse width modulation circuit 10B described in Supplementary Note 1, the masking unit 18 generates the second amplified signal Vg2 by masking the first amplified signal Vg1 for a predetermined period T1 after the polarity of the pulse width modulation signal Vp is inverted.

[0046] (Appendix 3) In the pulse width modulation circuit 10B described in Appendix 2, the masking unit 18 is a switch 18 connected between the amplifier circuit 11 and the integrator circuit 14, and the switch 18 is turned off only for a predetermined period T1 after the polarity of the pulse width modulation signal Vp is inverted, and is turned on for the rest of the period.

[0047] (Appendix 4) The motor drive device 1B includes a motor drive circuit 30, a motor control circuit 20, and a pulse-width modulation circuit 10B. The motor drive circuit 30 drives the motor M1. The motor control circuit 20 controls the motor drive circuit 30. The pulse-width modulation circuit 10B supplies a pulse-width modulation signal Vp to the motor control circuit 20. The pulse-width modulation circuit 10B includes an amplifier circuit 11, an integrator circuit 14, and a pulse-width modulation signal generator 16. The amplifier circuit 11 generates a first amplified signal Vg1 from a reference signal Vs from the motor drive circuit 30. The masker 18 generates a second amplified signal Vg2 by masking a predetermined period T1 of the first amplified signal Vg1. The integrator circuit 14 generates an error signal Verr from the second amplified signal Vg2 and the command signal Vin. The pulse-width modulation signal generator 16 generates a pulse-width modulation signal Vp, which is supplied to the motor control circuit 20, from the error signal Verr and the triangular wave signal Vt. The motor control circuit 20 controls the motor drive circuit 30 based on the pulse width modulation signal Vp supplied from the pulse width modulation circuit 10B.

[0048] According to the motor drive device 1B described in Supplementary Note 4, the influence of glitch noise that occurs in the internal signal of the pulse width modulation circuit 10B due to the delay time Δ that occurs in the reference signal Vs from the motor drive circuit 30 can be reduced.

[0049] (Appendix 5) In the motor drive device 1B described in Supplementary Note 4, the masking unit 18 generates the second amplified signal Vg2 by masking the first amplified signal Vg1 for a predetermined period T1 after the polarity of the pulse-width modulated signal Vp is inverted.

[0050] (Appendix 6) In motor drive device 1B described in Supplementary Note 5, masking unit 18 is switch 18 connected between amplifier circuit 11 and integration circuit 14. Switch 18 is turned off only for a predetermined period T1 after the polarity of pulse-width modulation signal Vp is inverted, and is turned on for the rest of the period.

[0051] (Appendix 7) In the motor driving device 1B according to any one of Supplementary Notes 4 to 6, the motor control circuit 20 and the motor control circuit 20 are configured as a single semiconductor integrated circuit.

[0052] (Appendix 8) In the motor driving device 1B according to any one of Supplementary Notes 4 to 6, the motor control circuit 20 and the motor control circuit 20 are each configured as individual semiconductor integrated circuits. [Explanation of symbols]

[0053] 1A, 1B Motor drive device 2 Variable DC power supply 10A, 10B Pulse width modulation circuit 11 Amplification circuit 12 Polarity switch 13 First operational amplifier 14 Integrator circuit 15 Second operational amplifier 16 Comparator (pulse width modulation signal generator) 17 Triangle wave generator 18 Switch (mask part) 20 Motor control circuit 30 Motor drive circuit 31 1st series circuit 32 Second series circuit 33 Third series circuit C1 capacitor M1 motor Ri Current detection resistor R0~R5 Resistors T1 mask period Q1~Q6 transistors SW1 First switch SW2 Second switch VCC power supply voltage Verr Error Signal Vg1 First amplified signal Vg2 Second amplified signal Vin command signal Vm mask signal Vp Pulse width modulated signal Vref1 First adjustment voltage Vref2 Second adjustment voltage Vs Current sense signal (reference signal) Vt Triangular wave signal Δ Delay Time

Claims

1. an amplifier circuit that generates a first amplified signal from a reference signal from a controlled object; a masking unit that generates a second amplified signal by masking a predetermined period of the first amplified signal; an integrating circuit that generates an error signal from the second amplified signal and a command signal; a pulse width modulation signal generating unit that generates a pulse width modulation signal to be supplied to the controlled object from the error signal and the triangular wave signal; A pulse width modulation circuit comprising:

2. 2. The pulse width modulation circuit according to claim 1, wherein the masking section generates the second amplified signal by masking the predetermined period of the first amplified signal after the polarity of the pulse width modulation signal is inverted.

3. the masking unit is a switch connected between the amplifier circuit and the integrating circuit, the switch is turned off only for the predetermined period after the polarity of the pulse width modulation signal is inverted, and is turned on for the rest of the period.

3. The pulse width modulation circuit of claim 2.

4. a motor drive circuit that drives the motor; a motor control circuit for controlling the motor drive circuit; a pulse width modulation circuit for supplying a pulse width modulation signal to the motor control circuit; Equipped with The pulse width modulation circuit is an amplifier circuit that generates a first amplified signal from a reference signal from the motor drive circuit; a masking unit that generates a second amplified signal by masking a predetermined period of the first amplified signal; an integrating circuit that generates an error signal from the second amplified signal and a command signal; a pulse width modulation signal generating unit that generates a pulse width modulation signal to be supplied to the motor control circuit from the error signal and the triangular wave signal; Equipped with the motor control circuit controls the motor drive circuit based on the pulse width modulation signal supplied from the pulse width modulation circuit; Motor drive device.

5. 5. The motor drive device according to claim 4, wherein the masking section generates the second amplified signal by masking a predetermined period of the first amplified signal after the polarity of the pulse width modulation signal is inverted.

6. the masking unit is a switch connected between the amplifier circuit and the integrating circuit, the switch is turned off only for the predetermined period after the polarity of the pulse width modulation signal is inverted, and is turned on for the rest of the period. The motor drive device according to claim 5 .

7. 7. The motor drive device according to claim 4, wherein the motor control circuit and the motor control circuit are configured as a single semiconductor integrated circuit.

8. 7. The motor drive device according to claim 4, wherein the motor control circuit and the motor control circuit are each configured as an individual semiconductor integrated circuit.

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