Intermittent operation control circuit

Abstract

To provide a system that acquires a highly accurate AD value while satisfying an electrical current consumption constraint without increasing an operating frequency of a CPU under a condition that a signal of 4 to 20 [mA] is used as an electrical current source for operating an internal electric circuit and an A / D conversion circuit of a ΔΣA / D conversion method is used.SOLUTION: An intermittent operation control circuit according to the present disclosure is connected to an external sensor (2000) and includes a system control unit (100), a delta-sigma AD converter (200), a processor (300), an SRAM (400), and a flash memory (500); wherein the system control unit (100) issues a command for switching between Active and Inactive, to each of the delta-sigma AD converter (200), the processor (300), the SRAM (400), the flash memory (500), and the sensor (2000).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed technology relates to an intermittent operation control circuit. [Background technology]

[0002] In the technical field of the chemical industry, such as petroleum refining, much technological development has been done regarding the automation of manufacturing processes. Most of the control devices used in automating manufacturing processes use a standard of 4-20 mA (sometimes called "4-20") as an analog signal output. The advantages of using this 4-20 mA output include the fact that it drops to 0 mA in the event of a disconnection, making it a fail-safe, that it is resistant to attenuation even over long distances, and that it can be easily converted to a 1-5 V voltage input by using a 250 Ω resistor.

[0003] Many regulating valves (also called "control valves") are used in factories and chemical plants to contribute to the automation of manufacturing processes. These regulating valves have a controller portion called a valve positioner and an actuator (drive portion). Valve positioners are sometimes simply called "positioners." A valve positioner is often used in such a way that a signal based on the above 4-20 mA standard is input from a host controller as a control signal that indicates the opening of the adjustment valve.

[0004] Automated equipment such as control valves used in factories and chemical plants may use signals sent from a higher-level controller not only as control signals but also as current sources to operate internal electrical circuits. When an automated device uses a 4-20 mA signal as a current source to operate its internal electrical circuit, the internal electrical circuit must operate normally even when the current is at the minimum limit of 4 mA. In other words, such an automated device must keep its overall current consumption below 4 mA under all conditions. If the overall current consumption cannot be kept below 4 mA, the automated device may not be able to operate correctly based on the control signal from the host controller.

[0005] When an automated device uses a 4-20 mA signal as a current source to operate its internal electrical circuitry, designing the device to keep its current consumption low is a very important issue.Incidentally, when an automated device uses a 4-20 mA signal as a current source to operate its internal electrical circuitry, such an automated device is sometimes called a "two-wire" device because it has only two signal terminals. Furthermore, even if an automated device has an internal battery or the like and does not use the 4-20 mA signal as a current source to operate the internal electrical circuitry, the current consumption is an important design issue because it affects the product's lifespan.

[0006] The sensors used in factories and chemical plants are not necessarily limited to those that output analog signals of 4-20 mA. Some systems used in factories and chemical plants include multiple types of capacitance sensors. For example, Patent Document 1 discloses an interface device that includes a signal conversion unit that converts the capacitance value (analog value) of a capacitive sensor into digital data (see, for example, "capacitance-to-digital conversion unit (22)" in Figure 5 of Patent Document 1). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-84103 Summary of the Invention [Problem to be solved by the invention]

[0008] The signal conversion unit disclosed in Patent Document 1 is configured using, for example, a successive approximation A / D conversion method, a ΔΣ A / D conversion method (referred to as a "delta-sigma A / D conversion method"), or the like. In particular, the ΔΣ A / D conversion method is often used when high-precision sensing is required. Here, the ΔΣ A / D conversion method is suited to high-precision sensing, but has the disadvantage of consuming larger current than, for example, the successive approximation A / D conversion method.

[0009] Taking the aforementioned regulating valve as an example, an angle sensor is used to detect the valve's opening. The so-called control board that drives the regulating valve is equipped with an A / D conversion circuit using the above-mentioned ΔΣ A / D conversion method to accurately read the analog signal output from the angle sensor. The control board then requires current to activate the angle sensor, A / D conversion circuit, and other electronic components such as the CPU, SRAM, and flash memory. Here, "activate" in the above context means to supply energy from an external source to enable the device to perform its function, or, in simple terms, to turn on the power.

[0010] In automated equipment such as regulating valves used in factories and chemical plants, when a 4-20 mA signal is used as a current source to operate the internal electrical circuitry and an A / D conversion circuit using the ΔΣ A / D conversion method is used, conventional control boards have strict specifications for the upper limit of current consumption, and only CPUs with low operating frequencies and low current consumption can be used, which is an issue.In addition, there are cases where it is desired to control automated equipment such as regulating valves used in factories and chemical plants with a cycle time of microseconds. The disclosed technology aims to provide a system that acquires highly accurate AD values ​​while satisfying current consumption constraints without increasing the CPU operating frequency, under the following conditions: a 4-20 mA signal is used as a current source to operate internal electrical circuits, and an A / D conversion circuit using a ΔΣ A / D conversion method is used. [Means for solving the problem]

[0011] The intermittent operation control circuit according to the present disclosure is connected to an external sensor and includes a system control unit, a delta-sigma AD converter, a processor, an SRAM, and a flash memory, and the system control unit issues commands to each of the delta-sigma AD converter, the processor, the SRAM, the flash memory, and the sensor to switch between Active and Inactive. [Effects of the Invention]

[0012] Because the intermittent operation control circuit according to the disclosed technology has the above-described technical features, it is possible to obtain high-precision AD values ​​while satisfying current consumption constraints without increasing the CPU operating frequency, under the conditions that a 4-20 mA signal is used as a current source to operate the internal electrical circuit and an A / D conversion circuit using a ΔΣ A / D conversion method is used. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a block diagram showing the configuration of an intermittent operation control circuit 1000 according to the first embodiment. [Figure 2] FIG. 2 is a timing chart of intermittent operation control circuit 1000 according to the first embodiment. [Figure 3] FIG. 3 is a block diagram showing the configuration of intermittent operation control circuit 1000 according to the second embodiment. [Figure 4] FIG. 4 is a timing chart of intermittent operation control circuit 1000 according to the second embodiment. [Figure 5] FIG. 5 is a block diagram showing the configuration of an intermittent operation control circuit 1000 according to the third embodiment. [Figure 6] FIG. 6 is a timing chart of intermittent operation control circuit 1000 according to the third embodiment. [Figure 7] FIG. 7 is a block diagram showing the configuration of an intermittent operation control circuit 1000 according to the fourth embodiment. [Figure 8] FIG. 8 is a timing chart of intermittent operation control circuit 1000 according to the fourth embodiment. [Figure 9] FIG. 9 is an explanatory diagram showing an example of the digital filter unit 220 according to the disclosed technique. [Figure 10] FIG. 10 is a table for explaining the processing of the scaling unit 230 according to the disclosed technique. [Figure 11] FIG. 11 is a block diagram illustrating the processing of the scaling unit 230 according to the disclosed technique. DETAILED DESCRIPTION OF THE INVENTION

[0014] Embodiment 1 Fig. 1 is a block diagram showing the configuration of an intermittent operation control circuit 1000 according to embodiment 1. As shown in Fig. 1, intermittent operation control circuit 1000 according to embodiment 1 includes a system control unit 100, a delta-sigma AD converter 200, a processor 300, an SRAM 400, a flash memory 500, and a general-purpose digital circuit 600. As shown in FIG. 1, the delta-sigma AD converter 200 includes a delta-sigma modulation section 210, a digital filter section 220, and a scaling section 230. Furthermore, as shown in FIG. 1, the intermittent operation control circuit 1000 according to the disclosed technique is connected to an external sensor 2000.

[0015] <<Intermittent operation control circuit 1000>> Intermittent operation control circuit 1000 according to the first embodiment is a component that controls automated equipment (not shown) such as regulating valves used in factories and chemical plants. One of the technical features of intermittent operation control circuit 1000 according to the present disclosure is that it includes system control unit 100, which will be described below. 1 represents a BUS in the intermittent operation control circuit 1000.

[0016] System Control Unit 100 The system control unit 100 according to the first embodiment is a component that issues a command to switch between Active and Inactive to each of the sensor 2000, the delta-sigma AD converter 200, the processor 300, the SRAM 400, the flash memory 500, and the general-purpose digital circuit 600. Here, Active is synonymous with power ON, as described above. In other words, the system control unit 100 issues a power ON / OFF command to each of the sensor 2000, the delta-sigma AD converter 200, the processor 300, the SRAM 400, the flash memory 500, and the general-purpose digital circuit 600, thereby realizing the intermittent operation control circuit 1000 as a time-sharing system.

[0017] Delta-Sigma AD Converter 200 The delta-sigma AD converter 200 is realized by an A / D conversion circuit using the ΔΣ A / D conversion method. As described above, the delta-sigma AD converter 200 includes a delta-sigma modulation unit 210, a digital filter unit 220, and a scaling unit 230. The details of the delta-sigma AD converter 200 will become clear from the following description.

[0018] Processor 300 The processor 300 is a CPU (also called a central processing unit, processing unit, arithmetic unit, microprocessor, microcomputer, or DSP) that executes programs stored in memory.

[0019] SRAM 400 SRAM400 is a static random access memory, a type of RAM that is a semiconductor memory that can be read and written. SRAM400 does not need to periodically rewrite its recorded contents, a process known as refreshing. As a result, SRAM400 consumes less power than DRAM of the same size. SRAM400 is used to read data required for calculations from storage (flash memory 500, described below) and temporarily store it there.

[0020] Flash Memory 500 The flash memory 500 is a non-volatile memory that is rewritable and retains its contents even when the power is turned off. The flash memory 500 is primarily used as storage.

[0021] General-purpose digital circuits 600 The general-purpose digital circuit 600 represents a general-purpose digital circuit that is always included in a microcontroller, such as an SPI (Serial Peripheral Interface), an I2C (Inter-Integrated Circuit), or a GPIO (General-Purpose Input / Output).

[0022] Fig. 2 is a timing chart of intermittent operation control circuit 1000 according to embodiment 1. In the timing chart shown in Fig. 2, a time period of 5 ms is divided into a "sensor + ADC phase" of the first half, which lasts 1 to 2 ms, and a "CPU phase" of the second half, which lasts 3 to 4 ms.

[0023] 2 is realized by the system control unit 100. Based on the operation timing illustrated in Fig. 2, the system control unit 100 sets the sensor 2000, and the delta-sigma modulation unit 210 and digital filter unit 220 in the delta-sigma AD converter 200 as active in the "sensor+ADC phase." Furthermore, the system control unit 100 sets the processor 300, SRAM 400, flash memory 500, and general-purpose digital circuit 600 as active in the "CPU phase." When the AD conversion result by the delta-sigma AD converter 200 is stored in the SRAM 400, the SRAM 400 may be set to Active even in the "sensor+ADC phase."

[0024] Thus, a technical feature of intermittent operation control circuit 1000 according to the first embodiment is that it includes system control section 100 and is realized as a time-sharing system. By having the above technical features, the intermittent operation control circuit 1000 according to the first embodiment has the advantage of being able to operate without exceeding the upper limit of current consumption (for example, 4 mA) under the conditions that a signal of 4-20 mA is used as a current source for operating the internal electric circuitry and an A / D conversion circuit employing a ΔΣ A / D conversion method is used.

[0025] Embodiment 2 Intermittent operation control circuit 1000 according to the second embodiment is a modified example of intermittent operation control circuit 1000 according to the disclosed technique. Unless otherwise specified, the same reference numerals as those used in the first embodiment are used in the second embodiment. Furthermore, in the second embodiment, explanations that overlap with those in the first embodiment are omitted as appropriate.

[0026] Fig. 3 is a block diagram showing the configuration of intermittent operation control circuit 1000 according to embodiment 2. As shown in Fig. 3, intermittent operation control circuit 1000 according to embodiment 2 includes a system control unit 100, a delta-sigma AD converter 200, a processor 300, an SRAM 400, a flash memory 500, a general-purpose digital circuit 600, and a sample-and-hold circuit 700. 1 according to the first embodiment, Fig. 3 according to the second embodiment shows that intermittent operation control circuit 1000 is provided with sample and hold circuit 700. In this way, intermittent operation control circuit 1000 according to the disclosed technique may be configured so that sample and hold circuit 700 acquires an analog signal output from external sensor 2000.

[0027] <<Sample and hold circuit 700>> The sample and hold circuit 700 is, as the name suggests, a circuit that samples an analog signal and holds the value for a certain period of time. The sample and hold circuit 700 is also called a sample and hold circuit or a track and hold circuit. The sample-and-hold circuit 700 according to the technique of the present disclosure is used for the purpose of separating the phases in which the sensor 2000 and the delta-sigma AD converter 200 become active.

[0028] Fig. 4 is a timing chart of the intermittent operation control circuit 1000 according to embodiment 2. In the timing chart shown in Fig. 4, a time period of 5 [ms] is divided into a "sensor phase" of the first half of 1 [ms], an "ADC phase" of the middle half of 1 [ms], and a "CPU phase" of the last half of 3 [ms].

[0029] 4 is realized by the system control unit 100. Based on the operation timing illustrated in Fig. 4, the system control unit 100 sets the sensor 2000 and the sample-and-hold circuit 700 to Active in the "sensor phase." Next, the system control unit 100 sets the delta-sigma modulation unit 210 and the digital filter unit 220 in the delta-sigma AD converter 200 to Active in the "ADC phase." Finally, the system control unit 100 sets the processor 300, SRAM 400, flash memory 500, and general-purpose digital circuit 600 to Active in the "CPU phase." As shown in FIG. 4, the sample and hold circuit 700 is active in both the "sensor phase" and the "ADC phase."

[0030] The sample and hold circuit 700 can hold the voltage value output by the sensor 2000. By utilizing this property, the intermittent operation control circuit 1000 according to the second embodiment can make the sensor 2000 inactive and the delta-sigma AD converter 200 active at the same time, and perform AD conversion based on the voltage held by the sample and hold circuit 700.

[0031] Thus, in addition to the technical features described in the first embodiment, the intermittent operation control circuit 1000 according to the second embodiment includes a sample and hold circuit 700 that is active in both the "sensor phase" and the "ADC phase." By being provided with the above technical features, intermittent operation control circuit 1000 according to embodiment 2 has the effect of intermittent operation control circuit 1000 according to embodiment 1, and in addition thereto, has the effect of being able to make sensor 2000, which consumes a large amount of current, and delta-sigma AD converter 200, which also consumes a large amount of current, active in different phases.

[0032] Embodiment 3 Intermittent operation control circuit 1000 according to the third embodiment is a modified example of intermittent operation control circuit 1000 according to the disclosed technique. Unless otherwise specified, the same reference numerals as those used in the previous embodiments are used in the third embodiment. Furthermore, in the third embodiment, explanations that overlap with those in the previous embodiments are omitted as appropriate.

[0033] FIG. 5 is a block diagram showing the configuration of intermittent operation control circuit 1000 according to the third embodiment. A plurality of sensors 2000, including sensors 2000-1 and 2000-2, are connected to intermittent operation control circuit 1000 shown in FIG. 5. In this manner, one control board may process signals from a plurality of sensors 2000 and control a plurality of actuators (not shown). Intermittent operation control circuit 1000 shown in FIG. 5 includes a sample-and-hold circuit 700-1 that samples and holds the voltage value of the analog signal output from sensor 2000-1, and a sample-and-hold circuit 700-2 that samples and holds the voltage value of the analog signal output from sensor 2000-2.

[0034] 5, there are at least as many sample and hold circuits 700 as there are connected sensors 2000. Each sample and hold circuit 700 samples and holds the output of one corresponding sensor 2000. Fig. 5 shows that a selection circuit (switcher) that switches between sample and hold circuit 700-1 and sensor 2000-2 is controlled by the system control unit 100.

[0035] FIG. 6 is a timing chart of the intermittent operation control circuit 1000 according to the third embodiment. The operation timing illustrated in FIG. 6 is also realized by the system control unit 100. The operation timing illustrated in FIG. 6 includes "sensor 1 phase," "sensor 2 phase," "ADC1 phase," and "ADC2 phase." st Phase," "ADC2 ndThe "ADC1 phase" and "CPU phase" are divided into five phases. In the "sensor 1 phase", the system control unit 100 sets the sensor 2000-1 and the sample-and-hold circuit 700-1 to Active. In the "sensor 2 phase", the system control unit 100 sets the sensor 2000-2 and the sample-and-hold circuit 700-2 to Active. st Phase" and "ADC2 nd In the "phase", the system control unit 100 sets the delta-sigma AD converter 200 (the delta-sigma modulation unit 210 and the digital filter unit 220) to Active. Finally, in the "CPU phase", the system control unit 100 sets the processor 300, the SRAM 400, the flash memory 500, and the general-purpose digital circuit 600 to Active. As shown in FIG. 6, the sample and hold circuit 700-1 includes a “sensor 1 phase”, a “sensor 2 phase”, and an “ADC1 st The sample-and-hold circuit 700-2 is preferably set to Active in the three phases of "Sensor 2 Phase", "ADC1 Phase", and "ADC2 Phase". st Phase," "ADC2 nd It is recommended to select Active in the three phases of "Phase". Furthermore, as shown in Figure 6, "ADC1 st In the "ADC2 phase", the sample and hold circuit 700-1 nd In the "phase", the sample and hold circuit 700-2 may be selected.

[0036] In this way, the intermittent operation control circuit 1000 according to the present disclosure may include sample and hold circuits 700 equal to the number of sensors 2000 to be connected. By having the above configuration, the intermittent operation control circuit 1000 according to the disclosed technology has the effect of shifting the operation timing of the multiple sensors 2000 connected thereto, and being able to operate within the constraints of the upper limit of current consumption in all phases.

[0037] Embodiment 4 Intermittent operation control circuit 1000 according to the fourth embodiment is a modified example of intermittent operation control circuit 1000 according to the disclosed technique. Unless otherwise specified, the same reference numerals as those used in the previous embodiments are used in the fourth embodiment. Furthermore, in the fourth embodiment, explanations that overlap with those in the previous embodiments are omitted as appropriate.

[0038] FIG. 7 is a block diagram showing the configuration of an intermittent operation control circuit 1000 according to the fourth embodiment. The intermittent operation control circuit 1000 shown in FIG. 7 is connected to a plurality of sensors 2000, including sensors 2000-1 and 2000-2. As shown in the third embodiment, a single control board may process signals from a plurality of sensors 2000 and control a plurality of actuators (not shown). The intermittent operation control circuit 1000 shown in FIG. 7 includes a sample-and-hold circuit 700-1 that samples and holds the voltage value of an analog signal output from sensor 2000-1, and a sample-and-hold circuit 700-2 that samples and holds the voltage value of an analog signal output from sensor 2000-2. Furthermore, the intermittent operation control circuit 1000 shown in FIG. 7 includes a delta-sigma AD converter 200-1 that performs ADC on the voltage value held by sample-and-hold circuit 700-1, and a delta-sigma AD converter 200-2 that performs ADC on the voltage value held by sample-and-hold circuit 700-2. That is, the intermittent operation control circuit 1000 according to the fourth embodiment is configured such that the number of channels of the delta-sigma AD converter 200 provided is equal to the number of sensors 2000 to be connected.

[0039] The configuration including a plurality of channels of the delta-sigma AD converter 200 as illustrated in FIG. 7 is particularly effective when the current consumption of the sensor 2000 is dominant compared to the current consumption of the delta-sigma AD converter 200.

[0040] Fig. 8 is a timing chart of the intermittent operation control circuit 1000 according to the fourth embodiment. The operation timing illustrated in Fig. 8 is also realized by the system control unit 100. The operation timing illustrated in Fig. 8 is divided into four phases: "sensor 1 phase," "sensor 2 phase," "ADC phase," and "CPU phase." As can be seen by comparison with FIG. 6 relating to the third embodiment, in the intermittent operation control circuit 1000 according to the fourth embodiment, AD conversion is performed in parallel in the channels of multiple delta-sigma AD converters 200 in the same single "ADC phase."

[0041] In this way, the intermittent operation control circuit 1000 according to the technique of the present disclosure may be provided with the same number of channels of the delta-sigma AD converter 200 as the number of sensors 2000 to be connected. By having the above configuration, the intermittent operation control circuit 1000 according to the present disclosure can perform AD conversion in parallel in the same "ADC phase."

[0042] Embodiment 5 Intermittent operation control circuit 1000 according to the fifth embodiment is a modified example of intermittent operation control circuit 1000 according to the disclosed technique. Unless otherwise specified, the same reference numerals as those used in the previous embodiments are used in the fifth embodiment. Furthermore, in the fifth embodiment, explanations that overlap with those in the previous embodiments are omitted as appropriate.

[0043] 9 is an explanatory diagram showing an example of the digital filter unit 220 according to the disclosed technique. The digital filter unit 220 may be, for example, a SINC filter or a CIC filter. 9, the SINC filter is composed of an accumulator and a differentiator. The discrete transfer function F(z) of the SINC filter can be expressed by the following formula. TIFF2025163703000002.tif14166 Here, z appearing in Equation (1) is an operator in the Z transform (also referred to as the "Z operator"). Furthermore, N is the integration period of the SINC filter. In FIG. 9, a third-order SINC is shown, and in this case, N=3. A third-order SINC filter is sometimes expressed as a "SINC3 filter" to clearly indicate the order. The SINC filter has the property that the longer the integration period (N) is made, the more effective it is as a low-pass filter, but on the other hand, the longer the calculation time becomes.

[0044] The output bit width of the SINC filter is given by the following formula: TIFF2025163703000003.tif9166 Here, b and s in equation (2) represent the bit width and sign bit of the signal input to the filter, respectively. Equation (2) suggests that the coefficient of the scaling performed by the scaling unit 230 needs to be changed depending on the value of N, which is the integration period of the digital filter unit 220. The derivation of the formulas (1) and (2) is described in detail in the following paper, the lead author of which is the first inventor of the present application. Reference paper: H. Kuribayashi and T. Kajita, “Area-Efficient Decimation Filter with 50 / 60Hz Power-Line Noise Suppression for ΔΣ A / D Converters”, SICE Journal of Control, Measurement, and System Integration, Vol. 10, No. 3, pp. 165-169, May 2017

[0045] Fig. 10 is a table explaining the processing of the scaling unit 230 according to the disclosed technique. More specifically, Fig. 10 is a table summarizing which values ​​should be used as scaling coefficients in the scaling performed by the scaling unit 230 when b = 2 and s = 1 (see Equation (2)). In the table shown in Fig. 10, the first column from the left indicates "N," which is the integration period of the SINC filter. Furthermore, the third column from the right indicates the scaling "coefficients" used in the scaling performed by the scaling unit 230. If the settable value of N is limited to values ​​that can be expressed as a power of 2, the scaling "coefficient" used in the scaling performed by scaling unit 230 may be one type, "0.66667" (cases of N=256, 512, 1024 in FIG. 10). This means that the AD conversion result is signed 24 bits, and the range that the output can take is from 0x80_0000 to 0x7F_FFFF. However, in actual practice, there are cases where it is desired to set the integration period (N) of the digital filter unit 220 in detail without any restrictions. If the settable integration period (N) of the digital filter unit 220 were limited to values ​​that can be expressed as a power of 2, a situation would arise in which the sampling period of the delta-sigma AD converter 200 would have to be shortened, resulting in high specs and a high price for the entire device. In the intermittent operation control circuit 1000 according to the disclosed technique, the delta-sigma AD converter 200 includes a scaling unit 230, and performs scaling based on the lookup table of scaling "coefficients" shown in FIG. 10, so that the integration period (N) of the digital filter unit 220 can be set flexibly and precisely.

[0046] Fig. 11 is a block diagram illustrating the processing of the scaling unit 230 according to the disclosed technique. In Fig. 11, a symbol with a circle and a multiplier "x" indicates that a coefficient is multiplied in the scaling performed by the scaling unit 230. The example in Fig. 11 shows that coefficients 1 to n are prepared, and that the coefficients are switched according to "N," which is the integration period of the SINC filter. Fig. 11 also shows that, after the coefficient is multiplied, the lower bits (corresponding to the bits below the decimal point) are truncated.

[0047] In this way, in the intermittent operation control circuit 1000 according to the technique of the present disclosure, the scaling section 230 may switch the scaling coefficient according to the integration period (N) of the digital filter section 220 (that is, the SINC filter). By including the scaling section 230 described above, the intermittent operation control circuit 1000 according to the presently disclosed technique can finely set the integration period (N) of the digital filter section 220 (that is, the SINC filter) without any restrictions.

[0048] (Addendum) One aspect of the intermittent operation control circuit 1000 according to the disclosed technology is connected to an external sensor 2000 and includes a system control unit 100, a delta-sigma AD converter 200, a processor 300, an SRAM 400, and a flash memory 500, and the system control unit 100 issues commands to each of the delta-sigma AD converter 200, the processor 300, the SRAM 400, the flash memory 500, and the sensor 2000 to switch between Active and Inactive. Due to this technical feature, the intermittent operation control circuit 1000 according to the disclosed technology has the effect of being able to operate without exceeding the upper limit of current consumption (for example, 4 mA) under the conditions that a 4-20 mA signal is used as a current source to operate the internal electrical circuitry and an A / D conversion circuit using the ΔΣ A / D conversion method is used.

[0049] In another aspect of the intermittent operation control circuit 1000 according to the disclosed technology, the delta-sigma AD converter 200 includes a delta-sigma modulation section 210, a digital filter section 220, and a scaling section 230, and the digital filter section 220 is a SINC filter. This means that the intermittent operation control circuit 1000 according to the disclosed technique can use a general-purpose ΔΣ AD converter equipped with a SINC filter.

[0050] Another aspect of the intermittent operation control circuit 1000 according to the disclosed technique may further include a sample-and-hold circuit 700 provided in the preceding stage of the delta-sigma AD converter 200 to sample and hold the output of the sensor 2000. By further including the sample-and-hold circuit 700, the intermittent operation control circuit 1000 according to the technique of the present disclosure can shift the phases in which the sensor 2000 and the delta-sigma AD converter 200 become active.

[0051] Another aspect of the intermittent operation control circuit 1000 according to the disclosed technology may include sample-and-hold circuits 700 in at least the same number as the number of connected sensors 2000, each of which samples and holds the output of one corresponding sensor 2000, and which are selected by a selection circuit controlled by the system control unit 100. By providing the same number of sample-and-hold circuits 700 as the number of connected sensors 2000, the intermittent operation control circuit 1000 according to the disclosed technology can shift the operation timing of the multiple connected sensors 2000, and operate within the constraints of the upper limit of current consumption in all phases.

[0052] In another aspect of the intermittent operation control circuit 1000 according to the disclosed technique, the scaling section 230 may switch the scaling coefficient according to the integration period (N) of the digital filter section 220 (that is, the SINC filter). By including such a scaling section 230, the intermittent operation control circuit 1000 according to the present disclosure can finely set the integration period (N) of the digital filter section 220 (that is, the SINC filter) without any restrictions. [Industrial Applicability]

[0053] The disclosed technology can be applied to the control of automated equipment such as regulating valves used in factories and chemical plants, and has industrial applicability. [Explanation of symbols]

[0054] 100 system control unit, 200 delta-sigma AD converter, 210 delta-sigma modulation unit, 220 digital filter unit, 230 scaling unit, 300 processor, 400 SRAM, 500 flash memory, 600 general-purpose digital circuit, 1000 intermittent operation control circuit, 2000 sensor.

Claims

1. It is connected to an external sensor, The system includes a system control unit, a delta-sigma AD converter, a processor, an SRAM, and a flash memory; the system control unit issues a command to switch between Active and Inactive to each of the delta-sigma AD converter, the processor, the SRAM, the flash memory, and the sensor; Intermittent operation control circuit.

2. the delta-sigma AD converter comprises a delta-sigma modulation unit, a digital filter unit, and a scaling unit; The digital filter unit is a SINC filter.

2. The intermittent operation control circuit according to claim 1.

3. a sample-and-hold circuit provided in a stage preceding the delta-sigma AD converter, which samples and holds the output of the sensor; 2. The intermittent operation control circuit according to claim 1.

4. the number of sample-and-hold circuits is at least the same as the number of sensors connected, each of which samples and holds the output of one corresponding sensor, and which is selected by a selection circuit controlled by the system control unit; 4. The intermittent operation control circuit according to claim 3.

5. the scaling unit switches a scaling coefficient depending on an integration period of the digital filter unit.

3. The intermittent operation control circuit according to claim 2.

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