Core substrate and manufacturing method thereof

Abstract

To provide a technique for suppressing pinhole defects from occurring on the surface of a conductive layer after half etching for adjusting the thickness of the conductive layer.SOLUTION: A core substrate includes an insulating base material, a pair of conductive layers laminated on both the front and back sides of the insulating base material, a through hole penetrating the insulating base material, and a through hole conductor plated into the through hole to connect the pair of conductive layers, and each of the pair of conductive layers includes a first electrolytic plated layer integrally formed with the through hole conductor, an electroless plated layer laminated on the first electrolytic plated layer, and a second electrolytic plated layer laminated on top of that.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a core substrate and a manufacturing method thereof. [Background technology]

[0002] A known conventional method for manufacturing a core substrate is to form a pair of conductive layers on both the front and back surfaces of an insulating base material while forming through-hole conductors by plating the insides of the through-holes (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2005-93934 A (paragraph

[0020] , Figure 4) Summary of the Invention [Problem to be solved by the invention]

[0004] In the conventional core substrate manufacturing method described above, half etching may be performed to adjust the thickness of the conductive layer after plating fills the through holes. After half etching, pinhole defects may occur on the surface of the conductive layer. [Means for solving the problem]

[0005] One aspect of the invention is a core substrate comprising an insulating base material, a pair of conductive layers laminated on both the front and back sides of the insulating base material, a through hole penetrating the insulating base material, and a through hole conductor plated into the through hole to connect the pair of conductive layers, wherein each of the pair of conductive layers includes a first electrolytic plated layer integrally formed with the through hole conductor, an electroless plated layer laminated on the first electrolytic plated layer, and a second electrolytic plated layer laminated on top of that. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is an enlarged cross-sectional view of a core substrate according to a first embodiment. [Figure 2] FIG. 2A is a cross-sectional view of an insulating base material, FIG. 2B is a cross-sectional view of a core substrate on which a first electroless plating layer is formed, and FIG. 2C is a cross-sectional view of a core substrate on which a first electrolytic plating layer is formed. [Figure 3] FIG. 3A is a cross-sectional view of a core substrate on which a second electroless plating layer is formed, FIG. 3B is a cross-sectional view of a core substrate on which a second electrolytic plating layer is formed, and FIG. 3C is a cross-sectional view of a core substrate on which a surface to be etched is formed. [Figure 4] FIG. 4A is an enlarged cross-sectional view of a conventional core substrate, and FIG. 4B is an enlarged cross-sectional view of a conventional core substrate. [Figure 5] FIG. 5A is an enlarged cross-sectional view of the core substrate, and FIG. 5B is an enlarged cross-sectional view of the core substrate. DETAILED DESCRIPTION OF THE INVENTION

[0007] [First embodiment] A core substrate 10 according to a first embodiment and a method for manufacturing the same will be described with reference to Figures 1 to 3 and 5. As shown in Figure 1, the core substrate 10 includes an insulating base material 11 and a pair of conductive layers 20 laminated on the front and back surfaces of the insulating base material 11.

[0008] The insulating substrate 11 is, for example, a prepreg, which is a glass cloth impregnated with a thermosetting resin (epoxy resin, polyimide resin, etc.). Note that, for example, an insulating film for a build-up substrate (a film without a core material, for example, made of a thermosetting resin containing an inorganic filler) may also be used as the insulating substrate 11.

[0009] Through holes 12H are formed through insulating substrate 11. Through holes 12H are tapered, with the diameter decreasing from both the front and back sides of insulating substrate 11 toward the center in the thickness direction of insulating substrate 11. Through holes 12H are filled with through-hole conductors 12. Note that through holes 12H may have a smaller diameter in the middle than at both ends, or may have a uniform diameter.

[0010] Each of the pair of conductive layers 20 has a multilayer structure including copper foil 13, first and second electroless plated layers 16A and 16B, and first and second electrolytic plated layers 14 and 15. First and second electroless plated layers 16A and 16B are, for example, electroless copper plated layers, and first and second electrolytic plated layers 14 and 15 are, for example, electrolytic copper plated layers. Electroless plating is also commonly called chemical plating.

[0011] Copper foil 13 is laminated only on both the front and back surfaces of insulating substrate 11, but not on the inner surfaces of through-hole 12H. First electroless plated layer 16A is laminated on insulating substrate 11 and the inner surfaces of through-hole 12H and is a conductive layer for supplying power to first electroless plated layer 14. First electroless plated layer 14 is laminated on first electroless plated layer 16A and is integrally formed with through-hole conductor 12 in through-hole 12H. Second electroless plated layer 16B is laminated on first electroless plated layer 14, and second electroless plated layer 15 is laminated on top of that. Conical depressions 14C and 16C are formed on the surfaces of first electroless plated layer 14 and second electroless plated layer 16B, extending from the center of through-hole 12H. The surface of second electroless plated layer 15, including the portion extending from the center of through-hole 12H, is generally flat.

[0012] In this embodiment, the pair of conductive layers 20 includes copper foil 13 and first electroless plated layer 16A, but either one of them may be omitted. The first and second electroless plated layers 16A, 16B and the first and second electrolytic plated layers 14, 15 are, for example, copper plated, but are not limited thereto and may be nickel, gold, or silver plated, for example.

[0013] This concludes the description of core substrate 10 of this embodiment. Next, a method for manufacturing core substrate 10 will be described with reference to FIGS. (1) An insulating substrate 11 is prepared as a core substrate 11K with copper foils 13 laminated on both sides thereof. The core substrate 11K is subjected to an etching process to thin the entire copper foils 13 on both sides (see FIG. 2A).

[0014] (2) Next, a laser is irradiated onto the copper foil 13 of the insulating base material 11 to form through-holes 12H. After removing resin residue inside the through-holes 12 by desmearing, electroless plating is performed to laminate first electroless plated layers 16A on both the front and back surfaces of the insulating base material 11 and the inner surfaces of the through-holes 12H (see FIG. 2B).

[0015] (3) Next, a first electrolytic plating process is performed using first electroless plated layer 16A as a seed layer. Cleaned insulating base material 11 is immersed in an electrolytic plating bath filled with an electrolytic plating solution, and first electrolytic plated layer 14 is deposited on the surface of insulating base material 11. At this time, insulating foreign matter 100 adheres to first electrolytic plated layer 14. Furthermore, through-hole conductor 12 is formed inside through-hole 12H, and recessed portions 14C are formed on both ends of the through-hole conductor 12 (see FIG. 2C).

[0016] (4) After being removed from the electrolytic plating bath, insulating base material 11 is subjected to a cleaning process and then immersed in a chemical plating bath filled with a chemical plating solution, whereby second electroless plated layer 16B is deposited on first electrolytic plated layer 14 (see FIG. 3A). The portion of second electroless plated layer 16B that is formed on depression 14C becomes depression 16C.

[0017] (5) Next, a second electrolytic plating process is performed. After being removed from the chemical plating bath, insulating substrate 11 is washed and then immersed in the electrolytic plating bath again. Then, second electrolytic plated layer 15 is deposited on the surface of second electroless plated layer 16B (see FIG. 3B).

[0018] (6) After rinsing and drying, a half-etching process is performed to adjust the thickness of second electrolytic plated layer 15. This makes the surface of second electrolytic plated layer 15 a flat etched surface 15A (see FIG. 3C).

[0019] In the conventional manufacturing method of core substrate 10A, the electroless plating step (4) described above is not performed, and instead the second electrolytic plating step is performed after the first electrolytic plating step. Here, insulating foreign matter 100 adhering to the surface of first electrolytic plated layer 14 is often a non-conductive material such as dust or dirt. Therefore, in the conventional manufacturing method of core substrate 10A, plating is not deposited on insulating foreign matter 100, which is a non-conductive material, in the second electrolytic plating step, and pinholes 19 with insulating foreign matter 100 at the bottom are formed in second electrolytic plated layer 15. Furthermore, when second electrolytic plated layer 15 is half-etched, the etching solution seeps into pinholes 19, making insulating foreign matter 100 susceptible to falling off. This can lead to the problem of insulating foreign matter 100 falling off unexpectedly (see FIG. 4B).

[0020] In contrast, in this embodiment, an electroless plating step is performed between the first electrolytic plating step and the second electrolytic plating step. This causes a second electroless plated layer 16B to be deposited on insulating foreign matter 100 adhering to first electrolytic plated layer 14 (see FIG. 5A). Then, in the second electrolytic plating step, plating is deposited using second electroless plated layer 16B on insulating foreign matter 100 as a seed layer, and second electroless plated layer 15 is formed over second electroless plated layer 16B without generating pinholes 19 (see FIG. 5B). This allows insulating foreign matter 100 to be contained within conductive layer 20, eliminating the problem of insulating foreign matter 100 falling off unexpectedly.

[0021] In addition, the through-hole 12H in this embodiment has a tapered shape that narrows in diameter toward the center of the thickness direction of the core substrate 10, so that the through-hole 12H is easily filled with plating in the first electrolytic plating process, making it less likely that voids will occur inside the through-hole conductor 12.

[0022] [Other embodiments] (1) In this embodiment, second electroless plated layer 16B is laminated between first electroless plated layer 14 and second electroless plated layer 15, but it may also be laminated on second electroless plated layer 15. Furthermore, second electroless plated layer 16B may be laminated not only on conductive layer 20 laminated on insulating substrate 11, but also on the conductive layer of a buildup layer laminated on conductive layer 20. In this case, electrolytic plating is performed on the upper surface of the buildup layer and the via holes to form via conductors and an electroless plated layer, and then electroless plated layer 16B is laminated thereon.

[0023] (2) In this embodiment, the thickness of second electrolytic plated layer 15 is adjusted by half-etching, but the thickness may also be adjusted by polishing.

[0024] Although the present specification and drawings disclose specific examples of the technology included in the scope of the claims, the technology described in the claims is not limited to these specific examples, but also includes various modifications and variations of the specific examples, and also includes parts of the specific examples taken independently. [Explanation of symbols]

[0025] 10 Core Board 11 Insulating substrate 12 through-hole conductor 12H through hole 13 Copper foil 14 First electrolytic plating layer 15 Second electrolytic plating layer 15A Etched surface 16B Second electroless plating layer 19 Pinhole 20 Conductive layer 100 Insulating foreign matter

Claims

1. A core substrate comprising an insulating base material, a pair of conductive layers laminated on both the front and back sides of the insulating base material, a through-hole penetrating the insulating base material, and a through-hole conductor filled with plating in the through-hole to connect the pair of conductive layers, Each of the pair of conductive layers includes a first electrolytic plated layer integrally formed with the through-hole conductor, an electroless plated layer laminated on the first electrolytic plated layer, and a second electrolytic plated layer laminated on top of that.

2. 2. The core substrate according to claim 1, wherein insulating foreign matter is attached to the first electrolytic plating layer, The electroless plated layer is laminated on the first electrolytic plated layer and the insulating foreign matter.

3. The core substrate according to claim 1, The upper surface of the second electrolytic plated layer is an etching surface that is half-etched.

4. The core substrate according to claim 1, Each of the pair of conductive layers includes a metal foil formed on the surface of the insulating base material and a power supply electroless plating layer formed on the metal foil for power supply to the first electrolytic plating layer.

5. The core substrate according to claim 1, The through hole has a shape in which the inner diameter at the middle portion is smaller than that at both ends.

6. A method for manufacturing a core substrate according to any one of claims 1 to 5, a first electrolytic plating step in which the through-hole conductor is formed and the first electrolytic plating layer is laminated; an electroless plating step in which the electroless plating layer is laminated; and a second electrolytic plating step of laminating the second electrolytic plated layer.

7. 7. A method for manufacturing a core substrate according to claim 6, The method includes a step of adjusting the thickness of the conductive layer after the second electrolytic plating step.

8. The method for manufacturing a core substrate according to claim 7, The step of adjusting the thickness of the conductive layer is half etching.

9. 7. The method for manufacturing a wiring board according to claim 6, The through holes are formed by a laser.

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