Wafer and semiconductor device

Abstract

To provide a wafer and a semiconductor device that can achieve stable characteristics.SOLUTION: A wafer according to an embodiment includes a substrate and a first layer. The first layer includes Alz1Ga1-z1N (0<z1≤1). The first layer includes a first region and a second region. The first region is between the substrate and the second region. A first region oxygen concentration in the first region is lower than a substrate oxygen concentration in the substrate. The first region oxygen concentration is lower than a second region oxygen concentration in the second region.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a wafer and a semiconductor device.

Background Art

[0002] For example, in a semiconductor device based on a wafer containing nitrides, stable characteristics are desired.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a wafer and a semiconductor device capable of obtaining stable characteristics.

Means for Solving the Problems

[0005] According to an embodiment of the present invention, the wafer includes a substrate and a first layer. The first layer contains Al z1 Ga 1-z1 N (0 < z1 ≦ 1). The first layer includes a first region and a second region. The first region is between the substrate and the second region. The oxygen concentration in the first region in the first region is lower than the oxygen concentration in the substrate in the substrate. The oxygen concentration in the first region is lower than the oxygen concentration in the second region in the second region.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. [Figure 2] FIG. 2 is a graph illustrating the concentration of elements in the wafer. [Figure 3]FIG. 3 is a graph illustrating the concentration of elements in a wafer. [Figure 4] 4(a) and 4(b) are microscope images of the wafer. [Figure 5] FIG. 5 is a schematic cross-sectional view illustrating the wafer according to the first embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and in each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

[0008] (First embodiment) FIG. 1 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. 1, the wafer 210 according to the embodiment includes a substrate 18s and a first layer 11. As will be described later, the wafer 210 may further include other layers.

[0009] The first direction D1 from the base 18s to the first layer 11 is defined as the Z-axis direction. A direction perpendicular to the Z-axis direction is defined as the X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is defined as the Y-axis direction. The base 18s and the first layer 11 lie along the XY plane.

[0010] The first layer 11 is Al z1 Ga 1-z1It includes N (0 < z1 ≤ 1). The composition ratio z1 may be, for example, 0.8 or more and 1 or less. The first layer 11 may be, for example, an AlN layer.

[0011] The first layer 11 includes a first region 11a and a second region 11b. The first region 11a is between the substrate 18s and the second region 11b. It was found that the amount of warpage of the substrate 18s differed depending on the oxygen concentration relationship in these regions.

[0012] Figures 2 and 3 are graphs illustrating the element concentrations in the wafer. These horizontal axes are the positions pZ in the Z-axis direction (thickness direction). The left axis in these figures is the oxygen concentration C(O). The right axis in these figures is the Al count number C(Al). Figure 2 corresponds to the first sample SPL1. Figure 3 corresponds to the second sample SPL2.

[0013] As shown in Figure 2, in the first sample SPL1, the first region oxygen concentration C11a in the first region 11a is lower than the substrate oxygen concentration C18s in the substrate 18s. The first region oxygen concentration C11a is lower than the second region oxygen concentration C11b in the second region 11b.

[0014] As shown in Figure 3, in the second sample SPL2, the first region oxygen concentration C11a in the first region 11a is lower than the substrate oxygen concentration C18s in the substrate 18s. The first region oxygen concentration C11a is higher than the second region oxygen concentration C11b in the second region 11b.

[0015] Thus, the oxygen profiles are different between the first sample SPL1 and the second sample SPL2. On the other hand, in the first sample SPL1, the amount of warpage of the wafer 210 is 32 μm. In the second sample SPL2, the amount of warpage of the wafer 210 is 96 μm.

[0016] The oxygen concentration profile in the first layer 11 can suppress warpage of the wafer. For example, the occurrence of cracks can be suppressed. Instability of characteristics caused by cracks or the like can be suppressed. According to the embodiment, a wafer capable of obtaining stable characteristics can be provided.

[0017] 4(a) and 4(b) are microscope images of the wafer. These figures are AFM (Atomic Force Microscope) images of the surface of the first layer 11 in the wafer 210. FIG. 4(a) corresponds to the first sample SPL1. FIG. 4(b) corresponds to the second sample SPL2. As shown in FIG. 4(b), the surface of the second sample SPL2 is relatively homogeneous. As shown in FIG. 4(a), island-shaped regions (convex portions) are observed in the first sample SPL1. It is believed that the island-shaped regions (convex portions) relieve stress in the first sample SPL1, reducing the amount of warpage.

[0018] In an embodiment, the substrate oxygen concentration C18s may be high, for example, to improve the interface characteristics between the first layer 11 and the substrate 18s, for example, to reduce the dislocation density of the first layer 11.

[0019] In this embodiment, the second region oxygen concentration C11b may be lower than the substrate oxygen concentration C18s. By having the first region oxygen concentration C11a and the second region oxygen concentration C11b lower than the substrate oxygen concentration C18s, the occurrence of excessive unevenness is suppressed. Appropriate unevenness allows for a small amount of warpage. For example, high crystal quality can be maintained.

[0020] The difference between the first sample SPL1 and the second sample SPL2 is obtained by, for example, changing the conditions for forming the first layer 11 (e.g., epitaxial growth). For example, a high second-region oxygen concentration C11b can be easily obtained by increasing the oxygen concentration in the atmosphere during the formation of the second region 11b compared to that during the formation of the first region 11a. For example, a high second-region oxygen concentration C11b can be easily obtained by increasing the water concentration in the atmosphere during the formation of the second region 11b compared to that during the formation of the first region 11a. For example, a high second-region oxygen concentration C11b can be easily obtained by increasing the water concentration in the Al source gas during the formation of the second region 11b compared to that during the formation of the first region 11a. For example, a high second-region oxygen concentration C11b can be easily obtained by decreasing the water concentration in the nitrogen source gas during the formation of the second region 11b compared to that during the formation of the first region 11a.

[0021] In the embodiment, the first region 11a contacts the substrate 18s. The second region 11b may contact the first region 11a. The substrate 18s may include, for example, silicon.

[0022] The first region oxygen concentration C11a is, for example, 1×10 16 cm -3 5x10 or more 17 cm -3 The second region oxygen concentration C11b may be, for example, 1×10 17 cm -3 More than 1×10 18 cm -3 The substrate oxygen concentration C18s is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is fine.

[0023] The first layer 11 may have a first layer thickness tr1 (see FIG. 1) of, for example, 100 nm or more and 200 nm or less. The first region 11a may have a first region thickness t1 (see FIG. 1) of, for example, 50 nm or more and 100 nm or less. The second region 11b may have a second region thickness t2 (see FIG. 1) of, for example, 50 nm or more and 100 nm or less.

[0024] As shown in FIG. 1, the wafer 210 may further include a second layer 12. The second layer 12 contains Al z2 Ga 1-z2 N (0 < z2 < 1, z2 < z1). The first layer 11 is provided between the substrate 18s and the second layer 12. As in the first sample SPL1 of FIG. 2, the second layer 12 does not contain oxygen. Or, the second layer oxygen concentration C12 in the second layer 12 is lower than the second region oxygen concentration C11b. The second layer oxygen concentration C12 may be lower than the first region oxygen concentration C11a. The second layer 12 is, for example, an AlGaN layer. The composition ratio of Al in the second layer 12 may decrease as it moves away from the second layer 12. The second layer thickness tr2 (see FIG. 1) of the second layer 12 may be, for example, 10 nm or more and 500 nm or less.

[0025] As shown in FIG. 1, the wafer 210 may further include a third layer 13. The third layer 13 contains Al z3 Ga 1-z3 N (0 ≤ z3 ≤ 1). The second layer 12 is between the first layer 11 and the third layer 13. As in the first sample SPL1 of FIG. 2, the third layer 13 does not contain oxygen. Or, the third layer oxygen concentration C13 in the third layer 13 is lower than the second region oxygen concentration C11b. The third layer oxygen concentration C13 may be lower than the first region oxygen concentration C11a.

[0026] As shown in FIG. 1, the wafer 210 may further include a fourth layer 14. The fourth layer 14 contains Al z4 Ga 1-z4 N (0 ≤ z4 ≤ 1). The fourth layer 14 may be, for example, a GaN layer. The third layer 13 is between the second layer 12 and the fourth layer 14. The fourth layer 14 does not contain oxygen. Or, the fourth layer oxygen concentration C14 in the fourth layer 14 is lower than the second region oxygen concentration C11b. The fourth layer oxygen concentration C14 may be lower than the first region oxygen concentration C11a.

[0027] As shown in FIG. 1, the wafer 210 may further include a first semiconductor layer 10 and a second semiconductor layer 20. The first semiconductor layer 10 contains Al x1 Ga 1-x1 N (0 ≤ x1 < 1). The second semiconductor layer 20 contains Al x2Ga 1-x2 It contains N(0 < x2 ≤ 1, x1 < x2). The first semiconductor layer 10 is provided between the third layer 13 and the second semiconductor layer 20. The first semiconductor layer 10 is provided between the fourth layer 14 and the second semiconductor layer 20. The composition ratio x1 may be, for example, 0 or more and 0.15 or less. The first semiconductor layer 10 is, for example, a GaN layer. The composition ratio x2 may be, for example, more than 0.15 and 0.3 or less. The second semiconductor layer 20 is, for example, an AlGaN layer.

[0028] The carbon concentration in the fourth layer 14 may be higher than the carbon concentration in the first semiconductor layer 10.

[0029] The first layer 11, the second layer 12, the third layer 13, the fourth layer 14, the first semiconductor layer 10, and the second semiconductor layer 20 are included in the nitride member 10M.

[0030] FIG. 5 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. As shown in FIG. 5, in the wafer 211 according to the embodiment, the third layer 13 includes a plurality of films. The configuration of the wafer 211 excluding this may be the same as the configuration of the wafer 210.

[0031] In the wafer 211, the third layer 13 includes a plurality of first films 13a and a plurality of second films 13b. In the first direction D1 from the substrate 18s to the first layer 11, one of the plurality of first films 13a is between one of the plurality of second films 13b and another one of the plurality of second films 13b. One of the plurality of second films 13b is between one of the plurality of first films 13a and another one of the plurality of first films 13a. The first film 13a contains Al y1 Ga 1-y1 N(0 < y1 ≤ 1). The second film 13b contains Al y2 Ga 1-y2 N(0 ≤ y2 < y1). The third layer 13 is, for example, a superlattice layer. High crystal quality can be obtained. The amount of warpage can be suppressed.

[0032] (Second Embodiment) The second embodiment relates to a semiconductor device. The semiconductor device includes the wafer 210 and its modifications described in the first embodiment.

[0033] FIG. 6 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. As shown in FIG. 6, the semiconductor device 110 according to the embodiment includes the wafer 210 according to the first embodiment, a nitride member 10M, a first electrode 51, a second electrode 52, and a third electrode 53.

[0034] The nitride member 10M includes, for example, a first semiconductor layer 10 and a second semiconductor layer 20. The first semiconductor layer 10 contains Al x1 Ga 1-x1 N (0 ≦ x1 < 1). The second semiconductor layer 20 contains Al x2 Ga 1-x2 N (0 < x2 ≦ 1, x^1 < x2). The composition ratio x1 may be, for example, 0 or more and 0.15 or less. The first semiconductor layer 10 is, for example, a GaN layer. The composition ratio x2 may be, for example, more than 0.15 and 0.3 or less. The second semiconductor layer 20 is, for example, an AlGaN layer.

[0035] The first semiconductor layer 10 is provided between the third layer 13 and the second semiconductor layer 20. The first semiconductor layer 10 is provided between the fourth layer 14 (see FIG. 1) and the second semiconductor layer 20.

[0036] The second direction D2 from the first electrode 51 to the second electrode 52 intersects the first direction D1. The second direction D2 is, for example, the X-axis direction. The position of the third electrode 53 in the second direction D2 is between the position of the first electrode 51 in the second direction D2 and the position of the second electrode 52 in the second direction D2.

[0037] The second semiconductor layer 20 includes a first semiconductor portion 21 and a second semiconductor portion 22. The direction from the first semiconductor portion 21 to the second semiconductor portion 22 is along the second direction D2. The first electrode 51 is electrically connected to the first semiconductor portion 21. The second electrode 52 is electrically connected to the second semiconductor portion 22.

[0038] The current flowing between the first electrode 51 and the second electrode 52 is controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be, for example, a potential based on the potential of the first electrode 51. The first electrode 51 functions as, for example, a source electrode. The second electrode 52 functions as a drain electrode. The third electrode 53 functions as a gate electrode. The semiconductor device 110 is, for example, a transistor.

[0039] The first semiconductor layer 10 includes a region facing the second semiconductor layer 20. A carrier region is formed in this region. The carrier region is, for example, a two-dimensional electron gas. The semiconductor device 110 is, for example, a HEMT (High Electron Mobility Transistor).

[0040] In the semiconductor device 110 according to the embodiment, for example, cracks are suppressed. According to the embodiment, it is possible to provide a semiconductor device that can obtain stable characteristics.

[0041] As shown in FIG. 6, in this example, at least a portion of the third electrode 53 is provided between the first semiconductor portion 21 and the second semiconductor portion 22 in the second direction D2. The third electrode 53 is, for example, a recessed gate electrode. For example, a high threshold voltage is obtained. For example, normally-off operation is obtained. At least a portion of the third electrode 53 may be provided between a portion of the first semiconductor layer 10 and another portion of the first semiconductor layer 10 in the second direction D2.

[0042] For example, the first semiconductor layer 10 includes a first partial region 10a, a second partial region 10b, a third partial region 10c, a fourth partial region 10d, and a fifth partial region 10e. The direction from the first partial region 10a to the first electrode 51 is along the first direction D1. The direction from the second partial region 10b to the second electrode 52 is along the first direction D1. The direction from the third partial region 10c to the third electrode 53 is along the first direction D1.

[0043] The position of the fourth partial region 10d in the second direction D2 is between the position of the first partial region 10a in the second direction D2 and the position of the third partial region 10c in the second direction D2. The position of the fifth partial region 10e in the second direction D2 is between the position of the third partial region 10c in the second direction D2 and the position of the second partial region 10b in the second direction D2.

[0044] The direction from the fourth partial region 10d to the first semiconductor portion 21 is along the first direction D1. The direction from the fifth partial region 10e to the second semiconductor portion 22 is along the first direction D1. In this example, a portion of the third electrode 53 is located between the fourth partial region 10d and the fifth partial region 10e in the second direction D2. A high threshold voltage is obtained. For example, normally-off operation is stably achieved.

[0045] 6, the semiconductor device 110 may further include a first insulating member 41. The first insulating member 41 includes a first insulating portion 41p. The first insulating portion 41p is provided between the third electrode 53 and the nitride member 10M. The first insulating portion 41p functions as, for example, a gate insulating film.

[0046] FIG. 7 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. 7, the semiconductor device 111 according to the embodiment includes the wafer 210 according to the first embodiment, a nitride member 10M, a first electrode 51, a second electrode 52, and a third electrode 53. In the semiconductor device 111, the third electrode 53 does not overlap with the second semiconductor layer 20 in the second direction D2. Except for this, the configuration of the semiconductor device 111 may be similar to that of the semiconductor device 110.

[0047] For example, normally-on operation is obtained in the semiconductor device 111. The first insulating member 41 may be omitted in the semiconductor device 111. The semiconductor device 111 may be used as, for example, a high-frequency switching element.

[0048] In an embodiment, information regarding the shape of the nitride region, etc. can be obtained, for example, by electron microscope observation. Information regarding the composition and elemental concentration in the nitride region can be obtained, for example, by EDX (Energy Dispersive X-ray Spectroscopy), or SIMS (Secondary Ion Mass Spectrometry), etc. Information regarding the composition in the nitride region may be obtained, for example, by reciprocal lattice space mapping, etc.

[0049] The embodiment may include the following technical solutions. (Technical Solution 1) A substrate, Al z1 Ga 1-z1 A first layer containing N (0 < z1 ≤ 1), Comprising, The first layer includes a first region and a second region, The first region is between the substrate and the second region, The oxygen concentration in the first region in the first region is lower than the oxygen concentration in the substrate in the substrate, The oxygen concentration in the first region is lower than the oxygen concentration in the second region in the second region, a wafer.

[0050] (Technical Solution 2) The oxygen concentration in the second region is lower than the oxygen concentration in the substrate, the wafer according to Technical Solution 1.

[0051] (Technical Solution 3) The first region is in contact with the substrate, The second region is in contact with the first region, the wafer according to Technical Solution 1 or 2.

[0052] (Technical Solution 4) The substrate includes silicon, the wafer according to Technical Solution 3.

[0053] (Technical Solution 5) The oxygen concentration in the first region is 1×10 16 cm -3 or more and 5×10 17 [[ID=-3 A wafer according to any one of Technical Solutions 1 to 4, as follows.

[0054] (Technical Solution 6) The oxygen concentration in the second region is 1×10 17 cm -3 or more and 1×10 18 cm -3 or less. A wafer according to Technical Solution 5.

[0055] (Technical Solution 7) The oxygen concentration in the substrate is 1×10 18 cm -3 or more and 1×10 20 cm -3 or less. A wafer according to any one of Technical Solutions 1 to 6.

[0056] (Technical Solution 8) The thickness of the first layer of the first layer is 100 nm or more and 200 nm or less. A wafer according to any one of Technical Solutions 1 to 7.

[0057] (Technical Solution 9) The thickness of the first region of the first region is 50 nm or more and 100 nm or less. A wafer according to Technical Solution 8.

[0058] (Technical Solution 10) The thickness of the second region of the second region is 50 nm or more and 100 nm or less. A wafer according to Technical Solution 9.

[0059] (Technical Solution 11) Al z2 Ga 1-z2 Further comprising a second layer containing N(0 < z2 < 1, z2 < z1), The first layer is provided between the substrate and the second layer, The second layer does not contain oxygen, or the oxygen concentration in the second layer is lower than the oxygen concentration in the second region. A wafer according to any one of Technical Solutions 1 to 10.

[0060] (Technical Solution 12) The wafer according to Technical Proposal 11, wherein the oxygen concentration of the second layer is lower than the oxygen concentration of the first region.

[0061] (Technical Proposal 13) Al z3 Ga 1-z3 Further comprising a third layer containing N(0≦z3≦1), The second layer is between the first layer and the third layer, The wafer according to Technical Proposal 11 or 12, wherein the third layer does not contain oxygen or the oxygen concentration of the third layer in the third layer is lower than the oxygen concentration of the second region.

[0062] (Technical Proposal 14) The wafer according to Technical Proposal 13, wherein the oxygen concentration of the third layer is lower than the oxygen concentration of the first region.

[0063] (Technical Proposal 15) The third layer includes a plurality of first films and a plurality of second films, In the first direction from the substrate to the first layer, one of the plurality of first films is between one of the plurality of second films and another one of the plurality of second films, and the one of the plurality of second films is between the one of the plurality of first films and another one of the plurality of first films, The plurality of first films include Al y1 Ga 1-y1 Containing N(0<y1≦1), The plurality of second films include Al y2 Ga 1-y2 Containing N(0≦y2<y1), the wafer according to Technical Proposal 13 or 14.

[0064] (Technical Proposal 16) Al z4 Ga 1-z4 Further comprising a fourth layer containing N(0≦z4≦1), The third layer is between the second layer and the fourth layer, The wafer according to any one of Technical Proposals 13 to 15, wherein the fourth layer does not contain oxygen or the oxygen concentration of the fourth layer in the fourth layer is lower than the oxygen concentration of the second region.

[0065] (Technical Proposal 17) Al x1 Ga 1-x1 A first semiconductor layer containing N(0≦x1<1), Al x2 Ga 1-x2 A second semiconductor layer containing N(0<x2≦1, x1<x2), further comprising The wafer according to any one of Technical Proposals 13 to 16, wherein the first semiconductor layer is provided between the third layer and the second semiconductor layer.

[0066] (Technical Proposal 18) The wafer according to any one of Technical Proposals 1 to 12, a first electrode, a second electrode, a third electrode, Al x1 Ga 1-x1 A first semiconductor layer containing N(0≦x1<1), Al x2 Ga 1-x2 A second semiconductor layer containing N(0<x2≦1, x1<x2), comprising The first semiconductor layer is provided between the first layer and the second semiconductor layer, A second direction from the first electrode to the second electrode intersects a first direction from the substrate to the first layer, A position of the third electrode in the second direction is between a position of the first electrode in the second direction and a position of the second electrode in the second direction,[[ID=5l]] The second semiconductor layer includes a first semiconductor portion and a second semiconductor portion,[[ID=5l]] A direction from the first semiconductor portion to the second semiconductor portion is along the second direction, The first electrode is electrically connected to the first semiconductor portion, The second electrode is electrically connected to the second semiconductor portion, a semiconductor device.

[0067] (Technical Proposal 19) The semiconductor device described in Technical Proposal 18, wherein at least a portion of the third electrode is provided between the first semiconductor portion and the second semiconductor portion in the second direction.

[0068] (Technical proposal 20) The semiconductor device described in Technical Proposal 18, wherein at least a portion of the third electrode is provided between a portion of the first semiconductor layer and another portion of the first semiconductor layer in the second direction.

[0069] According to the embodiment, it is possible to provide a wafer and a semiconductor device that can obtain stable characteristics.

[0070] In this specification, "electrically connected" includes a state in which multiple conductors are physically in contact with each other and a current flows between these multiple conductors. "Electrically connected" also includes a state in which multiple conductors are connected to each other and a current flows between these multiple conductors.

[0071] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of the elements included in the wafer and semiconductor device, such as the substrate, layers, and electrodes, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from known ranges.

[0072] Furthermore, any combination of two or more elements of each specific example within the scope of technical feasibility is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0073] In addition, all wafers and semiconductor devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the wafers and semiconductor devices described above as embodiments of the present invention also fall within the scope of the present invention, as long as they include the gist of the present invention.

[0074] In addition, within the scope of the concept of the present invention, a person skilled in the art may come up with various modifications and alterations, and these modifications and alterations are also considered to fall within the scope of the present invention.

[0075] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0076] 10, 20: first and second semiconductor layers, 10M: nitride member, 10a-10e: first to fifth partial regions, 11-14: first to fourth layers, 11a, 11b: first and second regions, 13a, 13b: first and second films, 18s: base, 21, 22: first and second semiconductor portions, 41: first insulating member, 41p: first insulating portion, 51-53: first to third electrodes, 110, 111: semiconductor device, 210, 211: wafer, C(Al): count number, C(O): oxygen concentration, C11a, C11b: first and second region oxygen concentrations, C12 to C14: second to fourth layer oxygen concentrations, C18s: substrate oxygen concentration, D1, D2: first and second directions, SPL1, SPL2: first and second samples, pZ: position, t1, t2: first and second region thicknesses, tr1, tr2: first and second layer thicknesses

Claims

1. a substrate; Al ｚ１ Ga １－ｚ１ a first layer including N (0<z1≦1); Equipped with the first layer includes a first region and a second region; the first region is between the substrate and the second region, a first region oxygen concentration in the first region is lower than a substrate oxygen concentration in the substrate; The first region oxygen concentration is lower than the second region oxygen concentration in the second region.

2. 2. The wafer according to claim 1, wherein the second region oxygen concentration is lower than the substrate oxygen concentration.

3. the first region is in contact with the substrate, The wafer according to claim 1 , wherein the second region is in contact with the first region.

4. The wafer of claim 3 , wherein the substrate comprises silicon.

5. Al ｚ２ Ga １－ｚ２ a second layer including N (0<z2<1, z2<z1); the first layer is provided between the substrate and the second layer, The wafer according to claim 1 , wherein the second layer does not contain oxygen, or the second layer oxygen concentration in the second layer is lower than the second region oxygen concentration.

6. Al ｚ３ Ga １－ｚ３ N (0≦z3≦1), the second layer is between the first layer and the third layer; The wafer according to claim 5 , wherein the third layer does not contain oxygen, or the third layer oxygen concentration in the third layer is lower than the second region oxygen concentration.

7. the third layer includes a plurality of first films and a plurality of second films; In a first direction from the substrate to the first layer, one of the plurality of first films is between one of the plurality of second films and another one of the plurality of second films, and the one of the plurality of second films is between the one of the plurality of first films and another one of the plurality of first films; The plurality of first films are Al ｙ１ Ga １－ｙ１ N (0<y1≦1), The plurality of second films are Al ｙ２ Ga １－ｙ２ 7. The wafer of claim 6, comprising N (0≦y2<y1).

8. A wafer according to any one of claims 1 to 5; A first electrode; A second electrode; A third electrode; Al ｘ１ Ga １－ｘ１ a first semiconductor layer including N (0≦x1<1); Al ｘ２ Ga １－ｘ２ a second semiconductor layer including N (0<x2≦1, x1<x2); Equipped with the first semiconductor layer is provided between the first layer and the second semiconductor layer, a second direction from the first electrode to the second electrode intersects with a first direction from the substrate to the first layer; a position of the third electrode in the second direction is between a position of the first electrode in the second direction and a position of the second electrode in the second direction; the second semiconductor layer includes a first semiconductor portion and a second semiconductor portion; a direction from the first semiconductor portion to the second semiconductor portion is along the second direction; the first electrode is electrically connected to the first semiconductor portion; The second electrode is electrically connected to the second semiconductor portion.

9. The semiconductor device according to claim 8 , wherein at least a portion of the third electrode is provided between the first semiconductor portion and the second semiconductor portion in the second direction.

10. The semiconductor device according to claim 8 , wherein at least a portion of said third electrode is provided between a portion of said first semiconductor layer and another portion of said first semiconductor layer in said second direction.

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