Pixel coupling

Abstract

To provide a focal plane array (FPA) and a readout integrated circuit (ROIC) suitable for low light level (LLL) imaging.SOLUTION: An imaging system comprises: a focal plane array (FPA) comprising a plurality of photodiodes; a pixel circuitry array (PCA) comprising a plurality of transistors, where an input node of a transistor of the plurality of transistors is connected to each photodiode collection node of the FPA; and biasing circuitry. The biasing circuitry is configured to: selectively bias a first portion of the plurality of transistors into an inactive configuration; reverse-bias a substrate of each transistor of the first portion of the plurality of transistors; selectively bias a second portion of the plurality of transistors into an active configuration; and reverse-bias the shared substrate to a different reverse bias than the reverse bias of each transistor substrate of the first portion of the plurality of transistors.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure, in some embodiments thereof, relates to optical detection using focal plane arrays (FPAs) and readout integrated circuits (ROICs), and more particularly, but not exclusively, to low light level (LLL) imaging using FPAs and ROICs. [Background technology]

[0002] Acknowledgment of the above references herein should not be inferred as meaning that they are in any way relevant to the patentability of the presently disclosed subject matter. Summary of the Invention

[0003] Example 1. An imaging system, a focal plane array (FPA) comprising a plurality of photodiodes hosted by a shared substrate, each photodiode having a collection node; a pixel circuitry array (PCA) including a plurality of transistors, an input node of one of the plurality of transistors being connected to each photodiode collection node of the FPA; and A bias circuit, Selectively biasing a first portion of the plurality of transistors to an inactive configuration; reverse biasing a substrate of each transistor of a first portion of the plurality of transistors; and Selectively biasing a second portion of the plurality of transistors into an active configuration; and a bias circuit configured to reverse bias the shared substrate to a reverse bias that is different from the reverse bias of each transistor substrate of the first portion of the plurality of transistors.

[0004] Example 2. The imaging system of claim 1, wherein each transistor in the second portion injects a photocurrent signal received from a photodiode collection node connected remotely from the transistor.

[0005] Example 3. The imaging system of claim 2, wherein photocurrent injection in the second portion of the transistor prevents charge buildup in a photodiode connected to the second portion of the transistor.

[0006] Example 4. The imaging system of any one of claims 2-3, wherein photocurrent injection of the transistors of the second portion maintains reverse bias of the shared substrate.

[0007] Example 5. The imaging system of any one of claims 1 to 4, wherein the FPA is hosted by an FPA wafer and the PCA is hosted by a PCA wafer that is a different wafer from the FPA wafer.

[0008] Example 6. The imaging system of claim 5, wherein the FPA wafer comprises a direct bandgap material.

[0009] Example 7. The imaging system according to any one of claims 5 to 6, wherein the FPA wafer has a heterostructure.

[0010] Example 8. The imaging system of claim 7, wherein the photodiode collection node comprises a material having a wider bandgap than the shared substrate.

[0011] Example 9. The imaging system of any one of claims 1 to 8, wherein the photodiode is an infrared detection photodiode having a photon absorption region comprising InGaAs, InSb, or HgCdTe.

[0012] Example 10. The imaging system of any one of claims 5 to 9, wherein the PCA wafer comprises silicon and the plurality of transistors comprises metal oxide semiconductor field effect transistors (MOSFETs).

[0013] Example 11. The imaging system according to any one of claims 1 to 10, further comprising a plurality of connectors, each of the transistors being connected to a corresponding one of the plurality of photodiodes by one of the plurality of connectors.

[0014] Example 12. The imaging system of claim 11, wherein the plurality of connectors comprises one of copper-to-copper connections and indium bumps.

[0015] Example 13. An imaging system as described in any one of claims 1 to 11, wherein photodiodes in a first portion of the FPA associated with transistors in the first portion are spatially interspersed on the FPA with photodiodes in a second portion of the FPA associated with transistors in the second portion, and each active transistor in the second portion collects photocurrent from photodiodes in the second portion and at least one photodiode in the first portion.

[0016] Example 14. The imaging system of claim 13, wherein for at least a portion of the FPA, the photodiodes of the first portion and the photodiodes of the second portion are evenly distributed, and each active transistor of the second portion collects photocurrent from an equal number of photodiodes of the first portion.

[0017] Example 15. Each of the photodiodes is connected to an input node of one of the plurality of transistors; 15. The imaging system of claim 1, wherein the substrate of the transistor of the first portion is reverse biased to reverse bias the input node to prevent leakage of charge from the input node of the transistor of the first portion to the substrate.

[0018] Example 16. The imaging system of claim 15, wherein the substrates of the transistors in the second portion are reverse biased.

[0019] Example 17. The photodiode and transistor are implemented in a p-type configuration. The substrate of the photodiode is reverse biased to a reverse bias voltage Vdetcom, and 17. The imaging system according to claim 15, wherein a substrate of the transistor in the first portion is reverse biased to a voltage Vhigh that is higher than a reverse bias voltage Vdetcom of the photodiode, where Vhigh>Vdetcom.

[0020] Example 18. An imaging system as described in any one of claims 12 to 17, wherein the bias circuit is configured to deactivate the transistors of the first portion by biasing the switching terminals of the transistors of the first portion to a deactivation voltage, and to activate the transistors of the second portion by biasing the switching terminals of the transistors of the second portion to an activation voltage different from the deactivation voltage.

[0021] Example 19. An imaging system as described in any one of claims 12 to 17, wherein the PCA comprises a plurality of rows of pixel circuits, the switching terminals of the transistors of the pixel circuits of each row of the pixel circuit array are biased to the same voltage, and the first portion comprises at least one row of the pixel circuit array.

[0022] Example 20. A PCA includes a plurality of rows of pixel circuits, and the pixel circuits of one or more rows of the pixel circuit array include a plurality of bias lines for biasing switching terminals of different transistors of the row to different voltages; and 18. The imaging system according to claim 12, wherein the bias circuit is configured to supply different bias voltages to at least two of the plurality of bias lines.

[0023] Example 21. Different bias voltages are an activation voltage for biasing a portion of the transistors in one or more rows into an active configuration; and a deactivation voltage that biases a portion of the transistors in one or more rows into an inactive configuration.

[0024] Example 22. The imaging system according to any one of claims 18 to 21, wherein the transistor is a field effect transistor (FET), and the switching terminal is a gate of the FET.

[0025] Example 23. The imaging system according to any one of claims 18 to 21, wherein the transistor is a bipolar junction transistor (BJT) and the switching terminal is the base of the BJT.

[0026] Example 24. The imaging system according to any one of claims 12 to 23, wherein each pixel circuit includes a readout circuit.

[0027] Example 25. The imaging system of claim 24, wherein the readout circuit includes an integration capacitor connected to the transistor of each pixel circuit and configured to store the charge received via the transistor.

[0028] Example 26. The imaging system according to any one of claims 24 to 25, wherein the readout circuitry includes a charge trans-impedance amplifier (CTIA).

[0029] Example 27. The imaging system of any one of claims 24 to 25, wherein the readout circuitry includes a direct injection (DI) readout circuitry.

[0030] Example 28: The readout circuit comprises: Buffer direct injection (BDI) readout circuitry, a source-follower per detector (SFD) readout circuit, Gate-modulation input (GMI) readout circuit, a shared-buffered direct injection (SBDI) readout circuit, or 26. The imaging system of claim 24, further comprising one of: a switch current integration (SCI) readout circuit.

[0031] Example 29. The imaging system of any one of claims 12 to 28, comprising a processing circuit configured to receive image data from a PCA, the processing circuit having a number less than the number of pixels.

[0032] Example 30. An imaging method for using a focal plane array (FPA) having a plurality of photodiodes hosted by a shared substrate and a pixel circuit array (PCA) coupled to the FPA and having a plurality of transistors, a transistor corresponding to each photodiode of the FPA, the method comprising: selecting a first portion of the plurality of transistors as inactive transistors and a second portion of the plurality of transistors as active transistors; biasing the first partial transistor in an inactive configuration and the second partial transistor in an active configuration; reverse biasing the shared substrate to reverse bias a photodiode connected to the transistor of the second portion; reverse biasing a substrate of each transistor of a first portion of the plurality of transistors to a reverse bias different from the reverse bias of the shared substrate; and and acquiring one or more images using the FPA and the PCA.

[0033] Example 31. The method of claim 30, wherein biasing includes reverse biasing a substrate of the first portion transistor to a stronger reverse bias than the reverse bias of the shared substrate of the photodiode to prevent charge leakage from the first portion transistor to the substrate.

[0034] Example 32. The FPA and PCA are implemented in a p-type configuration, and reverse biasing includes biasing the photodiode to a voltage Vdetcom; 32. The method of claim 31 , wherein reverse-biasing the substrate comprises biasing the substrate to a voltage Vhigh, where Vhigh>Vdetcom.

[0035] Example 33. The method of any one of claims 30-32, wherein biasing includes biasing switching terminals of the transistors of the first portion to a deactivation voltage and biasing switching terminals of the transistors of the second portion to an activation voltage that is higher than the deactivation voltage.

[0036] Example 34. The method of any one of claims 30-33, wherein selecting includes selecting active transistors spatially interspersed with inactive transistors.

[0037] Example 35. Selecting the first portion includes selecting one or more rows of the PCA; and 35. The method of any one of claims 30 to 34, wherein biasing comprises biasing one or more rows of transistors in an inactive configuration.

[0038] Example 36. The method of any one of claims 30 to 35, wherein acquiring includes accumulating charge in an integrator circuit of a pixel circuit associated with an active transistor of the PCA.

[0039] Example 37. The method of claim 36, wherein acquiring includes reading out and amplifying the charge through readout circuitry of a pixel circuit associated with the active transistor.

[0040] Example 38: An imaging system, 1. A pixel array comprising: a focal plane array (FPA) comprising a plurality of photodiodes hosted by a shared substrate, each photodiode having a collection node; a pixel circuit array (PCA) comprising a plurality of pixel circuits, each pixel circuit having an input node electrically connected to a collection node of a photodiode; a readout circuit; A bias circuit, Disconnecting an input node of a first portion of the pixel circuit from the readout circuit; connecting an input node of the second portion of the pixel circuit to a readout circuit; and and a bias circuit configured to maintain accumulated charge at input nodes of the first portion of pixels to forward bias the photodiodes of the first portion.

[0041] Example 39. The imaging system of any one of claims 1 to 29, wherein the different reverse bias is a stronger reverse bias.

[0042] Below is a non-exhaustive list of some exemplary embodiments of the present disclosure. The present disclosure also includes embodiments including fewer than all of the features of an example, and embodiments that use features from multiple examples, even if not listed below.

[0043] Unless otherwise defined, all technical and / or scientific terms used herein have the meaning commonly understood by one of ordinary skill in the art to which this disclosure belongs. Methods and / or materials similar or equivalent to those described herein can be used in the practice and / or testing of embodiments of the present disclosure, and exemplary methods and / or materials are described below. With regard to the exemplary embodiments described below, the materials, methods, and examples are illustrative and are not intended to be necessarily limiting.

[0044] Some embodiments of the present disclosure may be embodied as a system, a method, or a computer program product. For example, some embodiments of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which may be referred to generally herein as a "circuit," "module," and / or "system."

[0045] Implementation of the methods and / or systems of some embodiments of the present disclosure may include performing and / or completing selected tasks manually, automatically, or a combination thereof. Depending on the actual instrumentation and / or equipment of some embodiments of the methods and / or systems of the present disclosure, some selected tasks may be implemented by hardware, software, or firmware, and / or a combination thereof, for example, using an operating system.

[0046] For example, hardware for performing selected tasks according to some embodiments of the present disclosure may be implemented as a chip or circuit. As software, selected tasks according to some embodiments of the present disclosure may be implemented as a plurality of software instructions executed by a computing device using, for example, any suitable operating system.

[0047] In some embodiments, one or more tasks according to some exemplary embodiments of the methods and / or systems described herein are performed by a data processor, such as a computing platform, for executing a plurality of instructions. Optionally, the data processor includes volatile memory for storing instructions and / or data, and / or non-volatile storage, e.g., for storing instructions and / or data. Optionally, a network connection is also provided. A user interface, e.g., a display and / or user input device, is optionally provided.

[0048] Some embodiments of the present disclosure may be described below with reference to flowchart diagrams and / or block diagrams. For example, exemplary methods and / or apparatus (systems) and / or computer program products according to embodiments of the present disclosure are shown. It will be understood that each step of the flowchart diagrams and / or blocks of the block diagrams, and / or combinations of steps of the flowchart diagrams and / or blocks of the block diagrams, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executing on the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more of the flowchart steps and / or block diagram blocks.

[0049] These computer program instructions may also be stored on a computer-readable medium that can instruct a computer (e.g., in memory, locally and / or cloud-hosted), other programmable data processing apparatus, or other device to function in a particular manner, such that the instructions stored on the computer-readable medium can be used to produce an article of manufacture including instructions that implement the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0050] Computer program instructions may also be executed by one or more computing devices to cause a series of operational steps to be performed on the computing device, other programmable apparatus, and / or other device to generate a computer-implemented process, such that the executing instructions provide a process for implementing the function(s) / act(s) specified in one or more blocks of the flowcharts and / or block diagrams.

[0051] Some of the methods described herein are generally designed for use by computers only and may not be feasible and / or practical for purely manual execution by a human expert. A human expert wishing to perform a similar task manually may be expected to use a different method, for example, one that takes advantage of specialized knowledge and / or the pattern recognition capabilities of the human brain, that is potentially more efficient than manually performing the steps of the methods described herein. [Brief explanation of the drawings]

[0052] In order to better understand the subject matter disclosed herein, and to illustrate how it may be carried out in practice, embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which: [Figure 1] 1 is a simplified schematic diagram of a portion of an imaging system according to some embodiments of the present disclosure. [Figure 2] 1 is a detection method according to some embodiments of the present disclosure. [Figure 3A] FIG. 2 is a simplified schematic diagram of a portion of an FPA and an ROIC, according to some embodiments of the present disclosure. [Figure 3B] FIG. 1 is a simplified schematic diagram of a portion of a PCA of an ROIC, according to some embodiments of the present disclosure. [Figure 3C] FIG. 1 is a simplified schematic diagram of a portion of a PCA of an ROIC, according to some embodiments of the present disclosure. [Figure 4] 1 is a simplified schematic cross-sectional view of a portion of a detector array and an ROIC according to some embodiments of the present disclosure. [Figure 5] 1 is a simplified schematic cross-sectional view of a portion of a detector array and an ROIC according to some embodiments of the present disclosure. [Figure 6] FIG. 2 is a simplified schematic diagram of a portion of the circuitry of an imaging system according to some embodiments of the present disclosure. [Figure 7A] 1 is a simplified diagram of an exemplary readout circuit according to some embodiments of the present disclosure. [Figure 7B]1 is a simplified diagram of an exemplary readout circuit according to some embodiments of the present disclosure. [Figure 8] 1 is a simplified schematic diagram of a portion of an imaging system according to some embodiments of the present disclosure. [Figure 9A] FIG. 1 is a simplified schematic diagram illustrating the layout of active and inactive pixels of an imaging system portion, according to some embodiments of the present disclosure. [Figure 9B] FIG. 1 is a simplified schematic diagram illustrating the layout of active and inactive pixels of an imaging system portion, according to some embodiments of the present disclosure. [Figure 9C] FIG. 1 is a simplified schematic diagram illustrating the layout of active and inactive pixels of an imaging system portion, according to some embodiments of the present disclosure. [Figure 10A] FIG. 1 is a simplified schematic band diagram according to some embodiments of the present disclosure. [Figure 10B] FIG. 1 is a simplified schematic band diagram according to some embodiments of the present disclosure. [Figure 11A] FIG. 1 is a simplified schematic band diagram according to some embodiments of the present disclosure. [Figure 11B] FIG. 1 is a simplified schematic band diagram according to some embodiments of the present disclosure.

[0053] In some embodiments, but not by way of limitation, in different figures, like numerals are used to refer to like elements, for example, element 102 in FIG. 1 corresponding to element 302 in FIG. 3A. DETAILED DESCRIPTION OF THE INVENTION

[0054] The present disclosure, in some embodiments thereof, relates to optical detection using focal plane arrays (FPAs) and readout integrated circuits (ROICs), and more particularly, but not exclusively, to low light level (LLL) imaging using FPAs and ROICs.

[0055] [overview] A broad aspect of some embodiments of the present invention relates to increasing the effective pixel pitch of a focal plane array (FPA) that includes an array of photodiodes hosted by a shared substrate by switching off a portion of the photodiodes (referred to herein as the "first portion"), such that the first portion of the photodiodes become "inactive" and photocarriers generated in the shared substrate, including in areas of the inactive photodiodes, are collected by the active photodiodes.

[0056] In some embodiments, inactive photodiodes accumulate charge at their collection nodes (and / or elements electrically connected to these collection nodes accumulate charge). The accumulation of charge carriers at the collection nodes of deactivated photodiodes can repel photocurrent, including, for example, photocurrent generated in regions of the substrate associated with the deactivated photodiodes. The repelled carriers are then collected by active photodiodes in the shared substrate, e.g., they migrate to the collection nodes of the active photodiodes. In some embodiments, charge accumulates at the inactive photodiode collection nodes because the flow of charge carriers from the photodiode collection nodes is prevented.

[0057] In some embodiments, the FPA is part of an imaging system that includes multiple pixel circuits in a pixel circuit array (PCA), and each photodiode in the FPA is connected to an associated pixel circuit in the PCA. The photodiode and pixel circuit together are referred to herein as a "pixel unit." In some embodiments, at least a portion of the charge carriers (referred to herein as "photocarriers," specifically "photoholes" and "photoelectrons") generated by incident photons in the photodiode are associated with an inactive photodiode and pass through the pixel circuit of the active photodiode for detection. Generally, references to "photocarriers" herein refer to minority carriers in the photon absorption layer or substrate (e.g., holes in an n-type system and electrons in a p-type system). In an exemplary embodiment, the photon absorption layer (PAL) is n-type, the material is doped with donor impurities to make electrons the majority carriers and holes the photo-generated minority carriers, and charge transport relies on minority carrier (hole) collection.

[0058] In some embodiments, the FPA is configured to detect infrared (IR) light, and the materials of the FPA include III-V materials, II-VI materials, and other compound semiconductors. In some embodiments, the FPA includes III-V materials, which consist of elements from groups III and V of the periodic table, and potential advantages include the availability of tunable electronic properties and / or direct bandgap composition.

[0059] One aspect of some embodiments of the present disclosure relates to the injection of photocurrent that reaches the collection node of a photodiode through a transistor of an associated pixel circuit. The collection node of the photodiode may be connected (e.g., via a connector) to the input node of the transistor of the respective pixel circuit. In some embodiments, the transistor of the pixel circuit corresponding to an inactive photodiode is switched off, preventing current flow from the input node (and photodiode collection node), the transistor input node, and the collection node of the photodiode that accumulates charge. The transistor and pixel circuit associated with an inactive photodiode are referred to herein as the inactive transistor and inactive pixel circuit, respectively.

[0060] In some embodiments, photocarriers are not stored in the collection node of the active pixel, but are injected (continuously flowing) through the active pixel circuitry into a storage element (e.g., an integration capacitor). A potential advantage is that the signal photocurrent does not remain at the active photodiode collection node. This may maintain the state (e.g., potential) experienced by the generated photocurrent, which continues to be repelled by the inactive photodiode collection node and / or attracted by the active photodiode collection node.

[0061] For example, as opposed to charge that can accumulate on the collection node of an active photodiode (e.g., due to periodic discharge to provide a readout signal), a potential advantage is that the voltage across the active photodiode is maintained and does not change during the integration process, e.g., during the readout time. This is particularly advantageous when the photodiode is formed of a low resistivity material (e.g., a III-V material) and changes in the photodiode voltage can result in large dark currents and / or nonlinear amplification of the signal current.

[0062] An aspect of some embodiments of the present invention relates to biasing a first portion of transistors of a pixel circuit of a PCA "off," also referred to as an "inactive" configuration, and biasing a second portion of transistors of the pixel circuit of the PCA "on," also referred to as an "active" configuration. The transistors of the pixel circuit are each disposed in a current path between a respective photodiode and a detection circuit. In some embodiments, the transistors are FETs (field effect transistors), e.g., MOSFETs (metal oxide silicon FETs), and the active transistors are biased to establish a channel between their source and drain.

[0063] A potential advantage of switching off portions of the pixel circuit and detecting the photocurrent generated by multiple photodiodes in a single pixel circuit is the efficient summation of the detected charge in the photodiodes, with less noise introduced into the detected signal associated with the summation. For example, the only noise associated with detecting photocarriers is the noise associated with passing through the components of a single pixel circuit. For example, the thermal noise of a single integrating capacitor is added to the photocurrent signal of multiple photodiodes.

[0064] Here, the noise may be lower compared to summing techniques implemented in either the analog or digital domain, such as adding detection signals from multiple pixels by connecting photodiodes in parallel or integrating capacitors in pixel circuits in parallel, and adding detection signals from multiple pixels by reading them out and converting them to analog-to-digital (ADC).

[0065] Without being bound by theory, it is theorized that, assuming that the noise sources of different pixels are statistically independent, summing of signals (e.g., using the summation technique described in the previous paragraph) will also sum the noise variance. If the noise can be approximated by the pixel variance, then the total variance of the summed signals will be multiplied by 1 / N by the summation (where N is the number of pixels whose measurements are summed). If the signal is approximated by the mean of the measurements and the noise is approximated by the standard deviation, where the standard deviation is the square root of the variance, then the summation will be multiplied by the square root of the number of pixels summed.

[0066]

number

[0067] Furthermore, the summation reduces the read noise floor by the same factor

[0068]

number

[0069] In contrast, summing the detected signals by biasing inactive pixel units to effectively sum the signals in the active pixel units does not increase read noise and is theorized to potentially improve SNR, for example, for low light levels where read noise may be significant relative to the signal.

[0070] When higher light levels are being detected (e.g., when readout noise is less important and / or can be ignored), biasing the inactive pixel units for the same period of time could, in theory, provide a larger detected signal on the integration capacitor of the active pixel units, potentially allowing for an increase in imaging frame rate (e.g., the capacitor would have a higher charge and could be read / discharged more frequently).

[0071] In some embodiments, an active pixel unit (and associated pixel circuitry including transistors) is adjacent to an inactive pixel unit, and the area of ​​the FPA associated with both the active pixel unit and the adjacent inactive pixel unit forms an enlarged detector pixel area (e.g., active photodiodes are evenly distributed over at least one area of ​​the FPA, which then effectively has an enlarged pixel pitch).

[0072] An aspect of some embodiments of the present invention relates to preventing leakage of accumulated charge from the collection node of an inactive photodiode and the input node of an associated transistor. A potential advantage is improved accuracy of the detection signal provided by the active pixel unit. In some embodiments, leakage is prevented by biasing the substrate of the input node of the inactive pixel circuit.

[0073] In some embodiments, the pixel circuit is separate from the photodiode, the photodiode may be hosted by a different material than the pixel circuit, and / or the material properties of the photodiode and the input node may be different.

[0074] In an exemplary embodiment, the photodiodes and pixel circuits are hosted by different wafers, and each photodiode is connected to the pixel circuit (its input node) by a connector. In some embodiments, the photodiodes and pixel circuits are hosted by wafers formed from different materials, for example, the pixel circuit is on a silicon wafer and the photodiode is on a III-V material substrate.

[0075] In some embodiments, the separation between the pixel circuit and the photodiode enables and / or facilitates the implementation of different biasing of the substrates of the pixel circuit and the photodiode, e.g., enabling a different biasing of the input node of the inactive pixel circuit (e.g., different from the biasing of the photodiode) to prevent leakage of stored charge.

[0076] A potential advantage of separating the photodiode from the pixel circuitry is that noise associated with parasitic light is reduced (e.g., eliminated), where photocurrent is generated in non-photodiode structures (e.g., pn junctions associated with the pixel circuitry).

[0077] In some embodiments, the input node of the active pixel is biased with what may be referred to as an "increased reverse bias magnitude," or a "higher reverse voltage magnitude," or a "stronger reverse bias" compared to the bias voltage applied to the photodiode substrate to reverse bias the photodiode. In a p-type system (also called a "p-on-n system" where the transistor and photodiode are formed on an n-type substrate), the stronger reverse bias involves applying a voltage to the n-type substrate of the inactive transistor that is more positive than the voltage applied to the n-type photodiode substrate. In an n-type system (also called an "n-on-p system" where the transistor and photodiode are formed on an n-type substrate), the stronger reverse bias involves applying a voltage to the p-type substrate of the inactive transistor that is more negative than the voltage applied to the p-type photodiode substrate.

[0078] A potential benefit of this stronger reverse bias on the inactive transistor substrate is to prevent leakage of accumulated charge from the inactive pixel units without adversely changing the bias of the photodiodes of the FPA, which may be selected for optimal light detection, for example. The biasing of the input nodes of the inactive pixel unit transistors may be understood as preventing accumulated charge (such as that received from the collection node of the inactive photodiode) from forward biasing the junction between the input node and its substrate.

[0079] The ability to reduce leakage without changing the bias of the photodiode can be particularly advantageous when the photodiode is hosted by a material with lower resistivity and / or a higher tendency for dark current (e.g., associated with higher levels of impurities and / or crystalline non-idealities), for example, when the photodiode is implemented with III-V materials and / or uses heterostructures.

[0080] In some embodiments, the active photodiode of the FPA is reverse-biased. Here, for inactive pixel units, the terminal of the transistor of the associated inactive pixel circuit connected to the photodiode (referred to herein as the “transistor input node”) is also reverse-biased with respect to the transistor's substrate and / or channel. Without wishing to be bound by theory, it is theorized that the bias creates a charge carrier potential well at a node (referred to herein as the “floating node”), the node including a portion of the photodiode connected to a portion of the transistor (referred to herein as the photodiode “collection node”). It is theorized that charge carriers accumulate in the potential well, and as the well fills, additional photocarriers generated in the photodiode substrate are repelled by the charge occupying the well, and the additional carriers then diffuse toward the active transistor for detection in the active transistor's pixel circuit.

[0081] Accumulated charge at the inactive photodiode collection node can locally change the bias of the inactive photodiode collection node-photodiode substrate junction, potentially repelling generated photocarriers (e.g., the junction becomes forward biased).

[0082] Similarly, with respect to the electrical connection of the collection node of the inactive photodiode to the input node of the inactive transistor, the input node of the inactive transistor tends to become forward biased, which in some embodiments is prevented by biasing the transistor substrate (thus potentially preventing leakage from the inactive transistor input node to the transistor substrate).

[0083] In some embodiments, the inactive transistor substrate bias is configured to provide a balanced condition at the inactive transistor input node-transistor substrate interface. The inactive transistor substrate bias may be configured to minimize reverse bias, which can contribute to carrier injection from the transistor substrate to the photodiode substrate and potentially contribute these "dark current" carriers to photocurrent noise that may be collected in the active pixel unit.

[0084] Additionally or alternatively, in some embodiments, the bias of the inactive transistor substrate may be configured to minimize forward bias at the inactive transistor input node-transistor substrate junction that may contribute to carrier leakage from the inactive transistor input node to the transistor substrate, potentially resulting in capture of generated photocarriers by the inactive photodiode collection node.

[0085] In some embodiments, for example, under low photocurrent levels LLL, the bias can be selected to reverse bias the inactive transistor input node-transistor substrate, and noise increasing photocurrent is selected in this tradeoff.

[0086] In some embodiments, the transistors are p-type transistors, and the p-type portion of each photodiode is connected to the drain of the associated transistor. The bias of the n-type portion of the photodiode (e.g., the n-type substrate of the FPA) is high, as are the biases of the inactive transistor substrate and gate. The bias of the active transistor gate can be configured to provide a channel for the active transistor device.

[0087] Optionally, the substrate of the active transistor may be biased to the same voltage as the substrate of the inactive transistor. The transistor substrate bias may be a stronger reverse bias (more negative in p-type systems) than that of the photodiode reverse bias. For active transistors, it is theorized that the bias experienced at the junction between the transistor input node and the transistor substrate is dominated by the active channel of the transistor, potentially providing an equilibrium condition that prevents leakage of photocurrent into the transistor substrate and / or injection of carriers from the transistor substrate into the transistor input node. In some embodiments, a reverse bias may be experienced at the active transistor input node-active transistor substrate junction where it is theorized that injection current from the substrate is low relative to the photocurrent measurement signal.

[0088] In some embodiments, the FPA is configured to detect light in the near-infrared (NIR) and short-wave infrared (SWIR) regions, where the photodiode may include III-V materials such as indium gallium arsenide (InGaAs), gallium arsenide (GaAs), and indium phosphide (InP), all of which exhibit direct bandgap behavior.

[0089] In some embodiments, the FPA is configured to detect mid-wave infrared (MWIR) and / or long-wave infrared (LWIR) light, and the FPA may include compound semiconductors such as mercury cadmium telluride (HgCdTe), lead selenide (PbSe), and lead sulfide (PbS).

[0090] Additionally, in some embodiments, the FPA may include materials such as gallium antimonide (GaSb), indium antimonide (InSb), and indium arsenide (InAs), aluminum gallium arsenide (AlGaAs), and indium gallium phosphide (InGaP).

[0091] In some embodiments, an imaging system including an FPA and a PCA is used in infrared imaging under low light levels (LLL). In some embodiments, LLL conditions may be defined as corresponding to a natural nighttime environment, e.g., ranging from full moon illumination to lunar conditions, or intermediate illumination levels therein. In some embodiments, LLL conditions are defined as conditions below about 10 μm 2 The LLL state may be defined as resulting in a charge generation of 10 ke or less for a pixel size of 10 ke or less. The specific charge level may depend on the pixel size, with larger pixels storing more charge, while smaller pixels storing less charge. In some embodiments, the LLL state corresponds to a photocurrent that requires an active amplification scheme, such as a capacitive transimpedance amplifier (CTIA) architecture, where the generated photocurrent may be too low to adequately bias a passive amplification scheme, such as a direct injection (DI) or buffered direct injection (BDI) architecture.

[0092] In an exemplary embodiment, the photodiode is formed from a heterostructure with a large bandgap at the surface of the photodiode collection node where the photodiode connects to the pixel circuitry. A potential benefit is the reduction of noise currents flowing into and out of the surface associated with the generation and recombination of charge carriers due to, for example, Shockley read hole traps and surface defects, e.g., surface impurities and / or crystalline non-idealities and / or unbonded dangling bonds.

[0093] In some embodiments, the imaging system is a multi-function system configured to operate, for example, at a variety of different light levels and / or resolutions. For example, the functions may include one or more of the following: laser pulse recognition, event-based imaging, and distance measurement. Although "charge sharing," in which a mixture of inactive and active pixels is used, is described herein with respect to imaging, applying the described systems and / or techniques is envisioned and encompassed for other uses of pixelated detectors, such as range measurement.

[0094] For example, in some embodiments, pixelated systems are used to recognize and / or identify laser pulses, such as in determining the arrival (e.g., time of arrival) of a laser pulse in distance measurement applications. In this case, the positional accuracy provided by which pixels sense the arrival of the laser pulse may be sacrificed for sensitivity (e.g., if the intensity of the laser pulse is low relative to the system's ability to identify its arrival). For example, according to the techniques and / or systems described herein, some of the laser-detecting pixels are biased to be inactive.

[0095] In some embodiments, the same system may be used for both imaging light (e.g., infrared light) and detecting laser pulses (e.g., a multifunction system that uses reflected laser pulses to acquire images and determine distance), and a mix of inactive and active pixels may be used for both functions. Alternatively, in some embodiments, images may be acquired with different bias settings to measure the laser pulses and the images, and different selections of pixels may be inactive in one mode (image acquisition mode and laser pulse detection mode).

[0096] Here, in some embodiments, biasing as described herein to increase the effective pixel pitch is selectively used based on, for example, light level, where in some embodiments, pixel units are selectively activated and / or deactivated to increase the effective pixel pitch and / or effective collection area (e.g., beyond that provided by activating all of the pixel units), for example, for low light level (LLL) operation.

[0097] In an exemplary embodiment, the readout circuit of the pixel circuit includes a charge transimpedance amplifier (CTIA). Potential advantages of using a CTIA include a fixed and / or stable diode bias and / or a large bandwidth.

[0098] A stable diode bias can be associated with a large CTIA input impedance.

[0099] CTIA may provide a large bandwidth (e.g., compared to DI) when DI is subject to low-pass filtering effects at the detector node, which may be more problematic (in terms of its effect on the signal, e.g., SNR) when the photocurrent is low, e.g., below LLL.

[0100] In some embodiments, existing bias lines are used to implement active and inactive biasing of different pixel circuits of the PCA, where in some embodiments, power supply circuits (also referred to herein as "drive circuits" or "bias circuits") are configured to provide different bias voltages to different rows of the PCA, and in some embodiments, additional bias lines are fabricated within the ROIC, for example, to inactively bias some of the pixel circuits of a row.

[0101] In some embodiments, correlated double sampling (CDS) techniques are used in conjunction with biasing techniques as described herein, for example, for LLL scenarios.

[0102] In exemplary embodiments, the readout circuitry of the pixel unit is CTIA-based (Capacitive Transimpedance Amplifier-based), and in some embodiments is combined with CDS technology, eg for LLL scenarios.

[0103] Before describing at least one embodiment of the invention in detail, it is to be understood that the invention is not necessarily limited in its application to the details of construction and arrangement of components and / or methods set forth in the following description and / or illustrated in the drawings and / or examples. The invention is capable of other embodiments or of being practiced and carried out in various ways.

[0104] FIG. 1 is a simplified schematic diagram of a portion of an imaging system 100 according to some embodiments of the present disclosure.

[0105] In some embodiments, system 100 includes an array 102 (also referred to herein as a "focal plane array (FPA)" and a "photodetector array") of photodetectors (also referred to herein as "photodetectors," "photosensors," "detectors," and "pixels"), where, in some embodiments, one or more photodetectors (e.g., each photodetector) of the array include a photodiode.

[0106] Exemplary materials for the photodetector array include, for example, direct bandgap materials, IV materials (e.g., silicon), III-V materials, and II-VI materials, and the structure of the FPA wafer can be monolithic or heterostructure. In some embodiments, the material and / or structure of the photodiode is selected based on the desired detection wavelength. In some embodiments, the photodiode is an infrared detection photodiode, for example, a photodiode comprising InGaAs, InSb, or HgCdTe.

[0107] In some embodiments, system 100 includes a readout integrated circuit (ROIC) 104 that hosts an array of pixel circuits (also referred to herein as a "pixel circuit array" (PCA)).

[0108] The ROIC may be hosted by a different wafer and / or may be formed using a different material than the FPA. In an exemplary embodiment, the PCA is disposed on the ROIC 104 below the FPA 102.

[0109] Alternatively, in some embodiments, the photodiodes of the FPA and the pixel circuitry of the PCA may be integrated onto a single wafer, with the substrates being electrically separated and / or isolated from one another.

[0110] In some embodiments, each detector in the photodetector array of FPA 102 is associated with a pixel circuit in the PCA. In some embodiments, each photodetector is associated with a single corresponding pixel circuit in the PCA, and each pixel circuit, in some embodiments, includes a pixel transistor (e.g., transistors 472, 473 in FIG. 4, transistors 572, 574 in FIG. 5, transistors 672, 673 in FIG. 6).

[0111] In some embodiments, each pixel circuit is connected to a photodiode of FPA 102 to provide a "pixel unit," where, in some embodiments, a connector connects each photodiode to a corresponding pixel circuit (e.g., photodiode 328, connector 352, pixel circuit 330 in FIGS. 3A-B). In some embodiments, the measurement signal (e.g., voltage and / or current and / or charge) at the pixel circuit is transferred to readout circuit 106, for example, via connection 126.

[0112] In some embodiments, each pixel circuit includes readout circuitry, e.g., for collecting the photocurrent and / or driving the photocurrent outside the pixel array. In some embodiments, the readout circuitry (e.g., of each pixel circuit) includes one or more integration elements (also referred to herein as "storage elements" and "charge accumulators"), e.g., for storing detected charge received from a photodiode connected to the pixel circuit. In some embodiments, the readout circuitry includes one or more amplification elements (e.g., for amplifying the detected charge) and / or switching circuitry (for selective readout of the detected charge by transferring the charge to the readout circuitry). Exemplary pixel units 676, 677 are shown in and / or described with respect to FIG. 6.

[0113] In some exemplary embodiments, the PCA includes between 100K and 20M pixel circuits, or between 300K and 10M pixel circuits, or between 300K and 5M pixel circuits, or a fewer, greater, or intermediate number or range.

[0114] In some embodiments, bias for elements of the FPA 102 and / or PCA is provided by one or more on-chip power supplies 108, where in some embodiments, an on-chip power supply 110 receives power from an off-chip power supply 108.

[0115] In some embodiments, the power supply 110 provides one or more of a gate bias 118 for inactive transistors, a gate bias 120 for active transistors, a bias 122 for the photodiode of the FPA, and a substrate bias 124 for the transistor of the PCA.

[0116] In some embodiments, the ROIC hosts a processing unit 112 that includes, for example, on-chip memory and / or processing circuitry. In some embodiments, the imaging system 100 includes an off-ROIC memory and processing circuitry (MPC) 114, which is connected to, for example, the on-chip processing unit 112.

[0117] Here, in some embodiments, power supply 110 biases one or more portions of the ROIC according to control instructions received from MPC 112 and / or MPC 114. Here, in some embodiments, the portions of the ROIC responsible for biasing the inactive and / or active pixel transistors (e.g., including power supply and / or processing circuit portions) are referred to herein as "drive circuitry" or "bias circuitry."

[0118] In some embodiments, imaging system 100 includes one or more user interfaces 116 configured, for example, to receive input from a user and / or to display data received from a user. User interfaces 116 are connected to one or both of MPCs 112, 114 for receiving and / or outputting data.

[0119] Optionally, in some embodiments, imaging system 100 includes one or more additional elements, such as when the pixel circuits of the PCA include pixel multifunction circuits, such as elements for one or more of laser detection, laser detection, event imaging, and ranging (e.g., one or more pixel circuits, e.g., each pixel circuit).

[0120] FIG. 2 is a detection method according to some embodiments of the present disclosure.

[0121] At 200, in some embodiments, it is selected which pixels of the FPA should be biased in an active configuration and which pixels should be biased in an inactive configuration.

[0122] In some embodiments, the density of active pixels (e.g., defined by the ratio of inactive pixels to active pixels) is selected to provide, e.g., an effective pixel detection area and / or effective pixel pitch that is different from (e.g., larger than) that provided by activating all of the pixels.

[0123] Optionally, in some embodiments, the density of the active pixels may be selected differently, for example, for different portions of the FPA, e.g., the density of the active pixels in different portions of the FPA may be different, for example, as shown in and / or described with respect to FIG. 8.

[0124] Optionally, in some embodiments, the density and / or number and / or percentage of activated pixels are selected based on light levels, where in some embodiments the density of active pixels in different portions of the FPA are selected, for example, by the light levels for each portion, and the light level data used for selection in some embodiments includes previously acquired measurement data.

[0125] Optionally, in some embodiments, the density and / or number and / or percentage of activated pixels is selected based on a protocol including a series of defined densities / numbers / percentages. For example, in some embodiments, imaging is an iterative process, whereby imaging is repeatedly performed on at least one portion of the pixel unit array using a series of densities / numbers / percentages. For example, in an exemplary embodiment, one or more images are first acquired in which at least one portion of the pixel array has a first density / number / percentage (e.g., all pixels of at least one portion are active), and a successive (or one or more successive) images are acquired with a reduced density / number / percentage. In some embodiments, imaging is performed when at least one portion has a reduced density / number / percentage more than once.

[0126] At 202, in some embodiments, pixel units selected to be active are biased (also referred to as "driven") to an active state, e.g., pixel circuit transistors are biased to an on state and inactive pixel transistors are biased to an off state.

[0127] At 204, in some embodiments, an effective image is acquired using the FPA and associated pixel circuitry of the ROIC, the effective resolution of the image being less than that provided by the FPA pixel density, at least in part of the FPA.

[0128] FIG. 3A is a simplified schematic diagram of a portion of an FPA 302 and an ROIC 304, according to some embodiments of the present disclosure.

[0129] In some embodiments, the FPA 302 and the ROIC 304 are on different wafers (e.g., having different materials), and the photodiode of the FPA 302 is connected to the ROIC 304 (e.g., by a connector, e.g., the connector in FIG. 3B). Alternatively, in some embodiments, the FPA 302 and the ROIC 304 are provided by a single monolithic wafer, e.g., the FPA and the ROIC are implemented on different layers of the wafer.

[0130] In some embodiments, each region of FPA 302 that hosts a photodiode corresponds to an area that houses connected pixel circuitry (e.g., region 328 of FPA 302 connected to region 330 of ROIC 304). While the lines on FPA 302 illustrate different regions of FPA 302 associated with different photodiodes, it should be understood that in some embodiments, there is no physical separation between the photon absorption and / or substrate regions within the photodiodes of the FPA. Here, in some embodiments, the photodiode array is delineated by separated wells of different doped material. For example, if the FPA wafer and / or substrate and / or photon absorption layer comprises n-type material, the photodiodes are provided by separately delineated p-type wells, for example, as shown in FIGS. 4 and / or 5.

[0131] FIG. 3B is a simplified schematic diagram of a portion of the PCA of ROIC 304, according to some embodiments of the present disclosure.

[0132] 3B illustrates an embodiment in which, for a portion of a row of a PCA, one or more bias lines provide one or more bias voltages to the transistors in the row of the PCA, for example, allowing some of the pixel circuits in the row to be activated and some of the pixel circuits in the row to be switched off.

[0133] FIG. 3B illustrates the ROIC 304 of FIG. 3A without the FPA 302, in some embodiments. A connector 352 is shown in FIG. 3B. Here, in some embodiments, each photodiode of the FPA is connected to a corresponding region of the ROIC 302 by a connector, e.g., connector 352 connects region 328 (FIG. 3A) to region 330. In some embodiments, connector 352 includes a micropad. In some embodiments, connector 352 includes an indium bump. In some embodiments, connector 352 includes a copper-to-copper connection.

[0134] 3B shows bias circuits for active and inactive pixel circuits in some embodiments. Exemplary configurations including active and inactive pixel circuits are shown by shading of the active pixel circuits (e.g., active pixel circuit 354) and black gate bias circuitry 320 of the active circuit. Inactive pixel circuits with gray gate bias circuitry 318 are shown without shading (e.g., inactive pixel circuit 330).

[0135] In some embodiments, the pixel circuits each have a connection 326 to a readout circuit (not shown).

[0136] FIG. 3C is a simplified schematic diagram of a portion of a PCA of an ROIC, according to some embodiments of the present disclosure.

[0137] 3C shows an embodiment in which the rows of the PCA have a single bias line, and the rows are selectively activated (shade pixel circuitry) and switched off, e.g., as described elsewhere herein. A potential advantage of the embodiment of FIG. 3C is that modifications to existing ROIC circuitry can be made, e.g., in the drive circuitry, without making modifications to the PCA.

[0138] FIG. 4 is a simplified schematic cross-sectional view of a portion of a detector array 402 and an ROIC 404, according to some embodiments of the present disclosure.

[0139] FIG. 4 shows an exemplary structure of photodiodes 474, 475 of FPA 402 and transistors 472, 473 of the pixel circuit of ROIC 404.

[0140] Photodiodes 474, 475 have collection nodes 450, 451, respectively.

[0141] Transistors 472, 473 each have an input node 456, 457 connected to a corresponding photodiode collection node, collection nodes 450, 451, respectively.

[0142] Exemplary transistors 472, 473 are MOSFETs, each having a source 458, 459, a drain 456, 457, and a gate 476, 477 separated from channel regions 462, 463 by oxide layers 478, 479. While a MOSFET implementation is shown, it should be understood that in some embodiments other transistor types are used, for example, bipolar junction transistors (BJTs).

[0143] Exemplary photodiodes 474, 475 of FPA 402 are provided in some embodiments by regions 450, 451 that are oppositely doped to the material of the FPA wafer. For example, if FPA wafer 402 comprises n-type material, then in some embodiments regions 450, 451 are p-doped.

[0144] 4, both first transistor 472 and second transistor 473 are biased in an active configuration, e.g., biasing gates 476, 477 to active transistor gate bias voltage 420 (which may depend on a downstream voltage via connecting circuitry 426, e.g., a downstream voltage associated with the detection circuitry (e.g., readout circuit type)) allows carrier conduction (e.g., the bias places carriers in the channel) through channel regions 462, 463. Charge carriers 468, 469 (generated upon absorption of photons 466, 467, respectively) travel from photodiodes 474, 475, through connectors 452, 453, channels 462, 463, and connecting circuitry 426 to a readout circuit (not shown).

[0145] In some embodiments, the body of the FPA 402 is biased to a voltage Vdetcom 422 to reverse bias the photodiodes 474, 475, and the active transistors 472, 473 are biased to an active transistor gate bias 420 to allow charge carriers from the photodiodes 474, 475 to pass, for example, via a connection circuit 426 towards a readout circuit.

[0146] Here, for a p-type system (on an n-type system) in some embodiments, Vdetcom > active transistor gate bias 420. In some embodiments, the active transistor gate bias may be selected according to a detection circuit, for example, as described with respect to FIGS.

[0147] In some embodiments, the transistors 472, 473 are p-type, and the p-type region 450, 451 of each photodiode is connected to the drain 456, 457 of the corresponding transistor 472, 473.

[0148] Where transistors 472, 473 are p-type, in some embodiments the transistors are formed by fabrication on top of n-wells (e.g., of p-type wells forming source and drain) on a p-type wafer, as shown in FIG. 4, where, for example, the shaded areas of the dots are p-type and the unshaded areas are n-type.

[0149] FIG. 5 is a simplified schematic cross-sectional view of a portion of the detector array 402 and the ROIC 404, according to some embodiments of the present disclosure.

[0150] In some embodiments, Figure 5 shows the same cross section as Figure 4, e.g., like components have like numbers. However, in Figure 5, first transistor 572 is biased in an off configuration to provide an "inactive" transistor, and second transistor 473, in some embodiments, is an adjacent transistor biased in an active configuration (e.g., as shown in Figure 5) (becoming the "active" transistor).

[0151] For example, the active transistor 473 and photodiodes 474, 475 of the FPA 402 are biased as described with respect to FIG.

[0152] In some embodiments, the inactive transistor gate bias 518 of the gate 476 of the inactive transistor 572 is with respect to a voltage Vcc configured to prevent carrier conduction through the channel region 562 (e.g., the gate bias depletes the channel of carriers). In an exemplary embodiment, when Vcc 518 is greater than the voltage Vdetcom 422, the photodiode is reverse biased. Vcc>Vdetcom.

[0153] The gate bias 518, 420 may be influenced by the characteristics and / or conditions of the transistor, such as by one or more of doping, gate oxide thickness, body effect, gate leakage current, channel length modulation effect, and temperature.

[0154] Without being bound by theory, it is theorized that the biasing of the inactive transistor 572 creates a potential well at the junctions 450, 456 of the inactive transistor 572 and the associated photodiode 474. The junctions 450, 456 are also referred to herein as "adjacent hybridization regions" and "floating nodes," and in some embodiments, have the same dopant category (e.g., p-type). The floating node is theorized to collect photocarriers 568, which drive the potential of the floating node to a positive value (e.g., for p-on-n photodiodes and p-channel transistors, the photocarriers are positive and are also referred to herein as "holes"). Here, as theorized, the potential of the floating node Vfn, when charged with the potential Vdetcom, is higher than the diode bias well 422. Vfn>Vdetcom. The potential at the floating node is theorized to act as a barrier, preventing additional photocarriers 566 from entering the floating node (e.g., once the potential well is filled), and once the potential well is filled, the floating node reaches an equilibrium state. After equilibrium of the floating node is achieved, the generated additional photocarriers 566 are theorized to be transferred by diffusion 570 through FPA wafer 402 to active diode 475, where they are collected, for example, through active transistor 473, for example, to charge a connected integrating capacitor (not shown).

[0155] Once equilibrium for the floating node is reached, it is theorized that the transfer process of generated charge carriers continues (e.g., is constant) as long as the equilibrium is maintained. If there is carrier leakage 582 from the floating node potential well, for example, from the transistor terminal (e.g., drain) 456 to the substrate 580 of the inactive transistor 572, it is theorized that the generated carriers will be captured by the floating node instead of diffusing to be detected, for example, by the active pixel circuitry. This could potentially reduce the detection signal-to-noise ratio (SNR), for example, because the detection signal collected by the active pixel circuitry is reduced and / or the detection noise is increased.

[0156] In some embodiments, the substrate 580 of the inactive transistor 472 is biased (e.g., reverse-biased) to a voltage Vhigh 524, where in some embodiments the substrate bias Vhigh 524 is a higher voltage (more positive in a p-type system) than the voltage of the reverse bias of the diode of the FPA 402, e.g., in a p-type system, Vhigh 524 > Vdetcom 422. A potential benefit is the prevention and / or reduction of charge transfer 582 (leakage) from floating nodes, e.g., from the transistor drain 456 to the substrate 580. In exemplary embodiments, Vhigh is 0.1-1 V, or 0.2-0.8 V, or 0.4-0.6 V, or about 0.5 V higher than Vdetcom, or a lower, higher, or intermediate voltage than Vdetcom.

[0157] Optionally, the substrate 581 of the active transistor 473 is biased to the same voltage as the substrate 580 of the inactive transistor 572 (voltages 524, 525 are the same), with the potential advantage being the ability to provide tight and / or symmetrical substrate bias circuits.

[0158] In an exemplary embodiment, if the photon absorption layer is p-type, the bias voltage follows the relationship: Vhigh 524, 525>Vdetcom 422>Vcc 518>Vbias 420

[0159] If the photon absorption layer of the photodiode is n-type, the bias voltage may obey the following relationship: Vhigh 524, 525 <Vdetcom 422<Vcc 518<Vbias 420

[0160] Here, in some embodiments, the substrate reverse bias is with respect to Vhigh, the photodiode reverse bias is with respect to Vdetcom, the inactive transistor gate bias is Vcc, and the active transistor gate bias is less than or equal to Vbias.

[0161] While the illustration in FIG. 5 is of two transistors 572, 473 and associated photodiodes 474, 475, it should be understood that this description is applicable to multiple such transistors in an imaging system where some of the pixel units are actively biased and at least one of the pixel units is inactively biased.

[0162] FIG. 6 is a simplified schematic diagram of some circuitry of an imaging system 600, according to some embodiments of the present disclosure.

[0163] In some embodiments, system 600 includes multiple ROIC pixel units 676, 677 (also referred to herein as "pixel units"). Each pixel unit, in some embodiments, includes a photodiode 674, 675 of an FPA (e.g., FPA 102 of FIG. 1, FPA 302 of FIG. 3A, FPA 402 of FIG. 4 and FIG. 5) and a pixel circuit of an ROIC corresponding to the photodiode. In some embodiments, each pixel unit includes a connector 652, 653 connecting each diode to a corresponding pixel circuit (e.g., connector 652, 653 corresponding to connector 352 of FIG. 3B).

[0164] In some embodiments, a portion of the pixel units are in an active configuration 677 and a portion of the pixel units 676 are in an inactive configuration. In some embodiments, for each active pixel unit, at least one pixel unit is inactive, or 1 to 50, or 1 to 10, or 1 to 4 pixel units, or a lower, higher, or intermediate range or number of pixel units are inactive for each active pixel unit. In exemplary embodiments, the increase in effective detection area per active pixel (e.g., defined by the inactive pixels around each active pixel) increases symmetrically, e.g., there are 4, or 8, or 16, or 25, or more squared number of inactive pixels for each active pixel unit.

[0165] In some embodiments, there are fewer inactive pixel units than active pixel units. In some embodiments, for one or more regions of the detector, the proportion and / or distribution of active pixels is selected to symmetrically increase the effective area associated with each active pixel, for example, for each active pixel there are 1, or 4, or 9, or 16, or 25, or a greater squared number of inactive pixels.

[0166] In some embodiments, different portions of the FPA have different proportions of active and inactive pixel units, for example, including one or more features as shown in and / or described with respect to FIG.

[0167] In some embodiments, the system 600 is operable in a configuration in which some of the pixel units are active 677 (e.g., by biasing transistors 620 of the pixel circuits in an on configuration) and some 676 of the pixel units are inactive, with transistors 672 of the inactive pixel circuits biased in an off configuration.

[0168] In some embodiments, the pixel circuitry (e.g., for each pixel unit 676, 677) includes transistors 672, 673, integration and amplification circuitry 678, 679. Optionally, in some embodiments, the pixel units include readout circuits 690, 691, 626.

[0169] In some embodiments, (e.g., for an active pixel unit 677) an integration and amplification circuit 679 (also referred to herein as a "readout circuit") stores the charge received from the photodiodes 674, 675 via transistor 673 and then transfers the charge to a readout circuit external to the pixel unit (e.g., a readout circuit hosted by processing unit 112 in FIG. 1), for example, when switch 691 is closed. In some embodiments, the readout circuit is configured to store the received charge (e.g., the charge stored by the integration capacitor).

[0170] In some embodiments, the readout circuitry, e.g., readout circuits 678, 679 (e.g., including integration and amplification circuitry), which may be fully or partially hosted by the pixel unit, includes circuitry employing one of a capacitive transimpedance amplifier (CTIA), direct injection (DI), buffered direct injection (BDI), source follower per detector (SFD), gated modulation input (GMI), shared buffer direct injection (SBDI), and switched current integration (SCI).

[0171] In an exemplary embodiment, readout circuitry, e.g., readout circuits 678, 679, which may be fully or partially hosted by the pixel unit, includes circuits employing capacitive transimpedance amplifiers (CTIA), direct injection (DI), buffered direct injection (BDI), and source followers per detector (SFD).

[0172] A particular exemplary embodiment of the readout circuits 678, 679 is shown in Figures 7A and 7B.

[0173] Here, in some embodiments, an exemplary readout circuit includes one or more features of that illustrated and / or described in Hsieh et al., "Focal-plane-arrays and CMOS readout techniques of infrared imaging systems," Circuits and Systems for Video Technology, IEEE Transactions on 7.594-605.10.1109 / 76.611171, which is incorporated herein by reference in its entirety.

[0174] In some embodiments, the DI&BDI readout circuit is used for imaging of larger capacitances where the integrator capacitor can store a large amount of charge, e.g., where the photocurrent is high relative to the exposure (e.g., frame rate associated with the frequency of the integrating capacitor discharge).

[0175] FIG. 7A-B are schematic diagrams of an exemplary readout circuit according to some embodiments of the present disclosure.

[0176] FIG. 7A shows an exemplary direct injection (DI) readout circuit 778a including, for example, an integration capacitor 792a and a readout amplifier 794a. Here, in some embodiments, an active pixel transistor (for example, referring back to FIG. 6, the active transistor 673) forms part of the readout amplifier circuit. For example, in some embodiments, the gate bias 620 of the active pixel transistor 673 is selected such that the transistor operates as a current buffer while defining a diode voltage. The source of the DI transistor is connected to a diode that defines this node voltage value to Vbias + Vthreshold.

[0177] FIG. 7B shows an exemplary CTIA readout circuit including, for example, an integration capacitor 792b and a CTIA amplifier 794b. When the transistor output is connected to the integrating CTIA amplifier, the first input 771 of the CTIA amplifier and the second input 773 of the CTIA amplifier are biased to a reference voltage VREF. In some embodiments, the CTIA bias voltage is lower than the voltage used to bias the gates of the non-active transistors, and Vcc:VREF < Vcc. In some embodiments, VREF is 50 - 500 mV, or 100 - 500 mV, or 100 - 400 mV, or lower, or higher, or an intermediate voltage, or a range lower than Vcc. In some embodiments, a VREF lower than Vcc ensures the active operation of the amplifier and / or the active transistor.

[0178] An integrating capacitor 792b provides feedback across the CTIA amplifier 794b. In some embodiments, for example, in conjunction with the feedback of capacitor 792b, the active transistor 625 is biased at its gate / base 620 to a voltage less than the CTIA bias voltage VREF, less than a threshold voltage; VREF-VThreshold, where VThreshold is the voltage required to activate the active transistor. For example, when the gate / base voltage is less than or equal to VThreshold, current flow through the active transistor is switched on.

[0179] A potential advantage of the CTIA readout circuit is the ability to select the reset voltage, potentially providing the ability to have a large dynamic range for the same supply voltage.

[0180] FIG. 8 is a simplified schematic diagram of a portion of an imaging system according to some embodiments of the present disclosure.

[0181] In some embodiments, different regions of the FPA 802 and / or PCA of the ROIC 804 have different percentages of activated pixels (e.g., activated detector pixels of the FPA and / or activated pixel circuits of the PCA). For example, regions of the FPA 802 and / or PCA 804 may have different percentages of activated pixels. For example, in some embodiments, the shaded central region 896 illustrates an embodiment in which the central region (e.g., comprising multiple pixels) has a higher percentage of activated pixels than the peripheral regions of the FPA and / or PCA. For example, the detector may have a higher effective resolution in the central region (e.g., if the central region is "hotter") and the peripheral region may have a lower effective resolution to minimize noise (e.g., if the peripheral region has LLL).

[0182] 9A-C are simplified diagrams illustrating layouts of active and inactive pixels of portions of an imaging system according to some embodiments of the present disclosure.

[0183] For example, Figure 9A shows a ratio of 1:8, Figure 9B shows an embodiment with a ratio of 1:15 where the pixel area is potentially divided between active pixels, and Figure 9C shows a ratio of 1:24. In some embodiments, exemplary ratios include a ratio of 1:(square number - 1). 10A-B are simplified schematic band diagrams according to some embodiments of the present disclosure.

[0184] FIG. 10A shows a band diagram for a cross section along line AA in FIG. 5, ie, through the active photodiode and transistor, in some embodiments.

[0185] FIG. 10B shows a band diagram for a cross section along line BB in FIG. 5, ie, through the inactive photodiode and transistor, in some embodiments.

[0186] In some embodiments, the reference numbers of the layers and vias correspond to the reference numbers in FIG. 5, eg, element 402 corresponds to element 1002, element 525 corresponds to 1025, and so on.

[0187] 10A-B show an embodiment in which a photodiode is hosted by a first material having a bandgap 1084 that is different from the bandgap 1086 of a second material of the connected transistor. The first material may be a direct bandgap material and the second material may be silicon.

[0188] 10A-B show a p-type system (p-on-n) in which the substrates 1002, 1080, 1081 are n-type, the photodiode collection nodes 1050, 1051 are p-type, and the input nodes 1056, 1057 are p-type. As mentioned above, in some embodiments, the system is n-type, and the band diagram should be correspondingly inverted. The conductive connectors 1052, 1053 provide Fermi levels (FL), shown as dashed lines, on either side of the connectors 1052, 1053 with the same energy.

[0189] In some embodiments, the first material is indium gallium arsenide (InGaAs) and the second material is silicon (Si), the photodiode substrate 1002 comprises n-type InGaAs, the photodiode collection nodes 1050, 1051 comprise p-type InGaAs, the transistor input nodes 1056, 1057 comprise p-type Si, and the transistor substrates 1080, 1081 comprise n-type Si.

[0190] In FIG. 10A, which shows the active pixel unit, the photodiodes (1002, 1051) are reverse biased, with FL 1092 of the n-type photodiode substrate 1002 being lower than FL 1088 of the p-type photodiode collection node.

[0191] FIG. 10A illustrates an embodiment in which the transistor input node-transistor substrate 1057-1081 p-n junctions are in equilibrium (unbiased), i.e., have a constant voltage across the junction, as indicated by the Fermi level being constant from the Fermi level of the photodiode collection node. FL 1088 crosses connector 1053 to input node 1057. Photoholes collected from reverse-biased photodiodes 1002-1051 flow into p-type input node 1057, are then collected, and flow through the transistor channel (e.g., in a direction perpendicular to the plane of the figure, e.g., along channel 1063, see FIG. 5), and it is theorized that the transistor channel controls the position of input node 1057FL. Transistor substrate bias potential 1025, in some embodiments, is configured to hold input node p-n junctions 1057-1081 in equilibrium (e.g., along with other transistor characteristics).

[0192] In some embodiments, for example, if the potential on 1025 is insufficiently negative, pn junctions 1057-1081 are in a reverse bias state (not shown), potentially resulting in a small reverse bias leakage current of the input node-substrate pn junctions 1057-1081, which in some embodiments is assumed to be negligible compared to the photocurrent.

[0193] In FIG. 10B , which shows an inactive pixel unit, the photodiodes (1002, 1050) are forward biased, which may refer, for example, to a localized region of the photodiode array adjacent to the photodiode collection node, and a change from reverse bias (as experienced by the active photodiodes 1002, 1051) changes locally to forward bias in association with the collection of charge at the inactive photodiode collection node 1050 (e.g., as shown in FIG. 5 where charge is stored at collection node 456).

[0194] In some embodiments, the bias 1024 of the inactive transistor is sufficiently positive so that the pn junctions of the substrate-input nodes 1080-1056 are forward biased and prevent accumulated holes from leaking into the substrate 1080. Figure 10B shows an embodiment in which the pn junctions 1080-1056 are in a balanced state. In some embodiments, for example, to achieve this balance, the bias of the substrate 1080 is made to be a more positive voltage than the bias of the photodiode 1022 (a p-type configuration).

[0195] In some embodiments, pn junctions 1080-1056 may be reverse biased, which can result in the injection of holes from the silicon substrate into the inactive transistor input nodes, potentially generating a reverse bias photodiode current that can then be collected by the active photodiode.

[0196] 11A-B are simplified schematic band diagrams according to some embodiments of the present disclosure.

[0197] FIG. 11A shows a band diagram for a cross section along line AA in FIG. 5, ie, through the active photodiode and transistor, in some embodiments.

[0198] FIG. 11B shows a band diagram for a cross section along line BB in FIG. 5, ie, through the inactive photodiode and transistor, in some embodiments.

[0199] In some embodiments, the reference numbers of the layers and vias correspond to the reference numbers in FIG. 5, eg, element 402 corresponds to element 1102 and element 525 corresponds to 1125.

[0200] 11A-B show an embodiment in which the photodiode is formed in a heterostructure in which the collection node of the photodiode has a bandgap larger than the bandgap of the photodiode substrate. The transistor may be formed from a monolithic material.

[0201] In some embodiments, the photodiode substrate 1102 comprises n-type InGaAs (which may have a bandgap 1184 smaller than the bandgap of the transistor material 1186, as opposed to the larger bandgap shown), and the photodiode collection nodes 1150, 1151 comprise p-type indium phosphide (InP), which has a larger bandgap 1198, for example, larger than the photodiode substrate and / or pixel circuit material. In some embodiments, the transistor input nodes 1156, 1157 comprise p-type Si, and the transistor substrates 1180, 1181 comprise n-type Si.

[0202] For example, similar to the embodiment shown in FIG. 10A, the active pixel unit has reverse-biased photodiodes 1102, 1151 and balanced transistor input node-transistor substrate junctions 1157-1181.

[0203] For example, similar to the embodiment shown in FIG. 10B, the inactive pixel units are forward biased in the region of the photodiodes 1102, 1150 and the transistor input node-transistor substrate junctions 1156-1180 in equilibrium.

[0204] It is theorized that a heterostructure with a large bandgap 1198 at the surface 1199 of the photodiode collection node potentially reduces noise currents flowing into and out of the surface associated with, for example, Shockley read hole traps and charge carrier generation and recombination due to surface defects, e.g., surface impurities and / or crystalline non-idealities and / or unbonded dangling bonds.

[0205] [General matters] As used within this document, the term "about" refers to ±20%.

[0206] The terms "comprises," "comprising," "includes," "including," "having," and their conjugations mean "including but not limited to."

[0207] The term "consisting of" means "including and limited to."

[0208] As used herein, singular forms such as "a," "an," and "the" include plural forms unless the context clearly dictates otherwise.

[0209] Within this application, various quantifications and / or expressions may include the use of ranges. The range format should not be construed as an inflexible limitation on the scope of the disclosure. Accordingly, descriptions containing ranges should be considered to have specifically disclosed all possible subranges as well as individual numerical values ​​within that range. For example, description of a range such as 1 to 6 should be considered to have specifically disclosed subranges such as 1 to 3, 1 to 4, 1 to 5, 2 to 4, 2 to 6, 3 to 6, etc., as well as individual numbers within the stated range and / or subrange, e.g., 1, 2, 3, 4, 5, and 6. Whenever a numerical range is given herein, it is meant to include any recited numbers (fractional or integer) within the stated range.

[0210] It should be understood that certain features that are described in the context of separate embodiments (e.g., for clarity) may also be provided in combination in a single embodiment. Various features of the disclosure that are described in the context of a single embodiment (e.g., for brevity) may also be provided separately or in any suitable subcombination, or may be suitable for use in any other described embodiment. Features described in the context of various embodiments should not be considered essential features of those embodiments unless the embodiments are inoperable without those elements.

[0211] While this disclosure has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, this application is intended to embrace all such alternatives, modifications, and variations that fall within the spirit and broad scope of the appended claims.

[0212] All references (e.g., publications, patents, patent applications) mentioned herein are incorporated by reference in their entirety, as if each individual publication, patent, or patent application were individually indicated to be incorporated by reference herein. Citation or identification of any reference in this application should not be construed as an admission that such reference is available as prior art to the present disclosure. Additionally, any priority documents and / or documents related to this application (e.g., concurrently filed applications) are incorporated by reference herein in their entirety.

[0213] When section headings are used herein, they should not be construed as necessarily limiting.

Claims

1. 1. An imaging system, comprising: a focal plane array (FPA) comprising a plurality of photodiodes hosted by a shared substrate, each photodiode having a collection node; a pixel circuit array (PCA) including a plurality of transistors, an input node of one of the plurality of transistors being connected to each photodiode collection node of the FPA; and A bias circuit, selectively biasing a first portion of the plurality of transistors to an inactive configuration; reverse biasing a substrate of each transistor of the first portion of the plurality of transistors; and selectively biasing a second portion of the plurality of transistors into an active configuration; and reverse biasing the shared substrate to a reverse bias that is different from the reverse bias of each transistor substrate of the first portion of the plurality of transistors.

2. 10. The imaging system of claim 1, wherein each transistor in the second portion injects a photocurrent signal received from the connected photodiode collection node remote from the transistor.

3. 3. The imaging system of claim 2, wherein photocurrent injection into the transistors of the second portion prevents charge buildup in photodiodes connected to the transistors of the second portion.

4. 4. The imaging system of claim 2, wherein photocurrent injection of the transistors in the second portion maintains the reverse bias of the shared substrate.

5. The imaging system of any one of claims 1 to 4, wherein the FPA is hosted by an FPA wafer, and the PCA is hosted by a PCA wafer that is a different wafer from the FPA wafer.

6. The imaging system of claim 5 , wherein the FPA wafer comprises a direct bandgap material.

7. The imaging system of any one of claims 5 to 6, wherein the FPA wafer is a heterostructure.

8. The imaging system of claim 7 , wherein the photodiode collection node comprises a material having a wider bandgap than the shared substrate.

9. 9. The imaging system of claim 1, wherein the photodiode is an infrared detection photodiode having a photon absorption region comprising InGaAs, InSb, or HgCdTe.

10. The imaging system of any one of claims 5 to 9, wherein the PCA wafer comprises silicon and the plurality of transistors comprise metal oxide semiconductor field effect transistors (MOSFETs).

11. 11. The imaging system of claim 1, further comprising a plurality of connectors, wherein each of the transistors is connected to a corresponding one of the plurality of photodiodes by one of the plurality of connectors.

12. The imaging system of claim 11 , wherein the plurality of connectors comprises one of copper-to-copper connections and indium bumps.

13. 12. The imaging system of claim 1, wherein photodiodes in a first portion of the FPA associated with transistors in the first portion are spatially interspersed on the FPA with photodiodes in a second portion of the FPA associated with transistors in the second portion, and each active transistor in the second portion collects photocurrent from photodiodes in the second portion and at least one photodiode in the first portion.

14. 14. The imaging system of claim 13, wherein for at least a portion of the FPA, the photodiodes in the first portion and the photodiodes in the second portion are evenly distributed, and each active transistor in the second portion collects photocurrent from an equal number of photodiodes in the first portion.

15. each of the photodiodes is connected to an input node of one of the plurality of transistors; 15. The imaging system of claim 1, wherein substrates of the transistors in the first portion are reverse biased to reverse bias the input nodes to prevent charge leakage from the input nodes to the substrates of the transistors in the first portion.

16. The imaging system of claim 15 , wherein the substrates of the transistors in the second portion are reverse biased.

17. the photodiode and transistor are implemented in a p-type configuration; the substrate of the photodiode is reverse biased to a reverse bias voltage Vdetcom; and 17. The imaging system of claim 15, wherein the substrate of the transistor in the first portion is reverse biased to a voltage Vhigh that is higher than the reverse bias voltage Vdetcom of the photodiode, where Vhigh>Vdetcom.

18. 18. The imaging system of claim 12, wherein the bias circuit is configured to deactivate the transistors of the first portion by biasing switching terminals of the transistors of the first portion to a deactivation voltage, and to activate the transistors of the second portion by biasing switching terminals of the transistors of the second portion to an activation voltage different from the deactivation voltage.

19. 18. The imaging system of claim 12, wherein the PCA comprises a plurality of rows of pixel circuits, switching terminals of transistors of pixel circuits of each row of the pixel circuit array are biased to the same voltage, and the first portion comprises at least one row of the pixel circuit array.

20. the PCA comprises a plurality of rows of pixel circuits, the pixel circuits of one or more rows of the pixel circuit array including a plurality of bias lines for biasing switching terminals of different transistors of the row to different voltages; and The imaging system according to any one of claims 12 to 17, wherein the bias circuit is configured to supply different bias voltages to at least two of the plurality of bias lines.

21. The different bias voltages are: the activation voltage for biasing a portion of the transistors in the one or more rows into the active configuration; and the deactivation voltage biasing some of the transistors in the one or more rows into the inactive configuration.

22. The imaging system according to any one of claims 18 to 21, wherein the transistor is a field effect transistor (FET), and the switching terminal is a gate of the FET.

23. 22. The imaging system of claim 18, wherein the transistor is a bipolar junction transistor (BJT) and the switching terminal is the base of the BJT.

24. The imaging system according to any one of claims 12 to 23, wherein the pixel circuits each include a readout circuit.

25. 25. The imaging system of claim 24, wherein the readout circuitry includes an integration capacitor connected to a transistor of each pixel circuit and configured to store charge received through the transistor.

26. The imaging system of any one of claims 24 to 25, wherein the readout circuitry comprises a charge transimpedance amplifier (CTIA).

27. The imaging system of any one of claims 24 to 25, wherein the readout circuitry comprises a direct injection (DI) readout circuitry.

28. The readout circuit includes: Buffer Direct Injection (BDI) readout circuitry; a source follower per detector (SFD) readout circuit; Gate modulation input (GMI) readout circuitry; a shared buffer direct injection (SBDI) read circuit, or 26. The imaging system of any one of claims 24 to 25, comprising one of: a switched current integration (SCI) readout circuit.

29. 29. The imaging system of any one of claims 12 to 28, comprising a processing circuit configured to receive image data from the PCA, the processing circuit having a number less than the number of pixels.

30. 1. An imaging method for using a focal plane array (FPA) having a plurality of photodiodes hosted by a shared substrate, and a pixel circuit array (PCA) coupled to the FPA and having a plurality of transistors, a transistor corresponding to each photodiode of the FPA; The imaging method includes: selecting a first portion of the plurality of transistors as inactive transistors and a second portion of the plurality of transistors as active transistors; biasing the first partial transistor in an inactive configuration and biasing the second partial transistor in an active configuration; reverse biasing the shared substrate to reverse bias a photodiode connected to the second portion of transistors; reverse biasing a substrate of each transistor of the first portion of the plurality of transistors to a reverse bias different from the reverse bias of the shared substrate; and and acquiring one or more images using the FPA and the PCA.

31. 31. The method of claim 30, wherein the biasing comprises reverse biasing a substrate of a transistor in the first portion to a stronger reverse bias than a reverse bias of the shared substrate of the photodiode to prevent charge leakage from the transistor in the first portion to the substrate.

32. the FPA and PCA are implemented in a p-type configuration, and reverse biasing includes biasing the photodiode to a voltage Vdetcom; 32. The method of claim 31 , wherein the reverse biasing the substrate comprises biasing the substrate to a voltage Vhigh, where Vhigh>Vdetcom.

33. 33. The method of any one of claims 30 to 32, wherein the biasing comprises biasing switching terminals of transistors of the first portion to a deactivation voltage and biasing switching terminals of transistors of the second portion to an activation voltage that is higher than the deactivation voltage.

34. A method according to any one of claims 30 to 33, wherein said selecting comprises selecting active transistors that are spatially interspersed with said inactive transistors.

35. the selecting the first portion includes selecting one or more rows of the PCA; and The method of any one of claims 30 to 34, wherein the biasing comprises biasing transistors in the one or more rows into the inactive configuration.

36. A method according to any one of claims 30 to 35, wherein said obtaining comprises accumulating charge in an integrator circuit of a pixel circuit associated with the active transistor of the PCA.

37. 37. The method of claim 36, wherein the obtaining comprises reading out and amplifying the charge through readout circuitry of the pixel circuit associated with the active transistor.

38. 1. An imaging system, comprising:

1. A pixel array comprising: a focal plane array (FPA) comprising a plurality of photodiodes hosted by a shared substrate, each photodiode having a collection node; a pixel circuit array (PCA) comprising a plurality of pixel circuits, each pixel circuit having an input node electrically connected to a collection node of a photodiode; a readout circuit; A bias circuit, disconnecting an input node of a first portion of the pixel circuit from the readout circuit; connecting an input node of a second portion of the pixel circuit to the readout circuit; and and a bias circuit configured to maintain accumulated charge at the input nodes of the pixels of the first portion so as to forward bias the photodiodes of the first portion.

39. The imaging system of any one of claims 1 to 29, wherein the different reverse bias is a stronger reverse bias.

Images