Semiconductor device

Abstract

To provide a semiconductor device capable of improving distance measurement accuracy while satisfying communication standards.SOLUTION: A baseband circuit BBC, when transmitting, divides the original pulse signal into a plurality of divided pulse signals so that frequency bandwidths of the pulse signals fall within a frequency bandwidth range regulated by UWB communication standards and common frequency ranges overlap with each other, and transmits the divided pulse signals sequentially with a prescribed transmission interval through an analogue front-end circuit AFE to a reception terminal. On the other hand, when receiving, the baseband circuit BBC inputs a plurality of divided pulse signals received sequentially with a prescribed time difference, corrects the time difference as if received simultaneously, and further corrects a phase of the plurality of divided pulse signals so as to be continuously in the common frequency range. The baseband circuit BBC synthesizes the plurality of divided pulse signals after the correction to restore the original pulse signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, for example, a semiconductor device for wireless communication. [Background technology]

[0002] Patent Document 1 discloses a signal processing device for ultrasonic testing that can appropriately measure an object to be tested. The device first generates ultrasonic waves by driving an ultrasonic probe using multiple burst wave signals with different frequencies, and then directs the ultrasonic waves toward the object to be tested. The device then receives multiple reflected waves corresponding to the multiple burst wave signals that have been incident on the object to be tested, and obtains multiple detection signals by performing detection processing on the received signals. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-131307 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, technologies using Bluetooth (registered trademark) and the like have been known as ranging technologies. Meanwhile, in recent years, attention has been focused on UWB (Ultra Wide Band) technology, which utilizes an ultra-wide frequency bandwidth, in order to achieve higher ranging accuracy. However, the radio frequency and frequency bandwidth are limited by the UWB communication standard. As a result, it has become difficult to achieve higher ranging accuracy in a typical UWB system. Therefore, there is a demand for a technology that can achieve higher ranging accuracy in a UWB system without violating the communication standard.

[0005] The embodiments described below have been made in consideration of the above, and other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment is a device for UWB wireless communication implemented in a transmitting terminal or a receiving terminal different from the transmitting terminal. The semiconductor device includes a baseband circuit, a reference oscillation circuit, a local oscillation circuit, and an analog front-end circuit. The baseband circuit includes a memory for storing a transmitting program or a receiving program and a processor for executing the transmitting program or the receiving program, and processes a baseband signal. The reference oscillation circuit generates a reference oscillation signal. The local oscillation circuit generates a local signal using the reference oscillation signal. The analog front-end circuit performs frequency conversion from the baseband signal to a high-frequency signal or from the high-frequency signal to the baseband signal using the local signal. Here, when the semiconductor device is implemented in the transmitting terminal, the baseband circuit performs processes (a) and (b) based on the transmitting program, and when the semiconductor device is implemented in the receiving terminal, the baseband circuit performs processes (c), (d), and (e) based on the receiving program. In process (a), the baseband circuit divides the original pulse signal that will become the baseband signal into multiple divided pulse signals, including a first divided pulse signal and a second divided pulse signal, so that each frequency bandwidth falls within the frequency bandwidth specified in the UWB communication standard and so that a common frequency range, which is part of the frequency bandwidth, overlaps. In process (b), the baseband circuit sequentially transmits the multiple divided pulse signals to a receiving terminal via an analog front-end circuit at a first transmission interval. Meanwhile, in process (c), the baseband circuit inputs the multiple divided pulse signals, which have been sequentially received with a time difference based on the first transmission interval, via the analog front-end circuit and corrects the time difference between the multiple divided pulse signals so that they appear to be received simultaneously. In process (d), the baseband circuit corrects the phases of the multiple divided pulse signals so that they are continuous within the common frequency range. In process (e), the baseband circuit restores the original pulse signal by adding the multiple divided pulse signals after the time difference correction in process (c) and the phase correction in process (d). [Effects of the Invention]

[0007] According to the embodiment, it is possible to improve distance measurement accuracy while satisfying communication standards. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration example of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a schematic diagram illustrating an example of processing content when the transmission circuit shown in FIG. 1 divides a pulse signal. [Figure 3] FIG. 3 is a schematic diagram illustrating an example of the processing content of the time difference correction performed by the receiving circuit shown in FIG. [Figure 4] FIG. 4 is a schematic diagram illustrating an example of the contents of the phase correction process performed by the receiving circuit shown in FIG. [Figure 5] FIG. 5 is a schematic diagram illustrating the operation principle when the receiving circuit shown in FIG. 1 estimates the phase difference between two divided pulse signals. [Figure 6] FIG. 6 is a flowchart showing an example of detailed processing contents of the transmission circuit shown in FIG. [Figure 7] FIG. 7 is a schematic diagram for explaining in more detail part of the processing contents shown in FIG. [Figure 8] FIG. 8 is a schematic diagram for explaining in more detail part of the processing contents shown in FIG. [Figure 9] FIG. 9 is a schematic diagram for explaining in more detail part of the processing contents shown in FIG. [Figure 10] FIG. 10 is a flowchart showing an example of detailed processing contents of the receiving circuit shown in FIG. [Figure 11] FIG. 11 is a schematic diagram for explaining in more detail part of the processing contents shown in FIG. [Figure 12] FIG. 12 is a schematic diagram for explaining in more detail part of the processing contents shown in FIG. [Figure 13]FIG. 13 is a schematic diagram for explaining in more detail part of the processing contents shown in FIG. [Figure 14] FIG. 14 is a schematic diagram illustrating an example of processing content obtained by modifying FIG. [Figure 15] FIG. 15 is a schematic diagram illustrating an example of a distance measurement method using a UWB system. [Figure 16A] FIG. 16A is a waveform diagram showing an example of a pulse signal used in a UWB system. [Figure 16B] FIG. 16B is a diagram showing an example of the frequency characteristics of the pulse signal shown in FIG. 16A. [Figure 17A] FIG. 17A is a schematic diagram showing an example of a method for dividing the frequency bandwidth of an original pulse signal during transmission in a UWB system. [Figure 17B] FIG. 17B is a schematic diagram showing an example of a method for dividing the frequency bandwidth of an original pulse signal during transmission in a UWB system. [Figure 18A] FIG. 18A is a schematic diagram showing an example of a method for restoring the original pulse signal from a plurality of divided pulse signals during reception in a UWB system. [Figure 18B] FIG. 18B is a schematic diagram showing an example of a method for restoring the original pulse signal from a plurality of divided pulse signals during reception in a UWB system. [Figure 19] FIG. 19 is a schematic diagram showing an example of a problem that occurs when a frequency bandwidth division method is used in a UWB system. [Figure 20] FIG. 20 is a schematic diagram showing an example of another problem that occurs when a frequency bandwidth division method is used in a UWB system. DETAILED DESCRIPTION OF THE INVENTION

[0009] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0010] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, the same components are generally designated by the same reference numerals, and repeated description thereof will be omitted.

[0012] <Configuration of semiconductor device> 1 is a block diagram showing a schematic configuration example of a semiconductor device 10 according to an embodiment. The semiconductor device 10 is a semiconductor device for UWB wireless communication that is mounted on a transmitting terminal or a receiving terminal different from the transmitting terminal. The semiconductor device 10 is, for example, an SoC (System on Chip) configured on a single semiconductor chip.

[0013] 1 includes an oscillator circuit OSC, a local oscillator circuit LOSC, a baseband circuit BBC, and an analog front-end circuit AFE. The oscillator circuit OSC is connected to a crystal oscillator XTAL provided external to the semiconductor device 10. The oscillator circuit OSC and the crystal oscillator XTAL thereby constitute a reference oscillator circuit ROSC that generates a reference oscillation signal RO, in other words, a crystal oscillator circuit. Although not shown in the figure, the semiconductor device 10 operates based on a clock signal generated using the reference oscillation signal RO.

[0014] The local oscillator circuit LOSC uses a reference oscillator signal RO to generate local signals LO1 and LO2 that are synchronized with the reference oscillator signal RO. The local signals LO1 and LO2 have frequencies on the order of GHz or 10 GHz based on UWB communication standards, for example, and are signals with a phase difference of 90 degrees from each other. Specifically, the local oscillator circuit LOSC can be configured, for example, by a PLL (Phase Locked Loop) circuit or the like.

[0015] The baseband circuit BBC includes a processor PRC, a memory MEM, a data transfer circuit DTC, and a divided pulse signal extraction circuit PDE, and processes a baseband signal. The processor PRC is, for example, a central processing unit (CPU) or a digital signal processor (DSP). The memory MEM includes a nonvolatile memory NVM and a volatile memory RAM. The nonvolatile memory NVM is, for example, a magnetoresistive random access memory (MRAM) or a flash memory. The volatile memory RAM is, for example, a static RAM (SRAM).

[0016] The nonvolatile memory NVM stores a transmission program PRGtx and a reception program PRGrx. The processor PRC executes the transmission program PRGtx and the reception program PRGrx stored in an MRAM or the like or copied from a flash memory or the like to the volatile memory RAM. By executing the transmission program PRGtx, the processor PRC functions as a pulse signal generation circuit PLSG and a pulse signal division circuit PLSD. In other words, the transmission program PRGtx causes the processor PRC to function as a pulse signal generation circuit PLSG and a pulse signal division circuit PLSD.

[0017] Furthermore, the processor PRC executes the reception program PRGrx to function as a time difference correction circuit TDCC, a phase difference estimation circuit PHDE, a phase correction circuit PHCC, and a signal restoration circuit RESC. In other words, the reception program PRGrx causes the processor PRC to function as a time difference correction circuit TDCC, a phase difference estimation circuit PHDE, a phase correction circuit PHCC, and a signal restoration circuit RESC.

[0018] The volatile memory RAM has a transmission data storage area AR-TXD and a reception data storage area AR-RXD. As will be described in detail later, the processor PRC generates a transmission digital signal based on a transmission program PRGtx. The processor PRC then stores the generated transmission digital signal in the transmission data storage area AR-TXD. The data transfer circuit DTC sequentially transfers the transmission digital signal stored in the transmission data storage area AR-TXD to the analog front-end circuit AFE. The data transfer circuit DTC can be realized, for example, using a circuit similar to a DMA (Direct Memory Access) controller.

[0019] As will be described in detail later, the divided pulse signal extraction circuit PDE stores the received digital signal from the analog front-end circuit AFE in the received data storage area AR-RXD. The divided pulse signal extraction circuit PDE can also be realized using a circuit similar to a DMA controller, for example. The processor PRC processes the received digital signal stored in the received data storage area AR-RXD based on the receiving program PRGrx.

[0020] The analog front-end circuit AFE includes digital-to-analog converters DAC1 and DAC2, analog-to-digital converters ADC1 and ADC2, a frequency conversion circuit FCV, a transmission amplifier AMP, and a reception amplifier LNA. The digital-to-analog converters DAC1 and DAC2 are stored in a transmission data storage area AR-TXD and convert a transmission digital signal input via a data transfer circuit DTC into a transmission analog signal. The transmission analog signal, and therefore the transmission digital signal, is also a baseband signal, and in UWB, becomes a transmission pulse signal Ptx.

[0021] The analog-to-digital converters ADC1 and ADC2 convert the received analog signal from the frequency conversion circuit FCV into a received digital signal. The received analog signal, and therefore the received digital signal, is also a baseband signal, and in UWB, becomes a received pulse signal Prx. The analog-to-digital converters ADC1 and ADC2 then store the converted received digital signal in a received data storage area AR-RXD via a divided pulse signal extraction circuit PDE.

[0022] In this example, a pair of digital-to-analog converters DAC1 and DAC2 and a pair of analog-to-digital converters ADC1 and ADC2 are provided to perform quadrature modulation / quadrature demodulation (IQ modulation / IQ demodulation). However, various circuit types are known for the analog front-end circuit AFE used in UWB, and it is not necessarily limited to the circuit type shown in FIG.

[0023] The frequency conversion circuit FCV includes a transmission conversion circuit CVtx and a reception conversion circuit CVrx. The transmission conversion circuit CVtx includes filters FLTt1 and FLTt2, mixers MIXt1 and MIXt2, and an adder ADD. The reception conversion circuit CVrx includes filters FLTr1 and FLTr2, and mixers MIXr1 and MIXr2.

[0024] In the transmitting conversion circuit CVtx, filters FLTt1 and FLTt2 filter the transmit analog signal, i.e., the transmit pulse signal Ptx, from the digital-to-analog converters DAC1 and DAC2. Mixers MIXt1 and MIXt2 multiply the filtered signal by local signals LO1 and LO2 from the local oscillator circuit LOSC. An adder ADD adds the signals from mixers MIXt1 and MIXt2.

[0025] With this configuration, the transmitting conversion circuit CVtx performs frequency conversion from a baseband signal to a high-frequency signal, i.e., up-conversion, using the local signals LO1 and LO2 from the local oscillator circuit LOSC. Furthermore, in this example, the transmitting conversion circuit CVtx inputs the I and Q signals that make up the transmission pulse signal Ptx from the digital-to-analog converters DAC1 and DAC2, and performs quadrature modulation using the local signals LO1 and LO2 that are 90 degrees out of phase with each other.

[0026] Meanwhile, in the receiving conversion circuit CVrx, mixers MIXr1 and MIXr2 multiply the high-frequency signal from the receiving amplifier LNA by local signals LO1 and LO2 from the local oscillator circuit LOSC. Filters FLTr1 and FLTr2 filter the signals from mixers MIXr1 and MIXr2 and output the filtered signals to analog-to-digital converters ADC1 and ADC2.

[0027] With this configuration, the receiving conversion circuit CVrx uses the local signals LO1 and LO2 from the local oscillator circuit LOSC to perform frequency conversion from a high-frequency signal to a baseband signal, i.e., down-conversion. Furthermore, in this example, the receiving conversion circuit CVrx inputs the high-frequency signal from the receiving amplifier LNA and performs quadrature demodulation to an I signal and a Q signal using the local signals LO1 and LO2.

[0028] The transmitting amplifier AMP amplifies the high-frequency signal from the transmitting conversion circuit CVtx, specifically the adder ADD. The transmitting amplifier AMP then radiates the amplified high-frequency signal RFtx into the air via an antenna ANT provided outside the semiconductor device 10. Meanwhile, the receiving amplifier LNA, for example, a low-noise amplifier, amplifies the high-frequency signal RFrx received by the external antenna ANT and outputs the amplified high-frequency signal to the receiving conversion circuit CVrx, specifically the mixers MIXr1 and MIXr2.

[0029] The pulse signal generating circuit PLSG, pulse signal dividing circuit PLSD, transmission data storage area AR-TXD, data transfer circuit DTC, digital-to-analog converters DAC1 and DAC2, transmission conversion circuit CVtx, and transmission amplifier AMP constitute a transmission circuit TXC, while the time difference correction circuit TDCC, phase difference estimation circuit PHDE, phase correction circuit PHCC, signal restoration circuit RESC, reception data storage area AR-RXD, analog-to-digital converters ADC1 and ADC2, reception conversion circuit CVrx, and reception amplifier LNA constitute a reception circuit RXC.

[0030] In this example, the baseband circuit BBC is realized by program processing using the processor PRC. However, the baseband circuit BBC is not limited to the processor PRC, and may be realized using, for example, an FPGA (Field Programmable Gate Array) or a dedicated digital circuit. In other words, the semiconductor device 10 shown in FIG. 1 may include an FPGA or a dedicated digital circuit. Before describing the details of the semiconductor device 10 shown in FIG. 1, various elemental technologies that the present inventors have considered as a premise for the embodiment will be described below.

[0031] <Distance measurement method> Fig. 15 is a schematic diagram illustrating an example of a distance measurement method using a UWB system. The UWB system shown in Fig. 15 includes two transmitting and receiving terminals TRX1 and TRX2. The two transmitting and receiving terminals TRX1 and TRX2 are respectively equipped with semiconductor devices 10a and 10b as shown in Fig. 1.

[0032] In such a UWB system, first, the transmitting / receiving terminal TRX1 functions as a transmitting terminal and transmits a pulse signal to the transmitting / receiving terminal TRX2 at timing t0. The transmitted pulse signal arrives at the transmitting / receiving terminal TRX2 after a time of flight ToF. The transmitting / receiving terminal TRX2 functions as a receiving terminal and estimates the arrival timing tOA1 of the pulse signal from the transmitting / receiving terminal TRX1. Then, the transmitting / receiving terminal TRX2 functions as a transmitting terminal and transmits a pulse signal to the transmitting / receiving terminal TRX1 after waiting a predetermined waiting time Tw from the estimated arrival timing tOA1.

[0033] The pulse signal from the transceiver terminal TRX2 reaches the transceiver terminal TRX1 after the flight time ToF. The transceiver terminal TRX1 functions as a receiving terminal and estimates the arrival timing tOA2 of the pulse signal from the transceiver terminal TRX2. Then, the transceiver terminal TRX1 calculates the flight time ToF from "2ToF + Tw". That is, the transceiver terminal TRX1 can calculate the flight time ToF by subtracting the waiting time Tw from the time from the timing t0 to the arrival timing tOA2 and dividing the subtraction result by 2. Furthermore, the transceiver terminal TRX1 can also calculate the distance between the two transceiver terminals TRX1 and TRX2 based on the flight time ToF.

[0034] <Regarding the pulse signal based on the UWB standard> FIG. 16A is a waveform diagram showing an example of pulse signals Pa and Pb used in a UWB system. FIG. 16B is a diagram showing an example of the frequency characteristics of the pulse signals Pa and Pb shown in FIG. 16A. In the UWB system, as shown in FIG. 16A, pulse signals Pa and Pb with high peaks and narrow time widths are used. Then, by transmitting and receiving such pulse signals Pa and Pb between two terminals, the distance measurement as described in FIG. 15 is performed.

[0035] Here, in distance measurement, the measurement error can increase as the time width of the pulse signals Pa and Pb increases. That is, the estimation errors of the arrival timings tOA1 and tOA2 shown in FIG. 15 can increase. Therefore, in order to improve the ranging accuracy, it is desirable to use a pulse signal having a sharper waveform shape.

[0036] On the other hand, in such a pulse signal, as the waveform shape becomes sharper, that is, as the peak becomes higher and the time width becomes narrower, the frequency bandwidth increases. In the example shown in FIG. 16B, the frequency bandwidth of the pulse signal Pa is 250 MHz. In contrast, the frequency bandwidth of the pulse signal Pb having a sharper waveform shape is 500 MHz.

[0037] However, the allowable frequency bandwidth can usually be limited to a predetermined value based on the communication standard in order to avoid interference with other communication devices. For example, when the allowable frequency bandwidth is limited to 250 MHz, it may be difficult to perform distance measurement using the pulse signal Pb having a sharper waveform shape as it is. As a result, it may also be difficult to improve the ranging accuracy.

[0038] <Regarding the division of the frequency bandwidth> Therefore, a method of dividing the frequency bandwidth of the pulse signal can be considered. FIGS. 17A and 17B are schematic diagrams showing an example of a method of dividing the frequency bandwidth of the original pulse signal at the time of transmission in a UWB system. FIG. 17A shows the amplitude (Mag) spectrum and phase (Phase) spectrum of the original pulse signal POtx used for transmission. The original pulse signal POtx has a frequency bandwidth from frequency f1 to frequency f2.

[0039] Also, FIG. 17A shows two or two-channel spectrum masks SMc1, SMc2. Each spectrum mask SMc1, SMc2 defines an allowable range based on the communication standard regarding the frequency bandwidth and amplitude included in the pulse signal. In this example, the spectrum mask SMc1 limits the pulse signal to a bandwidth from frequency f1 to frequency f3 (<f2). On the other hand, the spectrum mask SMc2 limits the pulse signal to a bandwidth from frequency f3 to frequency f2.

[0040] The semiconductor device 10 divides the original pulse signal POtx into two divided pulse signals PD1, PD2 having different frequency bandwidths using two spectrum masks SMc1, SMc2 so as to be within the range of the frequency bandwidth defined by the communication standard. Then, as shown in FIG. 17B, the semiconductor device 10 sequentially transmits the two divided pulse signals PD1, PD2 with a time shift. Thereby, the frequency bandwidth of the signal transmitted at one time can satisfy the communication standard.

[0041] 18A and 18B are schematic diagrams showing an example of a method for restoring the original pulse signal from a plurality of divided pulse signals PD1 and PD2 during reception in a UWB system. As shown in FIG. 18A, the semiconductor device 10 sequentially receives the plurality of divided pulse signals PD1 and PD2 transmitted with a time lag, and corrects the time difference to cancel out the time lag. That is, the semiconductor device 10 corrects the time difference between the plurality of divided pulse signals PD1 and PD2 so that the plurality of divided pulse signals PD1 and PD2 are received simultaneously at timing t1.

[0042] Then, as shown in Fig. 18A, the semiconductor device 10 restores the original pulse signal POrx by combining, more specifically adding, the signals that have undergone time difference correction. Ideally, the restored pulse signal POrx has the same waveform as the original pulse signal POtx at the time of transmission. That is, as shown in Fig. 18B, the amplitude spectrum and phase spectrum of the restored original pulse signal POrx are the same as the amplitude spectrum and phase spectrum of the original pulse signal POtx at the time of transmission shown in Fig. 17A.

[0043] <Problems with frequency bandwidth division methods> However, the frequency bandwidth division methods described in Figures 17A, 17B, 18A, and 18B can cause the following problems. Figure 19 is a schematic diagram showing an example of problems that can occur when a frequency bandwidth division method is used in a UWB system. The first problem, as shown in Figure 19, is that divided pulse signals PD1 and PD2 received at the receiving terminal may experience phase shifts 21 and 22 based on the phase PHo of the original pulse signal POtx at the time of transmission.

[0044] The main cause of such phase shifts 21 and 22 is that, for example, the two transmitting / receiving terminals TRX1 and TRX2 shown in FIG. 15 do not share the reference oscillation circuit ROSC shown in FIG. 1. That is, the transmitting / receiving terminal TRX1 is connected to a crystal oscillator XTAL mounted on the transmitting / receiving terminal TRX1 and operates based on the oscillation of the crystal oscillator XTAL. On the other hand, the transmitting / receiving terminal TRX2 is connected to another crystal oscillator XTAL mounted on the transmitting / receiving terminal TRX2 and operates based on the oscillation of the crystal oscillator XTAL. As a result, the frequencies and phases recognized by the two transmitting / receiving terminals TRX1 and TRX2 may, strictly speaking, be different from each other.

[0045] When such phase shifts 21 and 22 occur, a discontinuity point 24 occurs in the restored original pulse signal POrx at the boundary between phase PHr1 of divided pulse signal PD1 and phase PHr2 of divided pulse signal PD2. As a result, a pulse signal POrx having a waveform different from that of the original pulse signal POrx at the transmitting terminal may be restored at the receiving terminal. If a pulse signal POrx different from that at the time of transmission is restored in this way, the accuracy of ranging may decrease when performing distance measurement as described in FIG. 15 based on the pulse signal POrx.

[0046] Fig. 20 is a schematic diagram showing an example of another problem that occurs when a frequency bandwidth division method is used in a UWB system. As shown in Fig. 20, for example, when the antenna ANT is used as a reference, the transmission interval Ttx of the two divided pulse signals PD1 and PD2 at the transmitting / receiving terminal TRX1 and the reception interval Trx of the two divided pulse signals PD1 and PD2 at the transmitting / receiving terminal TRX2 are the same length.

[0047] For this reason, for example, the two transmitting and receiving terminals TRX1 and TRX2 may store in advance a common number of clock cycles "N" that represents the transmission interval Ttx and the reception interval Trx. This allows the transmitting and receiving terminal TRX2 to align the two divided pulse signals PD1 and PD2 to the same timing t1 by internal processing based on the common number of clock cycles "N," as shown in FIG. 18A.

[0048] However, in reality, the two transmitting / receiving terminals TRX1 and TRX2 do not share the reference oscillation circuit ROSC shown in FIG. 1. Therefore, as a second problem, as shown in FIG. 20, the number of clock cycles "N" in the transmitting / receiving terminal TRX1, which represent the transmission interval Ttx and the reception interval Trx, may differ from the number of clock cycles "M" in the transmitting / receiving terminal TRX2. As a result, it may be difficult to perform high-precision restoration processing using the method of determining a common number of clock cycles "N" as described above. Therefore, it is advantageous to use the semiconductor device 10 shown in FIG. 1, particularly the baseband circuit BBC.

[0049] <Outline of the main parts of the transmission circuit> Fig. 2 is a schematic diagram illustrating an example of the processing content when the transmission circuit TXC shown in Fig. 1 divides a pulse signal. In Fig. 2, the transmission circuit TXC divides the original pulse signal POtx having a frequency bandwidth from frequency f1 to frequency f2 into multiple, in this example, two divided pulse signals PD1 and PD2, similar to the case of Fig. 17A, so that each frequency bandwidth falls within the frequency bandwidth range defined by the UWB communication standard.

[0050] 17A, the transmission circuit TXC divides the original pulse signal POtx into two divided pulse signals PD1 and PD2 so that the common frequency range 30, which is part of the frequency bandwidth, overlaps.The transmission circuit TXC then transmits the two divided pulse signals PD1 and PD2 in sequence at a predetermined transmission interval, similar to the case of FIG.

[0051] <Outline of the main parts of the receiving circuit> 18A, the receiver circuit RXC first sequentially receives multiple, for example, two divided pulse signals PD1 and PD2 at a predetermined reception interval, i.e., a time difference based on a predetermined transmission interval. The baseband circuit BBC in the receiver circuit RXC then corrects the time difference between the two divided pulse signals PD1 and PD2 sequentially input via the analog front-end circuit AFE to make them appear as if they were received simultaneously. However, in this case, the baseband circuit BBC uses a method of calculating a correlation function, as described below, rather than the method of determining a common number of clock cycles "N" representing the transmission interval Ttx and the reception interval Trx, as described in FIG. 20.

[0052] [Time difference correction] Fig. 3 is a schematic diagram illustrating an example of the processing contents of the time difference correction performed by the receiving circuit RXC shown in Fig. 1. First, the divided pulse signal extraction circuit PDE shown in Fig. 1 extracts, for example, received digital signals Drd1 and Drd2 corresponding to the divided pulse signals PD1 and PD2, respectively, from the received digital signals from the analog-digital converters ADC1 and ADC2, based on the time difference of the above-mentioned common number of clock cycles "N."

[0053] Then, the divided pulse signal extraction circuit PDE stores the extracted received digital signals Drd1 and Drd2 in the received data storage area AR-RXD, as shown in Fig. 3. However, as described in Fig. 20, the correct time difference between the two divided pulse signals PD1 and PD2 is not necessarily the same number of clock cycles "N," but can also be any number before or after that.

[0054] Therefore, the baseband circuit BBC in the receiving circuit RXC uses the received digital signals Drd1 and Drd2 stored in the received data memory area AR-RXD to calculate the correlation function of the two divided pulse signals PD1 and PD2 when the reception timing of one of the divided pulse signals PD1 and PD2, here PD2, is shifted, as shown in Figure 3. The baseband circuit BBC then searches for the amount of shift that maximizes the correlation function of the two divided pulse signals PD1 and PD2, i.e., the similarity. Specifically, the baseband circuit BBC calculates the correlation function of the two divided pulse signals PD1 and PD2, i.e., the inner product, based on equation (1). <Drd1,Drd2> =Σ(Drd1[i] Drd2[j]) …(1)

[0055] In equation (1), Drd1[i] is the digital value of divided pulse signal PD1 sampled at sampling timing [i]. Drd2[j] is the digital value of divided pulse signal PD2 sampled at shifted sampling timing [j]. The baseband circuit BBC performs the calculation shown in equation (1) to find the shift amount that maximizes the inner product, and applies this shift amount to perform time difference correction to match the reception timings of the two divided pulse signals PD1 and PD2.

[0056] In the example shown in Figure 3, when the receive timing of divided pulse signal PD2 is shifted starting from the common clock cycle number "N", the inner product is maximized for shift amount candidate [1]. The baseband circuit BBC can match the receive timing of the two divided pulse signals PD1 and PD2 by applying shift amount candidate [1] to correct the time difference.

[0057] [About phase correction] Fig. 4 is a schematic diagram illustrating an example of the contents of the phase correction process performed by the receiving circuit RXC shown in Fig. 1. As shown in Fig. 4, the baseband circuit BBC in the receiving circuit RXC corrects the phases of the two divided pulse signals PD1 and PD2 after time difference correction so that they are continuous within the common frequency range 30. Specifically, as shown in Fig. 4, the baseband circuit BBC corrects, for example, the phase PHr2 of the divided pulse signal PD2 to a phase PHr2c so that it is continuous with the phase PHr1 of the divided pulse signal PD1 within the common frequency range 30.

[0058] The baseband circuit BBC then combines, more specifically adds, the two phase-corrected divided pulse signals PD1 and PD2 to restore the original pulse signal POrx. By performing such time difference correction and phase correction, the restored original pulse signal POrx at the time of reception has a waveform identical to that of the original pulse signal POtx at the time of transmission.

[0059] On the other hand, in order to perform the phase correction shown in Fig. 4, it is necessary to obtain the phase difference between the phase PHr1 of the divided pulse signal PD1 and the phase PHr2 of the divided pulse signal PD2. One method for obtaining such a phase difference is, for example, a method using a Fourier transform. However, using a Fourier transform can require a large amount of calculation.

[0060] Therefore, to obtain the phase difference, the baseband circuit BBC multiplies the divided pulse signal PD1 by the divided pulse signal PD2 and extracts the DC component from the multiplication result. That is, the baseband circuit BBC removes the AC component by applying a low-pass filter to the multiplication result. This allows the baseband circuit BBC to estimate the phase difference between the phase PHr1 of the divided pulse signal PD1 and the phase PHr2 of the divided pulse signal PD2 with a small amount of calculation.

[0061] 5 is a schematic diagram illustrating the operating principle when the receiving circuit RXC shown in FIG. 1 estimates the phase difference between two divided pulse signals PD1 and PD2. First, the multiplication result of divided pulse signal PD1 and divided pulse signal PD2 is given by equation (2). In equation (2), f1, θ1, and A1 are the frequency, phase, and amplitude of divided pulse signal PD1, respectively. f2, θ2, and A2 are the frequency, phase, and amplitude of divided pulse signal PD2, respectively. 2A1cos(2πf1t+θ1) A2cos(2πf2t+θ2) =A1A2cos{2π(f1+f2)t+(θ1+θ2)}+A1A2cos{2π(f1-f2)t+(θ1-θ2)} …(2)

[0062] Here, in equation (2), if frequencies f1 and f2 do not match, no DC component is generated. On the other hand, if frequencies f1 and f2 match, the DC component "A1A2cos(θ1-θ2)" is generated. Therefore, by applying a low-pass filter to the multiplication result, the DC component "A1A2cos(θ1-θ2)" is extracted.

[0063] The extracted DC component “A1A2cos(θ1-θ2)” is the common frequency range 30 in FIG. X Therefore, the baseband circuit BBC detects the phase difference "θ1-θ2" at this matching frequency f X Based on the phase difference "θ1-θ2" at the time of the divided pulse signal PD1, the phase PHr1 of the divided pulse signal PD1 and the phase PHr2c of the divided pulse signal PD2 can be made continuous in the common frequency range 30 as shown in FIG.

[0064] <Detailed operation of the transmitting circuit TXC> Fig. 6 is a flowchart showing an example of detailed processing contents of the transmission circuit TXC shown in Fig. 1. Figs. 7, 8 and 9 are schematic diagrams for explaining in more detail some of the processing contents shown in Fig. 6. In Fig. 6, first, the pulse signal generation circuit PLSG generates an original pulse signal POtx (step S101). As shown in Fig. 7, the original pulse signal POtx has a frequency f 1L to frequency f 2H It has a frequency bandwidth of up to

[0065] Next, in step S102, the pulse signal division circuit PLSD divides the original pulse signal POtx into a plurality of divided pulse signals, for example, two divided pulse signals PD1 and PD2, so that each frequency bandwidth falls within the frequency bandwidth range defined by the UWB communication standard. At this time, the pulse signal division circuit PLSD divides the original pulse signal POtx into the two divided pulse signals PD1 and PD2 so that the common frequency range 30 overlaps. Then, the pulse signal division circuit PLSD stores transmission digital signals Dtd1 and Dtd2 corresponding to the two divided pulse signals PD1 and PD2, respectively, in the transmission data memory area AR-TXD.

[0066] Specifically, in step S102, the pulse signal division circuit PLSD divides the original pulse signal POtx into two divided pulse signals PD1 and PD2 using two filters FLTd1 and FLTd2, as shown in Fig. 7. The filter FLTd1 divides the original pulse signal POtx into two divided pulse signals PD1 and PD2 at a frequency f 1L From frequencies below frequency f 1H On the other hand, the filter FLTd2 has a passband up to the frequency f 2L ( <f 1H ) to frequency f 2H The common frequency range 30 has a passband up to a frequency f 2L to frequency f 1H The range is up to.

[0067] The two filters FLTd1 and FLTd2 have frequency characteristics such that a predetermined gain value, in this example, "1," is obtained in a frequency band excluding the common frequency range 30. On the other hand, the two filters FLTd1 and FLTd2 have frequency characteristics such that the sum of the gain value of the filter FLTd1 and the gain value of the filter FLTd2 is the predetermined gain value "1" in the common frequency range 30. In other words, the filter FLTd obtained by combining the two filters FLTd1 and FLTd2 has the predetermined gain value "1" in the frequency bandwidth of the original pulse signal POtx.

[0068] 6, the data transfer circuit DTC sequentially transfers the two divided pulse signals PD1 and PD2, more specifically, the transmission digital signals Dtd1 and Dtd2, stored in the transmission data storage area AR-TXD to the digital-analog converters DAC1 and DAC2 at a predetermined transmission interval Ttx. Specifically, as shown in FIG. 8, the transmission digital signals Dtd1 and Dtd2 are stored as time-series data in the areas of memory addresses MADR allocated in order from predetermined starting addresses #A1 and #A2 in the transmission data storage area AR-TXD.

[0069] The data transfer circuit DTC sequentially reads out the transmission digital signals Dtd1 from the transmission data storage area AR-TXD at a transfer rate of, for example, several GHz, and then sequentially reads out the transmission digital signals Dtd2 after a predetermined transmission interval Ttx. The digital-to-analog converters DAC1 and DAC2 convert the sequentially read out transmission digital signals Dtd1 and Dtd2 into analog signals at a sampling frequency of, for example, several GHz, the same as the transfer rate.

[0070] Subsequently, in step S104 shown in Fig. 6, the transmitting conversion circuit CVtx upconverts the two divided pulse signals PD1 and PD2, which have been converted into analog signals by the digital-to-analog converters DAC1 and DAC2, into high-frequency signals using local signals LO1 and LO2, as shown in Fig. 9. Next, the transmitting amplifier AMP amplifies the upconverted high-frequency signals as shown in Fig. 9 (step S105). Then, the transmitting amplifier AMP radiates the amplified high-frequency signal RFtx into the air via the external antenna ANT (step S106).

[0071] <Detailed operation of the receiving circuit RXC> Fig. 10 is a flowchart showing an example of detailed processing contents of the receiving circuit RXC shown in Fig. 1. Fig. 11, Fig. 12 and Fig. 13 are schematic diagrams that more specifically explain part of the processing contents shown in Fig. 10. In Fig. 10, first, the receiving circuit RXC receives a high frequency signal RFrx via an external antenna ANT (step S201).

[0072] 11, the receiving amplifier LNA amplifies the received high-frequency signal RFrx. The receiving conversion circuit CVrx down-converts the amplified high-frequency signal to a baseband signal. The analog-to-digital converters ADC1 and ADC2 then sequentially convert the down-converted signal to a received digital signal at a sampling frequency of, for example, several GHz.

[0073] 10, the divided pulse signal extraction circuit PDE extracts two divided pulse signals PD1 and PD2 from the received digital signals from the analog-to-digital converters ADC1 and ADC2 based on a predetermined time difference. Then, the divided pulse signal extraction circuit PDE stores the extracted two divided pulse signals PD1 and PD2, more specifically, the received digital signals Drd1 and Drd2 corresponding to the two divided pulse signals PD1 and PD2, respectively, in the received data storage area AR-RXD.

[0074] 12, in step S203, the divided pulse signal extraction circuit PDE holds in advance the time difference determined based on the transmission interval Ttx, i.e., the value of the reception interval Trx, and extracts reception digital signals Drd1 and Drd2 corresponding to the two divided pulse signals PD1 and PD2 based on the time difference value.The divided pulse signal extraction circuit PDE then stores the extracted reception digital signals Drd1 and Drd2 in order as time-series data in the reception data storage area AR-RXD in areas of memory addresses MADR allocated in order from predetermined starting addresses #A1 and #A2.

[0075] However, as described in Fig. 20, the number of clock cycles representing the time difference at the transmitting terminal may differ from the number of clock cycles representing the same time difference at the receiving terminal. For this reason, as shown in Fig. 12, when matching the reception timings of the two received digital signals Drd1 and Drd2 stored in the received data storage area AR-RXD, a timing error Δt, and therefore a deviation in the memory address MADR, occurs.

[0076] Therefore, in step S204 shown in Fig. 10, the time difference correction circuit TDCC corrects the time difference between the two divided pulse signals PD1 and PD2 by performing the processing described in Fig. 3 using the received digital signals Drd1 and Drd2 stored in the received data memory area AR-RXD. That is, the time difference correction circuit TDCC brings the timing error Δt shown in Fig. 12 closer to zero. Note that, in order to perform the processing described in Fig. 3, the divided pulse signal extraction circuit PDE extracts the divided pulse signal PD2 including the time period before and after the predetermined time difference.

[0077] 10, the phase difference estimation circuit PHDE estimates the phase difference "θ1-θ2" between the two divided pulse signals PD1 and PD2 in the common frequency range 30 by performing the process described with reference to FIG. 5. That is, the phase difference estimation circuit PHDE estimates the phase correction amount to be used in the phase correction circuit PHCC. Then, based on the estimated phase difference, the phase correction circuit PHCC corrects the phases of the two divided pulse signals PD1 and PD2 so that they are continuous in the common frequency range 30, as shown in FIG. 4 (step S206). In the example shown in FIG. 4, the phase correction circuit PHCC corrects the phase PHr2 of the divided pulse signal PD2 to a phase PHr2c.

[0078] Fig. 13 is a block diagram showing a schematic configuration example of the phase correction circuit PHCC in Fig. 1. The phase correction circuit PHCC includes, for example, a digital complex mixer as shown in Fig. 13. Generally, the phase correction circuit PHCC uses such a complex mixer to multiply a received digital signal Drd2 corresponding to divided pulse signal PD2 by a cos θ component and a sin θ component, thereby shifting the phase of divided pulse signal PD2 by "θ". The value of "θ" is set to the value of the phase difference estimated in step S205 in Fig. 10, i.e., "θ1-θ2" in Fig. 5.

[0079] Specifically, the phase correction circuit PHCC receives the I and Q signals corresponding to the received digital signal Drd2. These I and Q signals are IQ demodulated by the mixers MIXr1 and MIXr2 shown in FIG. 1 and digitized by the analog-to-digital converters ADC1 and ADC2. The phase correction circuit PHCC multiplies the I and Q signals by cos θ and −sin θ, respectively. The phase correction circuit PHCC then adds the multiplication results, “I × cos θ” and “Q × (−sin θ),” to generate the I and Q signals with their phase differences corrected, i.e., the received digital signal Drd2.

[0080] Next, in step S207 shown in Fig. 10, the signal restoration circuit RESC restores the original pulse signal POrx by combining, more specifically adding, the two divided pulse signals PD1 and PD2 after the time difference correction in step 204 and the phase correction in step S206 as shown in Fig. 4. The restored original pulse signal POrx has a waveform similar to that of the original pulse signal POtx at the time of transmission.

[0081] <About modified examples> Fig. 14 is a schematic diagram illustrating an example of processing content modified from Fig. 2. Fig. 2 shows an example in which the original pulse signal POtx is divided into two divided pulse signals PD1 and PD2, but the number of divisions may be three or more. In the example shown in Fig. 14, the transmission circuit TXC, more specifically the pulse signal division circuit PLSD, divides the original pulse signal POtx having a frequency bandwidth from frequency f1 to frequency f2 into three divided pulse signals PD1, PD2, and PD3.

[0082] The divided pulse signals PD1 and PD2 have a common frequency range 30a, as in the case of FIG. 2. Similarly, the divided pulse signals PD2 and PD3 have a common frequency range 30b. The transmission circuit TXC sequentially transmits the three divided pulse signals PD1, PD2, and PD3 at a predetermined transmission interval Ttx, as in the case of FIG. 8, etc. Even when three divided pulse signals PD1, PD2, and PD3 are used, the processing described with reference to FIGS. 6 and 10 can be performed on the divided pulse signals PD2 and PD3 in addition to the divided pulse signals PD1 and PD2.

[0083] <Major Effects of the Embodiment> As described above, the semiconductor device according to one embodiment divides an original pulse signal into multiple divided pulse signals so that the common frequency range overlaps during transmission, and then transmits the divided pulse signals sequentially at a predetermined transmission interval. Furthermore, during reception, the semiconductor device corrects the multiple divided pulse signals received with a predetermined time difference so that they appear to be received simultaneously, and corrects the phases of the multiple divided pulse signals so that their phases are continuous within the common frequency range. This configuration allows the time width of the pulse signal to be narrowed while satisfying communication standards. As a result, ranging accuracy is improved. Furthermore, by correcting the time difference and phase, the waveform shape of the original pulse signal at the time of transmission can be restored with high accuracy during reception. This further improves ranging accuracy.

[0084] The invention made by the inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit of the invention. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0085] Furthermore, each unit is typically implemented by program processing using a CPU (Central Processing Unit). That is, each unit is implemented on the CPU by the CPU executing a program stored in memory. However, the implementation form of each unit is not limited to this software, and may be hardware such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit), or may be a combination of software and hardware.

[0086] The above-mentioned program may be stored in a non-transitory, tangible, computer-readable recording medium and then supplied to a computer. Examples of such a recording medium include magnetic recording media such as hard disk drives, optical recording media such as DVDs (Digital Versatile Discs) and Blu-ray Discs, and semiconductor memories such as flash memories and SSDs (Solid State Drives). [Explanation of symbols]

[0087] 10 Semiconductor device 30 Common Frequency Range ADC1, ADC2 analog-to-digital converters AFE Analog Front-End Circuit AR-RXD Received data storage area AR-TXD Transmission data storage area BBC baseband circuit DAC1, DAC2 Digital-to-analog converters DTC data transfer circuit Drd1, Drd2 received digital signal Dtd1, Dtd2 Transmit digital signal FCV frequency conversion circuit FLTd1, FLTd2 filters LO1,LO2 local signal LOSC local oscillator circuit MEM memory NVM Non-Volatile Memory PD1, PD2 divided pulse signal PDE divided pulse signal extraction circuit PHCC phase correction circuit PHDE phase difference estimation circuit PLSD Pulse signal divider circuit PLSG Pulse signal generation circuit POtx,POrx Original pulse signal PRC Processor PRGrx receiving program PRGtx sending program Prx Received pulse signal Ptx Transmit pulse signal RAM Volatile memory RESC Signal restoration circuit RFtx, RFrx high frequency signals RO Reference oscillation signal ROSC Reference Oscillator RXC Receiver circuit TDCC time difference correction circuit TXC transmitter circuit Trx Reception Interval Ttx transmission interval XTAL crystal oscillator

Claims

1. a baseband circuit for processing a baseband signal, the baseband circuit including a memory for storing a transmission program or a reception program and a processor for executing the transmission program or the reception program; a reference oscillation circuit that generates a reference oscillation signal; a local oscillation circuit that generates a local signal using the reference oscillation signal; an analog front-end circuit that performs frequency conversion from the baseband signal to a high-frequency signal or from the high-frequency signal to the baseband signal using the local signal; A semiconductor device for UWB (Ultra-Wide Band) wireless communication, which is mounted on a transmitting terminal or a receiving terminal different from the transmitting terminal, When the semiconductor device is mounted on the transmitting terminal, The baseband circuit, based on the transmission program, (a) dividing an original pulse signal that will become the baseband signal into a plurality of divided pulse signals including a first divided pulse signal and a second divided pulse signal so that each frequency bandwidth is within a range of a frequency bandwidth defined by a UWB communication standard and so that a common frequency range that is a part of the frequency bandwidth overlaps; (b) transmitting the plurality of divided pulse signals sequentially at a first transmission interval to the receiving terminal via the analog front-end circuit; When the semiconductor device is mounted on the receiving terminal, The baseband circuit, based on the receiving program, (c) inputting the plurality of divided pulse signals sequentially received with a time difference based on the first transmission interval via the analog front-end circuit, and correcting the time difference between the plurality of divided pulse signals so that they are received simultaneously; (d) correcting the phases of the plurality of divided pulse signals so that they are continuous within the common frequency range; (e) restoring the original pulse signal by adding the divided pulse signals after the time difference correction in (c) and the phase correction in (d); Semiconductor device.

2. 2. The semiconductor device according to claim 1, the reference oscillation circuit generates the reference oscillation signal based on the frequency of a quartz crystal oscillator connected to an external device of the semiconductor device; The semiconductor device includes: When mounted on the transmitting terminal, the crystal oscillator is connected to the transmitting terminal; When mounted in the receiving terminal, it is connected to the crystal oscillator mounted in the receiving terminal. Semiconductor device.

3. 2. The semiconductor device according to claim 1, The analog front-end circuit comprises: a frequency conversion circuit that performs the frequency conversion; a digital-to-analog converter or an analog-to-digital converter; Equipped with When the semiconductor device is mounted on the transmitting terminal, the digital-to-analog converter converts a plurality of transmission digital signals stored in the memory into analog signals, which are digital signals corresponding to the plurality of divided pulse signals, and outputs the analog signals to the frequency conversion circuit; When the semiconductor device is mounted in the receiving terminal, the analog-to-digital converter converts each of the plurality of divided pulse signals from the frequency conversion circuit into a digital signal and stores the digital signals in the memory as a plurality of received digital signals. Semiconductor device.

4. 4. The semiconductor device according to claim 3, the memory stores a first received digital signal and a second received digital signal corresponding to the first divided pulse signal and the second divided pulse signal, respectively; When correcting the time difference in (c), the baseband circuit uses the first received digital signal and the second received digital signal to calculate a correlation function between the first divided pulse signal and the second divided pulse signal when the reception timing of one of the first divided pulse signal and the second divided pulse signal is shifted. Semiconductor device.

5. 4. The semiconductor device according to claim 3, the memory stores a first received digital signal and a second received digital signal corresponding to the first divided pulse signal and the second divided pulse signal, respectively; In the phase correction in (d), the baseband circuit (d1) multiplies the first divided pulse signal and the second divided pulse signal by using the first received digital signal and the second received digital signal, and extracts a DC component from the multiplication result to estimate a phase difference between the first divided pulse signal and the second divided pulse signal in the common frequency range. Semiconductor device.

6. 6. The semiconductor device according to claim 5, During the phase correction in (d), the baseband circuit further (d2) multiplies the second divided pulse signal by a cos θ component and a sin θ component using a complex mixer, with the phase difference estimated in (d1) being θ, thereby shifting the phase of the second divided pulse signal by θ. Semiconductor device.

7. 4. The semiconductor device according to claim 3, When dividing the signal into the plurality of divided pulse signals in (a), the baseband circuit uses a first filter and a second filter to generate a first transmit digital signal and a second transmit digital signal corresponding to the first divided pulse signal and the second divided pulse signal, respectively; The first filter and the second filter are a frequency characteristic that provides a first gain value in a frequency band excluding the common frequency range; the gain value of the first filter and the gain value of the second filter have frequency characteristics such that the sum of the gain values ​​of the first filter and the second filter is the first gain value in the common frequency range; Semiconductor device.

8. 4. The semiconductor device according to claim 3, The memory includes: an MRAM that stores the transmission program or the reception program; a volatile memory in which the plurality of transmitted digital signals or the plurality of received digital signals is stored; Equipped with Semiconductor device.

9. Memory and a baseband circuit for processing a baseband signal; a reference oscillation circuit that generates a reference oscillation signal; a local oscillation circuit that generates a local signal using the reference oscillation signal; an analog front-end circuit that performs frequency conversion from the baseband signal to a high-frequency signal or from the high-frequency signal to the baseband signal using the local signal; A semiconductor device for UWB (Ultra-Wide Band) wireless communication, The baseband circuit includes: As a transmitting circuit, a pulse signal division circuit that divides the original pulse signal that becomes the baseband signal into a plurality of divided pulse signals including a first divided pulse signal and a second divided pulse signal so that each frequency bandwidth is within a range of a frequency bandwidth defined by a UWB communication standard and so that a common frequency range that is a part of the frequency bandwidth overlaps; a data transfer circuit that sequentially transmits the plurality of divided pulse signals at a first transmission interval via the analog front-end circuit; Equipped with As a receiving circuit, a time difference correction circuit that receives the plurality of divided pulse signals sequentially with a time difference based on the first transmission interval via the analog front-end circuit and corrects the time difference between the plurality of divided pulse signals so that the signals appear to be received simultaneously; a phase correction circuit that corrects the phases of the plurality of divided pulse signals so that they are continuous within the common frequency range; a signal restoration circuit that restores the original pulse signal by adding the divided pulse signals after the time difference correction circuit and the phase correction circuit have performed time difference correction and phase correction, respectively; Equipped with Semiconductor device.

10. 10. The semiconductor device according to claim 9, The analog front-end circuit comprises: a frequency conversion circuit that performs the frequency conversion; a digital-to-analog converter as the transmission circuit; an analog-to-digital converter as the receiving circuit; Equipped with the digital-to-analog converter converts the plurality of transmission digital signals stored in the memory into analog signals, which are digital signals corresponding to the plurality of divided pulse signals, and outputs the analog signals to a frequency conversion circuit; the analog-to-digital converter converts each of the plurality of divided pulse signals from the frequency conversion circuit into a digital signal, and stores the digital signals in the memory as a plurality of received digital signals; Semiconductor device.

11. 11. The semiconductor device according to claim 10, the memory stores a first received digital signal and a second received digital signal corresponding to the first divided pulse signal and the second divided pulse signal, respectively; the time difference correction circuit uses the first received digital signal and the second received digital signal to calculate a correlation function between the first divided pulse signal and the second divided pulse signal when a reception timing of one of the first divided pulse signal and the second divided pulse signal is shifted. Semiconductor device.

12. 11. The semiconductor device according to claim 10, further comprising a phase difference estimation circuit for estimating a phase correction amount used in the phase correction circuit, the memory stores a first received digital signal and a second received digital signal corresponding to the first divided pulse signal and the second divided pulse signal, respectively; the phase difference estimation circuit multiplies the first divided pulse signal and the second divided pulse signal by using the first received digital signal and the second received digital signal, and extracts a DC component from the multiplication result, thereby estimating a phase difference between the first divided pulse signal and the second divided pulse signal in the common frequency range. Semiconductor device.

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