Control circuit and power supply device

Abstract

To suppress disturbance of a waveform of an input current.SOLUTION: A control circuit is provided that controls switching operation of a first switching element and a second switching element with respect to a power supply circuit having the first switching element for controlling a first current and a second switching element for controlling a second current. The control circuit includes a phase detection circuit configured to generate a phase difference signal indicating a phase difference between the first current and the second current, and a phase correction circuit configured to correct a second phase with which the second switching element operates with reference to a first phase with which the first switching element operates based on the phase difference signal and a length of an ON period of the second switching element.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a control circuit and a power supply device. [Background technology]

[0002] A power factor correction circuit (hereinafter referred to as a PFC circuit) that operates in critical current mode improves the power factor of a power supply by making the waveform of the peak value of the inductor current flowing through the inductor similar to the rectified voltage obtained by rectifying an AC voltage. In this case, multiple PFC circuits may be operated in an interleaved manner (for example, Patent Documents 1 to 7 and Non-Patent Document 1). Patent Document 1: JP 2022-041912 A Patent Document 2: International Publication No. 2008 / 032768 Patent Document 3: JP 2010-119285 A Patent Document 4: International Publication No. 2011 / 122172 Patent Document 5: JP 2016-086463 A Patent Document 6: JP 2011-229364 A Patent Document 7: JP 2010-016973 A Non-patent document 1: Electronic Devices Division, Applied Technology Department, "MH2501SC / MH2511SC Application Note Ver.3.0", Shindengen Co., Ltd., November 11, 2020, Figures 8, 9, Waveform 2, pp. 9-10, 20 Summary of the Invention [Problem to be solved by the invention]

[0003] In a control circuit such as a PFC circuit, it is preferable that the waveform of the input current has minimal disturbance. [Means for solving the problem]

[0004] One aspect of the present invention provides a power supply circuit including a first switching element that controls a first current flowing through a first inductor and a second switching element that controls a second current flowing through a second inductor provided in parallel with the first inductor, and that outputs a sum current of a current corresponding to the first current and a current corresponding to the second current. The control circuit may include a phase detection circuit that generates a phase difference signal that indicates a phase difference between the first current and the second current. The control circuit may include a phase correction circuit that corrects a second phase in which the second switching element operates based on the phase difference signal and the length of an on-period of the second switching element, with reference to a first phase in which the first switching element operates.

[0005] In any of the above control circuits, the phase correction circuit may include an ON width detection circuit that detects the length of an ON period of the second switching element.In any of the above control circuits, the phase correction circuit may include an ON width adjustment circuit that adjusts the length of the ON period of the second switching element by an ON width adjustment amount that corresponds to the length of the ON period detected by the ON width detection circuit and the phase difference signal.

[0006] In any of the control circuits described above, the ON width adjustment circuit may increase the ON width adjustment amount as the ON period becomes longer.

[0007] In any of the control circuits described above, the on-width adjustment circuit may calculate the on-width adjustment amount by multiplying a correction reference value corresponding to the magnitude of the phase difference indicated by the phase difference signal by a gain that increases as the on-period becomes longer.

[0008] In any of the above control circuits, the on-width adjustment circuit may calculate at least one of an upper limit value and a lower limit value of the on-width adjustment amount according to the length of the on-period. In any of the above control circuits, the on-width adjustment circuit may calculate the on-width adjustment amount within a range determined by the calculated upper limit value and the calculated lower limit value.

[0009] In any of the above control circuits, the on-width adjustment amount may be set to an integer multiple of a minimum set value. In any of the above control circuits, the on-width adjustment circuit may adjust the on-period by the on-width adjustment amount of the minimum set value when the length of the on-period is shorter than a set reference value.

[0010] In any of the above control circuits, the on-width adjustment amount may be set to an integer multiple of a minimum setting value. In any of the above control circuits, when adjusting the on-width adjustment amount in the same direction on the time axis as a previous adjustment, the on-width adjustment circuit may add the minimum setting value to an absolute value of the on-width adjustment amount while maintaining the sign of the on-width adjustment amount used in the previous adjustment.

[0011] In any of the above control circuits, when adjusting the on-period in a direction opposite to the previous adjustment on the time axis, the on-width adjustment circuit may invert the sign of the on-width adjustment amount used in the previous adjustment and reset the absolute value of the on-width adjustment amount to the minimum set value.

[0012] In any of the above control circuits, the phase detection circuit may detect a phase difference between a first control signal that controls switching of the first switching element and a second control signal that controls switching of the second switching element, and generate the phase difference signal.

[0013] In any of the control circuits described above, the first switching element and the second switching element may operate in a current boundary mode.

[0014] In any of the above control circuits, the phase detection circuit may receive a first control signal that controls switching of the first switching element, and detect an on-interval during which the first switching element is turned on based on the first control signal.In any of the above control circuits, the phase correction circuit may calculate a phase error between the phase difference and half the on-interval, and correct the second phase based on the phase error.

[0015] In any of the control circuits described above, the phase correction circuit may include a signed subtractor that receives as input a first digital signal indicating half the magnitude of the on interval and a second digital signal indicating the magnitude of the phase difference, and calculates the signed phase error by digital calculation.

[0016] In any of the above control circuits, the phase detection circuit may include a counter that receives the first control signal and a clock signal, counts and outputs the number of pulses of the clock signal, and resets the output to an initial value when the first switching element is turned on. In any of the above control circuits, the phase detection circuit may include a multiplier that multiplies the output of the counter by 1 / 2. In any of the above control circuits, the phase detection circuit may include a first latch unit that receives the output of the multiplier and the first control signal, and outputs the first digital signal obtained by latching the output of the multiplier when the first switching element is turned on. In any of the above control circuits, the phase detection circuit may include a second latch unit that receives the signal indicating the timing when the second switching element is turned on and the output of the counter, and outputs the second digital signal obtained by latching the output of the counter when the second switching element is turned on.

[0017] In any of the above control circuits, the phase detection circuit may have a selection section that selects and outputs either the output of the counter or the output of the second latch section in response to a signal indicating the timing at which the second switching element is turned on.

[0018] In any of the control circuits described above, the phase correction circuit may include a signed adder that receives as input a reference value of the on-period of the second switching element and an on-width adjustment amount corresponding to the phase error output by the signed subtractor, and adds the on-width adjustment amount to the reference value of the on-period.

[0019] In any of the control circuits described above, the phase correction circuit may have a limiter that limits the ON width adjustment amount in accordance with a reference value of the ON period.

[0020] A second aspect of the present invention provides a power supply device including the power supply circuit according to the first aspect and the control circuit according to the first aspect.

[0021] A third aspect of the present invention provides a control circuit for controlling switching operations of a first switching element and a second switching element for a power supply circuit including a first switching element that controls a first current flowing through a first inductor and a second switching element that controls a second current flowing through a second inductor provided in parallel with the first inductor, and outputting a sum current of a current corresponding to the first current and a current corresponding to the second current. The control circuit may include a phase detection circuit that generates a phase difference signal indicating a phase difference between the first current and the second current. Any of the above control circuits may include a phase correction circuit that corrects a second phase in which the second switching element operates based on the phase difference signal, with a first phase in which the first switching element operates as a reference. In any of the above control circuits, the phase detection circuit may receive a first control signal that controls switching of the first switching element and detect an on-interval in which the first switching element is turned on based on the first control signal. In any of the above control circuits, the phase correction circuit may calculate a phase error between the phase difference and half the on-interval, and correct the second phase based on the phase error. In any of the control circuits described above, the phase correction circuit may include a signed subtractor that receives as input a first digital signal indicating half the magnitude of the on interval and a second digital signal indicating the magnitude of the phase difference, and calculates the signed phase error by digital calculation.

[0022] In any of the above control circuits, the phase detection circuit may include a counter that receives the first control signal and a clock signal, counts and outputs the number of pulses of the clock signal, and resets the output to an initial value when the first switching element is turned on. In any of the above control circuits, the phase detection circuit may include a multiplier that multiplies the output of the counter by 1 / 2. In any of the above control circuits, the phase detection circuit may include a first latch unit that receives the output of the multiplier and the first control signal, and outputs the first digital signal obtained by latching the output of the multiplier when the first switching element is turned on. In any of the above control circuits, the phase detection circuit may include a second latch unit that receives the signal indicating the timing when the second switching element is turned on and the output of the counter, and outputs the second digital signal obtained by latching the output of the counter when the second switching element is turned on.

[0023] A fourth aspect of the present invention provides a power supply device including the power supply circuit according to the third aspect and the control circuit according to the third aspect.

[0024] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a diagram illustrating an example of the configuration of a power supply device 200 according to an embodiment of the present invention. [Figure 2] FIG. 10 is a diagram showing an example of the temporal waveform of a first current IL1 in a current critical mode. [Figure 3] 10A and 10B are diagrams showing examples of time waveforms of a first current IL1, a second current IL2, and a sum current IL1+IL2 when operating in a single mode and an interleaved mode. [Figure 4] FIG. 2 is a diagram illustrating an overview of a control circuit 100. [Figure 5]3A to 3C are diagrams illustrating an example of time waveforms of an AC voltage Vac, a PI signal, a ramp signal, a first output signal OUT1, and a first current IL1. [Figure 6] 10 is a block diagram showing an example of a second control signal generating unit 150. FIG. [Figure 7] 10 is a timing chart illustrating an example of the operation of the second control signal generating section 150. [Figure 8] 10 is a diagram illustrating an example of limiting the ON width adjustment amount ΔTon in the ON width adjustment circuit 174. FIG. [Figure 9] FIG. 10 is a diagram illustrating an integration method. [Figure 10] 4 is a timing chart showing a more detailed example of each signal in the control circuit 100. [Figure 11] 10 shows an example of the time waveform of the input current in an embodiment in which the magnitude of the adjustment amount ΔTon is limited in accordance with the ON width Ton, and in a comparative example in which no limit is imposed. [Figure 12] 10 is a diagram illustrating another example of the configuration of the phase detection circuit 160 and the phase correction circuit 170. FIG. [Figure 13] 13 is a timing chart showing an example of the operation of the phase detection circuit 160 and the phase correction circuit 170 in the example of FIG. 12. [Figure 14] 10 is a timing chart showing another example of the operation of the phase detection circuit 160 and the phase correction circuit 170. DETAILED DESCRIPTION OF THE INVENTION

[0026] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0027] In this specification, the magnitude of a resistance value, a current value, a voltage value, or other parameter may be described as being equal or identical. These parameters are not limited to being completely equal, but may differ within the scope of the invention described in this specification. For example, equal or identical allows for an error of 10% or less.

[0028] In this specification, the term "circuit" refers not only to an analog circuit or a wired logic circuit, but also to a functional block (or means) included in a DSP (Digital Signal Processor) or a microcomputer, etc., that can perform digital arithmetic processing.

[0029] In describing a circuit, when it is said that element C is provided "between" element A and element B, it means that element C is provided between element A and element B in the current path. The above description does not limit the spatial position of element C.

[0030] FIG. 1 is a diagram showing an example of the configuration of a power supply device 200 according to an embodiment of the present invention. The power supply device 200 of this example functions as an AC-DC converter. The power supply device 200 of this example includes a power supply circuit 10 and a control circuit 100. The power supply circuit 10 generates a DC output voltage Vout corresponding to a predetermined target level from an AC voltage Vac input from an external power supply 12. The power supply 12 is, for example, a commercial power supply. The control circuit 100 controls the operation of the power supply circuit 10. The control circuit 100 may function as a PFC circuit that improves the power factor in the power supply circuit 10.

[0031] The power supply circuit 10 includes a first inductor 21, a second inductor 22, a first switching element 51, and a second switching element 52. An input voltage Vin obtained by rectifying an AC voltage Vac is input to the first inductor 21. A current flowing through the first inductor 21 is defined as a first current I L1The second inductor 22 is provided in parallel with the first inductor 21. An input voltage Vin obtained by rectifying the AC voltage Vac is input to the second inductor 22. The current flowing through the second inductor 22 is defined as a second current I L2 Let's say.

[0032] The first switching element 51 controls the first current I L1 The first switching element 51 of this example is provided between the first inductor 21 and the reference potential PGND, and switches whether or not the first inductor 21 is connected to the reference potential PGND.

[0033] The second switching element 52 controls the second current I L2 The second switching element 52 of this example is provided between the second inductor 22 and the reference potential PGND, and switches whether or not the second inductor 22 is connected to the reference potential PGND. The power supply circuit 10 controls the first current I L1 and a second current I L2 The sum of the current corresponding to the

[0034] The power supply circuit 10 of this example further includes a low potential line 15, a high potential line 13, a full-wave rectifier circuit 14, a capacitor 16, a first capacitor 41, a second capacitor 42, a first diode 31, a second diode 32, and voltage dividing resistors 33 and 34. The full-wave rectifier circuit 14 full-wave rectifies the input AC voltage Vac and outputs it as an input voltage Vin. The AC voltage Vac has an effective value of 100 to 240 V and a frequency of 50 to 60 Hz, for example.

[0035] The capacitor 16 is provided between the high potential line 13 and the low potential line 15. The capacitor 16 smoothes the input voltage Vin. The smoothed input voltage Vin is applied to the first inductor 21 and the second inductor 22 in this example.

[0036] The first diode 31 has an anode connected to the first inductor 21 and a first current I L1The first capacitor 41 is charged with a current corresponding to the first current I L1 When is a positive value, a current flows from the first inductor 21 to the first diode 31. A node between the anode of the first diode 31 and the first inductor 21 is connected to the first switching element 51. The first switching element 51 repeatedly turns on and off, so that the first inductor 21, the first diode 31, the first capacitor 41, and the first switching element 51 function as a boost chopper circuit.

[0037] The second diode 32 has an anode connected to the second inductor 22 and a second current I L2 The second capacitor 42 is charged with a current corresponding to the second current I L2 When is a positive value, a current flows from the second inductor 22 to the second diode 32. A node between the anode of the second diode 32 and the second inductor 22 is connected to the second switching element 52. The second switching element 52 repeatedly turns on and off, so that the second inductor 22, the second diode 32, the second capacitor 42, and the second switching element 52 function as a boost chopper circuit.

[0038] The cathode of the first diode 31 and the cathode of the second diode 32 are connected to the node 17. As a result, the first current I L1 and a second current I L2 A current corresponding to the sum of the current and the current corresponding to the

[0039] The first capacitor 41 and the second capacitor 42 are arranged in parallel with each other between the node 17 and the low potential line 15. The charging voltages of the first capacitor 41 and the second capacitor 42 are output as a DC output voltage Vout. In FIG. 1, the first capacitor 41 and the second capacitor 42 are electrolytic capacitors, but they may be other types of capacitors. Furthermore, in FIG. 1, the first capacitor 41 and the second capacitor 42 are shown as separate capacitors, but they may be combined into a single capacitor.

[0040] The voltage dividing resistors 33 and 34 are connected in series between the node 17 and the low potential line 15. The voltage dividing resistors 33 and 34 divide the output voltage Vout in accordance with their resistance ratio to generate a feedback voltage FB, which is input to a feedback terminal 106 of the control circuit 100. The control circuit 100 controls the switching operations of the first switching element 51 and the second switching element 52 in accordance with the feedback voltage FB, thereby adjusting the output voltage Vout to a predetermined target level.

[0041] The power supply circuit 10 may further include a first resistor 61, a second resistor 62, capacitors 80, 82, 84, and 86, a diode 71, and a diode 72. The first resistor 61 is provided between the first switching element 51 and a reference potential PGND. The second resistor 62 is provided between the second switching element 52 and a reference potential PGND.

[0042] The capacitor 80 and the capacitor 82 are connected in series with each other. In this example, the capacitor 80 is arranged on the high-voltage side, and the capacitor 82 is arranged on the low-voltage side. The capacitors 80 and 82 are arranged in parallel with the first switching element 51 and the first resistor 61. The diode 71 is connected in parallel with the capacitor 82. The anode of the diode 71 is connected to the node between the capacitor 80 and the capacitor 82, and the cathode is connected to the reference potential PGND. A voltage ZCD1 corresponding to the source-drain voltage of the first switching element 51 is generated at the node between the capacitor 80 and the capacitor 82. The voltage ZCD1 is proportional to the first current I L1 The voltage ZCD1 is input to the input terminal 102 of the control circuit 100.

[0043] The capacitor 84 and the capacitor 86 are connected in series with each other. In this example, the capacitor 84 is arranged on the high-voltage side, and the capacitor 86 is arranged on the low-voltage side. The capacitors 84 and 86 are arranged in parallel with the second switching element 52 and the second resistor 62. The diode 72 is connected in parallel with the capacitor 86. The anode of the diode 72 is connected to the node between the capacitors 84 and 86, and the cathode is connected to the reference potential PGND. A voltage ZCD2 corresponding to the source-drain voltage of the second switching element 52 is generated at the node between the capacitors 84 and 86. The voltage ZCD2 is proportional to the second current I L2 The voltage ZCD2 is input to the input terminal 104 of the control circuit 100.

[0044] The control circuit 100 of this example has an input terminal 102, an input terminal 104, a feedback terminal 106, an output terminal 108, an output terminal 110, and a reference potential terminal 112. A reference potential PGND is applied to the reference potential terminal 112.

[0045] The control circuit 100 generates a first output signal OUT1 and a second output signal OUT2 based on voltages ZCD1, ZCD2, and a feedback voltage FB input to input terminals 102, 104, and feedback terminal 106. The first output signal OUT1 is input to a control terminal of a first switching element 51, and the second output signal OUT2 is input to a control terminal of a second switching element 52. In this example, the first switching elements 51 and 52 are n-channel MOSFETs.

[0046] The control circuit 100 of this example is an integrated circuit that controls the switching operations of the first switching element 51 and the second switching element 52 so that the level of the output voltage Vout becomes a target level (e.g., 400 V) while improving the input power factor of the power supply circuit 10.

[0047] In the power supply circuit 10, the boost chopper circuit including the first inductor 21 is referred to as the a-phase, and the boost chopper circuit including the second inductor 22 is referred to as the b-phase. L1 and the second current I of phase b L2 The control circuit 100 may have a mode in which the power supply circuit 10 is controlled by an interleaving method in which the phases of the first and second switching elements 51 and 52 are shifted by 180 degrees from each other. The control circuit 100 may also operate each phase (e.g., the first switching element 51 and the second switching element 52) ​​in the power supply circuit 10 in a so-called current critical mode (also referred to as a critical mode).

[0048] The control circuit 100 of this example controls the first current I L1 The second current I L2 This allows for adjusting the phase of the first current I L1 and the second current I L2 The phase difference with the second current I is maintained at 180 degrees. L2 If the phase of the second current I is suddenly changed, the waveform of the input current input to the first inductor 21 and the second inductor 22 may become distorted, and the power factor may decrease.L2 This limits the amount of adjustment of the phase of the first current I L1 and the second current I L2 The phase difference between the second current I L2 The details of the limit on the amount of phase adjustment will be described later.

[0049] Figure 2 shows the first current I in the critical conduction mode. L1 1 is a diagram showing an outline of the time waveform of the second current I L2 The control circuit 100 may control the first current I L1 When the current value of the first current I becomes 0, the first switching element 51 is controlled to be in the ON state. L1 After a predetermined ON period has elapsed, the control circuit 100 controls the first switching element 51 to the OFF state. As a result, the first current I L1 The ON period may be determined according to the feedback voltage FB so that the output voltage Vout matches a predetermined target level. After turning off the first switching element 51, the control circuit 100 turns off the first current I L1 When the current value becomes 0, the control circuit 100 turns on the first switching element 51 again. By repeating this control, the control circuit 100 controls the switching operation of the first switching element 51.

[0050] When the capacitance of the first capacitor 41 or the second capacitor 42 is sufficiently large, the feedback voltage FB becomes substantially constant within a period of about one cycle of the AC voltage Vac. If the target level of the output voltage Vout becomes substantially constant within a period of about one cycle of the AC voltage Vac, the on-period of the first switching element 51 also becomes substantially constant within a period of about one cycle of the AC voltage Vac.

[0051] When the first switching element 51 is turned on, if the level of the input voltage Vin obtained by rectifying the AC voltage Vac increases, the first current I L1 As a result, the current value of the first current I L1 The waveform of the envelope connecting the peaks of the input voltage Vin is similar to that of the input voltage Vin.

[0052] 1st current I L1 When the peak value level of the first current I increases, the first switching element 51 turns off and the first current I L1 becomes zero. Therefore, when the level of the input voltage Vin is low, the switching frequency of the first switching element 51 becomes high, and when the level of the input voltage Vin is high, the switching frequency of the first switching element 51 becomes low.

[0053] Figure 3 shows the first current I when operating in single and interleaved mode. L1 , second current I L2 , sum current I L1 +I L2 In the single-mode system of this example, the second switching element 52 is always in the OFF state, and the second current I L2 The sum current I in single operation L1 +I L2 is the first current I L1 is the same as

[0054] In the interleaved method, the first current I L1 and the second current I L2 The switching operations of the first switching element 51 and the second switching element 52 are controlled so that the phases of the sum currents I L1 +I L2 The frequency of the first current I L1 The frequency is approximately twice that of the sum current I L1 +I L2 The ripple current at

[0055] In the interleaving method, the switching loss is distributed to multiple switching elements (in this example, the first switching element 51 and the second switching element 52). This reduces the load on each switching element, making thermal design easier. In addition, the sum current I L1 +I L2 The ripple current in can be reduced and the effective frequency can be increased, so the sum current IL1 +I L2 When filtering, the filter size can be reduced.

[0056] On the other hand, in the interleaving method, it is preferable to maintain the phase difference between the operations of each phase at a predetermined value. In the two-phase interleaving method as in this example, it is preferable to maintain the phase difference at 180 degrees. The control circuit 100 maintains the phase difference between the operations of each phase at a predetermined value by controlling the switching timing of each switching element.

[0057] 4 is a diagram illustrating an overview of the control circuit 100. The control circuit 100 of this example includes a digital control unit 130, a comparison circuit 114, a comparison circuit 116, an AD conversion circuit 117, a buffer 118, and a buffer 120.

[0058] The comparison circuit 114 detects the first current I L1 The comparison circuit 114 of this example detects the timing to turn on the first switching element 51 based on the first current I L1 The comparison circuit 114 of this example detects the timing when the first current I becomes almost 0 A. Almost 0 A means that the absolute value of the current value is equal to or less than a value slightly larger than 0. L1 and a reference voltage corresponding to approximately 0 A. The comparison circuit 114 of this example receives the first current I L1 is equal to or less than the reference current (almost 0 A) corresponding to the reference voltage, it indicates H logic, and the first current I L1 is greater than the reference current, the comparison result signal zc1 indicating L logic is output.

[0059] The comparison circuit 116 detects the second current I L2 The comparison circuit 116 of this example detects the timing to turn on the second switching element 52 based on the second current I L2 The comparison circuit 116 in this example detects the timing when the second current I L2 and a reference voltage corresponding to approximately 0 A. The comparison circuit 116 of this example receives the second current I L2is equal to or less than the reference current corresponding to the reference voltage, the second current I L2 is greater than the reference current, the comparison result signal zc2 indicating L logic is output.

[0060] The AD conversion circuit 117 converts the feedback signal FB into a digital signal. The digital control unit 130 generates a first control signal G_a and a second control signal G_b based on the comparison result signal zc1, the comparison result signal zc2, and the digital feedback signal FB. The first control signal G_a is a signal that indicates the switching timing of the first switching element 51. The second control signal G_b is a signal that indicates the switching timing of the second switching element 52. Each control signal may be a signal that indicates a logical H when the switching element is turned on and a logical L when the switching element is turned off.

[0061] The buffer 118 outputs a first output signal OUT1 corresponding to the first control signal G_a to the output terminal 108. The buffer 120 outputs a second control signal OUT2 corresponding to the second control signal G_b to the output terminal 110.

[0062] The digital control unit 130 of this example includes delay elements 132 and 134, an error amplifier 136, a timer circuit 138, a PI control unit 140, a comparison circuit 142, a set / reset latch circuit 144, and a second control signal generation unit 150. The delay element 132 delays the comparison result signal zc1 by a preset time and outputs it. The signal output by the delay element 132 is input to the set terminal of the set / reset latch circuit 144 and the timer circuit 138.

[0063] The timer circuit 138 outputs a ramp signal whose value gradually increases from an initial value, starting from the timing when the comparison result signal zc1 output by the delay element 132 transitions to logical H. The timer circuit 138 may output a ramp signal whose value increases by a predetermined value in response to each pulse of the input clock signal.

[0064] The error amplifier 136 detects the magnitude of the difference between the level of the output voltage Vout and a predetermined target level. In this example, the error amplifier 136 detects the magnitude of the difference between the magnitude of the feedback signal FB and a reference value corresponding to the target level.

[0065] The PI control unit 140 outputs a PI signal according to the magnitude of the difference detected by the error amplifier 136. The PI signal is a signal obtained by multiplying the first current I L1 The PI control unit 140 outputs a PI signal that lengthens the on-period as the level of the output voltage Vout becomes smaller than the target level, and outputs a PI signal that shortens the on-period as the level of the output voltage Vout becomes larger than the target level. For example, the PI control unit 140 outputs a larger PI signal as the level of the output voltage Vout becomes smaller than the target level.

[0066] The comparator circuit 142 compares the magnitude of the ramp signal output by the timer circuit 138 with the magnitude of the PI signal. In this example, the comparator circuit 142 outputs a comparison result signal that indicates L logic when the magnitude of the ramp signal is smaller than that of the PI signal, and H logic when the magnitude of the ramp signal is equal to or greater than that of the PI signal. Since the slope of the ramp signal is constant, the larger the PI signal, the later the timing at which the output of the comparator circuit 142 transitions from L logic to H logic. The comparison result signal of the comparator circuit 142 is input to the reset terminal of the set / reset latch circuit 144.

[0067] The set-reset latch circuit 144 outputs the first control signal G_a of logic H from the time when a logic H signal is input to the set terminal until the time when a logic H signal is input to the reset terminal. The set-reset latch circuit 144 also outputs the first control signal G_a of logic L from the time when a logic H signal is input to the reset terminal until the time when a logic H signal is input to the set terminal. When the first control signal G_a is logic H, the first switching element 51 is controlled to an ON state, and when the first control signal G_a is logic L, the first switching element 51 is controlled to an OFF state.

[0068] That is, the first current I L1becomes nearly zero and the comparison result signal zc1 output by the delay element 132 transitions to logical H, the first switching element 51 is turned on. After being turned on, the first switching element 51 is maintained in the on state for an on period corresponding to the magnitude of the PI signal indicating the difference between the output voltage Vout and the target level. After the on period has elapsed, a logical H signal is input to the reset terminal of the set-reset latch circuit 144, and the first switching element 51 is turned off.

[0069] The delay element 134 delays the comparison result signal zc2 output by the comparison circuit 116 by a preset time and outputs the delayed signal. The amount of delay in the delay element 134 may be the same as the amount of delay in the delay element 132. The comparison result signal zc2 output by the delay element 134 indicates the timing at which the second switching element 52 should be turned on.

[0070] The second control signal generating unit 150 generates the second control signal G_b based on the comparison result signal zc2 output by the delay element 134 and the first control signal G_a. The second control signal generating unit 150 may detect, from the first control signal G_a, the period from when the first switching element 51 is turned on to when it is turned on again. The second control signal generating unit 150 generates the second control signal G_b so as to turn on the second switching element 52 at the center of that period. This allows the phase difference between the operating phase of the first switching element 51 and the operating phase of the second switching element 52 to be maintained at 180 degrees.

[0071] FIG. 5 shows the AC voltage Vac, the PI signal, the ramp signal, the first output signal OUT1, and the first current I L1 10 is a diagram showing an example of a time waveform of the AC voltage Vac in this example, the voltage value of which gradually increases.

[0072] In this example, the PI signal has a constant magnitude. The ramp signal is a ramp signal that varies with the first current I L1becomes nearly 0 and the comparison result signal zc1 (see FIG. 4) of the delay element 132 transitions to logic H, the ramp signal starts to gradually increase from its initial value. The ramp signal may be a signal to which a predetermined level is added each time a pulse of the clock signal is input to the timer circuit 138. In this case, the ramp signal has a step-like waveform as shown in FIG.

[0073] The first output signal OUT1 is a first current I L1 becomes almost 0, the first switching element 51 is controlled to be in the ON state, and the first current I L1 increases. The first current I L1 The slope of the ramp signal increases according to the level of the AC voltage Vac. When the level of the ramp signal reaches the level of the PI signal, the first output signal OUT1 transitions to a logic L, and the first switching element 51 is turned off. As a result, the first current I L1 The first current I L1 When the first current I reaches approximately 0, the first switching element 51 is controlled to be in the ON state again. By repeating this operation, the first current I L1 is generated.

[0074] 6 is a block diagram showing an example of the second control signal generating section 150. The second control signal generating section 150 of this example includes a phase detection circuit 160, a phase correction circuit 170, and a gate control circuit 180.

[0075] The phase detector circuit 160 detects the first current I L1 and the second current I L2 The phase difference signal is a signal representing the phase difference between the first current I L1 The timing at which the second current I L2 The phase detection circuit 160 detects the first current I L1 and the second current I L2 The phase difference may be detected based on the first control signal G_a and the comparison result signal zc2.

[0076] The phase detection circuit 160 of this example includes an edge detection circuit 162, a counter 166, an edge detection circuit 164, and a multiplier 168. The edge detection circuit 162 detects the rising edge of the first control signal G_a. In other words, the edge detection circuit 162 detects the timing to turn on the first switching element 51.

[0077] The edge detection circuit 164 detects the rising edge of the comparison result signal zc2. That is, the edge detection circuit 162 detects the timing to turn on the second switching element 52. The second control signal G_b may be input to the phase detection circuit 160 instead of the comparison result signal zc2. In this case, the phase detection circuit 160 detects the rising edge of the second control signal G_b.

[0078] The counter 166 measures the time interval between rising edges of the first control signal G_a. That is, the counter 166 measures the time interval between the timings at which the first switching element 51 is turned on. The counter 166 may measure the time interval by counting the number of pulses of the clock signal input during the period from one rising edge to the next rising edge of the first control signal G_a. The counter 166 outputs an interval signal T_val indicating the size of the time interval.

[0079] The counter 166 measures the time interval from the rising edge of the first control signal G_a to the rising edge of the comparison result signal zc2. In other words, the counter 166 measures the phase difference between the timing when the first switching element 51 turns on and the timing when the second switching element 52 turns on. The counter 166 outputs a phase difference signal Gon_b indicating the magnitude of the phase difference. The first current I L1 and the second current I L2When the phase difference between the first control signal G_a and the second control signal G_b is 180 degrees, the magnitude of the phase difference signal Gon_b is half the magnitude of the interval signal T_vak. The phase detection circuit 160 may detect the phase difference between the first control signal G_a that controls the switching of the first switching element 51 and the second control signal G_b that controls the switching of the second switching element 52, and generate the phase difference signal Gon_b.

[0080] The multiplier 168 outputs a signal that is half the size of the interval signal T_vak. In this example, the multiplier 168 multiplies the digital value of the interval signal T_vak by 1 / 2 and outputs the result.

[0081] The phase correction circuit 170 corrects the second phase in which the second switching element 52 operates based on the output of the multiplier 168, which is the interval signal T_vak multiplied by 2, the phase difference signal Gon_b, and the length of the on-period of the second switching element 52. The phase correction circuit 170 corrects the second phase in which the second switching element 52 operates based on the first phase in which the first switching element 51 operates. For example, the first phase is the timing at which the first switching element 51 turns on, and the second phase is the timing at which the second switching element 52 turns on. Alternatively, the first phase is the phase of the rising edge of the first control signal G_a, and the second phase is the phase of the rising edge of the second control signal G_b. Alternatively, the first phase is the phase of the rising edge of the first output signal OUT1, and the second phase is the phase of the rising edge of the second output signal OUT2. The phase correction circuit 170 may adjust the second phase so that the relative phase of the second phase with respect to the first phase becomes a predetermined target value. The phase correction circuit 170 may adjust the phase difference of the second phase with respect to the first phase by adjusting the second phase without adjusting the first phase. For example, the phase correction circuit 170 adjusts the second phase so that the phase difference between the first phase and the second phase becomes 180 degrees.

[0082] The phase correction circuit 170 of this example adjusts the second phase by adjusting the on-period (i.e., on-width) of the second switching element 52. If the on-period of the second switching element 52 in a certain cycle is shortened, the second switching element 52 turns off earlier in that cycle, so the second phase in that cycle and thereafter relatively advances on the time axis. On the other hand, if the on-period of the second switching element 52 in a certain cycle is lengthened, the second switching element 52 turns off later, so the second phase in that cycle and thereafter relatively delays on the time axis. The second phase can be adjusted by such control.

[0083] The phase correction circuit 170 adjusts the second phase in accordance with the difference between the relative phase of the second phase with respect to the first phase and a target value (for example, 180 degrees). To achieve this, the second phase is adjusted in accordance with the difference between the output of the multiplier 168, which has halved the interval signal T_vak, and the phase difference signal Gon_b. However, if the second phase is changed suddenly, the waveform of the input current input to the first inductor 21 and the second inductor 22 will be disturbed, resulting in a deterioration in the power factor. For example, when the difference between the relative phase and the target value is relatively large, the difference is adjusted by adjusting the second current I L2 If an attempt is made to solve this problem by adjusting the phase in one cycle, the fluctuation of the second phase in that cycle will become large.

[0084] The phase correction circuit 170 of this example calculates the second current I L2 The phase correction circuit 170 limits the phase adjustment amount of the second phase in each cycle. The longer the on-period in each cycle, the greater the phase adjustment amount of the second phase in each cycle. If the on-period of the second switching element 52 is short and an attempt is made to adjust the second phase by a large amount, the ratio of the on-period fluctuation to the length of the original on-period becomes too large, resulting in significant distortion of the waveform of the input current to the inductor. In particular, if an attempt is made to significantly reduce the on-period when the on-period is short, the remaining on-period becomes too short, resulting in significant distortion of the waveform of the input current.

[0085] In response to this, by limiting the amount of phase adjustment of the second phase in accordance with the ON period of the second switching element 52, it is possible to suppress the disturbance of the waveform of the input current and improve the power factor. The adjustment of the second phase in accordance with the difference between the relative phase of the second phase with respect to the first phase and the target value is performed to adjust the second current I L2 This may be done gradually over multiple cycles.

[0086] The phase correction circuit 170 of this example includes an on-width detection circuit 172, an on-width adjustment circuit 174, and a calculation unit 176. The on-width detection circuit 172 detects the length of the on-period of the second switching element 52 in the cycle. The on-width detection circuit 172 may receive an on-period signal Ton_b_pre that specifies the on-period of the second switching element 52. The length of the on-period of the second switching element 52 specified by the on-period signal Ton_b_pre may be the same as the length of the on-period of the first switching element 51. The length of the on-period of the second switching element 52 specified by the on-period signal Ton_b_pre may be set in a manner similar to the length of the on-period of the first switching element 51 described with reference to FIGS. 4 and 5 .

[0087] The ON-width adjustment circuit 174 adjusts the length of the ON-period of the second switching element 52 using an ON-width adjustment amount that corresponds to the length of the ON-period detected by the ON-width detection circuit 172, the output of the multiplier 168 obtained by multiplying the interval signal T_vak by 2, and the phase difference signal Gon_b. As described above, the ON-width adjustment circuit 174 may adjust the second phase so that the relative phase of the second phase with respect to the first phase indicated by the phase difference signal Gon_b becomes a predetermined target value. The ON-width adjustment circuit 174 limits the ON-width adjustment amount of the ON-period of the second switching element 52 depending on the length of the ON-period. The ON-width adjustment circuit 174 increases the ON-width adjustment amount as the ON-period is longer and decreases the ON-width adjustment amount as the ON-period is shorter. The ON-width adjustment circuit 174 outputs a signal indicating the ON-width adjustment amount limited depending on the length of the ON-period to the calculation unit 176.

[0088] The calculation unit 176 adjusts the length of the on-period of the second switching element 52 by adding or subtracting the on-width adjustment amount calculated by the on-width adjustment circuit 174 to or from the on-period signal Ton_b_pre. The calculation unit 176 outputs an on-period signal Ton_b that indicates the length of the on-period after adjustment.

[0089] The gate control circuit 180 outputs the second control signal G_b based on the on-period signal Ton_b. The gate control circuit 180 may output the second control signal G_b that indicates H logic from the timing of the rising edge of the comparison result signal zc2 until the on-period indicated by the on-period signal Ton_b has elapsed, and that indicates L logic after the on-period has elapsed.

[0090] Fig. 7 is a timing chart illustrating an example of the operation of the second control signal generating unit 150. The horizontal axis in Fig. 7 represents time, and the vertical axis represents the level of each signal. In Fig. 7, one cycle is defined as the period from a rising edge of the first control signal G_a to the next rising edge.

[0091] 1st current I L1 When the first current I reaches approximately 0 A, the first control signal G_a becomes logic H, and the first switching element 51 is turned on. The first control signal G_a maintains logic H for a predetermined on-period Ton, and transitions to logic L after the on-period Ton has elapsed. As a result, the first current I L1 The edge detection circuit 162 detects the time interval T_val between rising edges of the first control signal G_a.

[0092] The comparison result signal zc2 is the second current I L2 When the second control signal G_b becomes high, the second current I L2 When the ON width is not adjusted by the ON width adjustment circuit 174, the second control signal G_b maintains the logic H for a predetermined ON period Ton, and transitions to the logic H after the ON period Ton has elapsed. In this case, as shown by the dotted waveform, the second current I L2 and the first current I L1The period of the first current I remains the same. L1 and the second current I L2 The phase difference between the two does not change.

[0093] As described above, the on-width adjustment circuit 174 adjusts the first current I L1 and the second current I L2 The on-period Ton of the second control signal G_b is adjusted by an on-width adjustment amount ΔTon according to the phase difference between the second control signal G_b and the interval signal T_val (in this example, the difference between the magnitude of the interval signal T_val×½ and the magnitude of the phase difference signal Gon_b). In FIG. 7, the on-period after adjustment is designated as Ton′. In the example of FIG. 7, the phase difference signal Gon_b is larger than half the interval signal T_val in each cycle. In this case, the on-width adjustment circuit 174 shortens the on-width Ton of the second control signal G_b to reduce the second current I L2 This allows the magnitude of the phase difference signal Gon_b to approach the magnitude of the interval signal T_val×½.

[0094] 6, the ON width adjustment circuit 174 may limit the magnitude of the ON width adjustment amount ΔTon based on the set value Ton of the ON period of the second control signal G_b in the cycle. L2 This prevents a sudden change in the phase of the first control signal G_a and also prevents the on-period Ton' after adjustment from becoming too short. The set value Ton may be the same as the on-period Ton of the first control signal G_a in the cycle.

[0095] 8 is a diagram illustrating an example of limiting the on-width adjustment amount ΔTon in the on-width adjustment circuit 174. In this example, the on-width adjustment circuit 174 increases the on-width adjustment amount ΔTon as the on-period of the second control signal G_b becomes longer. The on-width adjustment circuit 174 may limit the on-width adjustment amount ΔTon based on the set value Ton of the on-period in the current cycle, or may limit the on-width adjustment amount ΔTon based on the actual on-period Ton in the immediately preceding cycle.

[0096] The ON width adjustment circuit 174 of this example calculates the ON width adjustment amount ΔTon by multiplying a correction reference value corresponding to the magnitude of the phase difference indicated by the phase difference signal Gon_b by a gain that increases as the ON period Ton becomes longer. The correction reference value is set to a larger value as the phase difference increases. The correction reference value may be based on the difference between the magnitude of the interval signal T_val×½ and the magnitude of the phase difference indicated by the phase difference signal Gon_b. The correction reference value may be the ON width adjustment amount required to eliminate the phase difference with one ON width adjustment.

[0097] The gain by which the correction reference value is multiplied may be a value smaller than 1. The gain by which the correction reference value is multiplied may be 0.5 or less. The longer the on-period Ton, the larger the gain that the on-width adjustment circuit 174 increases. This allows the on-width adjustment amount ΔTon to be limited according to the length of the on-period Ton. In the example of FIG. 8, the gain is 0.5 when the on-period Ton is equal to or greater than the period α, and the gain is 0.25 when the on-period Ton is less than the period α. In the example of FIG. 8, the gain is changed in two steps, but the gain may be changed in more steps.

[0098] The on-width adjustment circuit 174 may calculate at least one of the upper limit and lower limit of the on-width adjustment amount ΔTon depending on the length of the on-period Ton. A table or an arithmetic expression indicating the relationship between the length of the on-period Ton and the upper limit and lower limit may be preset in the on-width adjustment circuit 174. The upper limit of the on-width adjustment amount ΔTon may be 0.5 times or less of the on-period Ton. The lower limit of the on-width adjustment amount ΔTon may be 0.05 times or more, or even 0.1 times or more, of the on-period Ton. The lower limit of the on-width adjustment amount ΔTon may be the length of one cycle of the clock signal input to the second control signal generation unit 150. The on-width adjustment circuit 174 may calculate the on-width adjustment amount ΔTon within a range determined by the calculated upper limit and lower limit.

[0099] The ON width adjustment circuit 174 may change the adjustment method for the second phase depending on the length of the ON period Ton. In this example, the ON width adjustment circuit 174 may change the adjustment method depending on whether the ON period Ton is equal to or greater than a predetermined reference value or less than the reference value. In the example of FIG. 8, the period β corresponds to the reference value. The period β is shorter than the period α.

[0100] When the on-period Ton is equal to or greater than the reference value, the on-width adjustment circuit 174 may use an instantaneous deviation method that reflects the phase difference between the first and second phases in the on-width adjustment amount ΔTon in the current cycle or the immediately following cycle. In the instantaneous deviation method, the phase difference between the first and second phases may be reflected in the on-width adjustment amount ΔTon in two or more subsequent cycles. When the on-period Ton is less than the reference value, the on-width adjustment circuit 174 may determine the on-width adjustment amount ΔTon using an integral method.

[0101] 9 is a diagram illustrating the integration method. The second control signal generation unit 150 of this example can set the on-width adjustment amount ΔTon to an integer multiple of a predetermined minimum setting value. The minimum setting value may be the length of one cycle of the clock signal input to the second control signal generation unit 150.

[0102] In the example of FIG. 9, the magnitude of the on-width adjustment amount ΔTon is expressed as a multiple of the minimum setting value. For example, when ΔTon=-1, the absolute value of the on-width adjustment amount ΔTon is 1 time the minimum setting value. When ΔTon=-2, the absolute value of the on-width adjustment amount ΔTon is 2 times the minimum setting value. Furthermore, when the sign of the on-width adjustment amount ΔTon is negative, the on-width adjustment amount ΔTon is subtracted from the on-period setting value Ton. When the sign of the on-width adjustment amount ΔTon is positive, the on-width adjustment amount ΔTon is added to the on-period setting value Ton. For example, when ΔTon=-1, the on-width adjustment amount ΔTon, which is 1 time the minimum setting value, is subtracted from the on-period setting value Ton. In this case, the adjusted on-period Ton' is shorter than the setting value of the on-period Ton.

[0103] 9 shows the waveform of the first control signal G_a and the waveform of the second control signal G_b in the first to sixth cycles side by side. Since the waveform of the first control signal G_a is common to each cycle, only the waveform for one cycle is shown. As described above, the second control signal generating unit 150 adjusts the ON period of the second control signal G_b so that the timing of the rising edge of the second control signal G_b (corresponding to the second phase) coincides with the timing of the center of each cycle of the first control signal G_a (position of T_val×½).

[0104] In the first cycle, the rising edge of the second control signal G_b is delayed from the timing of T_val×½, so the second control signal generating unit 150 shortens the ON period of the second control signal G_b to advance the second phase of the second control signal G_b relative to the first phase of the first control signal G_a.

[0105] As shown in the waveform of the first cycle, when the length of the on-period Ton is shorter than the set period β, the on-width adjustment circuit 174 may adjust the on-period of the second control signal G_b by the minimum set value of the on-width adjustment amount (ΔTon=−1). This makes it possible to suppress abrupt fluctuations in the on-period Ton.

[0106] As shown in the waveforms of the second to fourth cycles, when adjusting the on-period Ton in the same direction on the time axis as the adjustment in the previous cycle, the on-width adjustment circuit 174 may add a minimum set value to the absolute value of the on-width adjustment amount ΔTon while maintaining the sign of the on-width adjustment amount ΔTon used for the adjustment in the previous cycle. For example, in the second cycle, as in the first cycle, the on-period Ton of the second control signal G_b is adjusted to be shorter on the time axis. In this case, the sign of the on-width adjustment amount ΔTon in the second cycle is maintained the same as the sign of the on-width adjustment amount ΔTon in the first cycle (negative in this example). Furthermore, the minimum set value "1" is added to the absolute value "1" of the on-width adjustment amount ΔTon in the first cycle, thereby setting the absolute value of the on-width adjustment amount ΔTon in the second cycle to "2". By such processing, when adjusting the on-period Ton in the same direction on the time axis, the absolute value of the on-width adjustment amount ΔTon is gradually increased to adjust the second current I L2 This can speed up the phase adjustment.

[0107] As shown in the waveforms of the fourth and fifth cycles, when the ON width adjustment circuit 174 adjusts the ON period Ton in the opposite direction on the time axis to the adjustment in the previous cycle, it inverts the sign of the ON width adjustment amount ΔTon used for the adjustment in the previous cycle and resets the absolute value of the ON width adjustment amount ΔTon to the minimum set value. For example, in the fourth cycle, the ON period Ton of the second control signal G_b is adjusted to be shorter on the time axis, whereas in the fifth cycle, the ON period Ton is adjusted to be longer on the time axis. In this case, in the fifth cycle, the sign of the ON width adjustment amount ΔTon is inverted to positive and the absolute value of the ON width adjustment amount ΔTon is reset to the minimum set value "1". By such processing, the ON width adjustment amount ΔTon is converged early, and the second current I L2 This can speed up the phase adjustment.

[0108] 10 is a timing chart showing a more detailed example of each signal in the control circuit 100. In FIG. 10, the first current I L1 and the second current I L2While the first control signal G_a is at logic H, the first switching element 51 is in an ON state, and the first current I L1 While the first switching element 51 is in the ON state, the source-drain voltage Vds (phase a) of the first switching element 51 becomes approximately 0 V. When the first control signal G_a transitions to the L logic, the first current I L1 decreases. The first current I L1 Vds (phase a) maintains a high voltage until the first current I L1 When Vds (phase a) becomes almost 0, Vds (phase a) decreases from a high voltage. In this example, Vds (phase a) starts decreasing from a high voltage and then resonates according to the resonant frequency of the circuit. Although not shown in FIG. 10, in this example, the first current I L1 also resonates in the same way.

[0109] Voltage ZCD1 has a waveform similar to that of Vds (phase a). The comparison result signal zc1 output by comparison circuit 114 exhibits a logical H level while voltage ZCD1 is less than a predetermined reference voltage (-2 V in FIG. 10) and exhibits a logical L level while voltage ZCD1 is equal to or greater than the reference voltage. Due to the resonant waveform of Vds (phase a), the comparison result signal zc1 in this example has multiple rising edges within one cycle.

[0110] The comparator circuit 114 detects any rising edge of the comparison result signal zc1 in one cycle as a first current I L1 In the example of FIG. 10, the comparator circuit 114 may select and output the second rising edge (2) of the comparison result signal zc1 as the timing when the first current I L1 The timing at which the value of the signal becomes almost 0 is selected and output.

[0111] The rising edge of the comparison result signal zc1 output by the comparison circuit 114 is delayed by a predetermined delay amount Tondelay by the delay element 132 and input to the set-reset latch circuit 144. This causes the first control signal G_a to transition to logic H, and the next cycle begins.

[0112] The source-drain voltage Vds (phase b), voltage ZCD2, and comparison result signal zc2 of the second switching element 52 have waveforms similar to those of the source-drain voltage Vds (phase a), voltage ZCD1, and comparison result signal zc1 of the first switching element 51.

[0113] 10, a signal indicating half the interval between rising edges of the first control signal Ga_b is denoted as half_T. The signal half_T has a rising edge in the center of each cycle of the first control signal Ga_b and a falling edge at the boundary of each cycle. The signal half_T corresponds to the time interval T_val×½ output by the multiplier 168.

[0114] In this example, in the first cycle, the rising edge of the second control signal G_b is delayed relative to the rising edge of the signal half_T. The phase correction circuit 170 sets an adjustment amount ΔTon to reduce this delay. In this example, the adjustment amount ΔTon is set to −50 ns.

[0115] In this example, the calculation unit 176 adds the adjustment amount ΔTon set for each cycle to the set value Ton of the on-period in that cycle. In this example, since the adjustment amount ΔTon in the first cycle is a negative value, the on-period Ton' after adjustment in the first cycle is shorter than the on-period Ton. As a result, the phase (second phase) of the rising edge of the second control signal G_b advances, and the phase difference with the rising edge of the signal half_T decreases. In this example, in the second cycle, the phase difference between the rising edge of the second control signal G_b and the rising edge of the signal half_T is almost zero.

[0116] 11 shows an example of the time waveform of the input current in an example in which the magnitude of the adjustment amount ΔTon is limited according to the on-width Ton, and in a comparative example in which the magnitude is not limited. The input current is a current input from the full-wave rectifier circuit 14 to the first inductor 21 and the second inductor 22.

[0117] As shown in Figure 11, in the comparative example, the input current is significantly disturbed, especially at high phase angles (i.e., near the peak of the waveform). In contrast, in the example, sudden changes in the ON width are suppressed, so the input current disturbance is suppressed. Therefore, in the example, it is possible to suppress the input current disturbance and improve the response characteristics at the same time. This tendency remained the same even when the amplitude of the AC voltage Vac was changed.

[0118] 12 is a diagram showing another example of the configuration of the phase detection circuit 160 and the phase correction circuit 170. The phase detection circuit 160 and the phase correction circuit 170 may have the same functions as those in the example shown in FIG.

[0119] 6, the phase detection circuit 160 receives a first control signal G_a that controls the switching of the first switching element 51, detects the on-interval T_val during which the first switching element 51 is turned on based on the first control signal G_a, and outputs half the on-interval T_val, i.e., half_T_val. The phase detection circuit 160 also outputs a phase difference signal Gon_b based on the first control signal G_a and the comparison result signal zc2.

[0120] The phase correction circuit 170 calculates a phase error PE, which is the difference between the phase difference indicated by the phase difference signal Gon_b and half the on-interval (half_T_val), and corrects the second phase for turning on the second switching element 52 based on the phase error PE. The phase correction circuit 170 of this example corrects the second phase by adjusting the on-width Ton_b of the second switching element 52 based on the phase error PE.

[0121] The phase detection circuit 160 of this example includes a counter 181, a multiplier 182, a first latch unit 183, a second latch unit 184, and a selection unit 185. The first control signal G_a and the clock signal CLK are input to the counter 181. The counter 181 counts the number of pulses of the clock signal CLK and outputs a digital signal. The counter 181 resets the output Q to an initial value INIT (e.g., "0") when the first switching element 51 is turned on. The counter 181 of this example resets the output Q to the initial value at the timing of the rising edge of the first control signal G_a.

[0122] Multiplier 182 multiplies the output of counter 181 by 1 / 2 and outputs the result. Multiplier 182 may perform digital calculations.

[0123] The output of the multiplier 182 and the first control signal G_a are input to the first latch unit 183. The first latch unit 183 outputs a first digital signal obtained by latching the output of the multiplier 182 at the timing when the first switching element 51 is turned on. The first digital signal indicates the magnitude of half (half_T_val) of the on-interval T_val during which the first switching element 51 is turned on.

[0124] The second latch unit 184 receives a signal indicating the timing at which the second switching element 52 turns on (in this example, the comparison result signal zc2) and the output of the counter 181. The second latch unit 184 outputs a second digital signal that latches the output of the counter 181 at the timing at which the second switching element 52 turns on. The second digital signal indicates the magnitude of the phase difference Gon_b from when the first switching element 51 turns on to when the second switching element 52 turns on.

[0125] The selection unit 185 selects and outputs either the output of the counter 181 or the output of the second latch unit 184 in accordance with a signal (comparison result signal zc2 in this example) indicating the timing at which the second switching element 52 is turned on. The selection unit 185 may select the output of the counter 181 during the period from the timing at which the second switching element 52 is turned on until one cycle of the clock signal CLK has elapsed. The selection unit 185 may select the output of the second latch unit 184 during other periods. The selection unit 185 in this example selects the output of the counter 181 during the period in which the comparison result signal zc2 indicates H logic, and selects the output of the second latch unit 184 during the period in which the comparison result signal zc2 indicates L logic.

[0126] As described above, the second digital signal output by the second latch unit 184 indicates the magnitude of the phase difference Gon_b. However, because the second latch unit 184 and the like operate in response to the clock signal CLK, a delay of one clock occurs from when the output of the counter 181 becomes a value indicating the phase difference Gon_b until the phase difference Gon_b is reflected in the output of the second latch unit 184. By providing the selector unit 185, the phase difference Gon_b can be output even during this delay period.

[0127] The phase correction circuit 170 of this example has a signed subtractor 186, an ON width detection circuit 172, a gain circuit 188, a limiter 189, and a signed adder 190. The function of the ON width detection circuit 172 is similar to that of the example of FIG.

[0128] The signed subtractor 186 receives a first digital signal D1 indicating the magnitude of half the on-interval (half_T_val) and a second digital signal D2 indicating the magnitude of the phase difference Gon_b. The signed subtractor 186 calculates a signed phase error PE by digitally computing the difference (D1-D2) between the first digital signal D1 and the second digital signal D2. The sign of the phase error PE changes depending on whether the first digital signal D1 is larger or smaller than the second digital signal D2. For example, when the first digital signal D1 is larger than the second digital signal D2, the phase error PE indicates a positive value, and when the first digital signal D1 is smaller than the second digital signal D2, the phase error PE indicates a negative value.

[0129] The gain circuit 188 adjusts the gain by which the phase error PE is multiplied in accordance with the reference value (Ton_b_pre) of the on-period of the second switching element 52. The gain circuit 188 may multiply the phase error PE by a larger gain as the reference value of the on-period increases. The gain by which the gain circuit 188 multiplies may be the same as the example described in FIG. 8.

[0130] The limiter 189 limits the ON width adjustment amount ADJ that the gain circuit 188 inputs to the signed adder 190 in accordance with the reference value (Ton_b_pre) of the ON period of the second switching element 52. The ON width adjustment amount ADJ is a signed digital value. For example, the limiter 189 may limit the ON width adjustment amount ADJ to be within a range of −0.5 to 0.5 times the reference value (Ton_b_pre) of the ON period. If the output of the gain circuit 188 is outside this range, the limiter 189 may clamp the value of the ON width adjustment amount ADJ to the upper or lower limit of this range. By limiting the value of the ON width adjustment amount ADJ, it is possible to prevent the ON period of the second switching element 52 from becoming equal to or less than 0 or equal to or greater than the ON interval T_val.

[0131] The signed adder 190 receives a reference value (Ton_b_pre) for the on-period of the second switching element 52 and an on-width adjustment amount ADJ corresponding to the phase error PE output by the signed subtractor 186. The signed adder 190 adds the on-width adjustment amount ADJ to the reference value and outputs an on-period signal Ton_b. The on-period signal Ton_b is input to the gate control circuit 180 shown in FIG. 6.

[0132] The configuration of this example also makes it possible to precisely adjust the timing at which the second switching element 52 turns on. The on-width detection circuit 172 and the gain circuit 188 may be omitted. Although the multiplier 182 is used in this example, it is sufficient to have an arithmetic unit that halves the digital data received as the output of the counter 181, and the multiplier 182 may be a shifter that shifts 1-bit data by 1 bit or a divider that divides by 2.

[0133] Fig. 13 is a timing chart showing an example of the operation of the phase detection circuit 160 and the phase correction circuit 170 in the example of Fig. 12. In this example, Ton_b_pre is set to "10" and the gain in the gain circuit 188 is set to "1".

[0134] The output of the counter 181 is reset to an initial value of "0" at the timing of the rising edge of the first control signal G_a, and is incremented by "1" for each pulse of the clock signal CLK. The output value of the counter 181, "30," in the cycle immediately before the rising edge of the first control signal G_a corresponds to the on-interval T_val of the first switching element 51.

[0135] The first latch unit 183 captures and outputs the output value "15" of the multiplier 182 (half of the output value "30" of the counter 181) at the timing of the rising edge of the first control signal G_a. As a result, the first latch unit 183 outputs half the on interval (half_T_val) of the first switching element 51. The output of the first latch unit 183 is maintained until the next rising edge of the first control signal G_a.

[0136] The second latch unit 184 captures and outputs the output value "19" of the counter 181 at the timing of the rising edge of the comparison result signal zc2. As a result, the second latch unit 184 outputs the turn-on phase difference Gon_b between the first switching element 51 and the second switching element 52. The output of the second latch unit 184 is maintained until the next rising edge of the comparison result signal zc2. Note that the output value "21" of the second latch unit 184 exemplifies the value of the phase difference Gon_b in the previous cycle, and does not affect the processing of the current cycle described in FIG. 13. The same applies to the other parameters shown below the second latch unit 184.

[0137] The selection unit 185 selects and outputs the output value "19" of the counter 181 during a period in which the comparison result signal zc2 indicates logical H, and selects and outputs the output value "19" of the second latch unit 184 during a period in which the comparison result signal zc2 indicates logical L. This allows the selection unit 185 to output an appropriate phase difference Gon_b during all periods.

[0138] The signed subtractor 186 calculates the difference between the output value of the first latch unit 183 and the output value of the second latch unit 184. The output of the signed subtractor 186 is updated, for example, at the timing of the pulse of the comparison result signal zc2. In the example of FIG. 13, the phase error PE output from the signed subtractor 186 at that timing is 15-19=-4. If the phase error PE is negative, this indicates that the turn-on timing of the second switching element 52 lags behind the center of the on-interval of the first switching element 51.

[0139] The signed adder 190 receives an on-width adjustment amount ADJ corresponding to the phase error PE. In this example, the gain in the gain circuit 188 is "1." Furthermore, the value obtained by multiplying the phase error PE by the gain is within the limiting range of the limiter 189. Therefore, the signed adder 190 receives an on-width adjustment amount ADJ that is the same as the phase error PE. The signed adder 190 outputs an on-period signal Ton_b "6" obtained by adding the signed value of the on-width adjustment amount ADJ, "-4," to Ton_b_pre "10." The magnitude of the on-period signal Ton_b indicates the on-width of the current turn-on of the second switching element 52.

[0140] The gate control circuit 180 controls the on-width of the second switching element 52 in response to the on-period signal Ton_b. The gate control circuit 180 of this example may include an on-hold counter that decrements the on-period signal Ton_b by one in response to the cycle of the clock signal from the value "6" of the on-period signal Ton_b to a reference value "0." The gate control circuit 180 sets the second control signal G_b to logic H during the period from when the on-hold counter starts counting until the count value reaches the reference value "0," and sets it to logic L during other periods. This allows the on-width of the second switching element 52 to be adjusted in response to the phase error PE, thereby adjusting the switching phase of the second switching element 52. In this example, shortening the on-width of the second switching element 52 can advance the timing of the next turn-on of the second switching element 52, as described with reference to FIG. 7 and other figures.

[0141] Fig. 14 is a timing chart showing another example of the operation of the phase detection circuit 160 and the phase correction circuit 170. In the example of Fig. 13, the operation when the turn-on timing of the second switching element 52 is later than the reference timing has been described, but in the example of Fig. 14, an example is shown in which the turn-on timing of the second switching element 52 is earlier than the reference timing.

[0142] In this example, the phase difference "13" detected by the second latch unit 184 is smaller than the half on-period half_T_val "15" detected by the first latch unit 183. In this case, the signed subtractor 186 outputs a positive phase error "2." The signed adder 190 outputs an on-period signal Ton_b "12" by adding an on-width adjustment amount ADJ "2" to Ton_b_pre "10." The gate control circuit 180 controls the on-width of the second switching element 52 in accordance with the on-period signal Ton_b. In this example, by lengthening the on-width of the second switching element 52, the timing of the next turn-on of the second switching element 52 can be delayed.

[0143] In this example, the signed subtractor 186 calculates the signed phase error PE by digital calculation, so that the turn-on phase of the second switching element 52 can be advanced or delayed by simple processing.

[0144] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0145] 10... power supply circuit, 12... power supply, 13... high-potential line, 14... full-wave rectifier circuit, 15... low-potential line, 16... capacitor, 17... node, 21... first inductor, 22... second inductor, 31... first diode, 32... second diode, 33, 34... voltage dividing resistor, 41... first capacitor, 42... second capacitor, 51... first switching element, 5 2... second switching element, 61... first resistor, 62... second resistor, 71, 72... diode, 80, 82, 84, 86... capacitor, 100... control circuit, 102, 104... input terminal, 106... feedback terminal, 108... output terminal, 110... output terminal, 112... reference potential terminal, 114, 116... comparison circuit, 117... AD conversion circuit, 118, 120...buffer, 130...digital control unit, 132, 134...delay elements, 136...error amplifier, 138...timer circuit, 140...PI control unit, 142...comparison circuit, 144...set-reset-latch circuit, 150...second control signal generation unit, 160...phase detection circuit, 162, 164...edge detection circuit, 166...counter, 168...multiplier, 170 Phase correction circuit, 172 ON width detection circuit, 174 ON width adjustment circuit, 176 arithmetic unit, 180 gate control circuit, 181 counter, 182 multiplier, 183 first latch unit, 184 second latch unit, 185 selection unit, 186 signed subtractor, 188 gain circuit, 189 limiter, 190 signed adder, 200 power supply unit

Claims

1. A control circuit for a power supply circuit including a first switching element that controls a first current flowing through a first inductor and a second switching element that controls a second current flowing through a second inductor provided in parallel with the first inductor, and that outputs a sum current of a current corresponding to the first current and a current corresponding to the second current, the control circuit controlling switching operations of the first switching element and the second switching element, a phase detection circuit for generating a phase difference signal indicative of a phase difference between the first current and the second current; a phase correction circuit that corrects a second phase in which the second switching element operates based on the phase difference signal and the length of an on-period of the second switching element, with a first phase in which the first switching element operates as a reference; A control circuit comprising:

2. The phase correction circuit an on-width detection circuit that detects the length of an on-period of the second switching element; an on-width adjustment circuit that adjusts the length of the on-period of the second switching element by an on-width adjustment amount according to the length of the on-period detected by the on-width detection circuit and the phase difference signal; 2. The control circuit of claim 1, comprising:

3. The ON width adjustment circuit increases the ON width adjustment amount as the ON period becomes longer.

3. The control circuit of claim 2.

4. The ON width adjustment circuit calculates the ON width adjustment amount by multiplying a correction reference value corresponding to the magnitude of the phase difference indicated by the phase difference signal by a gain that increases as the ON period increases.

4. The control circuit of claim 3.

5. the on-width adjustment circuit calculates at least one of an upper limit value and a lower limit value of the on-width adjustment amount according to the length of the on-period; The ON width adjustment amount is calculated within a range determined by the calculated upper limit value and the calculated lower limit value.

4. The control circuit of claim 3.

6. The on-width adjustment amount can be set to an integer multiple of a minimum setting value, When the length of the ON period is smaller than a set reference value, the ON period is adjusted by the ON period adjustment amount of the minimum set value.

4. The control circuit of claim 3.

7. The on-width adjustment amount can be set to an integer multiple of a minimum setting value, When adjusting the on-period in the same direction on the time axis as the previous adjustment, the on-period adjustment circuit adds the minimum set value to the absolute value of the on-period adjustment amount while maintaining the sign of the on-period adjustment amount used in the previous adjustment.

3. The control circuit of claim 2.

8. When adjusting the on-period in the opposite direction to the previous adjustment on the time axis, the on-width adjustment circuit inverts the sign of the on-width adjustment amount used in the previous adjustment and resets the absolute value of the on-width adjustment amount to the minimum set value.

8. The control circuit of claim 7.

9. The phase detection circuit detects a phase difference between a first control signal that controls switching of the first switching element and a second control signal that controls switching of the second switching element, and generates the phase difference signal. A control circuit according to any one of claims 1 to 8.

10. The first switching element and the second switching element operate in a current critical conduction mode. A control circuit according to any one of claims 1 to 8.

11. the phase detection circuit receives a first control signal for controlling switching of the first switching element, and detects an on-interval during which the first switching element is turned on based on the first control signal; The phase correction circuit calculates a phase error between the phase difference and half the on interval, and corrects the second phase based on the phase error. A control circuit according to any one of claims 1 to 8.

12. The phase correction circuit has a signed subtractor that receives a first digital signal indicating half the magnitude of the on interval and a second digital signal indicating the magnitude of the phase difference and calculates the signed phase error by digital calculation.

12. The control circuit of claim 11.

13. The phase detection circuit a counter that receives the first control signal and a clock signal, counts the number of pulses of the clock signal, and outputs the counted number, and the output is reset to an initial value at the timing when the first switching element is turned on; a calculation unit that halves the output of the counter; a first latch unit that receives the output of the calculation unit and the first control signal, and outputs the first digital signal obtained by latching the output of the calculation unit at a timing when the first switching element is turned on; a second latch unit that receives a signal indicating the timing at which the second switching element is turned on and an output of the counter, and outputs the second digital signal obtained by latching the output of the counter at the timing at which the second switching element is turned on; 13. The control circuit of claim 12, comprising:

14. The phase detection circuit further includes a selection unit that selects and outputs either the output of the counter or the output of the second latch unit in response to a signal indicating the timing at which the second switching element is turned on.

14. The control circuit of claim 13.

15. The phase correction circuit has a signed adder that receives a reference value of the on-period of the second switching element and an on-width adjustment amount corresponding to the phase error output by the signed subtractor, and adds the on-width adjustment amount to the reference value of the on-period.

14. The control circuit of claim 13.

16. The phase correction circuit has a limiter that limits the ON width adjustment amount in accordance with a reference value of the ON period.

16. The control circuit of claim 15.

17. A power supply device comprising a power supply circuit and a control circuit, The power supply circuit includes: a first inductor; a first switching element that controls a first current flowing through the first inductor; a second inductor provided in parallel with the first inductor; a second switching element that controls a second current flowing through the second inductor; Equipped with outputting a sum current of a current corresponding to the first current and a current corresponding to the second current; the control circuit controls the switching operations of the first switching element and the second switching element for the power supply circuit; The control circuit a phase detection circuit for generating a phase difference signal indicative of a phase difference between the first current and the second current; a phase correction circuit that corrects a second phase in which the second switching element operates based on the phase difference signal and the length of an on-period of the second switching element, with a first phase in which the first switching element operates as a reference; A power supply device comprising:

18. A control circuit for a power supply circuit including a first switching element that controls a first current flowing through a first inductor and a second switching element that controls a second current flowing through a second inductor provided in parallel with the first inductor, and that outputs a sum current of a current corresponding to the first current and a current corresponding to the second current, the control circuit controlling switching operations of the first switching element and the second switching element, a phase detection circuit for generating a phase difference signal indicative of a phase difference between the first current and the second current; a phase correction circuit that corrects a second phase in which the second switching element operates based on a first phase in which the first switching element operates, based on the phase difference signal; Equipped with the phase detection circuit receives a first control signal for controlling switching of the first switching element, and detects an on-interval during which the first switching element is turned on based on the first control signal; the phase correction circuit calculates a phase error between the phase difference and half the on-interval, and corrects the second phase based on the phase error; The phase correction circuit has a signed subtractor that receives a first digital signal indicating half the magnitude of the on interval and a second digital signal indicating the magnitude of the phase difference and calculates the signed phase error by digital calculation. Control circuit.

19. The phase detection circuit a counter that receives the first control signal and a clock signal, counts the number of pulses of the clock signal, and outputs the counted number, and the output is reset to an initial value at the timing when the first switching element is turned on; a calculation unit that halves the output of the counter; a first latch unit that receives the output of the calculation unit and the first control signal, and outputs the first digital signal obtained by latching the output of the calculation unit at a timing when the first switching element is turned on; a second latch unit that receives a signal indicating the timing at which the second switching element is turned on and an output of the counter, and outputs the second digital signal obtained by latching the output of the counter at the timing at which the second switching element is turned on; 20. The control circuit of claim 18, comprising:

20. A power supply device comprising a power supply circuit and a control circuit, The power supply circuit includes: a first inductor; a first switching element that controls a first current flowing through the first inductor; a second inductor provided in parallel with the first inductor; a second switching element that controls a second current flowing through the second inductor; Equipped with outputting a sum current of a current corresponding to the first current and a current corresponding to the second current; the control circuit controls the switching operations of the first switching element and the second switching element for the power supply circuit; The control circuit a phase detection circuit for generating a phase difference signal indicative of a phase difference between the first current and the second current; a phase correction circuit that corrects a second phase in which the second switching element operates based on a first phase in which the first switching element operates, based on the phase difference signal; Equipped with the phase detection circuit receives a first control signal for controlling switching of the first switching element, and detects an on-interval during which the first switching element is turned on based on the first control signal; the phase correction circuit calculates a phase error between the phase difference and half the on-interval, and corrects the second phase based on the phase error; The phase correction circuit has a signed subtractor that receives a first digital signal indicating half the magnitude of the on interval and a second digital signal indicating the magnitude of the phase difference and calculates the signed phase error by digital calculation. power supply.

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