Chip package structure and method for manufacturing the same

Abstract

To provide a chip package structure having multiple stacked chips and a manufacturing method.SOLUTION: In a chip package structure 100, a first chip stack CS1 includes a plurality of first chips 110, a first molding layer 130, and at least one first vertical conductive element 120. The plurality of first chips are stacked sequentially, each including at least one first bond pad 112, which is not covered by the plurality of first chips. The first molding layer encapsulates the plurality of first chips. At least one first vertical conductive element penetrates the first molding layer and is disposed on and electrically connected to at least one of the first bond pads. A redistribution layer 140 is disposed on the first chip stack and electrically connected to the at least one first vertical conductive element.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a chip package structure and a method for manufacturing the chip package structure, and more particularly to a chip package structure having multiple chips stacked in series and a method for manufacturing such a chip package structure. [Background technology]

[0002] In semiconductor manufacturing processes, a packaging process can encapsulate semiconductor components, such as one or more chips, to form a semiconductor package structure to protect the semiconductor components. Today, the industry is making great efforts to develop package structures with excellent properties. For example, in 3D semiconductor devices (such as 3D memory devices), package structures with properties such as low cost, small size, short design time, strong protection, and / or favorable electrical properties (e.g., short electrical connection distance) have been developed. However, conventional package structures cannot simultaneously satisfy all of the aforementioned excellent properties. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention provides a chip package structure having multiple chips stacked one on top of the other, and a method for manufacturing such a chip package structure. [Means for solving the problem]

[0004] In one embodiment, a chip package structure includes a first chip stack and a redistribution layer. The first chip stack includes a plurality of first chips, a first molding layer, and at least one first vertical conductive element. The plurality of first chips are stacked sequentially, each of the plurality of first chips including at least one first bond pad, the first bond pad not being covered by the plurality of first chips. The first molding layer encapsulates the plurality of first chips. The at least one first vertical conductive element penetrates the first molding layer, and the at least one first vertical conductive element is disposed on and electrically connected to at least one of the first bond pads. The redistribution layer is disposed on the first chip stack and electrically connected to the at least one first vertical conductive element.

[0005] In another embodiment, a method for manufacturing a chip package structure is provided, the method including: stacking a plurality of first chips on a carrier board, each of the plurality of first chips having at least one first bond pad, the first bond pad not being covered by the plurality of first chips; forming at least one first vertical conductive element on at least one of the first bond pads to be electrically connected to the at least one first bond pad; forming a first molding layer to encapsulate the plurality of first chips and form a first chip stack, the at least one first vertical conductive element penetrating the first molding layer, the first chip stack including the plurality of first chips, the at least one first vertical conductive element, and the first molding layer; and forming a redistribution layer on the first molding layer to be electrically connected to the at least one first vertical conductive element.

[0006] Due to the design of the chip package structure of the present invention, the chip package structure has a smaller lateral size, and the signal transmission path between the chip of the chip package structure and the external device can be made smaller. Furthermore, the design time and cost of the chip package structure can be reduced. Meanwhile, when there is a chip offset during the manufacturing process, the reliability of the chip package structure can be improved.

[0007] These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic diagram showing a cross-sectional view of a chip package structure according to a first embodiment of the present invention; [Figure 2] FIG. 4 is a schematic diagram showing a cross-sectional view of a chip package structure according to a second embodiment of the present invention. [Figure 3] FIG. 10 is a schematic diagram showing a cross-sectional view of a chip package structure according to a third embodiment of the present invention. [Figure 4] FIG. 10 is a schematic diagram showing a cross-sectional view of a chip package structure according to a fourth embodiment of the present invention. [Figure 5] 1 is a flowchart illustrating a method for manufacturing a chip package structure according to an embodiment of the present invention. [Figure 6A] 3A to 3C are schematic diagrams illustrating statuses in a manufacturing method of a chip package structure according to an embodiment of the present invention; [Figure 6B] 3A to 3C are schematic diagrams illustrating statuses in a manufacturing method of a chip package structure according to an embodiment of the present invention; [Figure 6C] 3A to 3C are schematic diagrams illustrating statuses in a manufacturing method of a chip package structure according to an embodiment of the present invention; [Figure 6D] 3A to 3C are schematic diagrams illustrating statuses in a manufacturing method of a chip package structure according to an embodiment of the present invention; [Figure 6E] 3A to 3C are schematic diagrams illustrating statuses in a manufacturing method of a chip package structure according to an embodiment of the present invention; [Figure 6F] 3A to 3C are schematic diagrams illustrating statuses in a manufacturing method of a chip package structure according to an embodiment of the present invention; [Figure 6G] 3A to 3C are schematic diagrams illustrating statuses in a manufacturing method of a chip package structure according to an embodiment of the present invention; [Figure 6H] 3A to 3C are schematic diagrams illustrating statuses in a manufacturing method of a chip package structure according to an embodiment of the present invention; [Figure 6I] 3A to 3C are schematic diagrams illustrating statuses in a manufacturing method of a chip package structure according to an embodiment of the present invention; [Figure 6J] 3A to 3C are schematic diagrams illustrating statuses in a manufacturing method of a chip package structure according to an embodiment of the present invention; [Figure 6K] 3A to 3C are schematic diagrams illustrating statuses in a manufacturing method of a chip package structure according to an embodiment of the present invention; [Figure 7] 10 is a flowchart illustrating a method for manufacturing a chip package structure according to another embodiment of the present invention. [Figure 8] 10A and 10B are schematic diagrams illustrating a status in a manufacturing method of a chip package structure according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] While particular configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can also be used in a variety of other applications.

[0010] Certain terms are used throughout the description and appended claims to refer to particular components. As one skilled in the art will appreciate, electronics manufacturers may refer to components by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "including," "comprising," and "having" are used in an open-ended manner and should therefore be interpreted to mean "including, but not limited to." Thus, when the terms "including," "comprising," and / or "having" are used in the description of the present disclosure, they indicate the presence of corresponding features, regions, steps, operations, and / or components, but are not limited to the presence of one or more of the corresponding features, regions, steps, operations, and / or components.

[0011] It should be noted that references herein to "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but that not all embodiments necessarily include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of one of ordinary skill in the art to implement such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0012] In general, terminology may be understood, at least in part, from contextual usage. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular sense, or may be used to describe a combination of features, structures, or characteristics in the plural sense, depending at least in part on context. Similarly, terms such as "a" or "the" may also be understood to convey singular usage or to convey plural usage, depending at least in part on context.

[0013] It will be readily understood that the meanings of "on," "upper," and "above" in this disclosure should be interpreted in the broadest manner, such that "on" does not mean only "directly above" something, but can also include the meaning "on" something when there is an intervening feature or layer, and further such that "upper" or "above" does not mean only "on" or "above" something, but can also include the meaning "on" or "above" something (i.e., directly above) without the existence of an intervening feature or layer.

[0014] Additionally, spatially relative terms such as "below," "belower," "lower," "upper," "upper," and the like are used herein for ease of description to describe the relationship of one element or feature illustrated in the figures to another element or feature. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0015] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself can be patterned. The material added onto the substrate can be patterned or left unpatterned. Furthermore, the substrate can include a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and others. Alternatively, the substrate can be made from a non-conductive material, such as a glass wafer, a plastic wafer, or a sapphire wafer.

[0016] The term "layer" as used herein refers to a portion of material that includes a region having a thickness. A layer can extend throughout an underlying or overlying structure, or it can have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer can be a region of a homogeneous or non-homogeneous continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer can be positioned between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer and can include one or more layers therein and / or have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor layers and contact layers (on which contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.

[0017] As used herein, the term "nominal" refers to a desired or target value of a characteristic or parameter related to component or process operation, established during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​can result from slight variations in the manufacturing process or manufacturing tolerances. As used herein, the term "about" indicates a value of a given quantity that can vary based on the particular technology node associated with the semiconductor device in question. Based on the particular technology node, the term "about" can indicate, for example, a value that varies within a 10-30% range of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0018] Terms such as first, second, third, etc. may be used to describe various components, but such components are not limited by these terms. These terms are used herein merely to distinguish one component from another. These terms are not intended to rearrange the order of the components and / or the order of the manufacturing steps of the components. The claims may not use the same terms, but instead may use terms such as first, second, third, etc., in relation to the order in which the elements are claimed. Thus, a first component in the following description may be a second component in the claim.

[0019] 1, which is a schematic diagram illustrating a cross-sectional view of a chip package structure according to a first embodiment of the present invention. As shown in FIG. 1, the chip package structure 100 includes a first chip stack CS1 and a redistribution layer 140. In this embodiment, the first chip stack CS1 includes, but is not limited to, a plurality of first chips 110, a first molding layer 130, and at least one first vertical conductive element 120. Any other appropriate components may optionally be included in the first chip stack CS1.

[0020] The first chip 110 may be formed by a semiconductor manufacturing process, and the first chip 110 may be identical or different. For example, in some embodiments, the first chip 110 may be identical and have memory functionality, and in some embodiments, the first chip 110 may be different and have the same functionality or different functionality, but is not limited to the above. Any type of chip may be selected to serve as the first chip 110 based on requirements. Furthermore, in some embodiments, the first chip 110 may have a substrate and electronic components disposed on the substrate. The electronic components may include a 2D memory unit, a 3D memory unit, and / or other suitable components. For example, the electronic components may be a 3D memory unit, such that the first chip 110 has memory functionality and the chip package structure 100 may be a 3D memory device, but is not limited to the above. It should be noted that the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (i.e., "memory strings" herein) on a laterally oriented substrate, such that the memory strings extend perpendicular to the substrate.

[0021] 1 , the first chip stack CS1 includes, but is not limited to, four sequentially stacked first chips 110 (i.e., 110a, 110b, 110c, and 110d, respectively). In this embodiment, the first chips 110 may be attached to one another by a plurality of die attach films (DAFs) 114, which may be disposed on the undersides of three of the first chips 110b, 110c, and 110d, respectively. Furthermore, each of the first chips 110 includes at least one first bond pad 112 configured to be a component of a signal transmission path between the corresponding first chip 110 and an external device (such as a signal source or power supply, etc.). For simplicity, FIG. 1 only shows that each of the first chips 110 has one first bond-pad 112. However, in practice, each of the first chips 110 may have one or more first bond-pads 112. The first bond-pads 112 may include at least one conductive material, such as, but not limited to, a metallic conductive material and / or a transparent conductive material. The first bond-pads 112 are not covered by the first chips 110, so that some conductive elements (such as vertical conductive elements and / or connecting traces described below) may be disposed on the first bond-pads 112 and electrically connected to the pads 112. In this embodiment, the first chips 110 shown in FIG. 1 are stacked in a staircase shape to expose the first bond-pads 112, but are not limited to this.

[0022] First molding layer 130 may encapsulate and cover first chip 110 to protect first chip 110 and reduce physical and / or chemical damage (such as damage caused by oxidation, moisture, etc.) to first chip 110. First molding layer 130 may include epoxy resin and / or any other suitable molding compound.

[0023] Each first vertical conductive element 120 may be disposed on and electrically connected to at least one of the first bond pads 112. In FIG. 1 , the first chip stack CS1 includes a plurality of first vertical conductive elements 120, and each of the first vertical conductive elements 120 may be disposed on, but is not limited to, one of the first bond pads 112. Also, in this embodiment, each of the first vertical conductive elements 120 may be in contact with a corresponding first bond pad 112, but is not limited to this.

[0024] Furthermore, the first vertical conductive element 120 may penetrate the first molding layer 130 so that the first chip 110 may be electrically connected to components disposed on the first molding layer 130. In FIG. 1 , the extension direction of the first vertical conductive element 120 may be substantially parallel to the normal direction Dn of the first chip stack CS1 (i.e., the perpendicular direction to the surface of the first chip stack CS1), but is not limited to this. Furthermore, the first vertical conductive element 120 may include at least one conductive material, such as, but not limited to, gold, copper, aluminum, silver, and / or other suitable metals.

[0025] The redistribution layer 140 is disposed on the first chip stack CS1, and the redistribution layer 140 is electrically connected to the first vertical conductive element 120. Specifically, the redistribution layer 140 may include at least one conductive layer 142 and at least one insulating layer 144, and the conductive layer 142 may be electrically connected to the first vertical conductive element 120. The conductive layer 142 may include a metal material, any other suitable conductive material, or a combination thereof, and the insulating layer 144 may include an organic material or an inorganic material (such as a silicon dioxide material, a silicon nitride material, a silicon oxynitride material, or any other suitable insulating material, or a combination thereof). In some embodiments, as shown in FIG. 1 , the redistribution layer 140 may include one conductive layer 142 and one insulating layer 144. In some embodiments (not shown), the redistribution layer 140 may include multiple conductive layers 142 and multiple insulating layers 144.

[0026] In the redistribution layer 140 of FIG. 1 , the insulating layer 144 may have a plurality of openings 146 to expose a plurality of portions of the conductive layer 142. Furthermore, as shown in FIG. 1 , the chip package structure 100 may further include a plurality of solder balls 150 in contact with the exposed portions of the conductive layer 142. That is, each of the solder balls 150 corresponds to one of the openings 146. In this case, each of the solder balls 150 may serve as a signal input / output terminal. A signal from an external device may be input to the chip package structure 100 via the solder ball 150 (i.e., the signal input / output terminal), and / or a signal from the chip package structure 100 may be output to the external device. Note that each of the solder balls 150 may be electrically connected to at least one of the first vertical conductive elements 120.

[0027] In particular, the solder balls 150 may be arranged by designing the redistribution layer 140. Therefore, the chip package structure 100 may be easily joined to a circuit board for electrically connecting to an external device. In some embodiments, the distance between two adjacent ones of the solder balls 150 may be greater than the distance between two adjacent ones of the first vertical conductive elements 120 corresponding to these solder balls 150, but is not limited thereto. In some embodiments, the chip package structure 100 may be a fan-out type package, but is not limited thereto.

[0028] Because the first chips 110 are stacked together, the lateral size of the chip package structure 100 can be reduced. Because the chip package structure 100 uses the first vertical conductive element 120 and the redistribution layer 140 instead of the conventional wiring bonding technology (i.e., the bent wiring bonded between the pad and the bonding substrate), the lateral size of the chip package structure 100 can be further reduced (because the two ends of the bent wiring cannot be too close), and the signal transmission path between the first chip 110 and the external device can be made smaller. In addition, the bonding substrate used in the conventional wiring bonding technology does not exist in the chip package structure 100, so the design time and cost of the bonding substrate can be saved. On the other hand, when there is an offset of the first chip 110 during the manufacturing process of the chip package structure 100, the reliability of the formation of the first vertical conductive element 120 and the redistribution layer 140 is higher than that of the conventional wiring bonding technology.

[0029] The chip package structure 100 may optionally include any other suitable components or structures. For example, in FIG. 1 , the chip package structure 100 may further include a protective layer 160 disposed on a side of the first chip stack CS1 opposite the redistribution layer 140. The protective layer 160 is configured to provide stress compensation to the chip package structure 100 to reduce package warpage.

[0030] The chip package structure of the present invention is not limited to the above-mentioned embodiment. Further embodiments of the present invention will be described below. For ease of comparison, identical components will be labeled with the same symbols in the following description. The following description will focus on the differences between the embodiments, and the repeated parts will not be redundantly described.

[0031] Referring to FIG. 2, FIG. 2 is a schematic diagram showing a cross-sectional view of a chip package structure according to a second embodiment of the present invention. For the sake of simplicity, FIG. 2 only shows that each of the first chips 110 has one first bond pad 112. In practice, however, each of the first chips 110 may have one or more first bond pads 112. As shown in FIG. 2, the difference between this embodiment and the first embodiment is that the chip package structure 200 in this embodiment further includes at least one connecting wire 210, and each connecting wire 210 is electrically connected between two of the first bond pads 112 belonging to two of the first chips 110, so that one of the first vertical conductive elements 120 may be electrically connected to at least two of the first chips 110. 2 shows one connecting wire 210 electrically connected between two of the first bond pads 112 belonging to the two first chips 110c and 110d, respectively, and the top first vertical conductive element 120 is electrically connected to these two first chips 110c and 110d, but is not limited thereto. The connecting wire 210 may be disposed on any other suitable location, and any suitable number of connecting wires 210 may be used based on requirements. As an example, but not limited to, in some embodiments, one connection wiring 210 is electrically connected between two of the first bond pads 112 belonging to the two first chips 110c and 110d, respectively, and another connection wiring 210 is electrically connected between two of the first bond pads 112 belonging to the two first chips 110b and 110c, respectively, so that the top first vertical conductive element 120 (or another first vertical conductive element 120) is electrically connected to these three first chips 110b, 110c, and 110d.As another example, in some embodiments, one connection wiring 210 is electrically connected between two of the first bond pads 112 belonging to the two first chips 110c and 110d, another connection wiring 210 is electrically connected between two of the first bond pads 112 belonging to the two first chips 110b and 110c, and yet another connection wiring 210 is electrically connected between two of the first bond pads 112 belonging to the two first chips 110a and 110b, so that the top first vertical conductive element 120 (or another first vertical conductive element 120) is electrically connected to these four first chips 110a-110d, but this is not limiting.

[0032] Furthermore, the connecting wires 210 may be formed from a wire bonding process, and the connecting wires 210 may include at least one conductive material such as, but not limited to, gold, copper, aluminum, silver, and / or other suitable metals.

[0033] Referring to FIG. 3, FIG. 3 is a schematic diagram showing a cross-sectional view of a chip package structure according to a third embodiment of the present invention. For simplicity, FIG. 3 only shows that each of the first chips 110 has one first bond pad 112. However, in practice, each of the first chips 110 may have one or more first bond pads 112. As shown in FIG. 3, the difference between this embodiment and the first embodiment is that the chip package structure 300 in this embodiment further includes a second chip stack CS2 disposed between the first chip stack CS1 and the redistribution layer 140. The second chip stack CS2 may include, but is not limited to, multiple second chips 310, a second molding layer 330, and at least one second vertical conductive element 320. Any other appropriate components may optionally be included in the second chip stack CS2.

[0034] The second chip 310 may be fabricated by a semiconductor manufacturing process, and the second chip 310 may be the same or different. For example, in some embodiments, the second chip 310 may be the same and have memory functionality, and in some embodiments, the second chip 310 may be different and have the same functionality or different functionality, but is not limited thereto. Any type of chip may be selected to serve as the second chip 310 based on requirements. Furthermore, in some embodiments, the second chip 310 may have a substrate and electronic components disposed on the substrate. The electronic components may include 2D memory units, 3D memory units, and / or other suitable components.

[0035] In some embodiments, at least one of the second chips 310 may be identical to at least one of the first chips 110, but is not limited to this. In some embodiments, all of the second chips 310 may be different from all of the first chips 110.

[0036] 3, the second chip stack CS2 includes, but is not limited to, four sequentially stacked second chips 310 (i.e., 310a, 310b, 310c, and 310d, respectively). In this embodiment, the second chips 310 may be attached to one another by a plurality of die attach films 314, which may be disposed on the undersides of three of the second chips 310b, 310c, and 310d, respectively. Furthermore, each of the second chips 310 includes at least one second bond pad 312 that serves as a component of a signal transmission path between the corresponding second chip 310 and an external device. For simplicity, FIG. 3 only shows that each of the second chips 310 has one second bond-pad 312. However, in practice, each of the second chips 310 may have one or more second bond-pads 312. The second bond-pads 312 may include at least one conductive material, such as, but not limited to, a metallic conductive material and / or a transparent conductive material. The second bond-pads 312 are not covered by the second chip 310, so that some conductive elements (described later) may be disposed on the second bond-pads 312 and electrically connected to the pads 312. In this embodiment, the second chips 310 shown in FIG. 3 are stacked in a staircase shape to expose the second bond-pads 312, but are not limited to this.

[0037] The second molding layer 330 may encapsulate and cover the second chip 310 to protect the second chip 310 and reduce physical and / or chemical damage (such as damage caused by oxidation or moisture) to the second chip 310. The second molding layer 330 may include an epoxy resin and / or any other suitable molding compound. In some embodiments, the material of the second molding layer 330 may be the same as the material of the first molding layer 130, but is not limited to such.

[0038] Each second vertical conductive element 320 may be disposed on and electrically connected to at least one of the second bond pads 312. In FIG. 3 , the second chip stack CS2 includes a plurality of second vertical conductive elements 320, and each of the second vertical conductive elements 320 may be disposed on, but is not limited to, one of the second bond pads 312. Also, in this embodiment, each of the second vertical conductive elements 320 may be in contact with a corresponding second bond pad 312, but is not limited to this.

[0039] Furthermore, the second vertical conductive element 320 may penetrate the second molding layer 330 so that the second chip 310 may be electrically connected to components disposed on the second molding layer 330. In FIG. 3 , the extension direction of the second vertical conductive element 320 may be substantially parallel to the normal direction of the second chip stack CS2 (i.e., the perpendicular direction to the surface of the second chip stack CS2), but is not limited thereto. In some embodiments, the extension direction of the second vertical conductive element 320 may be substantially parallel to the extension direction of the first vertical conductive element 120 (i.e., the extension direction of the second vertical conductive element 320 is substantially parallel to the normal direction Dn of the first chip stack CS1), but is not limited thereto. Furthermore, the second vertical conductive element 320 may include at least one conductive material, such as, but not limited to, gold, copper, aluminum, silver, and / or other suitable metals. In some embodiments, the material of the second vertical conductive element 320 may be the same as the material of the first vertical conductive element 120, but is not limited to such.

[0040] 3 , the redistribution layer 140 is electrically connected to the second vertical conductive elements 320. Similarly, in the redistribution layer 140, the insulating layer 144 may further have additional openings 146 to expose additional portions of the conductor layer 142, and each of the solder balls 150 corresponding to one of the openings 146 may be electrically connected to at least one of the first vertical conductive elements 120 and / or at least one of the second vertical conductive elements 320.

[0041] Specifically, the functionality of the first chip stack CS1 may be the same as or different from the functionality of the second chip stack CS2, and the number of first chips 110 may be the same as or different from the number of second chips 310.

[0042] Furthermore, the chip package structure 300 may further include a die attach film 340 disposed on the bottom surface of the second chip stack CS2 such that the second chip stack CS2 may be attached to the first chip stack CS1 by the die attach film 340. In FIG. 3 , the second chip stack CS2 is stacked on the first chip stack CS1 in a staircase shape, but is not limited to this. Furthermore, in some embodiments, the first vertical conductive element 120 and the second vertical conductive element 320 may be positioned at different positions relative to the center of the chip package structure 300. For example, in FIG. 3 , the first vertical conductive element 120 may be positioned at the left portion relative to the center of the chip package structure 300, and the second vertical conductive element 320 may be positioned at the right portion relative to the center of the chip package structure 300, but is not limited to this. In some embodiments, the first vertical conductive element 120 and the second vertical conductive element 320 may be positioned at the same portion relative to the center of the chip package structure 300. For example, the first vertical conductive element 120 and the second vertical conductive element 320 may be positioned at the left portion relative to the center of the chip package structure 300. Furthermore, the second chip stack CS2 shown in FIG. 3 does not cover the first bond pad 112 and the first vertical conductive element 120, but is not limited to this.

[0043] In particular, the chip package structure 300 may further include a third molding layer 360 and at least one third vertical conductive element 350. The third molding layer 360 may encapsulate the first chip stack CS1 and the second chip stack CS2. In FIG. 3 , the third molding layer 360 may be configured to fill the gap between the first chip stack CS1 and the redistribution layer 140 and the gap between the second chip stack CS2 and the protection layer 160. The third molding layer 360 may include an epoxy resin and / or any other suitable molding compound. In some embodiments, the material of the third molding layer 360 may be the same as the material of the first molding layer 130 and / or the material of the second molding layer 330, but is not limited to this.

[0044] Each third vertical conductive element 350 may be disposed on and electrically connected to one of the first vertical conductive elements 120, and each third vertical conductive element 350 may be electrically connected to the redistribution layer 140. That is, the first bond pad 112 of the first chip 110 may be electrically connected to the redistribution layer 140 via the first vertical conductive element 120 and the third vertical conductive element 350. In FIG. 3 , the chip package structure 300 includes a plurality of third vertical conductive elements 350, and each of the third vertical conductive elements 350 may be in contact with a corresponding first vertical conductive element 120, but is not limited to this.

[0045] Furthermore, the third vertical conductive element 350 may penetrate the third molding layer 360. In FIG. 3 , the extension direction of the third vertical conductive element 350 may be substantially parallel to the normal direction Dn of the first chip stack CS1, but is not limited to this. In some embodiments, the extension direction of the third vertical conductive element 350 may be substantially parallel to the extension direction of the first vertical conductive element 120 and / or the extension direction of the second vertical conductive element 320, but is not limited to this. Furthermore, the second vertical conductive element 320 may include at least one conductive material, such as, but not limited to, gold, copper, aluminum, silver, and / or other suitable metals. In some embodiments, the material of the third vertical conductive element 350 may be the same as the material of the first vertical conductive element 120 and / or the material of the second vertical conductive element 320, but is not limited to this.

[0046] In some embodiments, the chip package structure 300 may further include another chip stack disposed between the second chip stack CS2 and the redistribution layer 140. In this case, the third molding layer 360 may also encapsulate this chip stack disposed between the second chip stack CS2 and the redistribution layer 140.

[0047] As a result, since the chip stacks are stacked, the lateral size of the chip package structure 300 can be reduced. Also, the lateral size of the chip package structure 300 can be further reduced due to the use of vertical conductive elements. On the other hand, when there is a chip offset in the manufacturing process, the reliability of forming the vertical conductive elements and the redistribution layer 140 is higher than that of the conventional wiring bonding technology.

[0048] Referring to FIG. 4, FIG. 4 is a schematic diagram showing a cross-sectional view of a chip package structure according to a fourth embodiment of the present invention. For the sake of simplicity, FIG. 4 only shows that each of the first chips 110 has one first bond pad 112 and each of the second chips 310 has one second bond pad 312. However, in reality, each of the first chips 110 may have one or more first bond pads 112, and each of the second chips 310 may have one or more second bond pads 312. As shown in FIG. 4, the difference between this embodiment and the third embodiment is that the first chip stack CS1 of the chip package structure 400 in this embodiment further includes a partial redistribution layer 440, which is disposed between the first vertical conductive element 120 and the third vertical conductive element 350. In other words, the partial redistribution layer 440 is on the first molding layer 130 .

[0049] The structure of the partial redistribution layer 440 is similar to that of the redistribution layer 140. In particular, the partial redistribution layer 440 may include at least one conductive layer 442 and at least one insulating layer 444, where the conductive layer 442 may be electrically connected between the first vertical conductive element 120 and the third vertical conductive element 350. The conductive layer 442 may include a metallic material, any other suitable conductive material, or a combination thereof, and the insulating layer 444 may include an organic material or an inorganic material. In some embodiments, as shown in FIG. 3 , the partial redistribution layer 440 may include one conductive layer 442 and one insulating layer 444. In some embodiments (not shown), the partial redistribution layer 440 may include multiple conductive layers 442 and multiple insulating layers 444.

[0050] In FIG. 4 , due to the partial redistribution layer 440, the third vertical conductive element 350 may not be disposed directly on the corresponding first vertical conductive element 120. That is, the corresponding third vertical conductive element 350 and the first vertical conductive element 120 may be disposed alternately in the normal direction Dn of the first chip stack CS1. Therefore, the third vertical conductive element 350 may be disposed at any other appropriate position. Furthermore, in this case, the second chip stack CS2 shown in FIG. 4 may overlap the first bond pad 112 of the first chip 110d and the uppermost first vertical conductive element 120, but is not limited thereto. As a result, the overlapping area of ​​the first chip stack CS1 and the second chip stack CS2 is increased to reduce the lateral size of the chip package structure 400.

[0051] An exemplary method for manufacturing the aforementioned chip package structure is disclosed below.

[0052] Referring to FIG. 5, FIG. 5 is a flowchart illustrating a method for manufacturing a chip package structure according to an embodiment of the present invention. It should be appreciated that the flowchart illustrated in FIG. 5 is exemplary. In some embodiments, some of the steps may be performed simultaneously or in a different order than that illustrated in FIG. 5. In some embodiments, any other suitable step may be added to method 500 before or after one of the existing steps of method 500. In the following content, method 500 shall be described with reference to FIG. 5. However, method 500 is not limited to these exemplary embodiments.

[0053] To more clearly explain the method 500, reference is further made to Figures 6A to 6K and Figure 3. Figures 6A to 6K are schematic diagrams respectively illustrating the status in the manufacturing method of the chip package structure 300 according to an embodiment of the present invention. It should be noted that Figures 6A to 6K and Figure 3 are further referred to to illustrate the manufacturing process of the chip package structure 300 shown in Figure 3 (i.e., the chip package structure 300 of the third embodiment).

[0054] 5, the first chips 100 are stacked on the carrier board CB1 (as shown in FIG. 6A). For example, in FIG. 6A, the first chips 110 are stacked in a staircase shape so that the first bond pads 112 are not covered by the first chips 110. Furthermore, a die attach film 114 may be disposed on the undersides of some of the first chips 110b, 110c, and 110d so that the first chips 110 may be attached to each other.

[0055] 5, a first vertical conductive element 120 is formed on the first bond pad 112 to be electrically connected to the first bond pad 112 (as shown in FIG. 6B). In some embodiments, the first vertical conductive element 120 may be formed by a bonding process, where an end of the first vertical conductive element 120 is bonded on the first bond pad 112 and another end of the first vertical conductive element 120 is not in contact with anything. Therefore, the extension direction of the first vertical conductive element 120 may be substantially parallel to the normal direction Dn of the first chip stack CS1.

[0056] Optionally, in some embodiments, a connection wiring 210 (see FIG. 2 ) may be formed that is electrically connected between two of the first bond pads 112 that respectively belong to two of the first chips 110, but is not limited thereto.

[0057] In step 530a of FIG. 5, a first molding layer 130 is formed to encapsulate the first chip 110 to form a first chip stack CS1 (as shown in FIGS. 6C and 6D), where the first chip stack CS1 includes the first chip 110, a first vertical conductive element 120, and the first molding layer 130.

[0058] 6C , a first molding layer 130 is formed to cover the first chip 110 and the first vertical conductive elements 120. Next, as shown in FIG. 6D , the surface of the first molding layer 130 is thinned to expose the ends of each first vertical conductive element 120. In other words, the step of forming the first molding layer 130 may include thinning the surface of the first molding layer 130 to expose the ends of each first vertical conductive element 120. Thus, the first vertical conductive elements 120 may be electrically connected to components formed on the first molding layer 130 in a subsequent manufacturing process. Furthermore, this thinning step may use a chemical mechanical polishing (CMP) process or any other appropriate process. Furthermore, after the first molding layer 130 is formed, the first vertical conductive elements 120 may penetrate the first molding layer 130.

[0059] Optionally, in some embodiments, a partial redistribution layer 440 (see FIG. 4) may be formed on the first molding layer 130 after the first molding layer 130 is formed, but is not limited to this.

[0060] 5, the second chips 310 are stacked on the carrier board CB1 (as shown in FIG. 6A). For example, in FIG. 6A, the second chips 310 are stacked in a staircase shape so that the second bond pads 312 are not covered by the second chips 310. Furthermore, a die attach film 314 may be disposed on the undersides of some of the first chips 310b, 310c, and 310d so that the second chips 310 may be attached to each other.

[0061] 5, a second vertical conductive element 320 is formed on the second bond pad 312 to be electrically connected to the second bond pad 312 (as shown in FIG. 6B). In some embodiments, the second vertical conductive element 320 may be formed by a bonding process, in which an end of the second vertical conductive element 320 is bonded onto the second bond pad 312 and another end of the second vertical conductive element 320 is not in contact with anything. Therefore, the extension direction of the second vertical conductive element 320 may be substantially parallel to the normal direction Dn of the second chip stack CS2 (e.g., in some embodiments, the second vertical conductive element 320 may be substantially parallel to the normal direction Dn of the first chip stack CS1).

[0062] In step 530b of FIG. 5, a second molding layer 330 is formed to encapsulate the second chip 310 to form a second chip stack CS2 (as shown in FIGS. 6C and 6D), where the second chip stack CS2 includes the second chip 310, a second vertical conductive element 320, and the second molding layer 330.

[0063] 6C , the second molding layer 330 is formed to cover the second chip 310 and the second vertical conductive elements 320. Next, as shown in FIG. 6D , the surface of the second molding layer 330 is thinned to expose the ends of each second vertical conductive element 320 so that the second vertical conductive elements 320 may be electrically connected to components formed on the second molding layer 330 in a subsequent manufacturing process. Furthermore, this thinning step may use a chemical mechanical polishing (CMP) process or any other suitable process. Furthermore, after the second molding layer 330 is formed, the second vertical conductive elements 320 may penetrate the second molding layer 330.

[0064] 5 and 6A, the carrier board in step 510a may be the same as the carrier board in step 510b, i.e., the first chip 110 and the second chip 310 may be stacked on the same carrier board CB1, but is not limited to this. Therefore, steps 510a and 510b may be performed simultaneously. In some embodiments (not shown), the carrier board in step 510a may be different from the carrier board in step 510b, and steps 510a and 510b may not be performed simultaneously.

[0065] 5 and 6B-6D, steps 520a and 520b may be performed simultaneously, and steps 530a and 530b may be performed simultaneously, such that first chip stack CS1 and second chip stack CS2 are formed on the same carrier board CB1, and first molding layer 130 and second molding layer 330 are formed of the same material. As shown in FIGS. 6C and 6D, first molding layer 130 and second molding layer 330 are directly connected to each other, but are not limited to this.

[0066] Next, in some embodiments, some steps may be added in the method 500. For example, because the first chip stack CS1 and the second chip stack CS2 are formed on the same carrier board CB1 in FIG. 6D , a step for removing the carrier board CB1 and a step for separating the first chip stack CS1 from the second chip stack CS2 are performed. More precisely, as shown in FIG. 6E , the carrier board CB1 may be removed so that the first chip stack CS1 and the second chip stack CS2 may be separated from the carrier board CB1. In some embodiments, a peeling process may be performed to separate the first chip stack CS1 and the second chip stack CS2 from the carrier board CB1, but this is not limiting. Next, the first chip stack CS1 and the second chip stack CS2 may be separated from each other. In some embodiments, a cutting process may be performed to separate the first chip stack CS1 from the second chip stack CS2, but this is not limiting. Optionally, after separating the first chip stack CS1 from the second chip stack CS2, a die attach film 340 may be further formed on the lower surface of the second chip stack CS2.

[0067] In step 540 of FIG. 5, a second chip stack CS2 is stacked on the first chip stack CS1 (as shown in FIG. 6F). Specifically, the first chip stack CS1 may be placed on another carrier board CB2, and then the second chip stack CS2 is stacked on the first chip stack CS1, which may be the same as or different from the aforementioned carrier board CB1. For example, in FIG. 6F, the second chip stack CS2 may be stacked on the first chip stack CS1 in a staircase shape so that the first bond pads 112 are not covered by the second chip stack CS2. Furthermore, in some embodiments, the second chip stack CS2 and the first chip stack CS1 are attached to each other via a die attach film 340 formed on the underside of the second chip stack CS2.

[0068] 5, a third vertical conductive element 350 is formed on the first vertical conductive element 120 that will be electrically connected to the first vertical conductive element 120 (as shown in FIG. 6G). The formation process of the third vertical conductive element 350 is similar to the formation process of the first vertical conductive element 120. In some embodiments, the third vertical conductive element 350 may be formed by a bonding process, in which an end of the third vertical conductive element 350 is bonded onto the first vertical conductive element 120, and another end of the third vertical conductive element 350 is not in contact with anything. Therefore, the extension direction of the third vertical conductive element 350 may be substantially parallel to the normal direction Dn of the first chip stack CS1.

[0069] In step 560 of FIG. 5, a third molding layer 360 is formed to encapsulate the first chip stack CS1 and the second chip stack CS2 (as shown in FIGS. 6H and 6I). Specifically, as shown in FIG. 6H, the third molding layer 360 is formed to cover the first chip stack CS1, the second chip stack CS2, and the third vertical conductive elements 350. Next, as shown in FIG. 6I, the surface of the third molding layer 360 is thinned to expose the ends of each third vertical conductive element 350 and each second vertical conductive element 320. Thus, the third vertical conductive elements 350 and the second vertical conductive elements 320 may be electrically connected to components formed in subsequent manufacturing processes. Furthermore, this thinning step may use a chemical-mechanical polishing process or any other suitable process. Additionally, after the third molding layer 360 is formed, the third vertical conductive elements 350 may penetrate the third molding layer 360 .

[0070] 5, a redistribution layer 140 is formed over the first chip stack CS1 and the second chip stack CS2 (as shown in FIG. 6J), which will be electrically connected to the first vertical conductive element 120, the second vertical conductive element 320, and the third vertical conductive element 350. The redistribution layer 140 may include at least one conductive layer 142 and at least one insulating layer 144, and the conductive layer 142 may be electrically connected to the first vertical conductive element 120. For example, in FIG. 6J, a conductive layer 142 may be formed and patterned on the first chip stack CS1 and the second chip stack CS2 so as to be electrically connected to the first vertical conductive element 120, the second vertical conductive element 320, and the third vertical conductive element 350 (in FIG. 6J, the conductive layer 142 may be in contact with the ends of the first vertical conductive element 120, the second vertical conductive element 320, and the third vertical conductive element 350), and then an insulating layer 144 may be formed on the conductive layer 142, and the insulating layer 144 may be patterned to form openings 146 to expose multiple portions of the conductive layer 142, but is not limited to this. Furthermore, the conductive layer 142 and the insulating layer 144 may be formed by one or more thin film deposition processes, including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and the conductive layer 142 and the insulating layer 144 may be patterned by, but not limited to, a photolithography process.

[0071] Furthermore, a plurality of solder balls 150 may be formed on the redistribution layer 440. More precisely, the solder balls 150 may be formed on the redistribution layer 140 in correspondence with the openings 146.

[0072] Next, in Figure 6K, the carrier board CB2 may be removed. In some embodiments, but not limited to, a peeling process may be performed to separate the first chip stack CS1 from the carrier board CB2.

[0073] Optionally, a protective layer 160 may be formed on the side of the first chip stack CS1 opposite the redistribution layer 140 to complete the chip package structure 300 shown in Figure 3. In some embodiments, the protective layer 160 may be deposited on the first chip stack CS1, but is not limited to such.

[0074] Referring to FIG. 7, FIG. 7 is a flowchart illustrating a method for manufacturing a chip package structure according to another embodiment of the present invention. It should be appreciated that the flowchart illustrated in FIG. 7 is exemplary. In some embodiments, some of the steps may be performed simultaneously or in a different order than that illustrated in FIG. 7. In some embodiments, any other suitable step may be added to method 700 before or after one of the existing steps of method 700. In the following content, method 700 shall be described with reference to FIG. 7. However, method 700 is not limited to these exemplary embodiments.

[0075] To more clearly explain the method 700, reference is further made to Figures 6A to 6D, Figure 8, and Figure 1. Figure 8 is a schematic diagram showing a status in a manufacturing method of a chip package structure according to another embodiment of the present invention. It should be noted that Figures 6A to 6D, Figure 8, and Figure 1 are further referred to to show the manufacturing process of the chip package structure 100 shown in Figure 1 (i.e., the chip package structure 100 of the first embodiment).

[0076] 7, reference may be made to the preceding paragraph and to FIG. 5, and therefore steps 510a, 520a, and 530a will not be redundantly described. Note that the second chip stack CS2 shown in FIGS. 6A to 6D may not be formed in this embodiment.

[0077] 7, a redistribution layer 140 is formed on the first chip stack CS1, which will be electrically connected to the first vertical conductive element 120 (as shown in FIG. 8). For a method of forming the redistribution layer 140, reference may be made to the content in the preceding paragraph, and repeated portions will not be redundantly described. Furthermore, solder balls 150 may be formed on the redistribution layer 140, corresponding to the openings 146.

[0078] The carrier board CB1 may then be removed. In some embodiments, but not limited to, a peeling process may be performed to separate the first chip stack CS1 from the carrier board CB1.

[0079] Optionally, a protective layer 160 may be formed on the side of the first chip stack CS1 opposite the redistribution layer 140 to complete the chip package structure 100 shown in FIG.

[0080] In summary, due to the design of the chip package structure of the present invention, the chip package structure has a smaller lateral size, and the signal transmission path between the chip of the chip package structure and the external device can be made smaller. Furthermore, the design time and cost of the chip package structure can be reduced. Meanwhile, when there is a chip offset in the manufacturing process, the reliability of the chip package structure can be improved.

[0081] The foregoing description of specific embodiments fully discloses the general nature of the present disclosure so that others, by applying knowledge within the purview of those skilled in the art, may readily modify and / or adapt such specific embodiments for various applications without departing from the general concepts of the present disclosure and without undue experimentation. Such adaptations and modifications are therefore intended to be within the spirit and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It should be understood that the language or terminology used herein is for the purpose of description, rather than limitation, as the language or terminology used herein would be interpreted by one of ordinary skill in the art in light of the teaching and guidance.

[0082] The embodiments of the present disclosure have been described above with the help of functional building blocks that illustrate implementation of specified functions and relationships of those functions. The boundaries of these functional building blocks have been arbitrarily defined herein for convenience of description. Alternative boundaries can be defined as long as the specified functions and relationships of those functions are appropriately performed.

[0083] The Summary and Abstract sections may present one or more, but not all, exemplary embodiments of the present disclosure contemplated by the inventors and, therefore, are not intended to limit the scope of the disclosure and the appended claims in any way.

[0084] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

[0085] [Additional note 1] a plurality of first chips stacked sequentially, each of the plurality of first chips including at least one first bond pad, the first bond pad not being covered by the plurality of first chips; a first molding layer encapsulating the plurality of first chips; a first chip stack including at least one first vertical conductive element extending through the first molding layer, the at least one first vertical conductive element being disposed over and electrically connected to at least one of the first bond pads; a redistribution layer disposed on the first chip stack and electrically connected to the at least one first vertical conductive element; A chip package structure comprising: [Additional note 2] A chip package structure further comprising a second chip stack disposed between the first chip stack and the redistribution layer, the second chip stack: a plurality of second chips stacked in series, each of the plurality of second chips including at least one second bond pad, the second bond pad not being covered by the plurality of second chips; a second molding layer encapsulating the plurality of second chips; at least one second vertical conductive element extending through the second molding layer, the at least one second vertical conductive element being disposed over and electrically connected to at least one of the second bond pads and electrically connected to the at least one of the second bond pads and the redistribution layer; The chip package structure according to claim 1, comprising: [Additional note 3] A chip package structure further comprising a third molding layer and at least one third vertical conductive element, 3. The chip package structure of claim 2, wherein the third molding layer encapsulates the first chip stack and the second chip stack, the at least one third vertical conductive element penetrates the third molding layer, the at least one third vertical conductive element is disposed on and electrically connected to the at least one first vertical conductive element, and the at least one third vertical conductive element is electrically connected to the redistribution layer. [Additional note 4] The chip package structure described in Appendix 3, wherein the extension direction of the at least one third vertical conductive element is substantially parallel to the normal direction of the first chip stack. [Additional note 5] The chip package structure described in Appendix 3, wherein the first chip stack further comprises a partial redistribution layer disposed between the at least one first vertical conductive element and the at least one third vertical conductive element. [Additional note 6] 3. The chip package structure of claim 2, wherein the second chip stack is stacked on the first chip stack in a staircase shape. [Additional note 7] 2. The chip package structure of claim 1, wherein the extension direction of the at least one first vertical conductive element is substantially parallel to the normal direction of the first chip stack. [Additional note 8] 2. The chip package structure according to claim 1, wherein the plurality of first chips are stacked in a staircase shape. [Additional note 9] The chip package structure of claim 1, further comprising a protective layer disposed on the side of the first chip stack opposite the redistribution layer. [Additional Note 10] The chip package structure described in Appendix 1, wherein the first chip stack further comprises connection wiring electrically connected between two of the first bonding pads belonging to two of the plurality of first chips, respectively. [Additional Note 11] A method for manufacturing a chip package structure, comprising: Stacking a plurality of first chips on a carrier board, each of the plurality of first chips having at least one first bond pad, the first bond pad not being covered by the plurality of first chips; forming at least one first vertical conductive element on at least one of the first bond pads, the first vertical conductive element being electrically connected to the at least one of the first bond pads; forming a first molding layer to encapsulate the plurality of first chips to form a first chip stack, wherein the at least one first vertical conductive element penetrates the first molding layer, and the first chip stack comprises the plurality of first chips, the at least one first vertical conductive element, and the first molding layer; forming a redistribution layer over the first chip stack, the redistribution layer being electrically connected to the at least one first vertical conductive element; A method for manufacturing a chip package structure, comprising: [Additional Note 12] A method for manufacturing a chip package structure, further comprising the step of stacking a second chip stack on the first chip stack before the step of forming the redistribution layer, the second chip stack: a plurality of second chips stacked in series, each of the plurality of second chips including at least one second bond pad, the second bond pad not being covered by the plurality of second chips; a second molding layer encapsulating the plurality of second chips; at least one second vertical conductive element extending through the second molding layer, the at least one second vertical conductive element being disposed over and electrically connected to at least one of the second bond pads; Item 12. The method for manufacturing a chip package structure described in item 11, wherein the redistribution layer is electrically connected to the at least one second vertical conductive element. [Additional Note 13] The second method for forming a chip stack comprises: stacking the plurality of second chips; forming the at least one second vertical conductive element on the at least one of the second bond pads; and forming the second molding layer to encapsulate the plurality of second chips. [Additional Note 14] A method for manufacturing a chip package structure, comprising: before the step of forming the redistribution layer, forming at least one third vertical conductive element on the at least one first vertical conductive element, the third vertical conductive element being electrically connected to the at least one first vertical conductive element; forming a third molding layer to encapsulate the first chip stack and the second chip stack, wherein the at least one third vertical conductive element penetrates the third molding layer; Item 13. The method for manufacturing a chip package structure described in item 12, wherein the redistribution layer is electrically connected to the at least one third vertical conductive element. [Additional Note 15] Item 13. A method for manufacturing a chip package structure according to item 12, wherein the first chip stack and the second chip stack are formed on the same carrier board. [Additional Note 16] Item 13. The method for manufacturing a chip package structure according to item 12, wherein the second chip stack is stacked on the first chip stack in a staircase shape. [Additional Note 17] forming the first molding layer; A method for manufacturing a chip package structure described in Appendix 11, comprising a step of thinning the surface of the first molding layer to expose an end of the at least one first vertical conductive element. [Additional Note 18] Item 12. The method for manufacturing a chip package structure according to item 11, wherein the plurality of first chips are stacked in a staircase shape. [Additional Note 19] Item 12. A method for manufacturing a chip package structure according to item 11, further comprising the step of removing the carrier board. [Additional Note 20] A method for manufacturing the chip package structure, comprising: 20. A method for manufacturing a chip package structure as described in Appendix 19, comprising, after the step of removing the carrier board, forming a protective layer on the side of the first chip stack opposite the redistribution layer. [Explanation of symbols]

[0086] 100, 200, 300, 400 chip package structure 110, 110a, 110b, 110c, 110d, 310, 310a, 310b, 310c, 310d chips 112, 312 Bonding Pad 114, 314 Die attach film 120, 320, 350 vertical conductive elements 130, 330, 360 molding layers 140 Redistribution layer 142, 442 conductive layer 144, 444 insulating layer 146 Aperture 150 solder balls 160 protective layer 210 Connection wiring 440 Partial redistribution layer CB1, CB2 carrier boards CS1, CS2 chip stack Dn Normal direction

Claims

1. a plurality of chips stacked together, each of the plurality of chips having bond pads that are not covered by the plurality of chips; a molding layer encapsulating the plurality of chips and separating a first subset of the plurality of chips from a second subset of the plurality of chips; a conductive layer on one side of the plurality of chips; A chip package structure comprising: a vertical conductive element having a via portion extending vertically within the molding layer and a landing portion extending laterally on the surface of the bond pad, connecting the conductive layer and the bond pad.

2. Further comprising a redistribution layer; The redistribution layer is the conductive layer coupled to the vertical conductive element; an insulating layer on the conductive layer, partially exposing the conductive layer; The chip package structure of claim 1 , comprising:

3. The chip package structure of claim 2 , further comprising solder balls contacting the exposed portions of the conductive layer through the openings in the insulating layer.

4. The chip package structure of claim 3 , wherein the solder balls comprise portions below the top surface of the insulating layer.

5. The chip package structure of claim 2 , further comprising two or more solder balls, each of the solder balls contacting a respective exposed portion of the conductive layer through a respective opening in the insulating layer.

6. The chip package structure of claim 5 , further comprising two or more of the vertical conductive elements, wherein the distance between two adjacent vertical conductive elements is smaller than the distance between two adjacent solder balls.

7. The chip package structure of claim 1 , wherein the conductive layer extends over the molding layer as a single layer.

8. The chip package structure according to claim 1 , wherein the vertical conductive elements extend in a direction perpendicular to the multiple chips and are connected to the conductive layer.

9. The chip package structure of claim 2 , wherein the redistribution layer comprises multiple conductive layers and multiple insulating layers.

10. The chip package structure of claim 1 , further comprising multiple vertical strings of memory cells.

11. The chip package structure of claim 1 , wherein the bond pad comprises two layers stacked on top of each other.

12. The chip package structure of claim 1 , wherein the multiple chips are stacked in a staircase shape to expose the bond pads.

13. The chip package structure of claim 1 , further comprising a protective layer disposed on a side of the plurality of chips opposite the conductive layer.

14. The chip package structure as claimed in claim 9 , further comprising a connection wire connected between two bond pads respectively belonging to two of the multiple chips.

15. a sub-rewiring layer located between the first subset of the multiple chips and the second subset of the multiple chips; The sub-redistribution layer is a sub-insulating layer separating the first subset of the plurality of chips from the second subset of the plurality of chips; a sub-conductive layer embedded in the sub-insulating layer and interconnecting a lower portion of the vertical conductive element with an upper portion of the vertical conductive element; The chip package structure of claim 1 , further comprising:

16. a first chip subset comprising a number of first chips stacked together, each of the number of first chips comprising a first bond pad not covered by the number of first chips; a second chip subset stacked on the first chip subset, the second chip subset comprising a number of second chips stacked together, the number of second chips each comprising a second bond pad not covered by the number of second chips; a first molding layer encapsulating the plurality of first chips; a second molding layer encapsulating the plurality of second chips; a conductive layer on one side of the second molding layer that is spaced apart from the plurality of second chips; a first vertical conductive element extending vertically to connect the conductive layer and the first bond pad; a second vertical conductive element extending vertically to connect the conductive layer and the second bond pad; A chip package structure comprising:

17. Further comprising a redistribution layer; The redistribution layer is the conductive layer coupled to the first vertical conductive element and the second vertical conductive element; an insulating layer on the conductive layer, partially exposing the conductive layer; The chip package structure of claim 16, comprising:

18. 20. The chip package structure of claim 17, further comprising solder balls contacting the exposed portions of the conductive layer through the openings in the insulating layer.

19. 20. The chip package structure of claim 18, wherein the solder balls comprise portions below the top surface of the insulating layer.

20. 20. The chip package structure of claim 18, wherein the solder balls are connected to the first vertical conductive element and the second vertical conductive element.

Images