Semiconductor device

Abstract

To provide a semiconductor device capable of achieving both high-speed switching and suppression of electromagnetic interference.SOLUTION: A semiconductor device 10 is connected to a power device 20, and includes: a gate driver unit 100 having a first circuit 101 and a second circuit 102; a resistance unit 110 for connecting a gate of the power device and the gate driver unit; and a first control circuit 130 connected to the gate driver unit. The first control circuit is configured to increase resistance of the power device by issuing an instruction to decrease a slew rate of the power device to the first circuit when the power device is turned off.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, and can be suitably used for, for example, a semiconductor device incorporating a gate driver unit for a power device. [Background technology]

[0002] Achieving even higher efficiency (reducing power loss) in traction motor systems is important for achieving carbon neutrality. Higher efficiency in traction motor systems will increase the driving distance per charge and improve the convenience of xEVs (EVs: Electric Vehicles, PHEVs: Plug-in Hybrid Electric Vehicles, etc.).

[0003] Additionally, to increase the efficiency of inverters installed in traction motor systems, the adoption of low-power-loss insulated gate bipolar transistors (IGBTs) and silicon carbide metal-oxide-semiconductor field-effect transistors (SiC-MOSFETs) is progressing.Increasing inverter efficiency requires reducing conduction loss and switching loss.

[0004] If the switching speed is increased in order to reduce switching loss, noise and ringing will occur when the motor is turned off, causing problems from the perspective of electromagnetic interference (EMI), such as communication errors with vehicle systems and the generation of jamming radio waves. Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, there is a need for a semiconductor device that can achieve both high-speed switching and suppression of electromagnetic interference.Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, a semiconductor device incorporates a state in which the power device is made highly resistant when the power device is turned off, thereby consuming the energy generated in the floating inductor without the need for additional circuitry, thereby achieving both high-speed switching and suppression of electromagnetic interference. [Effects of the Invention]

[0007] According to the embodiment, it is possible to provide a semiconductor device that can achieve both high-speed switching and suppression of electromagnetic interference. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a diagram illustrating the mechanism of ringing in a power device. [Figure 3] FIG. 3 is a diagram illustrating the mechanism of ringing in a power device. [Figure 4] FIG. 4 is a diagram illustrating waveforms when a power device is turned off. [Figure 5] FIG. 5 is a diagram illustrating the operation of the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a diagram illustrating the electrical characteristics of the power device according to the first embodiment. [Figure 7] FIG. 7 is a diagram illustrating the electrical characteristics of the power device according to the first embodiment. [Figure 8] FIG. 8 is a block diagram of the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a block diagram of the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a block diagram of the semiconductor device according to the first embodiment. [Figure 11]FIG. 11 is a block diagram of the semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is a block diagram of a semiconductor device according to the second embodiment. [Figure 13] FIG. 13 is a diagram illustrating the electrical characteristics of the power device according to the second embodiment. [Figure 14] FIG. 14 is a block diagram of a semiconductor device according to the second embodiment. [Figure 15] FIG. 15 is a block diagram of a semiconductor device according to the second embodiment. [Figure 16] FIG. 16 is a block diagram of a semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the specification and drawings, identical or corresponding components are designated by the same reference numerals, and duplicate explanations will be omitted. In the drawings, components may be omitted or simplified for the sake of convenience. Furthermore, at least some of the embodiments may be combined with each other in any desired manner.

[0010] <First Embodiment> 1 is a block diagram of a semiconductor device according to this embodiment. The semiconductor device 10 is connected to a power device 20, and includes a gate driver unit 100, a resistor section 110, a detection circuit 120, and a control circuit .

[0011] 1, the power device 20 is depicted as a MOSFET having a gate ("G" in FIG. 1), a source ("S" in FIG. 1), and a drain ("D" in FIG. 1), but the present disclosure is not limited thereto and is also suitable for an IGBT, etc. Examples of the MOSFET include a SiC-MOSFET, a Si-MOSFET, and a GaN-MOSFET.

[0012] The gate driver unit 100 includes at least a first circuit 101 and a second circuit 102. The resistance section 110 includes at least a first resistor 111 and a second resistor 112. The first circuit 101 and the first resistor 111 are connected to each other via a terminal T1, and the second circuit 102 and the second resistor 112 are connected to each other via a terminal T2.

[0013] The first circuit 101 and the second circuit 102 are each a multi-level gate driver circuit having at least two levels, High and Low, so that in a high load region where EMI occurs, the switching speed of the power device 20 can be reduced, thereby suppressing EMI (electromagnetic interference).

[0014] The first resistor 111 and the second resistor 112 are coupled to each other at terminals not connected to the gate driver unit 100, and are connected to the gate of the power device 20. In this way, the resistor section 110 connects the gate of the power device 20 and the gate driver unit 100.

[0015] The detection circuit 120 includes a monitor unit and a comparator. The monitor unit is configured to observe at least one of the gate voltage, the source-drain voltage, and the load current of the power device 20. The monitor unit may be provided as a separate circuit outside the semiconductor device 10, but if it is built into the detection circuit 120, additional components are not required, thereby enabling the semiconductor device 10 to be made smaller.

[0016] The comparator is configured to compare the electrical characteristics of the power device 20 observed by the monitor unit with a predetermined threshold value set in advance in the comparator, and transmit a signal Sig to the control circuit 130 when a comparison result that satisfies the set conditions is obtained.

[0017] The control circuit 130 is configured to issue an instruction to reduce the slew rate of the first circuit 101 when the power device 20 is turned off, depending on the result obtained by the detection circuit 120. The control circuit 130 is configured by a logic circuit or the like, and may be configured to be connected to a microcontroller unit (MCU).

[0018] In the example of the semiconductor device 10 shown in FIG. 1, the monitor unit is configured to observe the gate voltage of the power device 20 via the terminal T3, and the comparator is configured to compare the observed gate voltage with a predetermined threshold value.

[0019] When the voltage at the gate of the power device 20 becomes equal to or lower than a predetermined first threshold, the comparator transmits a signal Sig to the control circuit 130. Upon receiving the signal Sig, the control circuit 130 instructs the first circuit 101 to reduce the slew rate of the gate of the power device 20, and the first circuit 101 increases the resistance between the source and drain of the power device 20.

[0020] Here, the operation performed by the semiconductor device 10 according to the present disclosure on the power device 20 will be described.

[0021] The semiconductor device 10 according to the present disclosure configures an LRC series circuit (L: coil, R: resistor, C: capacitor) within the power module by intentionally creating a state in which the power device 20 is made highly resistant when the power device 20 is turned off. This allows the energy generated in the floating inductor within the power module to be consumed by the power device 20, thereby suppressing EMI.

[0022] That is, the semiconductor device 10 according to the present disclosure can be configured to have a pseudo snubber circuit and bypass capacitor. If a snubber circuit and bypass capacitor are actually provided around the power device 20, problems such as an increase in size and cost of the semiconductor device 10 and the power device 20 arise. On the other hand, the semiconductor device 10 according to the present disclosure can suppress EMI without adding these circuits.

[0023] Here, the mechanism by which ringing occurs will be explained. Figure 2 shows the power device 20 in an on (conducting) state. At this time, energy (E=1 / 2*L*I2, I: current) is stored in the floating inductor 200 around the power device 20.

[0024] 3(a) shows the moment when the power device 20 is turned off. At this time, the power device 20 is replaced by a capacitance 202 (see FIG. 3(b)). The energy stored in the floating inductor 200 has nowhere to go other than the floating inductor 200 and the bypass capacitor 201 provided in the power device 20, so LC resonance occurs, resulting in ringing.

[0025] Fig. 4 shows a waveform at turn-off, and Fig. 5 shows how the resistance of the power device 20 increases when the semiconductor device 10 according to the present disclosure is used. When ringing occurs, the power device 20 increases its resistance (see Fig. 5(a)), converting the power device 20 itself into a resistance component 203 and forming a pseudo-LRC series circuit without any additional circuitry (see Fig. 5(b)). This allows the energy stored in the floating inductor 200 to be dissipated by the LRC series circuit.

[0026] This makes it possible to appropriately increase the resistance between the source and drain of the power device 20 when the power device 20 is turned off, thereby making it possible to suppress EMI.

[0027] Thereafter, when the detection circuit 120 detects that the power device 20 has reached a gate voltage (second threshold) at which the influence of ringing on the power device 20 is eliminated, the control circuit 130 stops the reduction in the slew rate of the gate of the power device 20. If the resistance between the source and drain of the power device 20 is kept high in order to suppress EMI, the switching speed will decrease due to the high resistance of the power device 20. Therefore, by returning the power device 20 to its normal state when the influence of ringing is eliminated, the reduction in switching speed can be suppressed, thereby achieving both high-speed switching and suppression of electromagnetic interference.

[0028] The increase in resistance between the source and drain of the power device 20 will be explained using Fig. 6. Fig. 6(a) and (b) each show the change in gate voltage over time when the power device 20 is turned off. There are two possible timings for increasing the resistance between the source and drain of the power device 20:

[0029] One is to increase the resistance between the source and drain of the power device 20 during turn-off, as shown in Fig. 6(a). When the power device 20 switches, a Miller plateau period ("Miller Plateau" in Fig. 6(a)) occurs in which the voltage at the gate of the power device 20 does not decrease linearly but is steadily maintained at a certain value, and the gate voltage during this period is called the Miller plateau voltage.

[0030] 1, this Miller plateau voltage is used as a first threshold value ("Vth" in FIG. 6(a)) set in the comparator. Therefore, when it is observed that the voltage at the gate of the power device 20 has become equal to or lower than the Miller plateau voltage, the control circuit 130 reduces the slew rate of the gate of the power device 20, thereby increasing the resistance between the source and drain of the power device 20 ("High Resistance" in FIG. 6(a)).

[0031] Furthermore, when it is observed that the power device 20 has reached a voltage (second threshold, "Vth'" in FIG. 6(a)) at which the effect of ringing is eliminated, the control circuit 130 stops the decrease in the slew rate of the gate of the power device 20 and quickly switches the power device 20 to the OFF state. This makes it possible to suppress a decrease in switching speed due to an increase in the resistance of the power device 20.

[0032] The first and second thresholds are not limited to the above examples and can be changed arbitrarily or may be fixed values. The first and second thresholds can be changed via register settings within the gate driver unit 100, a primary side setting pin, a secondary side setting pin, etc. The primary side setting pin and the secondary side setting pin will be described later.

[0033] The on-resistance of the power device 20 can be adjusted by adjusting the gate voltage of the power device 20. Figure 6(c) shows the relationship between the gate voltage and the on-resistance of the power device 20. By lowering the gate voltage, the resistance between the source and drain of the power device 20 can be increased.

[0034] 6(b), the power device 20 is turned on again after being turned off, thereby increasing the resistance between the source and drain of the power device 20. Details of this will be described in the embodiment described later.

[0035] 7 shows the electrical characteristics of the power device 20 in the case where the semiconductor device 10 according to the present embodiment increases the resistance between the source and drain of the power device 20 (hereinafter referred to as the "high resistance mode"), alongside the electrical characteristics of a comparative example studied by the present inventors. FIG. 7(a) shows the time changes of the gate voltage, the source-drain voltage, and the load current of the power device 20 in the high resistance mode, and FIG. 7(b) shows the time changes of the load current of the power device 20 in the comparative example. As shown in FIG. 7(b), ringing occurs in the source-drain voltage and the load current in the power device 20 of the comparative example.

[0036] 1, the semiconductor device 10 reduces the slew rate and enters the high resistance mode when the gate voltage falls below the Miller plateau voltage ("Trg1" in FIG. 7(a)). It can be seen that the ringing of the voltage between the source and drain and the ringing of the load current are suppressed by entering the high resistance mode.

[0037] Next, an example of operating the semiconductor device 10 using the voltage between the source and drain of the power device 20 will be described with reference to Fig. 8. In the example of the semiconductor device 10 shown in Fig. 8, the monitor unit observes the voltage between the source and drain of the power device 20 via the terminal T3, and the comparator is configured to compare the observed voltage between the source and drain with a predetermined threshold value.

[0038] As shown in FIGS. 7(a) and 7(b), when the power device 20 is turned off, the voltage between the source and drain increases linearly even during the period when the voltage on the gate is at the Miller plateau voltage.

[0039] When the voltage between the source and drain of the power device 20 becomes equal to or greater than a predetermined threshold, the comparator transmits a signal Sig to the control circuit 130. Upon receiving the signal Sig, the control circuit 130 instructs the first circuit 101 to reduce the slew rate of the gate of the power device 20, and the first circuit 101 increases the resistance between the source and drain of the power device 20.

[0040] This makes it possible to appropriately increase the resistance between the source and drain of the power device 20 when the power device 20 is turned off, thereby making it possible to suppress EMI.

[0041] 8, the semiconductor device 10 reduces the slew rate and enters the high resistance mode when the voltage between the source and drain reaches a predetermined threshold value or higher ("Trg2" in FIG. 7(a)). It can be seen that the ringing of the voltage between the source and drain and the load current is suppressed by entering the high resistance mode.

[0042] Next, an example of operating the semiconductor device 10 using the load current of the power device 20 will be described with reference to Fig. 9. In the example of the semiconductor device 10 shown in Fig. 9, the monitor unit observes the load current of the power device 20 via terminals T3 and T4, and the comparator is configured to compare the observed load current with a predetermined threshold. Note that the load current is not limited to be detected by the monitor unit, and a current detection terminal of the power device 20 may also be used.

[0043] As shown in FIGS. 7(a) and 7(b), after the power device 20 is turned off and the period in which the gate voltage is at the Miller plateau voltage has passed, the load current decreases linearly.

[0044] When the load current of the power device 20 becomes equal to or less than a predetermined threshold, the comparator transmits a signal Sig to the control circuit 130. Upon receiving the signal Sig, the control circuit 130 instructs the first circuit 101 to reduce the slew rate of the gate of the power device 20, and the first circuit 101 increases the resistance between the source and drain of the power device 20.

[0045] This makes it possible to appropriately increase the resistance between the source and drain of the power device 20 when the power device 20 is turned off, thereby making it possible to suppress EMI.

[0046] 9, the semiconductor device 10 reduces the slew rate and enters the high resistance mode when the load current exceeds a predetermined threshold ("Trg3" in FIG. 7(a)). It can be seen that the ringing of the voltage between the source and drain and the ringing of the load current are suppressed by entering the high resistance mode.

[0047] Next, an example of operating the semiconductor device 10 by providing a clamp circuit in the power device 20 will be described with reference to Fig. 10. In the example of the semiconductor device 10 shown in Fig. 10, a Zener diode 140 is provided between the gate and drain of the power device 20. When a surge voltage occurs between the gate and drain of the power device 20, the Zener diode 140 fixes the overvoltage to a constant voltage, and an excess current (Zener current) flows through a resistor between terminals T3 and T4, allowing the monitor unit to detect the surge voltage.

[0048] When the Zener current becomes equal to or less than a predetermined threshold, the comparator transmits a signal Sig to the control circuit 130. Upon receiving the signal Sig, the control circuit 130 instructs the first circuit 101 to reduce the slew rate of the gate of the power device 20, and the first circuit 101 increases the resistance between the source and drain of the power device 20.

[0049] This makes it possible to appropriately increase the resistance between the source and drain of the power device 20 when the power device 20 is turned off, thereby making it possible to suppress EMI.

[0050] 10, the power device 20 is triggered by the occurrence of a surge voltage between the gate and drain ("Trg4" in FIG. 7(a)), causing the semiconductor device 10 to reduce the slew rate and enter the high resistance mode. It can be seen that the ringing of the voltage between the source and drain and the load current is suppressed by entering the high resistance mode period.

[0051] Next, an example in which the semiconductor device 10 is operated under management by a timer instead of the detection circuit 120 will be described with reference to FIG. 11. The example of the semiconductor device 10 shown in FIG. 11 has a configuration in which a register circuit 150 having a timer is provided upstream of the control circuit 130. The control circuit 130 and the register circuit 150 may be configured to be connected to a microcontroller unit (MCU), and in the configuration exemplified in FIG. 11, they are connected to the MCU via a transmit port Tx on the MCU side and a receive port Rx on the circuit side. The primary side setting pins used to change the first and second thresholds are on the MCU side, and the secondary side setting pins are on the power device side.

[0052] When the register circuit 150 detects the start of turn-off of the power device 20 via the terminal T5, it transmits a signal Sig to the control circuit 130 after a predetermined time has elapsed. The control circuit 130, which has received the signal Sig, instructs the first circuit 101 to reduce the slew rate of the gate of the power device 20, and the first circuit 101 increases the resistance between the source and drain of the power device 20.

[0053] This makes it possible to appropriately increase the resistance between the source and drain of the power device 20 when the power device 20 is turned off, thereby making it possible to suppress EMI.

[0054] 11, the power device 20 is turned off and a predetermined time has elapsed, which is triggered by the semiconductor device 10 ("Trg5" in FIG. 7(a)), causing the semiconductor device 10 to reduce the slew rate and enter the high resistance mode. It can be seen that the ringing of the voltage between the source and drain and the ringing of the load current are suppressed by the period of the high resistance mode.

[0055] <Embodiment 2> In this embodiment, a modified example of the semiconductor device according to the first embodiment will be described, particularly in the case where the power device 20 is turned on again after being turned off, as shown in Fig. 2(b), to increase the resistance between the source and drain of the power device 20. Note that the same components as those in the first embodiment will be denoted by the same reference numerals, and the description thereof may be omitted.

[0056] 12 is a block diagram of a semiconductor device according to this embodiment. The semiconductor device 10 is connected to a power device 20 and includes a gate driver unit 100, a resistor section 110, a detection circuit 120, a first control circuit 131, a second control circuit 132, and a register circuit 150 having a timer. The first control circuit 131 is connected to the first circuit 101, and the second control circuit 132 is connected to the second circuit 102. The first control circuit 131 and the second control circuit 132 may each be configured with a logic circuit or the like and connected to a microcontroller unit (MCU).

[0057] The detection circuit 120 includes a monitor unit and a comparator. The monitor unit is configured to observe at least one of the gate voltage, the source-drain voltage, and the load current of the power device 20. The monitor unit may be provided as a separate circuit outside the semiconductor device 10, but if it is built into the detection circuit 120, additional components are not required, thereby enabling the semiconductor device 10 to be made smaller.

[0058] The comparator is configured to compare the electrical characteristics of the power device 20 observed by the monitor unit with a predetermined threshold value set in advance in the comparator, and transmit a signal Sig1 to the register circuit 150 when a comparison result that satisfies the set condition is obtained.

[0059] Although the first circuit 101 and the second circuit 102 in the first embodiment are each multi-level gate driver circuits having at least two levels, High and Low, the present embodiment is not limited to this. For example, the semiconductor device 10 according to the present embodiment operates favorably even in a configuration in which the first circuit 101 is an n-type transistor and the second circuit 102 is a p-type transistor.

[0060] 12, the monitor unit monitors the gate voltage of the power device 20 via the terminal T3, and the comparator is configured to compare the monitored gate voltage with a predetermined threshold value. The predetermined threshold value is set to a gate voltage at which the power device 20 is considered to be turned off. The comparator sends a signal Sig1 to the register circuit 150 when the gate voltage of the power device 20 becomes equal to or lower than the threshold value.

[0061] After a predetermined time has elapsed since receiving the signal Sig1, the register circuit 150 outputs a signal Sig2 to the second control circuit 132 to turn the power device 20 on again, and sends a signal Sig3 to the first control circuit 131 to reduce the slew rate of the gate of the power device 20.

[0062] The second control circuit 132, which has received the signal Sig2, turns on the power device 20 again using the second circuit 102. The first control circuit 131, which has received the signal Sig3, uses the first circuit 101 to reduce the slew rate of the gate of the power device 20, thereby increasing the resistance between the source and drain of the power device 20.

[0063] As a result, after the power device 20 is turned off, the power device 20 can be turned on again to appropriately increase the resistance between the source and drain of the power device 20, thereby making it possible to suppress EMI.

[0064] 13 shows the electrical characteristics of the power device 20 when the power device 20 is in the high resistance mode due to the semiconductor device 10 according to the present embodiment, alongside the electrical characteristics of a comparative example studied by the present inventors. FIG. 13(a) shows the time changes in the gate voltage, source-drain voltage, and load current of the power device 20 in the high resistance mode, and FIG. 13(b) shows the time changes in the load current of the comparative example. As shown in FIG. 13(b), ringing occurs in the source-drain voltage and the load current of the power device 20 of the comparative example.

[0065] 12, after being turned off, the power device 20 is turned on again by the semiconductor device 10 when the gate voltage falls below a predetermined threshold ("Trg6" in FIG. 13(a)), and enters the high resistance mode. It can be seen that the ringing of the voltage between the source and drain and the ringing of the load current are suppressed by the period of the high resistance mode.

[0066] Next, an example of operating the semiconductor device 10 using the voltage between the source and drain of the power device 20 will be described with reference to Fig. 14. In the example of the semiconductor device 10 shown in Fig. 14, the monitor unit observes the voltage between the source and drain of the power device 20 via the terminal T3, and the comparator is configured to compare the observed voltage between the source and drain with a predetermined threshold value.

[0067] The comparator sends a signal Sig1 to the register circuit 150 when the voltage between the source and drain of the power device 20 is equal to or greater than the threshold value.

[0068] After a predetermined time has elapsed since receiving the signal Sig1, the register circuit 150 outputs a signal Sig2 to the second control circuit 132 to turn the power device 20 on again, and sends a signal Sig3 to the first control circuit 131 to reduce the slew rate of the gate of the power device 20.

[0069] The second control circuit 132, which has received the signal Sig2, turns on the power device 20 again using the second circuit 102. The first control circuit 131, which has received the signal Sig3, uses the first circuit 101 to reduce the slew rate of the gate of the power device 20, thereby increasing the resistance between the source and drain of the power device 20.

[0070] As a result, after the power device 20 is turned off, the power device 20 can be turned on again to appropriately increase the resistance between the source and drain of the power device 20, thereby making it possible to suppress EMI.

[0071] 14 is turned on again by the semiconductor device 10 and enters the high resistance mode when the voltage between the source and drain reaches or exceeds a predetermined threshold ("Trg7" in FIG. 13(a)). It can be seen that the ringing of the voltage between the source and drain and the load current is suppressed by entering the high resistance mode.

[0072] Next, an example of operating the semiconductor device 10 using the load current of the power device 20 will be described with reference to Fig. 15. In the example of the semiconductor device 10 shown in Fig. 15, the monitor unit observes the load current of the power device 20 via terminals T3 and T4, and the comparator is configured to compare the observed load current with a predetermined threshold. Note that the load current is not limited to be detected by the monitor unit, and a current detection terminal of the power device 20 may also be used.

[0073] The comparator sends a signal Sig1 to the register circuit 150 when the load current of the power device 20 becomes equal to or less than a predetermined threshold value.

[0074] After a predetermined time has elapsed since receiving the signal Sig1, the register circuit 150 outputs a signal Sig2 to the second control circuit 132 to turn the power device 20 on again, and sends a signal Sig3 to the first control circuit 131 to reduce the slew rate of the gate of the power device 20.

[0075] The second control circuit 132, which has received the signal Sig2, turns on the power device 20 again using the second circuit 102. The first control circuit 131, which has received the signal Sig3, uses the first circuit 101 to reduce the slew rate of the gate of the power device 20, thereby increasing the resistance between the source and drain of the power device 20.

[0076] As a result, after the power device 20 is turned off, the power device 20 can be turned on again to appropriately increase the resistance between the source and drain of the power device 20, thereby making it possible to suppress EMI.

[0077] 15 is turned on again by the semiconductor device 10 and enters the high resistance mode when the load current exceeds a predetermined threshold ("Trg8" in FIG. 13(a)). It can be seen that the ringing of the voltage between the source and drain and the ringing of the load current are suppressed by entering the high resistance mode.

[0078] Next, an example in which the operation of the semiconductor device 10 is managed by a timer instead of the detection circuit 120 will be described with reference to Fig. 16. The example of the semiconductor device 10 shown in Fig. 16 has a configuration in which a register circuit 150 having a timer is provided upstream of the first control circuit 131 and the second control circuit 132. The register circuit 150 may be configured to be connected to a microcontroller unit (MCU).

[0079] When the register circuit 150 detects the start of turning off the power device 20 via the terminal T5, it outputs a signal Sig2 to the second control circuit 132 to turn the power device 20 on again after a predetermined time has elapsed, and sends a signal Sig3 to the first control circuit 131 to reduce the slew rate of the gate of the power device 20.

[0080] The second control circuit 132, which has received the signal Sig2, turns on the power device 20 again using the second circuit 102. The first control circuit 131, which has received the signal Sig3, uses the first circuit 101 to reduce the slew rate of the gate of the power device 20, thereby increasing the resistance between the source and drain of the power device 20.

[0081] As a result, after the power device 20 is turned off, the power device 20 can be turned on again to appropriately increase the resistance between the source and drain of the power device 20, thereby making it possible to suppress EMI.

[0082] 16, the power device 20 is turned on again by the semiconductor device 10, and enters the high resistance mode, triggered by a time point ("Trg9" in FIG. 13(a)) after a predetermined time has elapsed since the power device 20 was turned off. It can be seen that the ringing of the voltage between the source and drain and the ringing of the load current are suppressed by the period of the high resistance mode.

[0083] The invention made by the present inventors has been specifically described above based on the embodiments, but it goes without saying that the present disclosure is not limited to the embodiments already described, and various modifications are possible within the scope that does not deviate from the gist of the present disclosure. [Explanation of symbols]

[0084] 10 Semiconductor devices 20 Power Devices 100 gate driver units 101 First Circuit 102 Second Circuit 110 Resistance section 111 First Resistance 112 The Second Resistance 120 Detection circuit 130 control circuit 131 first control circuit 132 second control circuit 140 Zener diode 150 Resistor Circuit 200 stray inductor 201 Bypass capacitor 202 capacity 203 Resistance Component

Claims

1. A semiconductor device connected to a power device, a gate driver unit including a first circuit and a second circuit; a resistor portion connecting the gate of the power device and the gate driver unit; a first control circuit connected to the gate driver unit; the first control circuit is configured to increase the resistance of the power device by issuing an instruction to the first circuit to reduce a slew rate of the power device when the power device is turned off. Semiconductor device.

2. Further, a detection circuit having a monitor unit and a comparator is provided, the monitor unit is configured to observe a voltage of the gate of the power device, the comparator is configured to compare the observed voltage with a predetermined threshold; the first control circuit is configured to increase the resistance of the power device when the voltage is equal to or less than the predetermined threshold. The semiconductor device according to claim 1 .

3. the first control circuit is configured to increase the resistance of the power device after the voltage becomes lower than a Miller plateau voltage. The semiconductor device according to claim 2 .

4. Further, a detection circuit having a monitor unit and a comparator is provided, the monitor unit is configured to observe a voltage between a source and a drain of the power device, the comparator is configured to compare the observed voltage with a predetermined threshold; the first control circuit is configured to increase the resistance of the power device when the voltage is equal to or greater than the predetermined threshold. The semiconductor device according to claim 1 .

5. Further, a detection circuit having a monitor unit and a comparator is provided, the monitor unit is configured to observe a load current of the power device, the comparator is configured to compare the observed load current with a predetermined threshold; the first control circuit is configured to increase the resistance of the power device when the load current is equal to or less than the predetermined threshold. The semiconductor device according to claim 1 .

6. The power supply further includes a detection circuit having a monitor unit and a comparator, and a clamp circuit connecting the drain and gate of the power device, the clamp circuit has a Zener diode connecting the gate driver unit and a drain of the power device; the comparator is configured to detect ringing by observing a current flowing through the Zener diode; the first control circuit is configured to increase the resistance of the power device when the ringing is detected. The semiconductor device according to claim 1 .

7. further comprising a register circuit connected to the first control circuit; the register circuit is configured to issue an instruction to the first control circuit to increase the resistance of the power device after a predetermined time has elapsed since the start of turn-off of the power device. The semiconductor device according to claim 1 .

8. moreover, a detection circuit having a monitor section and a comparator; a second control circuit connected to the second circuit; a register circuit connected to the detection circuit, the first control circuit, and the second control circuit; the monitor unit is configured to observe a voltage of the gate of the power device, the comparator is configured to compare the observed voltage with a predetermined threshold; the register circuit is configured to, after a predetermined time has elapsed since detecting that the voltage is equal to or lower than the predetermined threshold, issue an instruction to the second control circuit to turn on the power device, and thereafter issue an instruction to the first control circuit to increase the resistance of the power device. The semiconductor device according to claim 1 .

9. the register circuit is configured to issue an instruction to the first control circuit to increase the resistance of the power device after the predetermined time has elapsed since the voltage became lower than a Miller plateau voltage. The semiconductor device according to claim 8 .

10. moreover, a detection circuit having a monitor section and a comparator; a second control circuit connected to the second circuit; a register circuit connected to the detection circuit, the first control circuit, and the second control circuit; the monitor unit is configured to observe a voltage between a source and a drain of the power device, the comparator is configured to compare the observed voltage with a predetermined threshold; the register circuit is configured to, after a predetermined time has elapsed since detecting a state in which the voltage is equal to or greater than the predetermined threshold, issue an instruction to the second control circuit to turn on the power device, and then issue an instruction to the first control circuit to increase the resistance of the power device. The semiconductor device according to claim 1 .

11. moreover, a detection circuit having a monitor section and a comparator; a second control circuit connected to the second circuit; a register circuit connected to the detection circuit, the first control circuit, and the second control circuit; the monitor unit is configured to observe a load current of the power device, the comparator is configured to compare the observed load current with a predetermined threshold; the register circuit is configured to, after a predetermined time has elapsed since detecting that the load current is equal to or less than the predetermined threshold, issue an instruction to the second control circuit to turn on the power device, and thereafter issue an instruction to the first control circuit to increase the resistance of the power device. The semiconductor device according to claim 1 .

12. moreover, a second control circuit connected to the second circuit; a register circuit connected to the first control circuit and the second control circuit; the register circuit is configured to, after a predetermined time has elapsed since detecting the start of turn-off of the power device, issue an instruction to the second control circuit to turn on the power device, and thereafter issue an instruction to the first control circuit to increase the resistance of the power device. The semiconductor device according to claim 1 .

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