Memory device and manufacturing method thereof

Abstract

To provide a memory device.SOLUTION: A memory device includes a transistor, a first metal layer over the transistor, and a second metal layer over the first metal layer. The transistor includes a gate layer, a source region, and a drain region, in which the source region and the drain regions are at two sides of the gate layer. The first metal layer includes a bit line electrically connected to the drain region of the transistor. The second metal layer includes a first gate metal layer electrically connected to the gate layer of the transistor, and a first word line surrounding the first gate metal layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure and some embodiments relate to memory devices and methods for manufacturing the same. [Background technology]

[0002] Embedded non-volatile memory (eNVM) is a non-volatile memory technology that is directly integrated into a chip to store data. The information stored in eNVM can be retained even when the power is turned off. However, typical eNVMs have more complicated operations and processes. Therefore, there is an urgent need for eNVMs that can provide simple operations and simple processes. Summary of the Invention [Means for solving the problem]

[0003] Some embodiments of the present disclosure provide a memory device comprising: a transistor including a gate layer and a source region and a drain region, respectively, on either side of the gate layer; a first metal layer overlying the transistor and including a bit line electrically connected to the drain region of the transistor; a first gate metal layer electrically connected to the gate layer of the transistor; and a second metal layer overlying the first metal layer and including a first word line surrounding the first gate metal layer.

[0004] In some embodiments, the first metal layer further comprises a second gate metal layer electrically connected to the first gate metal layer of the second metal layer and to the gate layer of the transistor.

[0005] In some embodiments, the first metal layer further includes a source line electrically connected to a source region of the transistor.

[0006] In some embodiments, the memory device further comprises a third gate metal layer electrically connected to the first gate metal layer of the second metal layer, and a second word line surrounding the third gate metal layer, the third metal layer being on the second metal layer.

[0007] In some embodiments, the memory device further comprises a dielectric layer between the first gate metal layer and the first word line of the second metal layer.

[0008] Some embodiments of the present disclosure provide a method for manufacturing a memory device, comprising: forming a transistor including a gate layer and a source region and a drain region on either side of the gate layer; forming a first metal layer in the transistor including a bit line electrically connected to the drain region of the transistor; and forming a second metal layer in the first metal layer including the first gate metal layer electrically connected to the gate layer of the transistor and a first word line surrounding the first gate metal layer.

[0009] In some embodiments, the method further comprises forming a third metal layer in the second metal layer, the third metal layer including a second gate metal layer electrically connected to the first gate metal layer of the second metal layer and a second word line surrounding the first gate metal layer.

[0010] In some embodiments, the first word line in the second metal layer and the second word line in the third metal layer are formed with a similar mask.

[0011] In some embodiments, the first gate metal layer of the second metal layer and the second gate metal layer of the third metal layer are formed using the same mask.

[0012] In some embodiments, the first metal layer includes a first gate metal layer of the second metal layer and a third gate metal layer electrically connected to the gate layer of the transistor, and the first gate metal layer of the second metal layer and the third gate metal layer of the first metal layer are formed by a similar mask. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a perspective view of a memory device according to some embodiments of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA' in FIG. [Figure 3] FIG. 2 is a top view of the metal layer of FIG. 1 of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014] Some embodiments of the present disclosure relate to the formation of memory devices and methods of forming the same, and the present disclosure is applicable to single-poly silicon embedded non-volatile memory devices (single poly eNVM), such as flash memory, electrically erasable programmable read-only memory (EEPROM), one-time programmable memory (OTP memory), and multiple-time programmable memory (MTP memory). In the present disclosure, the process for forming the memory device is simple, and fewer masks can be used. Furthermore, the operation method of the memory device of the present disclosure is also simple.

[0015] FIG. 1 is a perspective view of a memory device according to some embodiments of the present disclosure. FIG. 2 is a cross-sectional view taken along line A-A' in FIG. 1. Referring to FIGS. 1 and 2, the memory device includes a plurality of transistors 100, a metal layer 200, and a metal layer 300. FIG. 1 illustrates a portion of a memory array in the memory device, e.g., one row of the memory array (aligned along a first direction D1). However, the memory array may actually be a two-dimensional array (aligned along a first direction D1 and a second direction D2). It should be noted that, to clearly depict the relative positions of each element in FIG. 1, some elements, e.g., dielectric layer 160, dielectric layer 260, and dielectric layer 360 in FIG. 2, are omitted from FIG. 1.

[0016] The transistor 100 may be arranged along a first direction D1. The transistor 100 includes a gate layer 112, a gate dielectric layer 114, and a semiconductor layer 120, where the gate layer 112 is on the gate dielectric layer 114, and the gate dielectric layer 114 is on the semiconductor layer 120. In some embodiments, the gate dielectric layer 114 is a tunnel oxide layer. In some embodiments, the equivalent thickness T1 of the gate dielectric layer 114 is about 90 angstroms ( FIG. 2 ), the length L1 of the gate dielectric layer 114 is about 0.05 micrometers ( FIG. 2 ), and the width W1 of the gate dielectric layer 114 is about 0.05 micrometers. The semiconductor layer 120 includes a well region 122 ( FIG. 2 ), a source region 126, and a drain region 124. The gate layer 112 and the gate dielectric layer 114 are on the well region 122, and the source region 126 and the drain region 124 are on either side of the gate layer 112 and the gate dielectric layer 114, respectively. In some embodiments, the gate layer 112 may be fabricated from a conductive material, such as polycrystalline silicon. The gate dielectric layer 114 may be fabricated from a suitable oxide layer, such as silicon oxide. The semiconductor layer 120 may be fabricated from a semiconductor, such as silicon, and the conductor type of the well region 122 may be different from the conductor type of the source region 126 and the drain region 124. For example, if the well region 122 is P-type, the source region 126 and the drain region 124 may be N-type. If the well region 122 is N-type, the source region 126 and the drain region 124 may be P-type. The well regions 122 of adjacent transistors 100 may be separated by an isolation structure 150, and the drain regions 124 of adjacent transistors 100 may be separated by the isolation structure 150. In some embodiments, the isolation structure 150 may be fabricated from a dielectric material, such as silicon oxide. The source regions 126 of adjacent transistors 100 are coupled. In some embodiments, the gate layers 112 may extend to the isolation structures 150, but adjacent gate layers 112 maintain electrical isolation.

[0017] A metal layer 200 is on the transistor 100. In this disclosure, the metal layer 200 can be considered a first metal layer (M1), and the metal layer 200 includes a gate metal layer 210, a bit line 220, and a source line 230. The gate metal layer 210 is on the gate layer 112 and the gate dielectric layer 114 of the transistor 100 and is electrically connected to the gate layer 112 of the transistor 100. The bit line 220 is electrically connected to the drain region 124 of the transistor 100. The source line 230 is electrically connected to the source region 126 of the transistor 100. Electrical connections between the gate metal layer 210 and the gate layer 112, between the bit line 220 and the drain region 124, and between the source line 230 and the source region 126 may be provided by via hole members V0. The vertical directions of the bit lines 220 and source lines 230 all extend along the second direction D2 (note that in this disclosure, the bit lines 220 and source lines 230 are not shown as fully extended to avoid ambiguity in the relationship between elements due to the bit lines 220 and source lines 230 shielding other elements). In the metal layer 200, a bit line 220 is provided between two adjacent gate metal layers 210 along the first direction D1, i.e., the gate metal layers 210 and the bit lines 220 may be arranged alternately. Note that both sides of some gate metal layers 210 may have a bit line 220 and a source line 230. In this disclosure, in the same row of the memory array (the memory array shown in FIG. 1), the drain region 124 of one transistor 100 corresponds to one bit line 220, and the source regions 126 of multiple transistors 100 correspond to one source line 230. The gate metal layers 210, the bit lines 220, and the source lines 230 may be fabricated from conductors. In some embodiments, the gate metal layer 210, the bit lines 220 and the source lines 230 may be made of the same material.

[0018] Metal layer 300 is on metal layer 200, and metal layer 300 and metal layer 200 have different patterns. In the present disclosure, metal layer 300 can be considered a second metal layer (M2). FIG. 3 shows a top view of metal layer 300 of FIG. 1 of the present disclosure. Referring to FIGS. 1 and 3, metal layer 300 includes gate metal layer 310 and word line 320. Gate metal layer 310 is electrically connected to gate layer 112 of transistor 100 and gate metal layer 210 of metal layer 200. Electrical connection between gate metal layer 310 and gate metal layer 210 may be provided by via hole member V1. Gate metal layer 310 of metal layer 300 may be aligned with gate metal layer 210 of metal layer 200 and have a substantially similar pattern. The difference between the metal layer 300 and the metal layer 200 is that the metal layer 300 includes a word line 320, while the metal layer 200 includes a bit line 220 and a source line 230. The word line 320 of the metal layer 300 surrounds the gate metal layer 310. Specifically, the word line 320 may have two extension portions 322 and multiple connection portions 324. The extension portions 322 of the word line 320 extend along the first direction D1 and are located on both sides of the gate metal layer 310. The connection portions 324 of the word line 320 connect the two extension portions 322. In this way, the periphery of the gate metal layer 310 may be surrounded by the extension portions 322 and connection portions 324 of the word line 320. In other words, in the metal layer 300, the connection portions 324 of the word line 320 are located between two adjacent gate metal layers 310. Meanwhile, metal layer 200 has bit lines 220 between two adjacent gate metal layers 210, without any portion of a word line. In some embodiments, connecting portions 324 of word lines 320 and bit lines 220 at least partially overlap in the vertical direction. In some embodiments, thickness T2 of word lines 320 may be on the order of 900 angstroms. Gate metal layer 310 and word lines 320 may be made of a conductor. In some embodiments, gate metal layer 310 and word lines 320 may be made of the same material.In some embodiments, since the extension direction (second direction D2) of the bit lines 220 and source lines 230 of the first metal layer 200 is different from the extension direction (first direction D1) of the word lines 320 of the second metal layer 300, by forming the word lines 320 above the bit lines 220 and source lines 230, mutual interference between the word lines 320 and the wiring of the bit lines 220 and source lines 230 below can be avoided.

[0019] A dielectric layer IL may be provided between the gate metal layer 310 and the word line 320 of the metal layer 300, and the metal layer 300 may be divided into multiple capacitances C. Each capacitance C includes, from the inside out, the gate metal layer 310, the dielectric layer IL, and the word line 320. In the present disclosure, one capacitance C corresponds to one transistor 100, i.e., the structure of the present disclosure is a 1T-1C structure. In some embodiments, the distance S between the gate metal layer 310 and the word line 320 may be approximately 0.045 micrometers. The length L2 of the gate metal layer 310 may be approximately 0.05 micrometers. The width W2 of the gate metal layer 310 may be approximately 0.045 micrometers.

[0020] Because the present disclosure has a 1T-1C structure, the memory device of the present disclosure has easy-to-operate characteristics. Specifically, by applying specific voltages to the well region 122, drain region 124, source region 126, and word line 320 of transistor 100, data write, erase, or read operations of the memory device can be completed. In some embodiments, when performing a write operation, a VPP voltage can be applied to the word line 320, a −VPP voltage can be applied to the bit line 220 (i.e., drain region 124), and a 0 voltage can be applied to the source line 230 (i.e., source region 126) and well region 122. When performing an erase operation, a VEE voltage can be applied to the well region 122, and a 0 voltage can be applied to the word line 320, bit line 220 (i.e., drain region 124), and source line 230 (i.e., source region 126). When performing a read operation, a VDD voltage can be applied to the word line 320 and the bit line 220 (i.e., the drain region 124), and a 0 voltage can be applied to the source line 230 (i.e., the source region 126) and the well region 122. The data write or erase operation of the present disclosure can be performed by Fowler-Nordheim Tunneling (FN Tunneling). If the memory device does not have a 1T-1C structure as disclosed herein, it may be complicated to operate the memory device because one capacitance may correspond to multiple transistors and different transistors may have different roles.

[0021] 1 and 2, the memory device of the present disclosure may further include a metal layer 400. In the present disclosure, the metal layer 400 can be considered a third metal layer (M3). The metal layer 400 includes a gate metal layer 410 and a word line 420. The gate metal layer 410 is electrically connected to the gate metal layer 310 of the metal layer 300. The word line 420 is electrically connected to the word line 320 of the metal layer 300. Electrical connections between the gate metal layer 410 and the gate metal layer 310 and between the word line 420 and the word line 320 may be provided by via hole members V2. The gate metal layer 410 of the metal layer 400 may be aligned with the gate metal layer 310 of the metal layer 300 and may have a substantially similar pattern. The word line 420 surrounds the gate metal layer 410. The word lines 420 of metal layer 400 may be aligned with and have a substantially similar pattern to the word lines 320 of metal layer 300. In some embodiments, a top view of metal layer 400 may be as shown in FIG. 3. The gate metal layer 410 and the word lines 420 may be made of a conductor. In some embodiments, the gate metal layer 410 and the word lines 420 may be made of the same material.

[0022] In some embodiments, the memory device of the present disclosure may further include other metal layers stacked above it, and thus the metal layer 400 may have a via hole member V3 to electrically connect the metal layer 400 to the metal layer above it. In the present disclosure, except for the metal layer 200, which does not include word lines, all other metal layers include gate metal layers and word lines, and the shapes of the gate metal layers in different metal layers are similar, and the shapes of the word lines in different metal layers are similar. Adding different numbers of metal layers increases the coupling ratio of the memory. In some embodiments, the metal layers of the memory device of the present disclosure may include two to eight metal layers. In the present disclosure, the gate layer 112, the via hole member V0, the gate metal layer 210, the via hole member V1, the gate metal layer 310, the via hole member V2, the gate metal layer 410, and the via hole member V3 may be collectively referred to as a floating gate structure.

[0023] The memory device of the present disclosure also has the advantage of being simple in process, specifically, in the manufacturing process of the memory device of the present disclosure, transistor 100 is formed, and then metal layer 200, metal layer 300, and metal layer 400 are formed in that order.

[0024] In some embodiments, before forming the transistor 100, a plurality of isolation structures 150 may be formed in the semiconductor layer 120 before forming the transistor 100. Forming the transistor 100 includes forming a gate dielectric layer 114 and a gate layer 112 on the semiconductor layer 120, and then performing an ion implantation process on the semiconductor layer 120 to form source and drain regions 126 and 124 on either side of the gate layer 112, with the remaining portion of the semiconductor layer 120 being referred to as a well region 122. After forming the transistor 100, a dielectric layer 160 may be formed on the transistor 100, and a via member V0 may be formed in the dielectric layer 160. The via member V0 may be electrically connected to the gate structure 110, the source and drain regions 126, and the drain region 124 of the transistor 100.

[0025] Then, a metal layer 200 is formed on the transistor 100. Forming the metal layer 200 may include forming a dielectric layer on the dielectric layer 160, patterning the dielectric layer, and forming a gate metal layer 210, a bit line 220, and a source line 230 in the dielectric layer. The gate metal layer 210, the bit line 220, and the source line 230 are all connected to a via hole member V0 so as to be electrically connected to the underlying devices. After forming the metal layer 200, a dielectric layer 260 may be formed on the metal layer 200, and a via hole member V1 may be formed in the dielectric layer 260. The via hole member V1 may be electrically connected to the gate metal layer 210.

[0026] Then, a metal layer 300 is formed on the metal layer 200. Forming the metal layer 200 may include forming a dielectric layer on the dielectric layer 260, patterning the dielectric layer, and forming a gate metal layer 310 and a word line 320 in the dielectric layer. The gate metal layer 310 is connected to a via hole member V1 so as to be electrically connected to the underlying device. After forming the metal layer 300, a dielectric layer 360 may be formed on the metal layer 300, and a via hole member V2 may be formed in the dielectric layer 360. The via hole member V2 may be electrically connected to the gate metal layer 310 and the word line 320.

[0027] Then, a metal layer 400 is formed on the metal layer 300. Forming the metal layer 400 may include forming a dielectric layer on the dielectric layer 360, patterning the dielectric layer, and forming a gate metal layer 410 and a word line 420 in the dielectric layer. The gate metal layer 410 and the word line 420 are connected to via members V2 so as to be electrically connected to the underlying devices. After forming the metal layer 400, an additional dielectric layer may be formed on the metal layer 400, and a via member V3 may be formed in the dielectric layer so as to be electrically connected to the gate metal layer 410. The via member V3 may be used to electrically connect the gate metal layer 410 to an upper metal layer.

[0028] In the present disclosure, the gate metal layer 210, the gate metal layer 310, and the gate metal layer 410 (a gate metal layer of another metal layer) may be formed using the same mask, and therefore the gate metal layer 210, the gate metal layer 310, and the gate metal layer 410 may have substantially the same shape. The word line 320 and the word line 420 (a word line of another metal layer) may be formed using the same mask, and therefore the word line 320 and the word line 420 may have substantially the same shape. In this manner, the memory device of the present disclosure may have a simple process, for example, the memory device of the present disclosure can be formed using fewer masks.

[0029] As described above, the memory device of the present disclosure has a simple process and a simple operation method. Specifically, the memory device of the present disclosure can be formed using fewer masks, thereby simplifying the process of the memory device of the present disclosure. Furthermore, since the memory device of the present disclosure has a 1T-1C structure, when performing memory data write, erase, and read operations, different voltages are applied to a single transistor element, thereby simplifying the complexity of performing memory operations.

[0030] The above are only some embodiments of the present disclosure, not all embodiments, and any equivalent changes made by a person skilled in the art to the technical solutions of the present disclosure after reading the specification of the present disclosure are included in the scope of the claims of the present disclosure. [Explanation of symbols]

[0031] 100:Transistor 112: Gate layer 114: Gate dielectric layer 120: Semiconductor layer 122: Well area 124: Drain region 126: Source area 150: Separated structure 160, 260, 360, IL: dielectric layer 200, 300, 400: Metal layer 210, 310, 410: Gate metal layers 220: bit line 230: Source line 320, 420: Word lines 322: Extended part 324: Connection part A-A': Line D1: 1st direction D2:Second direction L1, L2: length S: distance T1, T2: Thickness V0, V1, V2, V3: Via hole materials W1, W2: width

Claims

1. a transistor including a gate layer and a source region and a drain region on either side of the gate layer; a first metal layer overlying the transistor, the first metal layer including a bit line electrically connected to the drain region of the transistor; a second metal layer on the first metal layer, the second metal layer including a first gate metal layer electrically connected to the gate layer of the transistor and a first word line surrounding the first gate metal layer; A memory device comprising:

2. The first metal layer is The memory device of claim 1 , further comprising a second gate metal layer electrically connected to the first gate metal layer of the second metal layer and the gate layer of the transistor.

3. The first metal layer is 2. The memory device of claim 1, further comprising a source line electrically connected to the source region of the transistor.

4. 2. The memory device of claim 1, further comprising: a third gate metal layer electrically connected to the first gate metal layer of the second metal layer; and a second word line surrounding the third gate metal layer, the third metal layer being on the second metal layer.

5. 10. The memory device of claim 1, further comprising a dielectric layer between the first gate metal layer of the second metal layer and the first word line.

6. forming a transistor including a gate layer and a source region and a drain region on either side of the gate layer; forming a first metal layer on the transistor, the first metal layer including a bit line electrically connected to the drain region of the transistor; forming a second metal layer on the first metal layer, the second metal layer including a first gate metal layer electrically connected to the gate layer of the transistor and a first word line surrounding the first gate metal layer; A method for manufacturing a memory device comprising:

7. 7. The method of claim 6, further comprising forming a third metal layer in the second metal layer, the third metal layer including a second gate metal layer electrically connected to the first gate metal layer of the second metal layer, and a second word line surrounding the first gate metal layer.

8. 8. The method of claim 7, wherein the first word lines of the second metal layer and the second word lines of the third metal layer are formed using the same mask.

9. 8. The method of claim 7, wherein the first gate metal layer of the second metal layer and the second gate metal layer of the third metal layer are formed using the same mask.

10. The first metal layer is 8. The method of claim 7, further comprising a third gate metal layer electrically connected to the first gate metal layer of the second metal layer and the gate layer of the transistor, wherein the first gate metal layer of the second metal layer and the third gate metal layer of the first metal layer are formed using a similar mask.

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