Method for forming metal oxide layer and method for manufacturing semiconductor device

Abstract

To provide a metal oxide layer with high carrier mobility and a method for forming the same.SOLUTION: A method for forming a metal oxide layer includes a first step of forming a crystal part and a second step of forming a crystalline metal oxide layer using the crystal part as a nucleus. The metal oxide layer contains indium. The metal oxide layer is formed by an atomic layer deposition method, and a substrate heating temperature is higher than or equal to 150°C and lower than or equal to 250°C. A crystal orientation of a crystal grain included in the metal oxide layer is <111>, and a crystal orientation of the crystal part is <001>.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a metal oxide layer, a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a metal oxide layer and a method for manufacturing a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device. [Background technology]

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention.

[0005] Furthermore, it is known that transistors using oxide semiconductors have extremely low leakage current in an off state. For example, Patent Document 1 discloses a low-power central processing unit (CPU) that utilizes the low leakage current characteristic of transistors using oxide semiconductors. Furthermore, for example, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of transistors using oxide semiconductors.

[0006] Examples of oxide semiconductors that can be used for the active layer of a transistor include indium oxide, indium gallium zinc oxide, etc. Non-Patent Document 1 discloses a thin-film transistor whose active layer uses hydrogenated polycrystalline indium oxide formed by low-temperature solid-phase crystallization. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 [Non-patent literature]

[0008] [Non-Patent Document 1] Y. Magari et al., “High-mobility hydrogenated polycrystalline In2O3(In2O3:H) thin-film transistors”, nature COMMUNICATIONS, 13, 1078 (2022) [Non-patent document 2] N. Preissler et al., “Electrical transport, electrothermal transport, and effective electron mass in single-crystalline In2O3 films”, Phys.Rev.B,88,085305 (2013) [Non-patent document 3] Takashi Koida, "High Mobility Transparent Conductive Film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation 2019, Internet<URL:https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf> Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to provide a metal oxide layer having high carrier mobility.An object of one embodiment of the present invention is to provide a novel metal oxide layer.An object of one embodiment of the present invention is to provide a transistor, a semiconductor device, a memory device, or a display device to which the metal oxide layer is applied.

[0010] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a transistor with high on-state current.An object of one embodiment of the present invention is to provide a transistor with low parasitic capacitance.An object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, memory device, or display device.An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device, memory device, or display device with low power consumption.An object of one embodiment of the present invention is to provide a memory device with high operating speed.An object of one embodiment of the present invention is to provide a manufacturing method of the transistor, semiconductor device, memory device, or display device.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims. [Means for solving the problem]

[0012] One embodiment of the present invention is a method for forming a metal oxide layer, the method comprising: a first step of forming a crystal portion; and a second step of forming a crystalline metal oxide layer using the crystal portion as a nucleus. The metal oxide layer contains indium.

[0013] In the above method for producing a metal oxide layer, in the first step, the crystalline portion is preferably formed from one of the grains of a polycrystalline film.

[0014] In addition, the method for forming a metal oxide layer preferably includes a third step of forming an amorphous metal oxide film before the first step. In this case, in the first step, the crystalline portion is preferably formed on the amorphous metal oxide film. Furthermore, in the second step, the amorphous metal oxide film is preferably crystallized to form the metal oxide layer.

[0015] In the above method for producing a metal oxide layer, it is preferable that the metal oxide layer is formed by atomic layer deposition (ALD) and the substrate is heated to a temperature of 100°C or higher and 300°C or lower.

[0016] In the above method for producing a metal oxide layer, it is preferable that the metal oxide layer is formed by atomic layer deposition and the substrate is heated to a temperature of 150°C or higher and 250°C or lower.

[0017] One embodiment of the present invention is a method for forming a metal oxide layer, which includes a first step of forming a crystal portion on an insulating layer and a second step of forming a crystalline metal oxide layer on the crystal portion. The metal oxide layer contains indium. Prior to the second step, the top surface of the insulating layer is planarized by chemical mechanical polishing to have an average surface roughness of 0 nm or more and less than 3 nm.

[0018] In the above method for producing a metal oxide layer, it is preferable that the metal oxide layer undergoes lateral crystal growth in the second step and thereafter.

[0019] In the above method for producing a metal oxide layer, it is preferable that in the first step, a film that will become the crystalline portion is formed, and the film is processed using a wet etching method to form the crystalline portion.

[0020] In the method for producing the metal oxide layer, the crystal orientation of the crystal grains of the metal oxide layer is <111> It is preferable that:

[0021] In the method for producing the metal oxide layer, the crystal orientation of the crystal portion is <001> It is preferable that:

[0022] In the method for producing a metal oxide layer, the crystalline portion preferably contains indium, gallium, and zinc, and has a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition therearound, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition therearound.

[0023] In the above method for forming a metal oxide layer, it is preferable that the crystal orientation of the crystal grains in the metal oxide layer coincide or substantially coincide with the crystal orientation of the crystal portion.

[0024] In the above method for forming a metal oxide layer, the crystal portion preferably contains indium.

[0025] One embodiment of the present invention is a method for manufacturing a semiconductor device, including: a first step of forming a crystal portion on a first insulating layer; a second step of forming a crystalline metal oxide layer using the crystal portion as a nucleus; a third step of processing the metal oxide layer into an island shape; a fourth step of forming a second insulating layer to cover the metal oxide layer; a fifth step of forming an opening in the second insulating layer that overlaps with the metal oxide layer; a sixth step of forming a third insulating layer in the opening; and a seventh step of forming a conductive layer on the third insulating layer. The metal oxide layer contains indium.

[0026] In the method for manufacturing a semiconductor device, in the first step, the crystalline portion is preferably formed from one of the grains of the polycrystalline film.

[0027] In the above-described method for manufacturing a semiconductor device, the metal oxide layer is preferably formed by atomic layer deposition, and the substrate is preferably heated to a temperature of 100° C. or higher and 300° C. or lower.

[0028] In the above-described method for manufacturing a semiconductor device, the metal oxide layer is preferably formed by atomic layer deposition, and the substrate is preferably heated to a temperature of 150° C. or higher and 250° C. or lower.

[0029] One embodiment of the present invention is a method for manufacturing a semiconductor device, including a first step of forming a crystal portion on a first insulating layer, a second step of forming a crystalline metal oxide layer on the crystal portion, a third step of processing the metal oxide layer into an island shape, a fourth step of forming a second insulating layer to cover the metal oxide layer, a fifth step of forming an opening in the second insulating layer that overlaps the metal oxide layer, a sixth step of forming a third insulating layer in the opening, and a seventh step of forming a conductive layer on the third insulating layer. The metal oxide layer contains indium. Before the second step, the top surface of the first insulating layer is planarized by chemical mechanical polishing to have an average surface roughness of 0 nm or more and less than 3 nm.

[0030] In the above-described method for manufacturing a semiconductor device, the metal oxide layer is preferably subjected to lateral crystal growth in the second step and thereafter.

[0031] In the above-described method for manufacturing a semiconductor device, it is preferable that in the first step, a film to be the crystalline portion is formed, and the film is processed by wet etching to form the crystalline portion.

[0032] In the above-described method for manufacturing a semiconductor device, the crystal orientation of the crystal grains of the metal oxide layer is <111> It is preferable that:

[0033] In the above-described method for manufacturing a semiconductor device, the crystal orientation of the crystal portion is <001> It is preferable that:

[0034] In the method for manufacturing the semiconductor device, the crystal portion preferably contains indium, gallium, and zinc, and has a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereof, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition thereof.

[0035] In the above-described method for manufacturing a semiconductor device, the crystal orientation of the crystal grains in the metal oxide layer preferably coincides or substantially coincides with the crystal orientation of the crystal portion.

[0036] In the above-described method for manufacturing a semiconductor device, the crystal portion preferably contains indium.

[0037] One embodiment of the present invention is a metal oxide layer over an insulating layer, the metal oxide layer containing indium, the gallium concentration and the zinc concentration in the metal oxide layer being each 0.1 atomic % or less, the metal oxide layer having crystals with a cubic crystal structure, and the crystal orientation of the crystals with respect to a top surface of the insulating layer being <111> The average surface roughness of the upper surface of the insulating layer is equal to or greater than 0 nm and less than 3 nm. [Effects of the Invention]

[0038] According to one embodiment of the present invention, a metal oxide layer having high carrier mobility can be provided. According to one embodiment of the present invention, a novel metal oxide layer can be provided. According to one embodiment of the present invention, a transistor, a semiconductor device, a memory device, or a display device to which the metal oxide layer is applied can be provided.

[0039] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a transistor with small parasitic capacitance can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, memory device, or display device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device, memory device, or display device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided. According to one embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, memory device, or display device can be provided.

[0040] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims. [Brief explanation of the drawings]

[0041] [Figure 1] Figures 1(A) to 1(E) are perspective schematic views showing an example of a semiconductor device, and Figure 1(F) is a cross-sectional schematic view showing an example of a semiconductor device. [Figure 2] Fig. 2(A) is a cross-sectional view illustrating an indium oxide film, and Fig. 2(B) and Fig. 2(C) are diagrams illustrating the carrier concentration dependence of Hall mobility. [Figure 3] FIG. 3 is a diagram for explaining the carrier concentration dependence of the mobility of indium oxide, as disclosed in Non-Patent Document 2. [Figure 4] 4(A) to 4(E) are diagrams illustrating the crystal structure of metal oxides. [Figure 5] FIG. 5 is a diagram illustrating the crystallinity of metal oxides. [Figure 6] Figures 6(A), 6(C), 6(D), and 6(F) are perspective schematic views showing an example of a semiconductor device, and Figures 6(B) and 6(E) are cross-sectional schematic views showing an example of a semiconductor device. [Figure 7] FIG. 7 is a diagram illustrating the top surface shape of the layer. [Figure 8] 8(A) to 8(C) are schematic cross-sectional views showing an example of a semiconductor device. [Figure 9] Figures 9(A), 9(C), 9(E), and 9(G) are perspective schematic views showing an example of a method for manufacturing a semiconductor device, and Figures 9(B), 9(D), 9(F), and 9(H) are cross-sectional schematic views showing an example of a method for manufacturing a semiconductor device. [Figure 10] 10A and 10C are schematic perspective views illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 10B and 10D are schematic cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 11] Figures 11(A), 11(C), 11(E), and 11(G) are perspective schematic views showing an example of a method for manufacturing a semiconductor device, and Figures 11(B), 11(D), 11(F), and 11(H) are cross-sectional schematic views showing an example of a method for manufacturing a semiconductor device. [Figure 12] 12A to 12E and 12G are schematic perspective views illustrating an example of a method for manufacturing a semiconductor device, and Fig. 12F is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. [Figure 13] 13A to 13D are schematic perspective views showing an example of a method for manufacturing a semiconductor device. [Figure 14] 14(A), 14(B), and 14(D) are perspective schematic views showing an example of a method for manufacturing a semiconductor device, and Fig. 14(C) is a cross-sectional schematic view showing an example of a semiconductor device. [Figure 15] Fig. 15(A) is a plan view showing an example of a semiconductor device, and Fig. 15(B) to Fig. 15(D) are cross-sectional views showing an example of the semiconductor device. [Figure 16] Fig. 16(A) is a plan view showing an example of a semiconductor device, and Fig. 16(B) to Fig. 16(D) are cross-sectional views showing an example of the semiconductor device. [Figure 17] Fig. 17(A) is a plan view showing an example of a semiconductor device, and Fig. 17(B) to Fig. 17(D) are cross-sectional views showing an example of the semiconductor device. [Figure 18] FIG. 18 is a cross-sectional view showing an example of a semiconductor device. [Figure 19] 19A to 19C are cross-sectional views showing an example of a semiconductor device. [Figure 20] Fig. 20(A) is a plan view showing an example of a semiconductor device, and Fig. 20(B) to Fig. 20(D) are cross-sectional views showing an example of a semiconductor device. [Figure 21] Fig. 21(A) is a plan view showing an example of a semiconductor device, and Fig. 21(B) to Fig. 21(D) are cross-sectional views showing an example of a semiconductor device. [Figure 22] 22A to 22C are cross-sectional views showing an example of a semiconductor device. [Figure 23] Fig. 23(A) is a plan view showing an example of a semiconductor device, and Fig. 23(B) to Fig. 23(D) are cross-sectional views showing an example of a semiconductor device. [Figure 24] FIG. 24 is a cross-sectional view showing an example of a semiconductor device. [Figure 25] Fig. 25(A) is a plan view showing an example of a semiconductor device, and Fig. 25(B) to Fig. 25(D) are cross-sectional views showing an example of a semiconductor device. [Figure 26] Fig. 26(A) is a plan view showing an example of a semiconductor device, and Fig. 26(B) to Fig. 26(D) are cross-sectional views showing an example of a semiconductor device. [Figure 27] FIG. 27 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 28] 28A to 28G are diagrams illustrating examples of circuit configurations of memory cells. [Figure 29] FIG. 29 is a cross-sectional view showing an example of a semiconductor device. [Figure 30]30A and 30B are perspective views illustrating a configuration example of a semiconductor device. [Figure 31] FIG. 31 is a cross-sectional view showing an example of a semiconductor device. [Figure 32] FIG. 32 is a block diagram illustrating the CPU. [Figure 33] 33(A) and 33(B) are perspective views of the semiconductor device. [Figure 34] 34(A) and 34(B) are perspective views of the semiconductor device. [Figure 35] FIG. 35 is a conceptual diagram illustrating the hierarchy of a storage device. [Figure 36] 36(A) and 36(B) are perspective views showing an example of a display device. [Figure 37] FIG. 37 is a cross-sectional view showing an example of a display device. [Figure 38] FIG. 38 is a cross-sectional view showing an example of a display device. [Figure 39] 39(A) and 39(B) are diagrams showing an example of an electronic component. [Figure 40] Figures 40(A) to 40(C) are diagrams showing an example of a mainframe computer. Figure 40(D) ​​is a diagram showing an example of space equipment. Figure 40(E) is a diagram showing an example of a storage system applicable to a data center. [Figure 41] 41(A) to 41(F) are diagrams showing examples of electronic devices. [Figure 42] 42(A) to 42(G) are diagrams showing examples of electronic devices. [Figure 43] 43(A) to 43(F) are diagrams showing examples of electronic devices. [Figure 44] FIG. 44 shows the results of AFM measurement according to the example. DETAILED DESCRIPTION OF THE INVENTION

[0042] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0043] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0044] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0045] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking). Furthermore, the ordinal numbers attached to components in one part of this specification may not match the ordinal numbers attached to the same components in other parts of this specification or in the claims.

[0046] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an IGFET (Insulated Gate Field Effect Transistor) and a TFT (Thin Film Transistor).

[0047] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0048] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0049] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0050] In this specification and the like, the term "content" refers to the proportion of a component contained in a film. For example, when an oxide semiconductor layer contains metal elements X, Y, and Z, and the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is A, the number of atoms of each of the metal elements X, Y, and Z is A. X , A Y , A Z When the content of metal element X is X / (A X +A Y +A Z ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: X :B Y :B Z When the content of the metal element X is expressed as B X / (B X +B Y +B Z ) can be shown as

[0051] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0052] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0053] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0054] In this specification, the term "electrical connection" does not include cases where two nodes are connected via an insulator such as a dielectric of a capacitive element, a gate insulating film of a transistor, or an interlayer insulating film.

[0055] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0056] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0057] In this specification and the like, a cubic crystal structure may be referred to as a cubic crystal, a cubic crystal structure, etc. The same applies to other crystal systems (hexagonal, trigonal, tetragonal, orthorhombic, monoclinic, and triclinic).

[0058] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1A to 14D. The semiconductor device of one embodiment of the present invention includes a transistor having a semiconductor layer.

[0059] <Configuration of semiconductor device> 1(A) to 1(E) are perspective schematic diagrams of a semiconductor device. In FIG. 1(A), only the outlines of some components (insulating layers, etc.) are indicated by dotted lines. FIG. 1(B) is a perspective schematic diagram of a portion of FIG. 1(A) cut along a YZ plane including a dashed-dotted line. FIG. 1(C) is a perspective schematic diagram of a portion of FIG. 1(A) cut along an XZ plane including a dashed-two-dot line. In FIGS. 1(A) to 1(C), the X, Y, and Z directions are indicated by arrows. Although the same X, Y, and Z symbols are used in FIGS. 1(A) to 1(C), the directions do not necessarily have to match. In subsequent drawings, the X, Y, and Z directions do not necessarily have to match between the drawings.

[0060] 1A to 1C includes a substrate 10, an insulating layer 20 over the substrate 10, a semiconductor layer 30 over the insulating layer 20, an insulating layer 50 over the semiconductor layer 30, and a conductive layer 60 over the insulating layer 50. The semiconductor device also includes an insulating layer 80. Note that the semiconductor device of one embodiment of the present invention may include a layer 29.

[0061] 1(D) shows the substrate 10, insulating layer 20, layer 29, and semiconductor layer 30, which are components of the semiconductor device. FIG. 1(E) shows the substrate 10, insulating layer 20, and layer 29, which are components of the semiconductor device. FIG. 1(F) is a cross-sectional view of a portion of FIG. 1(A) taken along the YZ plane including the dashed dotted line. As shown in FIG. 1(F), the insulating layer 80 has an opening 89.

[0062] In the transistor according to one embodiment of the present invention, the conductive layer 60 functions as a gate electrode, and the insulating layer 50 functions as a gate insulating layer. The semiconductor layer 30 has a channel formation region. At least a part of a region of the semiconductor layer that overlaps with the conductive layer 60 with the insulating layer 50 interposed therebetween functions as the channel formation region.

[0063] A transistor according to one embodiment of the present invention includes a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor in a semiconductor layer 30 including a channel formation region. That is, the transistor can be referred to as an OS transistor. Note that in this specification and the like, a semiconductor layer including an oxide semiconductor can be referred to as an oxide semiconductor layer. Furthermore, since the semiconductor layer 30 includes a metal oxide, the semiconductor layer 30 can be referred to as a metal oxide layer.

[0064] An OS transistor is a transistor in which oxygen vacancies (V O The presence of oxygen vacancies and impurities may cause fluctuations in electrical characteristics and reduce reliability. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region is made i-type (intrinsic) or substantially i-type.

[0065] Furthermore, when an excessive amount of oxygen is supplied to the semiconductor layer 30, electron traps due to the excess oxygen are formed in the insulating layer 50. This makes the OS transistor more susceptible to positive drift degradation in a +GBT (Positive Gate Bias-Temperature) stress test. In other words, the amount of positive drift degradation in the +GBT stress test increases.

[0066] Therefore, in the semiconductor device of one embodiment of the present invention, the impurity concentration in the semiconductor layer 30 is preferably low. Also, an appropriate amount of oxygen is preferably supplied to the semiconductor layer 30. Also, it is preferable to reduce the amount of excess oxygen in the semiconductor layer 30.

[0067] The semiconductor layer 30 is preferably made of indium oxide. In this case, the semiconductor layer 30 contains indium and oxygen. The higher the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the higher the field-effect mobility of the transistor. Therefore, by using indium oxide for the semiconductor layer 30, the transistor can achieve a large on-state current and high frequency characteristics.

[0068] Furthermore, the indium oxide film preferably has crystallinity. For example, the indium oxide film preferably has crystal grains. Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains. A polycrystalline film is composed of two or more crystal grains, whereas a single-crystal film can be considered to be composed of one crystal grain. While crystal grain boundaries are observed in polycrystalline films, crystal grain boundaries are not observed in single-crystal films.

[0069] Unlike polycrystalline films, grain boundaries are not observed in the channel formation region of single-crystal films. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow are likely to segregate at grain boundaries. Therefore, when grain boundaries are present in the channel formation region, variations in transistor characteristics become significant. On the other hand, since grain boundaries are not observed in the channel formation region of a single-crystal film according to one embodiment of the present invention, the single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0070] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Alternatively, a semiconductor layer in which at least one crystal orientation is oriented in one direction in the channel formation region can be called a single crystal film.

[0071] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer and is located between the region in contact with the source electrode and the region in contact with the drain electrode. A semiconductor layer in which no crystal grain boundaries are observed in the region in contact with the source electrode and the region in contact with the drain electrode, a semiconductor layer in which the region in contact with the source electrode and the region in contact with the drain electrode is included in a single crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions located between the region in contact with the source electrode and the region in contact with the drain electrode can also be called a single crystal film. Alternatively, a semiconductor layer in which at least one crystal orientation is oriented in one direction in the region between the region in contact with the source electrode and the region in contact with the drain electrode can also be called a single crystal film.

[0072] In the channel formation region, the current path is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientations, etc. in the channel formation region or in the region between the region in contact with the source electrode and the region in contact with the drain electrode can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0073] The crystallinity of the semiconductor layer 30 can be analyzed by, for example, X-ray diffractometry (XRD), transmission electron microscopy (TEM), or electron diffraction (ED), or a combination of these techniques may be used for analysis.

[0074] Crystal grains can be confirmed, for example, in a high-resolution transmission electron microscope (TEM) image. Crystal grain boundaries can sometimes be confirmed, for example, in a high-resolution TEM image. That is, crystal grains and crystal grain boundaries can sometimes be observed in a high-resolution TEM image of a crystalline film. The total magnification for acquiring a TEM image is preferably 2,000,000 times or more, and more preferably 4,000,000 times or more.

[0075] The indium oxide film is preferably a single crystal. Since a single crystal does not have grain boundaries, carrier scattering at the grain boundaries can be suppressed, resulting in a transistor with high field-effect mobility and high reliability.

[0076] The indium oxide film may be polycrystalline or amorphous containing crystal grains. In this case, it is preferable that no crystal grain boundaries are observed in the channel formation region or that the grain boundary components are small. For example, by locating one crystal grain in the channel formation region, it is possible to achieve a structure in which no crystal grain boundaries are observed in the channel formation region. Even in such a structure, the same effects as in a structure in which the indium oxide film is single crystal can be achieved.

[0077] Two or more crystal grains may be located in the channel formation region. For example, when first and second crystal grains are located in the channel formation region, it is preferable that the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide. When the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide, a crystal grain boundary may not be observed at the boundary between the first and second crystal grains. When the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide, the formation of a crystal grain boundary between the first and second crystal grains can be suppressed. Therefore, even in this configuration, the same effect as in a configuration in which the indium oxide film is single crystal can be achieved. Note that the coincidence or substantially coincidence of the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain may be confirmed, for example, by a high-resolution TEM image. Specifically, in a high-resolution TEM image, it can be confirmed that the lattice fringes of the first crystal grains and the lattice fringes of the second crystal grains are continuously connected at the boundary between the first crystal grains and the second crystal grains.

[0078] In this specification, the term "grain boundary" refers to, for example, a boundary between adjacent crystal grains with different crystal orientations. Therefore, in this specification, the term "grain boundary" does not include a boundary between adjacent crystal grains with the same crystal orientation. For example, even if a boundary between two crystal grains is observed in a high-resolution TEM image, if the crystal orientations of the two crystal grains are the same or nearly the same, the boundary may not be called a grain boundary.

[0079] The crystal orientation can be evaluated from a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). It can also be evaluated from a pattern (also called an FFT pattern) obtained by performing fast Fourier transform (FFT) processing on a TEM image. The FFT pattern reflects the same reciprocal lattice space information as the diffraction pattern.

[0080] For example, when the difference in angle between the FFT patterns of the first and second crystal grains is between -5 and 5 degrees, preferably between -3 and 3 degrees, and more preferably between -2 and 2 degrees, the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain can be said to match or approximately match. Note that, for example, the angle of the FFT pattern in the

[0111] orientation refers to the acute angle formed by the approximation line between the spot resulting from the (222) plane or the spot resulting from the (-2-2-2) plane and the central spot, and a reference line (for example, a line extending in the vertical direction).

[0081] The degree of polycrystallinity of an indium oxide film can be evaluated by the grain size of the crystal grains. The grain size can be calculated, for example, by calculating the area of ​​the crystal grain and assuming a perfect circle corresponding to the calculated area as the diameter of the circle. The diameter in this case is sometimes called the area-equivalent diameter or the like.

[0082] The degree of polycrystallinity of an indium oxide film can also be evaluated by the extension length of the grain boundaries. The extension length of the grain boundaries can be calculated, for example, by extracting a field of view of a specific area from a TEM image of the film acquired at a total magnification at which the grain boundaries can be observed, and calculating the total length of the grain boundaries observed in that field of view. An indium oxide film with a grain boundary extension length of 0 nm can be considered to be single crystalline. Furthermore, the longer the extension length of the grain boundaries, the more grain boundary components there are.

[0083] The grain boundary extension length in the indium oxide film is preferably 0 nm or more and 1500 nm or less, more preferably 0 nm or more and 1000 nm or less, and even more preferably 0 nm or more and 800 nm or less. By having the indium oxide film with a grain boundary extension length in the above range in the semiconductor layer 30, a configuration in which no crystal grain boundaries are observed or the grain boundary components are small can be realized in the channel formation region. Note that, unless otherwise specified in this specification, the area of ​​the field of view used to calculate the grain boundary extension length is 90 nm square.

[0084] The thickness of the semiconductor layer 30 is preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, even more preferably 2.5 nm to 20 nm, even more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. The semiconductor layer 30 may have at least a portion with a thickness as described above. For example, the channel formation region of the semiconductor layer 30 may have a thickness as described above. Increasing the thickness of the semiconductor layer 30 increases the on-current of the transistor. On the other hand, if the thickness of the semiconductor layer 30 is too thick, the grain boundary extension length increases, which may result in a decrease in the on-current of the transistor due to carrier scattering at the grain boundary. Furthermore, reducing the thickness of the semiconductor layer 30 prevents a decrease in the threshold voltage, enabling a normally-off transistor. On the other hand, if the thickness of the semiconductor layer 30 is too thin, the crystallinity of the semiconductor layer 30 may vary across the substrate, resulting in variations in the electrical characteristics of the transistor. Therefore, by setting the film thickness of the semiconductor layer 30 within the above range, it is possible to improve the crystallinity of the semiconductor layer 30. By improving the crystallinity of the semiconductor layer 30, the semiconductor layer 30 can have crystal grains.

[0085] When a metal oxide contains indium and zinc, the metal oxide may have a c-axis aligned crystalline (CAAC) structure. The CAAC structure has fewer grain boundaries in the ab plane than a polycrystalline structure. Examples of metal oxides containing indium and zinc include indium zinc oxide (In-Zn oxide, also known as IZO (registered trademark)) and indium gallium zinc oxide (In-Ga-Zn oxide, also known as IGZO).

[0086] Among crystalline oxide semiconductor layers, an indium oxide film is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO film. Therefore, it can be said that an indium oxide film is a film through which one or both of hydrogen and oxygen are more easily supplied and from which one or both of hydrogen and oxygen are more easily discharged than, for example, an IGZO film. It can be said that an indium oxide film is a film that is more permeable to one or both of hydrogen and oxygen than, for example, an IGZO film. In other words, it can be said that an indium oxide film is a film that has a lower barrier property against one or both of hydrogen and oxygen than, for example, an IGZO film.

[0087] Indium oxide films are formed by heat treatment at a heating temperature of 400°C for 8 hours, with oxygen concentration of 1×10 20 atoms / cm 3 Over 2×10 21 atoms / cm 3 Less than or equal to 2 x 10 20 atoms / cm 3 More than 1×10 21 atoms / cm 3 Furthermore, the indium oxide film can transmit, for example, 1×10 20 atoms / cm 3 Over 2×10 21 atoms / cm 3 Less than or equal to 2 x 10 20 atoms / cm 3 More than 1×10 21 atoms / cm 3 It is preferable that the following oxygen has the property of diffusing within the crystal grains.

[0088] Oxygen in the indium oxide film diffuses through the grains and grain boundaries, and V present in the grains or grain boundaries O Therefore, the electrical characteristics and reliability of the transistor can be improved.

[0089] The permeability of the membrane to oxygen and hydrogen can be evaluated by calculation using a method called Nudged Elastic Band (NEB). Specifically, the permeability can be evaluated by calculating the migration barrier of oxygen and hydrogen atoms using the NEB method. The smaller the migration barrier value, the easier it is for the atoms to move (permeate).

[0090] An example of the calculation results is shown in Table 1. In2O3 shown in Table 1 is a crystal model of indium oxide, and IGZO shown in Table 1 is a crystal model of In-Ga-Zn oxide. Note that excess oxygen shown in Table 1 refers to oxygen that is not located at the oxygen site of the crystal lattice, or oxygen that is located between the lattice.

[0091] [Table 1]

[0092] From Table 1, it can be seen that the barriers to the movement of oxygen, hydrogen, and excess oxygen are large in the In-Ga-Zn oxide crystal model, but small in the indium oxide crystal model. This suggests that oxygen and hydrogen move more easily (permeate more easily) in indium oxide than in In-Ga-Zn oxide. It also suggests that the indium oxide film has higher permeability to oxygen atoms and hydrogen atoms than the In-Ga-Zn oxide film. Therefore, it is presumed that the indium oxide film is a film into which hydrogen and oxygen are easily supplied and from which hydrogen and oxygen are easily discharged. Furthermore, the V that occurred in the +GBT test O It is expected that this will have the effect of filling the gap with oxygen, thereby enabling the realization of highly reliable transistors.

[0093] As a result, as shown in Figure 2(A), an indium oxide film (InO X Oxygen (O) that diffuses into the indium oxide film passes through the indium oxide film and is released as oxygen molecules (O2). It may also react with hydrogen contained in the film and be released as water molecules (H2O). In addition, oxygen vacancies (V O) is present, the diffusing oxygen atoms compensate for the oxygen vacancies. Since oxygen diffuses easily into an indium oxide film, it can be said that oxygen vacancies are more easily compensated for in comparison with an IGZO film. In this way, an indium oxide film is easier to reduce oxygen vacancies in the film than an IGZO film, and by applying such an indium oxide film to a transistor, it is possible to realize a transistor that exhibits extremely high reliability.

[0094] Furthermore, as shown in Figure 2(A), the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and is released as hydrogen molecules (H2). Alternatively, as mentioned above, hydrogen reacts with oxygen contained in the film and is released as water molecules.

[0095] The content of the first element in the semiconductor layer 30 is preferably low. The concentration of the first element in the semiconductor layer 30 is also preferably low. In particular, the concentration of the first element in the channel formation region is preferably low. Here, the first element is at least one of boron, carbon, aluminum, silicon, zinc, and gallium. That is, in the semiconductor layer 30, the concentration of any one of boron, carbon, aluminum, silicon, zinc, and gallium is preferably low, the concentrations of two selected from boron, carbon, aluminum, silicon, zinc, and gallium are more preferably low, and the concentrations of all of boron, carbon, aluminum, silicon, zinc, and gallium are even more preferably low. The concentration of the first element in the semiconductor layer 30 is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less. The preferred concentration of the first element in the semiconductor layer 30 can also be said to be the preferred concentration of the first element in the channel formation region.

[0096] Furthermore, as will be described later, by using a precursor that has been distilled one or more times, it is possible to set the concentration of the first element in the semiconductor layer 30 to 0.01 atomic % (100 ppm) or less, 0.0001% (1 ppm) or less, 0.00001% (0.1 ppm or 100 ppb) or less, or 0.0000001% (0.001 ppm or 1 ppb) or less. In other words, the content (purity) of indium excluding oxygen in the semiconductor layer 30 can be set to 99.99 atomic % or more (4N), 99.9999 atomic % or more (6N), 99.99999 atomic % or more (7N), or 99.9999999 atomic % or more (9N), which may enable the formation of a semiconductor layer 30 having a purity comparable to the purity (10N) of silicon used in the semiconductor layer.

[0097] By reducing the concentrations of boron, carbon, aluminum, and silicon in the semiconductor layer 30, the crystallinity of the semiconductor layer 30 can be improved.

[0098] When the semiconductor layer 30 contains gallium atoms, the gallium atoms bond with excess oxygen atoms to form a Ga-O structure. The Ga-O structure functions as an acceptor that traps electrons. Therefore, a transistor having a semiconductor layer 30 containing gallium atoms and excess oxygen atoms exhibits a large variation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, by lowering the gallium concentration in the semiconductor layer 30, the variation in threshold voltage in the PBTS test can be reduced. This results in a transistor with high reliability when a positive bias is applied. Note that the same phenomenon as when the semiconductor layer 30 contains gallium atoms can occur when the semiconductor layer 30 contains zinc atoms.

[0099] Furthermore, aluminum atoms, gallium atoms, and zinc atoms have stronger bonding strength with oxygen atoms than indium atoms, so that by reducing the concentrations of aluminum, gallium, and zinc in the indium oxide film, it is possible to prevent the oxygen permeability from decreasing.

[0100] Furthermore, impurities such as the first element contained in the indium oxide film can become crystal nuclei. Reducing the impurities in the indium oxide film as much as possible reduces the number of crystal nuclei, which can promote the growth of large crystal grains, as described below.

[0101] Furthermore, when the indium oxide film is a polycrystalline film, the first element segregates at the grain boundaries, forming an oxide containing the first element. Because the oxide has insulating properties, it may cause a decrease in the on-state current or field-effect mobility of the transistor. By reducing the first element in the indium oxide film as much as possible, the on-state current or field-effect mobility of the transistor can be increased.

[0102] Furthermore, by reducing the impurities in the indium oxide film, it is possible to suppress impurity scattering. Therefore, a transistor with high field-effect mobility can be realized. For example, by setting the concentration of the first element in the semiconductor layer 30 within the above-mentioned preferable range, the field-effect mobility of the transistor can be increased to 100 cm 2 / (V·s) or more, preferably 150 cm 2 / (V·s) or more, preferably 200 cm 2 / (V·s) or more, more preferably 250 cm 2 / (V·s) or more.

[0103] In addition, in Non-Patent Document 2, the upper limit of the Hall mobility calculated assuming that the main causes of scattering in indium oxide are ionized impurities and polar optical phonons is 270 cm 2 / (V·s) (see Figure 3).

[0104] Here, we will explain the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO. Figure 2(B) shows the carrier concentration dependence of the hole mobility of silicon (Si) and indium oxide (InO X ), and Figure 2(C) is a schematic diagram of the carrier concentration dependence of the hole mobility for IGZO.

[0105] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as indicated by the arrows in Figure 2(C). On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as indicated by the arrows in Figure 2(B) (see Non-Patent Document 3). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is, and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties closer to silicon. Note that the characteristics of indium oxide shown in Figure 2(B) are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 2(B).

[0106] In Figure 2B, the low carrier concentration range R1 has extremely high hole mobility, and is therefore suitable for the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is the range where the carrier concentration is 1 × 10 15 cm -3 The range includes, for example, 1×10 14 cm -3 That's it, 1 x 10 18 cm -3 By sufficiently reducing the carrier concentration, the Hall mobility can be reduced to 270 cm 2 It is expected that the efficiency can be increased to about / (V·s).

[0107] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0108] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. 20 cm -3 The range includes, for example, 1×10 19 cm -3 That's it, 1 x 10 22 cm -3 By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 -4 It is expected that the resistance can be reduced to Ω·cm or less.

[0109] In the indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, tantalum, tungsten, molybdenum, tin, silicon, germanium, zirconium, hafnium, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0110] In this way, indium oxide, a region with a low carrier concentration is used as a channel formation region of a transistor, and a region with a high carrier concentration is used as a source region and a drain region of the transistor. That is, indium oxide can be said to be an oxide capable of valence electron control. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that is not usually conceived. By using this technical concept, a transistor that has high mobility, low off-current, and is capable of normally off operation can be realized.

[0111] The concentration of the first element can be evaluated using, for example, inductively coupled plasma-mass spectrometry (ICP-MS), XPS, secondary ion mass spectrometry (SIMS), time-of-flight secondary ion mass spectrometry (ToF-SIMS), Auger electron spectroscopy (AES), energy dispersive X-ray spectroscopy (EDX), inductively coupled plasma-atomic emission spectroscopy (ICP-AES), or the like.

[0112] Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, which may cause oxygen vacancies. This may result in fluctuations in electrical characteristics and reduced reliability. On the other hand, hydrogen present at the grain boundaries may terminate dangling bonds present at the grain boundaries, improving the electrical characteristics and reliability of the transistor. Therefore, it is preferable that the hydrogen concentration in the indium oxide film be reduced, but it may be higher than the concentration of the first element in some cases.

[0113] The band gap of indium oxide is greater than or equal to 2.5 eV and less than or equal to 3.7 eV. By using indium oxide, which has a wider band gap than silicon, for the semiconductor layer 30, the off-state current of the transistor can be reduced, and the power consumption of the semiconductor device can be sufficiently reduced.

[0114] An OS transistor is an accumulation-mode transistor that uses electrons as the majority carriers. That is, the carriers in an OS transistor are electrons. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility (carrier mobility). In other words, by using a metal oxide with a small effective mass of electrons in the semiconductor layer of a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0115] Here, the effective masses of single crystal indium oxide (here, In2O3) and single crystal silicon (Si) are shown in Table 2. The effective masses of electrons and holes shown in Table 2 are values ​​calculated by first-principles electronic structure calculations.

[0116] [Table 2]

[0117] As shown in Table 2, the effective mass of electrons in indium oxide is small. Therefore, by using indium oxide, which has a small effective mass of electrons, for the semiconductor layer 30, it is possible to realize a transistor with a large on-state current, a transistor with high field-effect mobility, and a transistor with high frequency characteristics (also called f characteristics). Indium oxide also has the characteristic that its effective mass of electrons is almost independent of the crystal orientation. Furthermore, the effective mass of electrons in indium oxide is smaller than the effective mass of electrons in, for example, silicon. Therefore, from the perspective of effective electron mass, the f characteristics of a transistor using indium oxide in the channel formation region are higher than the f characteristics of a Si transistor.

[0118] As shown in Table 2, the effective mass of holes in indium oxide is large. Therefore, by using indium oxide, which has a large effective mass of holes, for the semiconductor layer 30, a transistor with an extremely small off-state current can be realized. Furthermore, the effective mass of holes in indium oxide is larger than the effective mass of holes in, for example, silicon. Therefore, in terms of the effective mass of holes, the off-state current of a transistor using indium oxide for a channel formation region is sufficiently smaller than the off-state current of a Si transistor.

[0119] In a transistor using indium oxide for the semiconductor layer 30, the off-state current value per 1 μm of channel width at room temperature (25° C.) is 1 aA (1×10 -18 A) or less, or 1zA (1 x 10 -21 A) or less. In addition, the off-state current value at 85°C per 1 μm of channel width can be reduced to 1×10 -16 A / μm or less, preferably 1×10 -17 A / μm or less, preferably 1×10 -18 It is possible to reduce the off-state current per 1 μm of channel width at 125°C to 1 fA (1 × 10 -15 A) or less, or 1aA (1 × 10 -18 A) It is possible to do the following:

[0120] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. For example, the cutoff frequency (fT) of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be increased to 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher at room temperature (25°C).

[0121] The indium oxide film may contain one or more metal elements having a large period number in the periodic table, provided that the film has crystallinity. The greater the overlap of the orbitals of the metal elements, the greater the carrier conduction tends to be. Therefore, by including a metal element having a large period number in the periodic table, the field-effect mobility of the transistor may be improved. Examples of metal elements having a large period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, and light rare earth elements (lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium).

[0122] FIG. 1A shows an example in which the semiconductor layer 30 has a single-layer structure. The semiconductor layer 30 can have a stacked structure of two or more layers. For example, when the semiconductor layer 30 has a two-layer structure consisting of a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, it is preferable to use a metal oxide (typically indium oxide) applicable to the semiconductor layer 30 described above as the first semiconductor layer, and a metal oxide whose conduction band minimum is located closer to the vacuum level than the conduction band minimum of the first semiconductor layer as the second semiconductor layer. In this case, the first semiconductor layer can mainly function as a current path (channel). That is, the first semiconductor layer has a channel formation region on the surface on the second semiconductor layer side and in the vicinity thereof.

[0123] The above-described configuration can reduce carriers trapped at the interface of the first semiconductor layer and its vicinity. Also, the channel can be located away from the surface of the insulating layer 50, reducing the influence of surface scattering. This can increase the field-effect mobility of the transistor.

[0124] Examples of metal oxides that can be used for the second semiconductor layer include indium gallium oxide (In-Ga oxide), In-Zn oxide, indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), In-Ga-Zn oxide, indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), and indium tin oxide containing silicon oxide (ITSO). Alternatively, zinc oxide, aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), and aluminum tin oxide (Al-Sn oxide) can be used.

[0125] The In-Zn oxide used in the second semiconductor layer can have a composition of In:Zn=1:1 (atomic ratio) or thereabouts, In:Zn=2:1 (atomic ratio) or thereabouts, or In:Zn=4:1 (atomic ratio) or thereabouts. The IGZO used in the second semiconductor layer can have a composition of In:Ga:Zn=1:1:1 (atomic ratio) or thereabouts, In:Ga:Zn=1:3:2 (atomic ratio) or thereabouts, or In:Ga:Zn=1:3:4 (atomic ratio) or thereabouts. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio.

[0126] The crystallinity of the metal oxide contained in the second semiconductor layer is not particularly limited. For example, the second semiconductor layer may contain one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part).

[0127] 1(E) and 1(F), an island-shaped layer 29 is provided in contact with the upper surface of the insulating layer 20, and a semiconductor layer 30 is provided to cover the layer 29. In FIG.

[0128] The layer 29 has crystals. The layer 29 functions as a seed or nucleus when a process for increasing the crystallinity of the semiconductor layer 30 is performed. In other words, the layer 29 functions as a seed or nucleus when the semiconductor layer 30 grows crystals. In this specification and the like, the layer 29 or the crystals contained in the layer 29 can be referred to as a seed crystal or a crystal nucleus. Furthermore, since the layer 29 has crystals, the layer 29 can be referred to as a crystalline portion.

[0129] The crystal structure of indium oxide is cubic (bixbyite type). When indium oxide is used for the semiconductor layer 30, the layer 29 preferably has, for example, a hexagonal or trigonal crystal. In this case, the crystal orientation of the layer 29 relative to the surface of the layer 29 or the surface on which it is formed is preferably 1 / 2 . <001> By having a crystal with a crystal orientation of <111> The semiconductor layer 30 can be formed having a crystallinity of the order of 1 / 2. <001> In this case, the c-axis of the crystal is perpendicular or approximately perpendicular to the surface of layer 29 or the surface on which it is formed. Note that hexagonal or trigonal crystals can sometimes be referred to as crystals with a layered structure, and therefore the above structure can be considered as a structure in which semiconductor layer 30 having cubic crystals is formed on layer 29 having crystals with a layered structure. In other words, it can also be considered as a layered structure produced using heteroepitaxial growth technology or a technology similar to heteroepitaxial growth.

[0130] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the number; however, in this specification, due to formatting constraints, numbers may be expressed by adding a minus sign (-) before them instead of adding a bar above them. Individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0131] In this specification and the like, the crystal orientation of a crystal refers to the orientation relative to the surface of the substrate. <100> A crystal having a (100) plane parallel to the surface of the substrate can be said to have such a crystal orientation. However, this is not limited to the above, and the crystal orientation of the crystal can also be said to be the orientation relative to the surface of the insulating layer 20 or the surface on which the insulating layer 20 is formed.

[0132] Specific examples of materials that can be used for layer 29 include zinc oxide, In-Ga oxide, gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), In-Al-Zn oxide, In-Ga-Zn oxide, and In-Sn-Zn oxide. Layer 29 is preferably made of In-Ga-Zn oxide. In this case, layer 29 contains indium, gallium, zinc, and oxygen. Specifically, the composition is preferably In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, or In:Ga:Zn=1:3:2 [atomic ratio] or a composition close thereto. Metal oxides with these compositions are suitable for layer 29 because they readily form a layered structure.

[0133] In-Ga-Zn oxide and In-Sn-Zn oxide, etc., tend to have a CAAC structure. When an oxide having a CAAC structure is used for the layer 29, the c-axis of the crystals of the layer 29 is perpendicular or approximately perpendicular to the surface of the layer 29 or the surface on which the layer 29 is formed. In other words, the crystal orientation of the crystals of the layer 29 with respect to the surface of the layer 29 or the surface on which the layer 29 is formed is <001> Therefore, by using an oxide that easily has a CAAC structure for the layer 29, it is possible to improve the controllability of the crystal orientation of the crystal nuclei.

[0134] Here, the crystal structure of metal oxides is shown in Figures 4(A) to 4(E). Figure 4(A) shows the crystal structure of an In-Ga-Zn oxide with a composition of In:Ga:Zn = 1:1:1 [atomic ratio], viewed from a direction perpendicular to the c-axis. Figure 4(B) shows the plane indicated by the dashed line in Figure 4(A) viewed from the c-axis direction. Figure 4(C) shows the plane indicated by the dashed line in Figure 4(A) viewed from the c-axis direction. Figure 4(D) shows the plane indicated by the two-dot chain line in Figure 4(A) viewed from the c-axis direction. Mx in Figures 4(A), 4(C), and 4(D) represents Ga atoms or Zn atoms. Note that in Figure 4(A), the plane indicated by the dashed line, the plane indicated by the one-dot chain line, and the plane indicated by the two-dot chain line are sometimes collectively referred to as c-planes. FIG. 4(E) is a diagram showing the crystal structure of indium oxide as viewed from a direction perpendicular to the (111) plane.

[0135] The distance between metal atoms on the c-plane (arrows shown in each of Figures 4(B) to 4(D)) is said to be 0.330 nm. The In-In distance on the (111) plane (arrows shown in Figure 4(E)) is said to be 0.334 nm and 0.385 nm. This indicates that the arrangement of metal atoms is similar between the c-plane of the CAAC structure and the (111) plane of indium oxide. Therefore, oxides that readily form a CAAC structure can be suitably used for layer 29.

[0136] When an oxide that easily has a CAAC structure is used for the layer 29, the crystal orientation <111> 5 shows a cross-sectional view of the layer 29 and the insulating layer 20 and semiconductor layer 30 in the vicinity thereof. In FIG. 5, the crystal structure of the semiconductor layer 30 is <111> The direction of the crystal grains in the semiconductor layer 30 is indicated by arrows. <111> The orientation tends to be perpendicular or nearly perpendicular to the substrate surface (not shown) above layer 29, near the side of layer 29, and at a position distant from layer 29. This is different from the CAAC structure in which the c-axis of the crystal is perpendicular or nearly perpendicular to the surface on which semiconductor layer 30 is formed or the surface.

[0137] Layer 29 can also be made of an oxide with a cubic crystal structure. Having the same crystal structure as semiconductor layer 30 allows epitaxial growth of semiconductor layer 30 using layer 29 as a seed or nucleus, thereby improving the crystallinity of semiconductor layer 30. Note that oxides containing Group 3 elements in the periodic table tend to have a cubic crystal structure. Furthermore, Group 3 elements in the crystals are primarily present as trivalent cations. Therefore, layer 29 preferably contains at least one element capable of becoming a trivalent cation. The element capable of becoming a trivalent cation contained in layer 29 is preferably scandium, yttrium, cerium, gadolinium, erbium, ytterbium, or the like.

[0138] For example, an oxide containing one or both of yttrium and zirconium, erbium oxide, etc. can be used for the layer 29. Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, and yttrium zirconium oxide.

[0139] It is also preferable that the difference (also referred to as lattice mismatch) between the lattice constant or the length of the unit lattice vector of the crystal nucleus and the lattice constant or the length of the unit lattice vector of the crystal of the semiconductor layer 30 is small. By using an oxide that reduces the lattice mismatch for the layer 29, the crystallinity of the semiconductor layer 30 can be improved.

[0140] One method for evaluating the degree of lattice mismatch is to use the lattice mismatch value shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, an indium oxide film) with respect to the crystals of the formed film is calculated using the following formula (1). Hereinafter, the lattice mismatch Δa of the crystals of the formed film with respect to the crystals of the formed film may be simply referred to as the lattice mismatch Δa of the formed film with respect to the formed film.

[0141]

number

[0142] In formula (1), L1 is the lattice constant or the length of the unit lattice vector of the crystal of the formed film, and L2 is the lattice constant or the length of the unit lattice vector of the crystal of the formed film.

[0143] The lattice mismatch Δa of the crystal grains in the semiconductor layer 30 with respect to the crystal nuclei is preferably −10% to 10%, more preferably −5% to 5%, and even more preferably −3% to 3%. By using a material for layer 29 that reduces the lattice mismatch with the semiconductor layer 30, the crystallinity of the semiconductor layer 30 can be improved.

[0144] For example, the lattice constant of indium oxide crystal (bixbyite type) is said to be 1.01194 nm. Furthermore, the lattice constant of yttrium oxide crystal (bixbyite type) is said to be 1.05976 nm. Therefore, the lattice mismatch of indium oxide crystal with yttrium oxide crystal is −4.5%. Therefore, when indium oxide is used for semiconductor layer 30, yttrium oxide can be used for layer 29.

[0145] For example, the lattice constant of erbium oxide crystal (bixbyite type) is said to be 1.0582 nm. Therefore, the lattice mismatch of indium oxide crystal with erbium oxide crystal is -4.4%. Therefore, when indium oxide is used for semiconductor layer 30, erbium oxide can be used for layer 29.

[0146] For example, Zr is an example of yttrium zirconium oxide. 0.9 Y 0.1 O 1.95 The lattice constant of the crystal (fluorite type) is 0.51481 nm (see ICSD coll.code.248790). 0.9 Y 0.1 O 1.95The lattice mismatch of indium oxide crystal with indium oxide crystal is −1.7%. Therefore, when indium oxide is used for the semiconductor layer 30, yttrium zirconium oxide can be suitably used for the layer 29. Note that yttrium zirconium oxide contains yttrium, zirconium, and oxygen.

[0147] Adding yttrium or yttrium oxide to zirconium oxide, i.e., increasing the yttrium content in yttrium zirconium oxide to greater than 0 atomic%, can stabilize the crystalline structure of zirconium oxide. However, if the content is too high, the crystalline structure of yttrium zirconium oxide may change from a cubic system to another system, so it is preferable that the content is not too high. Therefore, for example, the yttrium content in yttrium zirconium oxide is preferably 2 atomic% or more and 15 atomic% or less, and more preferably 5 atomic% or more and 10 atomic% or less.

[0148] Alternatively, indium oxide may be used for the layer 29. By using indium oxide for the layer 29, the semiconductor layer 30 can be homoepitaxially grown using the layer 29 as a seed or nucleus, thereby improving the crystallinity of the semiconductor layer 30. In this case, the crystal orientation of the crystals in the layer 29 and the crystal orientation of the crystals in the semiconductor layer 30 coincide or substantially coincide.

[0149] There are no particular limitations on the material that can be used for layer 29. Layer 29 may be made of an insulating material, a semiconductor material, or a conductive material. When layer 29 is made of a semiconductor material, layer 29 may be considered as part of semiconductor layer 30.

[0150] FIG. 1(E) shows an example in which layer 29 is circular in plan view. However, the present invention is not limited to this. In plan view, layer 29 can be, for example, a circle or a substantially circular shape such as an oval, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, a star-shaped polygon, or any of these polygons with rounded corners. Furthermore, when sputtered particles are used for layer 29, layer 29 may be triangular or hexagonal in plan view.

[0151] 6(A) and 6(B), the layer 29 may have a tapered shape. For example, the angle between the top surface of the insulating layer 20 and the side surface of the layer 29 may be less than 90°, preferably 30° or more and less than 90°. By making the layer 29 tapered, the coverage of the semiconductor layer 30 can be improved and defects such as voids can be reduced. Furthermore, the crystal growth of the semiconductor layer 30 can be promoted.

[0152] 1A shows an example in which island-shaped layers 29 are provided. However, the present invention is not limited to this. For example, layer 29 may have a region extending in a direction perpendicular to the Z direction (X direction in FIG. 6C).

[0153] FIG. 1(A) shows an example in which layer 29 is provided in contact with the upper surface of insulating layer 20. However, the present invention is not limited to this. For example, as shown in FIGS. 6(D) and 6(E), layer 29 may be provided so as to fill a recess provided in insulating layer 20. This makes it possible to flatten the upper surface of insulating layer 20 and improve the crystallinity of semiconductor layer 30. Note that the recess may be an opening penetrating insulating layer 20. Furthermore, layer 29 filled in the recess may have an extending region (see FIG. 6(F)).

[0154] The thickness of layer 29 is preferably thin. For example, the thickness of layer 29 is preferably thinner than the thickness of semiconductor layer 30. Specifically, layer 29 preferably has a region with a thickness of 0.1 nm or more and less than 2 nm, and more preferably has a region with a thickness of 0.5 nm or more and less than 2 nm. By reducing the thickness of layer 29, the step between layer 29 and insulating layer 20 is reduced. This improves the coverage of semiconductor layer 30 and reduces defects such as voids. It also promotes crystal growth of semiconductor layer 30. Layer 29 may be layered or granular.

[0155] The upper surface of insulating layer 20 is preferably flat. If the upper surface of insulating layer 20 on which layer 29 is provided is uneven, the unevenness may cause crystal nuclei to form, which may hinder the growth of large crystal grains. Therefore, by flattening the upper surface of insulating layer 20, the generation of crystal nuclei can be suppressed, and crystallization and crystal growth in semiconductor layer 30 can be promoted using layer 29 as a seed or nucleus.

[0156] In this specification, when the upper surface of a film or layer is said to be flat, it also includes cases where the upper surface of the film or layer has a fine convex surface, a convex curved surface, a concave surface, a concave curved surface, an uneven shape, or the like.

[0157] FIG. 7 shows a schematic cross-sectional view of the insulating layer 20. FIG. 7 also illustrates the top surface shape of the insulating layer 20. In FIG. 7, the height difference H between adjacent convex and concave portions is indicated by a double-headed arrow, and the radius of curvature r of the convex portion is indicated. The height difference H is preferably 0 nm or more and less than 3 nm. By making the height difference H smaller than the preferred film thickness of the semiconductor layer 30 described below, it is possible to prevent the crystallization and crystal growth in the semiconductor layer 30 from being inhibited. Furthermore, the height difference H is more preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, even more preferably 0 nm or more and 0.3 nm or less, and even more preferably 0 nm or more and 0.1 nm or less. A height difference H of 0 nm refers to a case where no convex or concave portions are visible on the top surface of the film or layer. By making the height difference H smaller than the preferred film thickness of the layer 29 described above, the coverage of the semiconductor layer 30 can be improved and defects such as voids can be reduced. The radius of curvature r is preferably 1 nm or more and 100 nm or less, and more preferably 10 nm or more and 100 nm or less. An upper surface on which such irregularities exist can be said to be flat.

[0158] The height difference H and the curvature radius r can be evaluated by performing image analysis of a cross-sectional TEM image. When evaluating the height difference H and the curvature radius r of the top surface of the first layer by performing image analysis of a cross-sectional TEM image, a sample including a first layer and a second layer on the first layer is first prepared. Next, a cross-sectional TEM image of the sample is acquired, and the contrast (boundary of different brightness) observed in the TEM image is assumed to be the interface between the first layer and the second layer, i.e., the top surface of the first layer. The height difference H and the curvature radius r can be calculated based on the assumed top surface of the first layer. The height difference H can be calculated as an average value per field of view (e.g., 100 nm). The curvature radius r can be calculated as an average value per field of view (e.g., 100 nm).

[0159] In this specification, the upper surface of a film or layer is also said to be flat when the average surface roughness (Ra) of the upper surface of the film or layer is less than 3 nm. The average surface roughness (Ra) is a three-dimensional extension of the arithmetic mean roughness defined in JIS B 0601:2001 (ISO 4287:1997) so that it can be applied to curved surfaces. The average surface roughness (Ra) can be evaluated using an atomic force microscope (AFM). The average surface roughness (Ra) can be calculated, for example, over a 1 mm square area. If the layer is island-shaped and does not have a 1 mm square area in plan view, it may be calculated over the entire area of ​​the layer in plan view. The average surface roughness (Ra) described in this specification may also be referred to as root-mean-square roughness (Rq or RMS) or maximum height roughness (Rz). For example, the upper surface of a film or layer is said to be flat when at least one of the average surface roughness (Ra), root mean square roughness (Rq or RMS), and maximum height roughness (Rz) of the upper surface of the film or layer is less than 3 nm.

[0160] The flatness of the upper surface of the film or layer may also be evaluated by performing image analysis of the TEM image. For example, the contrast observed in the TEM image is assumed to represent the interface between the first layer and the second layer, and the shape of the interface is assumed to represent the roughness curve of the first layer. The arithmetic mean roughness can then be calculated from the assumed roughness curve. The reference length may be the length of the upper surface of the first layer observed in the TEM image, or the length of the region where the first layer and the second layer overlap. The reference length is, for example, 100 nm. In this case, it is preferable that either the vertical or horizontal direction of the observation range of the TEM image is 100 nm or more. If the arithmetic mean roughness of the upper surface of the first layer calculated using this method is less than 3 nm, the upper surface of the first layer can also be considered flat.

[0161] The average surface roughness (Ra) or arithmetic mean roughness of the upper surface of the insulating layer 20 is preferably 0 nm or more and less than 3 nm. By making the average surface roughness (Ra) or arithmetic mean roughness of the upper surface of the insulating layer 20 smaller than the preferred film thickness of the semiconductor layer 30 described below, it is possible to prevent inhibition of crystallization and crystal growth in the semiconductor layer 30. Furthermore, the average surface roughness (Ra) or arithmetic mean roughness of the upper surface of the insulating layer 20 is more preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, more preferably 0 nm or more and 0.5 nm or less, more preferably 0 nm or more and 0.3 nm or less, and even more preferably 0 nm or more and 0.2 nm or less. By making the average surface roughness (Ra) or arithmetic mean roughness of the upper surface of the insulating layer 20 smaller than the preferred film thickness of the layer 29 described above, it is possible to improve the coverage of the semiconductor layer 30 and reduce defects such as voids.

[0162] The thickness of the semiconductor layer 30 is preferably larger than the average surface roughness (Ra) or arithmetic mean roughness of the upper surface of the insulating layer 20, and is preferably, for example, 3 nm to 50 nm. This makes it possible to prevent the crystallization and crystal growth in the semiconductor layer 30 from being hindered.

[0163] The insulating layer 50 preferably has a function of supplying oxygen to the semiconductor layer 30. The insulating layer 50 preferably has a region containing oxygen that is desorbed by heating (hereinafter, may be referred to as excess oxygen). When the insulating layer having the region containing excess oxygen comes into contact with the semiconductor layer 30, oxygen can be supplied to the semiconductor layer 30. The oxygen supplied to the semiconductor layer 30 repairs oxygen vacancies, thereby reducing the amount of oxygen vacancies in the semiconductor layer 30. Examples of insulating materials that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0164] The insulating layer 50 preferably has a function of capturing or fixing (also referred to as gettering) oxygen. As described above, an indium oxide film is a film through which oxygen easily moves. Therefore, when the insulating layer 50 has the function of capturing or fixing oxygen, excess oxygen in the semiconductor layer 30 diffuses into the insulating layer 50, and the oxygen can be captured or fixed. Therefore, the OS transistor can suppress positive drift degradation in a +GBT stress test caused by excess oxygen. Examples of insulating materials having a function of capturing or fixing oxygen include aluminum oxide, hafnium oxide, hafnium zirconium oxide, and oxides containing hafnium and silicon (hafnium silicate).

[0165] Aluminum oxide, hafnium oxide, hafnium zirconium oxide, and hafnium silicate have the function of capturing or fixing hydrogen. As described above, an indium oxide film is a film through which hydrogen easily moves. Therefore, since the insulating layer 50 has the function of capturing or fixing hydrogen, hydrogen in the semiconductor layer 30 can be diffused into the insulating layer 50 and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 30 (particularly the hydrogen concentration in the channel formation region) can be reduced.

[0166] FIG. 1A shows an example in which the insulating layer 50 has a single layer structure. Note that the insulating layer 50 can have a stacked structure of two or more layers. When the insulating layer 50 has a stacked structure of two or more layers, it is preferable to use the insulating material (typically, aluminum oxide) applicable to the insulating layer 50 described above as the layer in contact with the semiconductor layer 30 among the two or more layers included in the insulating layer 50. With such a structure, oxygen can be supplied to the semiconductor layer 30, and the amount of oxygen vacancy can be reduced. Furthermore, excess oxygen in the semiconductor layer 30 can be discharged to the insulating layer 50. Furthermore, hydrogen in the semiconductor layer 30 can be captured or fixed.

[0167] The insulating layer 20 preferably has a function of supplying oxygen to the semiconductor layer 30. For example, the insulating layer 20 preferably has a region containing excess oxygen. The insulating layer 50 preferably has a function of capturing or fixing oxygen. With this configuration, oxygen is pushed into the semiconductor layer 30 from the insulating layer 20 side, reducing the amount of oxygen vacancy in the semiconductor layer 30, and further, excess oxygen in the semiconductor layer 30 is pulled from the insulating layer 50 side, reducing the excess amount of oxygen in the semiconductor layer 30. Therefore, a semiconductor device with good reliability can be provided.

[0168] Alternatively, the insulating layer 20 may have a function of capturing or fixing oxygen, and the insulating layer 50 may have a function of supplying oxygen to the semiconductor layer 30. With such a configuration, oxygen is pushed into the semiconductor layer 30 from the insulating layer 50 side, reducing the amount of oxygen vacancy in the semiconductor layer 30, and furthermore, excess oxygen in the semiconductor layer 30 is pulled from the insulating layer 20 side, reducing the excess amount of oxygen in the semiconductor layer 30. Therefore, a semiconductor device with excellent reliability can be provided.

[0169] Furthermore, it is preferable to use a material for the insulating layer 20 that has a smaller thermal expansion coefficient than the metal oxide used for the semiconductor layer 30. For example, a material for the insulating layer 20 that has a smaller thermal expansion coefficient than indium oxide can be used. Specifically, the thermal expansion coefficient of the insulating layer 20 is 0.01×10 -6 K -1 Over 5.5 x 10 -6 K -1 Preferably less than 0.01 x 10 -6 K -1 Over 5.0 x 10 -6 K -1 Preferably less than 0.01 x 10 -6 K -1 Over 3.0 x 10 -6 K -1 Less than 0.01 x 10 is preferable. -6 K -1 Over 1.0 x 10 -6 K -1The following is even more preferable. With this configuration, the semiconductor layer 30 containing indium oxide is in contact with or located near the insulating layer 20, which has a small thermal expansion coefficient, and tensile stress is applied to the indium oxide when the temperature is lowered, making the indium oxide energetically unstable. As a result, the indium oxide becomes a cubic crystal, which is more energetically stable. This promotes crystal growth, allowing the formation of cubic crystals with large grain sizes. Silicon oxide is suitable for the insulating layer 20 because it has a smaller thermal expansion coefficient than indium oxide.

[0170] The thermal expansion coefficients of oxide semiconductors and insulators are shown in Table 3. Table 3 shows the thermal expansion coefficients of IGZO and indium oxide (In2O3) as oxide semiconductors, and the thermal expansion coefficients of silicon oxide (SiO2), silicon nitride (Si3N4), and yttria-stabilized zirconia (YSZ) as insulators. Table 3 shows that silicon nitride can also be suitably used for insulating layer 20.

[0171] [Table 3]

[0172] FIG. 1(F) shows an example in which the insulating layer 20 has a single layer structure. The insulating layer 20 can have a stacked structure of two or more layers. When the insulating layer 20 has a stacked structure of two or more layers, it is preferable to use the insulating material (typically silicon oxide) applicable to the insulating layer 20 described above as a layer in contact with the semiconductor layer 30 among the two or more layers included in the insulating layer 20. With such a structure, the crystallinity of the semiconductor layer 30 can be improved.

[0173] 1(F) shows an example in which the insulating layer 20 is island-shaped like the semiconductor layer 30. However, the present invention is not limited to this. For example, as shown in FIG. 8(A), the insulating layer 20 may have a shape that has a convex portion at the portion that overlaps with the semiconductor layer 30, instead of having an island-shaped shape.

[0174] The conductive layer 60 is preferably made of a highly conductive material such as tungsten. Furthermore, the conductive layer 60 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion. Examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This can prevent the conductivity of the conductive layer 60 from decreasing.

[0175] Furthermore, the conductive layer 60 preferably uses a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. For example, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In-Zn oxide, and ITSO may be used. Indium gallium zinc oxide containing nitrogen may also be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an insulating layer outside the transistor may be captured.

[0176] The insulating layer 80 functions as an interlayer film. The insulating layer 50 and the conductive layer 60 are provided so as to fill an opening 89 provided in the insulating layer 80. The opening 89 is preferably provided in a position that does not overlap with the layer 29. The portion of the semiconductor layer 30 that does not overlap with the layer 29 is flat compared to the portion that overlaps with the layer 29. Therefore, by providing the opening 89 in a position that does not overlap with the layer 29, a channel is formed in a flat region of the semiconductor layer 30, and the electrical characteristics of the transistor can be improved.

[0177] As shown in FIG. 8B , the semiconductor device of one embodiment of the present invention can include conductive layers 40a and 40b that are spaced apart from each other over the semiconductor layer 30. The conductive layers 40a and 40b function as source and drain electrodes of the transistor, respectively. In FIG. 8B , the conductive layers 40a and 40b are in contact with at least part of the top surface and at least part of the side surface of the semiconductor layer 30. This structure increases the contact area between the conductive layer 40a or 40b and the semiconductor layer 30, thereby reducing the contact resistance between the conductive layer 40a and the semiconductor layer 30 and the contact resistance between the conductive layer 40b and the semiconductor layer 30.

[0178] 8C, the semiconductor device of one embodiment of the present invention can include a conductive layer 15 overlapping with the conductive layer 60 with the semiconductor layer 30 sandwiched therebetween. The semiconductor device illustrated in FIG. 8C also includes an insulating layer 16. The conductive layer 15 is covered with the insulating layer 16 and has a portion overlapping with the semiconductor layer 30 with the insulating layer 20 interposed therebetween.

[0179] In the structure shown in FIG. 8(C), the conductive layer 60 functions as a first gate electrode of the transistor, the insulating layer 50 functions as a first gate insulating layer of the transistor, the conductive layer 15 functions as a second gate electrode of the transistor, and the insulating layer 16 and the insulating layer 20 function as a second gate insulating layer of the transistor.

[0180] 8C, the semiconductor device may be configured without the insulating layer 50 and the conductive layer 60. In this case, the conductive layer 15 functions as a gate electrode of the transistor, and the insulating layer 16 and the insulating layer 20 function as gate insulating layers of the transistor. In this case, the structure of the transistor can be said to be a bottom-gate type.

[0181] <Example 1 of manufacturing method of semiconductor device> An example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described below. The example of the method for manufacturing a semiconductor device described here also includes a method for manufacturing a semiconductor layer.

[0182] 9(A), 9(C), 9(E), 9(G), 10(A), and 10(C) are perspective schematic views of the semiconductor device, and FIGS. 9(B), 9(D), 9(F), 9(H), 10(B), and 10(D) are cross-sectional views of the semiconductor device as viewed from the X direction.

[0183] The layers constituting the semiconductor device (insulating layer 20, layer 29, semiconductor layer 30, conductive layer 40a and conductive layer 40b, insulating layer 80, insulating layer 50, conductive layer 60, etc.) can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0184] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings or grooves with high aspect ratios.

[0185] Some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain higher amounts of elements such as carbon or chlorine than films formed by other film formation methods. Quantitative analysis of these elements can be performed using XPS or SIMS. When using the ALD method, the amount of carbon and chlorine contained in the film may be lower by employing a high substrate temperature during film formation and / or by performing an impurity removal process, compared to when the ALD method is used without these procedures.

[0186] Examples of the ALD method include a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0187] ALD film formation systems alternately introduce a first source gas (sometimes called a precursor, precursor, or metal precursor) and a second source gas (sometimes called a reactant, reactant, oxidizer, or non-metal precursor) into a chamber to form a film. The introduction of the source gases can be switched, for example, by switching between the respective switching valves (sometimes called high-speed valves). Furthermore, when introducing the source gases, an inert gas such as nitrogen (N), argon (Ar), or helium (He) may be introduced into the chamber together with the source gas as a carrier gas. The use of a carrier gas prevents the source gas from adsorbing to the inside of the piping and valves, even when the source gas has low volatility or a low vapor pressure, allowing the source gas to be introduced into the chamber. This also improves the uniformity of the film formed, which is preferable.

[0188] Furthermore, the ALD method allows for the deposition of films of any desired composition by simultaneously introducing multiple different precursors, or by controlling the number of cycles for each precursor.

[0189] First, as shown in FIGS. 9(A) and 9(B), a substrate 10 is prepared, and an insulating layer 20 is formed on the substrate 10. The upper surface of the insulating layer 20 is preferably flat. For example, the upper surface of the insulating layer 20 is preferably planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness. By flattening the upper surface of the insulating layer 20, the crystallinity of the semiconductor layer 30 to be formed later can be improved. For example, this can promote lateral growth of the crystals of the semiconductor layer 30 in the first heat treatment described below.

[0190] The insulating layer 20 can be formed, for example, by sputtering in an oxygen-containing atmosphere. By using a sputtering method that does not require the use of hydrogen-containing molecules in the film formation gas, the hydrogen concentration in the insulating layer 20 can be reduced. Furthermore, by forming the insulating layer 20 by sputtering in an oxygen-containing atmosphere, oxygen can be added to the insulating layer 20. Oxygen can be supplied from the insulating layer 20 to the semiconductor layer 30 by heat or the like applied after the formation of the semiconductor layer 30, thereby reducing oxygen vacancies. For example, by forming a silicon oxide film as the insulating layer 20 by sputtering, the upper surface of the insulating layer 20 can be flattened.

[0191] It is preferable to perform a heat treatment before forming the layer 29. The heat treatment is performed, for example, at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. By setting the temperature within the above range, deformation (distortion or warpage) of the substrate can be extremely reduced even when the heat treatment is performed.

[0192] The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm (0.001%) or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content is preferably about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen. By performing the heat treatment as described above, impurities such as hydrogen or water contained in the insulating layer 20 can be reduced before the semiconductor layer 30 is formed.

[0193] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb (1×10 -3 ppm) or less is preferable, and 0.1 ppb (1 × 10 -4ppm) or less is more preferable, and 0.05 ppb (5 × 10 -5 By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulating layer 20 and the like as much as possible.

[0194] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas.

[0195] Furthermore, it is preferable to perform a process of supplying oxygen before forming layer 29. This supplies oxygen to insulating layer 20, and oxygen can be supplied from insulating layer 20 to semiconductor layer 30 by heat or the like applied after the formation of semiconductor layer 30.

[0196] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment in an oxygen-containing atmosphere. The plasma treatment in this specification and the like includes microwave plasma treatment, which will be described later. Alternatively, oxygen may be supplied to the insulating layer 20 by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The deposited oxide film may be removed immediately or may be left as is. If the deposited oxide film is left as is, the oxide film can be used as part of the semiconductor layer 30. The oxygen-containing atmosphere includes not only oxygen gas (O2) but also atmospheres containing a gas of an oxygen-containing compound such as ozone (O3) or nitrous oxide (NO). The substrate temperature during the plasma treatment is set to be equal to or higher than room temperature (25°C) and equal to or lower than 450°C.

[0197] Next, a layer 29 is formed on the insulating layer 20 (FIGS. 9(A) and 9(B)). The layer 29 functions as a seed or nucleus for crystal growth of the semiconductor layer 30. Therefore, the layer 29 can be called a seed layer, a seed crystal, or the like.

[0198] There is no particular limitation on the method for forming layer 29. For example, layer 29 can be formed by forming a film that will become layer 29 and processing the film. The film can be formed using a sputtering method, a CVD method, a vacuum deposition method, an MBE method, a PLD method, an ALD method, or the like.

[0199] The layer 29 can be formed by a sputtering method. Forming the layer 29 by a sputtering method can improve the crystallinity of the layer 29. Furthermore, forming the layer 29 by a sputtering method in an atmosphere containing oxygen can add oxygen to the insulating layer 20.

[0200] If the sputtering target has a plurality of crystal grains, and the crystal grains have a layered structure and have interfaces that are prone to cleavage, the crystal grains may be cleaved by bombarding the sputtering target with ions, resulting in plate-shaped or pellet-shaped sputtering particles. The plate-shaped or pellet-shaped sputtering particles deposited on insulating layer 20 may be used as layer 29.

[0201] Furthermore, when a film that will become layer 29 is formed and then processed to form layer 29, either a wet etching method or a dry etching method, or both, can be used to process the film. It is more preferable to process the film using a wet etching method. The wet etching method may cause less damage than the dry etching method. Therefore, damage to insulating layer 20 can be reduced, and the flatness of the top surface of insulating layer 20 can be maintained.

[0202] Alternatively, the layer 29 shown in Figures 6(D) and 6(E) or the layer 29 shown in Figure 6(F) can be formed by forming a recess in the insulating layer 20, filling the recess with a film that will become the layer 29, and polishing the film by CMP or the like until the surface of the insulating layer 20 is exposed. This makes it possible to flatten the surface on which the semiconductor layer 30 will be formed.

[0203] As described above, by forming layer 29 before forming semiconductor layer 30, the thermal effect on semiconductor layer 30 can be reduced, and the reduction in the grain size of the crystals in semiconductor layer 30 and the increase in the grain boundaries can be suppressed.

[0204] Next, as shown in FIGS. 9(C) and 9(D), a semiconductor layer 30 is formed to cover the layer 29. The semiconductor layer 30 is preferably formed by sputtering. A noble gas (typically argon) or oxygen, or a mixture of a noble gas and oxygen, can be used as the sputtering gas. The ratio of the noble gas (typically argon) to the total sputtering gas is, for example, 50% to 100%, preferably 70% to 100%, and more preferably 90% to 100%. By increasing the ratio of the noble gas (typically argon) to the total sputtering gas, a semiconductor layer 30 with low crystallinity can be formed. Furthermore, a semiconductor layer 30 with many dangling bonds can be formed. This increases the etching rate of the semiconductor layer 30. This facilitates processing of the semiconductor layer 30, thereby improving the productivity of semiconductor devices. The semiconductor layer 30 with low crystallinity has, for example, an amorphous structure.

[0205] The sputtering gas may also contain hydrogen (H2). Introducing hydrogen when forming the semiconductor layer 30 using a sputtering method allows the formation of a semiconductor layer 30 with low crystallinity. Furthermore, during the formation of the semiconductor layer 30, the generation of crystal nuclei can be suppressed or the annihilation of crystal nuclei can be promoted. If there are many crystal nuclei, the grown crystals collide with each other, suppressing the growth of large grain sizes. In other words, the crystals will have small grain sizes. However, by suppressing the generation of crystal nuclei and annihilating some of the crystal nuclei in the film to reduce the number of crystal nuclei, and then performing the first heat treatment described below, crystal growth can be promoted from fewer crystal nuclei, thereby increasing the size of the crystal grains in the semiconductor layer 30.

[0206] The semiconductor layer 30 can also be formed by sputtering in an atmosphere containing oxygen. In this case, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the semiconductor layer 30 can be reduced. For example, oxygen or a mixed gas of oxygen and a noble gas may be used as the sputtering gas.

[0207] The semiconductor layer 30 may also be formed using an ALD method. A first precursor and a first oxidizing agent can be used to form the semiconductor layer 30. The first precursor preferably contains indium. In this case, an indium oxide film is formed as the semiconductor layer 30. That is, an oxide film containing a single element other than oxygen is formed. When the first precursor contains indium, a thermal ALD method can be used as the ALD method.

[0208] Examples of precursors that can be used that contain indium include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolato)indium.

[0209] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the indium-containing precursor. Examples of the inorganic indium-containing precursor include halogen-based indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). The decomposition temperature of indium trichloride is approximately 500°C to 700°C. Therefore, by using indium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0210] It is preferable to use a precursor with a low impurity concentration, i.e., a high purity, in the method for forming the semiconductor layer 30. For example, impurities in the semiconductor layer 30 can be reduced by using a precursor with a purity of 3N (99.9%) or higher, preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher.

[0211] The gallium content and aluminum content of the indium-containing precursor are each preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, even more preferably 50 ppm or less, even more preferably 10 ppm or less, and even more preferably 1 ppm or less. By using a precursor with a low gallium content, the gallium concentration in the semiconductor layer 30 can be reduced, thereby improving the reliability of the transistor. Furthermore, by using a precursor with a low aluminum content, the aluminum concentration in the semiconductor layer 30 can be reduced, thereby improving the crystallinity of the semiconductor layer 30.

[0212] Furthermore, as the precursor used in this embodiment, it is preferable to use a precursor purified by distillation (also called rectification or precision distillation) two or more times. By using such a precursor, it is easy to form a metal oxide film with few impurities, which is preferable. By performing distillation multiple times, it is possible to further suppress impurities originating from the starting materials used in the precursor production from remaining in the precursor, which is preferable. Note that the present invention is not limited to the above, and a precursor purified by distillation once, i.e., simple distillation, may also be used. By using simple distillation, it is possible to reduce production costs, which is preferable.

[0213] By performing one or more distillations, the aluminum content of the indium-containing precursor can be reduced to 100 ppm or less, 1 ppm or less, or 1 ppb (0.001 ppm) or less. By using the indium-containing precursor, it is possible to form an indium oxide film with a purity similar to that of silicon (10N) used in the semiconductor layer.

[0214] The first oxidizing agent may be ozone (O3), oxygen (O2), water (H2O), hydrogen peroxide (H2O2), or the like. The first oxidizing agent preferably contains at least one of ozone and oxygen. By using ozone, oxygen, or the like that does not contain hydrogen as the first oxidizing agent, the amount of hydrogen mixed into the insulating layer 20 can be reduced. The first oxidizing agent may contain at least one of water and hydrogen peroxide. This allows the formation of a semiconductor layer 30 with low crystallinity.

[0215] In this specification and the like, unless otherwise specified, when ozone, oxygen, or water is used as an oxidizing agent, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, or ion state.

[0216] The pulse time for introducing the first oxidizing agent is preferably 0.1 seconds or more and 30 seconds or less, more preferably 0.3 seconds or more and 15 seconds or less, and even more preferably 0.3 seconds or more and 10 seconds or less. By shortening the pulse time for introducing the first oxidizing agent and reducing the amount of the first oxidizing agent introduced, more hydrogen contained in the first precursor remains in the film. By leaving more hydrogen in the film, it is possible to suppress the generation of crystal nuclei and eliminate some of the crystal nuclei in the film, thereby reducing the number of crystal nuclei in the film.

[0217] Here, the substrate heating temperature when introducing the first precursor into the reaction chamber is preferably set to a temperature corresponding to the decomposition temperature of the first precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, the substrate heating temperature can be set to, for example, 100°C to 350°C, preferably 150°C to 300°C. When providing layer 29, the substrate heating temperature can be set to room temperature (25°C) to 300°C, preferably room temperature to 200°C, and more preferably room temperature to 150°C. Lowering the substrate heating temperature can reduce the crystallinity of semiconductor layer 30 during film formation.

[0218] When the semiconductor layer 30 has a laminated structure, the semiconductor layer 30 can also be formed using, for example, a sputtering method and an ALD method. For example, when the semiconductor layer 30 has a two-layer structure consisting of a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, the first semiconductor layer can be formed by an ALD method and the second semiconductor layer can be formed by a sputtering method. Since the ALD method is a film formation method with superior coverage compared to the sputtering method, forming the first semiconductor layer by the ALD method can improve the coverage of the semiconductor layer 30. In addition, damage to the base (here, the insulating layer 20) can be reduced, and the formation of a mixed layer at the interface between the base and the semiconductor layer 30 can be suppressed, resulting in higher crystallinity. In addition, forming the second semiconductor layer by a sputtering method can improve productivity.

[0219] Alternatively, the first semiconductor layer may be formed by sputtering, and the second semiconductor layer may be formed by ALD. Even if pinholes or discontinuities occur in the first semiconductor layer formed by sputtering, the overlapping portions can be filled with the second semiconductor layer formed by ALD, which has good coverage.

[0220] Next, the semiconductor layer 30 is processed into a desired shape. In Figures 9(E) and 9(F), the semiconductor layer 30 and the insulating layer 20 are processed into island shapes to form structures including the semiconductor layer 30 and the insulating layer 20. Specifically, the semiconductor layer 30 and the insulating layer 20 are processed so that multiple structures are provided spaced apart in the X direction and the Y direction.

[0221] 9(G) and 9(H), the insulating layer 20 may be processed so that a portion thereof that does not overlap with the semiconductor layer 30 remains. In this case, the insulating layer 20 can be said to have a convex portion at the portion that overlaps with the semiconductor layer 30.

[0222] It is preferable to supply a second element to the semiconductor layer 30 (this can also be referred to as adding or injecting the second element) before processing the semiconductor layer 30. This supplies the second element to the semiconductor layer 30. By supplying the second element to the semiconductor layer 30, the crystallinity of the semiconductor layer 30 can be reduced. This makes it easier to process the semiconductor layer 30, and can increase the productivity of semiconductor devices.

[0223] As the second element, it is preferable to use one or more of hydrogen and noble gases (helium, neon, argon, krypton, xenon, etc.).

[0224] Plasma treatment can be suitably used to supply the second element. The second element can be supplied by generating plasma in a gas atmosphere containing the second element to be supplied and performing plasma treatment. Devices that can be used to generate the plasma include dry etching devices, ashing devices, plasma CVD devices, and high-density plasma CVD devices. Supplying the second element at an accelerated rate increases the collision energy when the second element is supplied to the semiconductor layer 30, which is preferable because it can more effectively reduce the crystallinity of the semiconductor layer 30.

[0225] The supply of the second element is not limited to the above-mentioned method, and for example, ion implantation can also be used. Ion implantation can control the concentration profile in the depth direction with high precision by adjusting the ion acceleration energy and dose. Furthermore, by using an ion implantation method in which a source gas is ionized and the ions are mass-separated before supply, ions of a specific mass can be supplied, thereby increasing the purity of the supplied second element. Alternatively, by using an ion implantation method in which ions are supplied without mass separation, productivity can be improved. Unless otherwise specified in this specification, the presence or absence of mass separation is not limited. Note that a method in which ions are mass-separated before supplying them is sometimes called an ion implantation method, and a method in which ions are supplied without mass separation is sometimes called an ion doping method.

[0226] A gas containing a second element can be used as the source gas. When argon is used as the second element, argon gas can be used as the source gas. When argon and hydrogen are used as the second element, a mixed gas of argon gas and hydrogen gas can be used as the source gas. Alternatively, a mixed gas of a gas containing the second element and another gas can be used. Note that the source material used to supply the second element is not limited to a gas, and a solid or liquid can also be heated and vaporized for use.

[0227] Next, a first heat treatment is performed. The first heat treatment is preferably performed in an atmosphere containing at least one of hydrogen (H2) and nitrogen (N2), and more preferably in an atmosphere containing hydrogen (H2) and nitrogen (N2). At this time, the hydrogen flow ratio is preferably 3% to 15%, and more preferably 5% to 10%. The hydrogen flow ratio refers to the ratio of the flow rate of hydrogen gas to the total gas flow rate. The temperature of the first heat treatment is preferably 120°C to 300°C, more preferably 120°C to 250°C, and even more preferably 120°C to 200°C. The time period of the first heat treatment is preferably 1 hour to 8 hours.

[0228] The first heat treatment promotes epitaxial growth and lateral growth of crystal grains in the semiconductor layer 30, using the layer 29 as a seed or nucleus, thereby improving the crystallinity of the semiconductor layer 30. In particular, using a material with a low thermal expansion coefficient for the insulating layer 20 can promote crystal growth. For example, crystal grains are formed in the semiconductor layer 30 at the portion overlapping the layer 29, and the lateral growth of these crystal grains can cause the semiconductor layer 30 to grow crystal along the formation surface. That is, as shown in FIGS. 10(A) and 10(B), crystals grow laterally using the layer 29 as a seed or nucleus, and a region 31c expands. The region 31c has higher crystallinity than the region 31a. As the treatment time progresses, the region 31c further expands along the formation surface. Finally, at the end of the first heat treatment, the region 31c expands throughout the semiconductor layer 30 (FIGS. 10(C) and 10(D)). In this way, the crystallinity of the semiconductor layer 30 can be improved. Indium oxide with improved crystallinity due to the lateral growth of crystals from crystal nuclei can be called Lateral Growth Indium Oxide (LGIO).

[0229] Furthermore, by using silicon oxide, which has a small thermal expansion coefficient, for the insulating layer 20, and applying tensile stress to the indium oxide from the upper surface of the insulating layer 20 when the temperature is lowered, crystal growth of the semiconductor layer 30 can be promoted.

[0230] Subsequently, a second heat treatment is performed. The second heat treatment is preferably performed in an atmosphere containing nitrogen and oxygen (typically, a nitrogen:oxygen volume ratio of 4:1). The temperature of the second heat treatment is preferably higher than that of the first heat treatment. For example, the temperature is preferably 300°C or higher and 400°C or lower, more preferably 300°C or higher and 350°C or lower. The time period of the second heat treatment is preferably 1 hour or higher and 4 hours or lower.

[0231] The gas used in the second heat treatment is preferably highly purified. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being taken into the semiconductor layer 30 as much as possible.

[0232] The heat treatment used in the second heat treatment is not particularly limited, and for example, an electric furnace or an RTA device can be used.

[0233] By performing the first heat treatment at a temperature lower than that of the second heat treatment, the generation of crystal nuclei can be suppressed, and the crystal grain size can be increased. Since the first heat treatment is performed in a reducing atmosphere, the amount of oxygen vacancies in the semiconductor layer 30 increases. Therefore, by performing the second heat treatment, oxygen is supplied to the semiconductor layer 30, and the supplied oxygen can repair (null) the oxygen vacancies. Furthermore, by performing the first heat treatment at a temperature lower than that of the second heat treatment, impurities may remain in the semiconductor layer 30. Therefore, by performing the second heat treatment at a temperature higher than that of the first heat treatment, the impurity concentration in the semiconductor layer 30 can be reduced. Furthermore, the hydrogen concentration in the semiconductor layer 30 can be reduced. Furthermore, by performing the second heat treatment, the crystal grains in the semiconductor layer 30 can be made larger.

[0234] As described above, by performing the first heat treatment and the second heat treatment in this order, the crystal growth of the semiconductor layer 30 can be achieved, and the amount of oxygen vacancies and impurities in the semiconductor layer 30 can be reduced.

[0235] Note that microwave plasma treatment may be performed after the formation of the semiconductor layer 30. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the semiconductor layer 30 can be reduced. Furthermore, a crystalline region of the semiconductor layer 30 may grow.

[0236] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma processing refers to processing using a device with a power source that generates high-density plasma using microwaves. Microwave plasma processing can also be called microwave-excited high-density plasma processing.

[0237] By performing microwave plasma treatment in an atmosphere containing oxygen, the impurity concentration in the semiconductor layer 30 can be reduced. Examples of impurities include carbon. While the above example illustrates a configuration in which microwave plasma treatment is performed on the semiconductor layer 30 in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the semiconductor layer 30 in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may enhance the crystallinity of the semiconductor layer 30.

[0238] The microwave plasma treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa to 1000 Pa, more preferably 50 Pa to 700 Pa, and even more preferably 100 Pa to 400 Pa. The treatment temperature is preferably room temperature (25°C) to 750°C, more preferably 300°C to 500°C, and can be 400°C to 450°C.

[0239] When microwave plasma treatment is performed, the substrate may be heated. The substrate is preferably heated to a temperature above room temperature (e.g., 25°C), above 100°C, above 200°C, above 300°C, or above 400°C, and below 500°C or below 450°C. For example, the substrate is preferably heated to a temperature above room temperature and below 500°C, more preferably above 100°C and below 450°C, more preferably above 200°C and below 450°C, more preferably above 300°C and below 450°C, and even more preferably above 400°C and below 450°C.

[0240] Microwave plasma processing can be performed using, for example, oxygen gas and argon gas. Note that if the oxygen flow ratio (O2 / (O2+Ar)) in microwave plasma processing is too high, discharge becomes less stable. Therefore, for example, the oxygen flow ratio (O2 / (O2+Ar)) is preferably greater than 0% and less than 50%, more preferably greater than 0% and less than 40%, and even more preferably greater than 0% and less than 30%.

[0241] In microwave plasma treatment using oxygen and argon gases, the main oxygen radical is triplet oxygen (O( 3 P j )), singlet oxygen (O( 1 D2)), and oxygen ions (O2 + ) can take three states. Note that oxygen ions effectively act to reduce the hydrogen concentration in oxide films by microwave plasma processing. The amount of oxygen radicals in each state varies depending on the oxygen flow rate ratio or pressure in microwave plasma processing. For example, the amount of oxygen ions tends to increase under conditions of a low oxygen flow rate ratio and low pressure. On the other hand, if the oxygen flow rate ratio or pressure is excessively low, there is a concern that the control of the oxygen flow rate becomes unstable, making it difficult to stabilize the discharge and etching the oxide film. Therefore, for example, the oxygen flow rate ratio (O2 / (O2+Ar)) in microwave plasma processing is preferably greater than 0% and less than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0242] The shorter the microwave plasma treatment time, the higher the productivity. Therefore, for example, the microwave plasma treatment time is preferably 1 minute or more and 60 minutes or less, more preferably 1 minute or more and 30 minutes or less, and even more preferably 1 minute or more and 10 minutes or less.

[0243] By performing microwave plasma treatment in an oxygen-containing atmosphere, oxygen gas is converted into plasma using microwaves or high-frequency waves such as RF, and oxygen radicals generated by the plasma can act on the oxide semiconductor layer. Hydrogen can be removed from the oxide semiconductor layer by the action of plasma, microwaves, oxygen radicals, or the like. In this way, the hydrogen concentration in the oxide semiconductor layer can be reduced. Furthermore, carbon bonded to oxygen or hydrogen can also be removed in some cases. Thus, impurities can be reduced by performing microwave plasma treatment. Furthermore, by supplying the oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0244] Furthermore, a part of the oxygen present in the oxide semiconductor before the microwave plasma treatment reacts with hydrogen in the oxide semiconductor, in other words, the reaction "2H + O → H2O↑" occurs, and the hydrogen can be removed as H2O (also referred to as dehydration or dehydrogenation). H2O is one of the factors that hinder improvement of crystallinity, so it is preferable to remove it from the oxide semiconductor. Removing hydrogen in the oxide semiconductor as H2O and reducing the hydrogen concentration in the oxide semiconductor can also promote improvement of crystallinity. Note that the hydrogen concentration in the oxide semiconductor can be further reduced by increasing the temperature during the microwave plasma treatment.

[0245] After the microwave plasma treatment, a heat treatment may be performed without exposing the substrate to the outside air. The temperature of the heat treatment is, for example, preferably 100°C to 750°C, more preferably 300°C to 500°C, and even more preferably 400°C to 450°C. By setting the temperature within the above range, deformation (distortion or warpage) of the substrate can be significantly reduced even when the heat treatment is performed.

[0246] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0247] Oxygen supplied to the oxide semiconductor layer can be in various forms such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions with an unpaired electron). Note that the oxygen injected into the oxide semiconductor layer is preferably in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.

[0248] Note that before the insulating layer 50 is formed, treatment for supplying hydrogen to the semiconductor layer 30 (also referred to as hydrogenation treatment) may be performed. By supplying hydrogen to the semiconductor layer 30, dangling bonds present at crystal grain boundaries or the like may be terminated, and the electrical characteristics and reliability of the transistor may be improved. Note that examples of the treatment for supplying hydrogen include heat treatment and plasma treatment in an atmosphere containing hydrogen.

[0249] Next, an insulating layer 80 is formed to cover the semiconductor layer 30, and an opening 89 is formed in the insulating layer 80 so as to overlap a portion of the semiconductor layer 30. As described above, it is preferable to form the opening 89 at a position that does not overlap the layer 29.

[0250] Subsequently, an insulating layer 50 is formed to cover the opening 89. The insulating layer 50 is preferably formed using an ALD method. A second precursor and a second oxidizing agent can be used to form the insulating layer 50. The second precursor preferably contains one of aluminum and hafnium. In this case, an aluminum oxide film or a hafnium oxide film is formed as the insulating layer 50. In other words, an oxide film containing a single element other than oxygen is formed. Note that when the second precursor contains one of aluminum and hafnium, a thermal ALD method can be used as the ALD method.

[0251] Examples of precursors that can be used include aluminum chloride, trimethylaluminum, etc. Examples of precursors that can be used include hafnium tetrachloride, tetrakis(ethylmethylamido)hafnium (TEMAHf), etc.

[0252] The second oxidizing agent can be any of the materials that can be used for the first oxidizing agent described above. Note that the first oxidizing agent and the second oxidizing agent may be the same or different.

[0253] In the ALD process, precursors are introduced into a chamber and adsorbed onto the substrate surface. This adsorption of the precursor onto the substrate surface triggers a self-limiting mechanism for the surface chemical reaction, preventing further adsorption of the precursor onto the substrate. The optimum substrate temperature range within which this mechanism is activated is also known as the ALD window. The ALD window is determined by the precursor's temperature characteristics, vapor pressure, decomposition temperature, and other factors. Therefore, the ALD window varies from precursor to precursor. Therefore, when depositing oxide films containing multiple elements other than oxygen, the deposition conditions must be adjusted to account for the ALD window of each precursor. On the other hand, when depositing oxide films containing only a single element other than oxygen, such as indium oxide or aluminum oxide, the deposition conditions can be adjusted by considering only the ALD window of a single precursor, simplifying the process and enabling the formation of high-quality oxide films.

[0254] After the insulating layer 50 is formed, microwave plasma treatment is preferably performed. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the semiconductor layer 30 can be reduced. For details of the microwave plasma treatment, refer to the above description.

[0255] Subsequently, a conductive layer 60 is formed over the insulating layer 50 so as to fill the opening 89. In this manner, the semiconductor device shown in FIGS.

[0256] 8(B), when the conductive layer 40a and the conductive layer 40b are provided on the semiconductor layer 30, after forming the crystalline semiconductor layer 30, a conductive layer to become the conductive layer 40a and the conductive layer 40b is formed on the semiconductor layer 30, an insulating layer 80 is formed on the conductive layer, an opening 89 is formed in the insulating layer 80, and the conductive layer is removed from the portion overlapping with the opening 89. As a result, the conductive layer 40a and the conductive layer 40b are formed from the conductive layer.

[0257] 1A to 1F, the layer 29 and the semiconductor layer 30 in the vicinity of the layer 29 are left without being removed. This allows the number of manufacturing steps of the semiconductor device to be reduced. However, the present invention is not limited to this. For example, the layer 29 and the semiconductor layer 30 in the vicinity of the layer 29 may be removed.

[0258] When the semiconductor layer 30 is formed by the ALD method, the layer 29 may be used as a seed or nucleus to form a crystalline semiconductor layer 30 during the formation process. For example, by setting the substrate heating temperature during film formation by the ALD method to a range of 100°C to 300°C or 150°C to 250°C, the crystalline semiconductor layer 30 can be formed during film formation. In this case, a heat treatment for crystal growth of the semiconductor layer 30 is not necessary. Note that if the substrate heating temperature is too high, crystal nuclei may be formed, hindering the formation of large crystal grains. On the other hand, if the substrate heating temperature is too low, crystal growth may not occur during the formation process of the semiconductor layer 30. FIGS. 11(A) and 11(B) show the configuration in which the crystalline semiconductor layer 30 shown in FIGS. 10(C) and 10(D) is formed during the process of forming the semiconductor layer 30 described with reference to FIGS. 9(C) and 9(D). 11(A) and 11(B) illustrate the case where a layer 29 having a region extending in the X direction is used.

[0259] Even when a crystalline semiconductor layer 30 can be formed in the process of forming the semiconductor layer 30, at least one of the first heat treatment, the second heat treatment, the microwave plasma treatment, and the hydrogenation treatment may be performed, which may further enhance the crystallinity of the semiconductor layer 30.

[0260] Furthermore, if a crystalline semiconductor layer 30 can be formed in the process of forming the semiconductor layer 30, the layer 29 may be removed in a subsequent process. For example, as shown in Figures 11(C) and 11(D), the semiconductor layer 30 and the insulating layer 20 can be processed into an island shape, and the layer 29 can be removed. This allows the semiconductor layer 30 to have a flat upper surface.

[0261] Furthermore, if a crystalline semiconductor layer 30 can be formed during the process of forming the semiconductor layer 30, the semiconductor layer 30 can be processed into a desired shape after a layer is formed on the semiconductor layer 30. For example, as shown in FIGS. 11(E) to 11(H), a layer 35 can be formed on the semiconductor layer 30, and the layer 35, the semiconductor layer 30, and the insulating layer 20 can be processed into an island shape, while the layer 29 can be removed. The layer 35 may have a single-layer structure or a stacked structure of two or more layers. When the layer 35 has a stacked structure, it may be a stacked structure of the same material or a stacked structure of different materials. The different materials may be two or more materials selected from semiconductor materials, insulating materials, and conductive materials.

[0262] <Example 2 of manufacturing method of semiconductor device> Hereinafter, an example of a method for manufacturing a semiconductor device will be described, including a method for manufacturing a semiconductor layer that is partially different from the above. Note that to avoid repetition, explanations of parts common to the above will be omitted, and differences will be described in detail. Note that unless otherwise specified, the contents of the above-mentioned Example 1 of Method for Manufacturing a Semiconductor Device can be referenced for parts that are omitted.

[0263] In the following example of a method for fabricating a semiconductor device, a layer 29 that serves as a crystal nucleus can be formed from one grain of a polycrystalline film. More specifically, one of multiple grains in the polycrystalline film is selected, and the other grains that are not used are removed by etching to form layer 29. Figures 12(A) to 12(E) and 12(G) are schematic perspective views of each stage of the following example of the fabrication method.

[0264] First, an insulating layer 20 is formed on a substrate 10 (not shown), and a film 29f is formed on the insulating layer 20. After that, a resist mask 25 is formed to cover the film 29f (FIG. 12(A)).

[0265] The film 29f is a film, a part of which will later become the layer 29. The film 29f has a polycrystalline structure. The film 29f has a plurality of grains 29a and grain boundaries 29b between two grains 29a. In FIG. 12(A) and other figures, different hatching patterns are used to represent different grains 29a. The grain boundaries 29b are indicated by dashed lines.

[0266] It is preferable to use a so-called negative photosensitive resin, whose solubility decreases in exposed areas, as the resist mask 25. It is also preferable that the resist mask 25 has no sensitivity in a specific wavelength range. In particular, it is preferable that the resist mask 25 has no sensitivity in the wavelength range of visible light or X-rays.

[0267] Next, the film 29f is observed through the resist mask 25, and one grain 29a that meets certain requirements is extracted from among the multiple grains 29a contained within a predetermined range of the film 29f, and its coordinates are identified. These requirements include size, shape, and position. It is preferable that the shape of the grain 29a at least fits within the minimum irradiation area of ​​the exposure device used in the subsequent exposure process. At this time, if the resist mask 25 is not sensitive to the wavelength range of visible light (i.e., is translucent), an observation method using visible light can be applied.

[0268] The extraction of the grains 29a and the identification of their coordinates are preferably performed using an optical microscope using visible light. It is preferable to use images captured by a camera mounted on the optical microscope, rather than visual inspection, because this allows for automatic extraction of grains 29a that meet the requirements through image analysis. Image analysis can be performed using a pattern matching method or an analysis method using AI (artificial intelligence).

[0269] Here, to clarify the shape of the grains 29a, wet etching may be performed to etch away some of the grain boundaries. Furthermore, by utilizing differences in etching rate resulting from differences in crystal orientation, the heights of the multiple grains 29a can be made uneven, thereby clarifying the shape of the grains 29a. For example, when a metal oxide film such as indium oxide or IGZO is used for the film 29f, it is preferable to use, for example, a developer, a tetramethylammonium hydroxide (TMAH) aqueous solution, dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a mixed solution containing two or more of these. The chemical solution used for etching can be either acidic or alkaline. Furthermore, using a diluted aqueous solution of these chemicals can reduce the etching rate, thereby preventing the target grains from disappearing.

[0270] In addition to the optical microscope, the crystal orientation of the grains 29a may be identified by XRD analysis using X-rays. When forming multiple island-shaped semiconductor layers 30 within a substrate, aligning the crystal orientations of the grains 29a used as seed crystals can align the crystal orientations of the respective semiconductor layers 30, which may reduce variations in the electrical characteristics of the transistors due to variations in crystal orientation. Note that if the crystal orientation can be estimated using the AI, XRD analysis may not be necessary.

[0271] Next, exposure and development processes are performed. Light 27 is irradiated onto the region inside the identified grain 29a, and the portion of the resist mask 25 located above the region is exposed to light (FIG. 12(B)). A development process is then performed to form a resist mask 25m on the specific grain 29a (FIG. 12(C)). The light 27 is light in a wavelength range to which the resist mask 25 is sensitive, and light in the wavelength range of visible light or ultraviolet light can be used. At this time, it is preferable that the region irradiated with light 27 does not include grain boundaries 29b. Because grain boundaries 29b are regions with many defects, avoiding grain boundaries 29b can prevent defects from being included in the layer 29 to be formed later.

[0272] Subsequently, the portions of the film 29f that are not covered by the resist mask 25m are removed by etching, thereby forming island-shaped layers 29 (FIG. 12(D)). The layer 29 thus formed is a part of one grain 29a, and therefore has a single-crystal structure. Dry etching or wet etching can be used for the etching.

[0273] Thereafter, similarly to the above, a semiconductor layer 30 is formed to cover the layer 29, thereby forming a single-crystal semiconductor layer 30 (FIG. 12(E)). FIG. 12(F) is a schematic cross-sectional view of a region including the layer 29 in FIG. 12(E).

[0274] Here, it is preferable to use the same metal oxide for the semiconductor layer 30 and the layer 29. This allows the semiconductor layer 30 to grow homoepitaxially using the layer 29 as a seed or nucleus. At this time, the crystal orientation of the layer 29 and the crystal orientation of the semiconductor layer 30 coincide with each other.

[0275] Thereafter, a part of the semiconductor layer 30 may be removed by etching to form an island-shaped semiconductor layer 30 (FIG. 12(G)). FIG. 12(G) shows the case where the layer 29 is also removed by etching.

[0276] In this manner, it is possible to form a single-crystal semiconductor layer 30. Using the semiconductor layer 30 formed in this manner, a transistor having both a large on-state current and high reliability can be manufactured.

[0277] Note that a single-crystal semiconductor film may be formed by using the single-crystal semiconductor layer 30 thus formed as a seed crystal and forming an additional semiconductor film to cover the semiconductor layer 30. For example, if the layer 29 contains an element different from that of the semiconductor layer 30, the element may diffuse into the semiconductor layer 30 as an impurity. Therefore, by using a part of a region of the semiconductor layer 30 away from the layer 29 as a seed crystal and crystallizing a semiconductor film having the same composition as the semiconductor layer 30, a single-crystal semiconductor film with a low impurity concentration and high purity can be obtained.

[0278] <Example 3 of manufacturing method of semiconductor device> Although the above describes a method for manufacturing a crystalline semiconductor layer 30 by forming the semiconductor layer 30 on the core layer 29, the method is not limited to this. Below, an example of forming the core layer 29 on the semiconductor layer 30 will be described.

[0279] First, a semiconductor layer 30a is formed on the insulating layer 20 (FIG. 13(A)). The semiconductor layer 30a is a film with low crystallinity, such as an amorphous film or a microcrystalline film. The semiconductor layer 30a can be formed as a film with low crystallinity by, for example, forming the semiconductor layer 30a under conditions of low substrate temperature during film formation (e.g., less than 150°C, 100°C or less, 50°C or less, or room temperature). Furthermore, when the semiconductor layer 30a is formed by a sputtering method, crystallization during film formation can be suppressed by using a gas with a low oxygen ratio (e.g., 5% or less, preferably 0%) as the film formation gas during film formation, thereby forming a semiconductor layer 30a with low crystallinity.

[0280] Next, an island-shaped layer 29 is formed on the semiconductor layer 30a (FIG. 13(B)). The layer 29 has a single crystal structure. Note that, in FIG. 13(B), the contour shape of the layer 29 in a plan view is shown as a hexagon, but is not limited to this and may be any shape, such as a polygon other than a hexagon, a circle, or an ellipse.

[0281] Layer 29 can be formed, for example, by forming a polycrystalline film using the method exemplified in the above-mentioned Example Fabrication Method 2, and then etching away the remaining portions while leaving behind some of the specific grains.

[0282] When forming a polycrystalline film as layer 29, it is preferable to perform film formation under conditions where the substrate temperature is as low as possible (for example, below 150°C, preferably below 100°C). This prevents the semiconductor layer 30a from crystallizing and forming polycrystals during the formation of layer 29. When forming layer 29 by a sputtering method, layer 29 with higher crystallinity than semiconductor layer 30a can be formed by using a gas with a high oxygen ratio (for example, 10% or more, preferably 20% or more, more preferably 30% or more) as the film formation gas during film formation.

[0283] It is also preferable to use a method that minimizes the amount of heat applied during etching. For example, wet etching can be used to process the film at low temperatures, suppress etching damage, and form a layer 29 with fewer defects.

[0284] Alternatively, layer 29 may be formed by sputtering using a shielding mask such as a metal mask. This allows island-shaped layer 29 to be formed at desired locations. This method omits the film processing step, thereby simplifying the process. In this case, by using a polycrystalline sputtering target, minute particles (also called pellets) having a single-crystal structure that reflects the crystal structure of the sputtering target can be attached to specific locations on semiconductor layer 30a, and these can also be used as layer 29.

[0285] Subsequently, by performing a heat treatment, the semiconductor layer 30a is crystallized using the layer 29 as a seed crystal, thereby obtaining a single-crystal semiconductor layer 30 (FIG. 13(C)). For the heat treatment method, the description of the first heat treatment can be referred to.

[0286] Thereafter, unnecessary portions of the semiconductor layer 30 and the layer 29 are removed by etching to obtain island-shaped semiconductor layers 30 (FIG. 13(D)). Note that the layer 29 may not be removed.

[0287] In this manner, it is possible to form a single-crystal semiconductor layer 30. Using the semiconductor layer 30 formed in this manner, a transistor having both a large on-state current and high reliability can be manufactured.

[0288] [Application example] By using the method for forming a metal oxide layer of one embodiment of the present invention, a large-area semiconductor layer 30 can be formed. This enables mass production of transistors using the semiconductor layer 30 and semiconductor chips using the same with high yield. Hereinafter, a method for manufacturing a semiconductor chip 81 will be described with reference to FIGS.

[0289] 14(A) shows a schematic perspective view of a substrate 70. As shown in FIG. 14(A), a layer 29 is formed near the outer periphery of the substrate 70, and then a semiconductor layer 30 is formed over the entire surface of the substrate 70 so as to cover the layer 29. As a result, as shown in FIG. 14(B), crystal growth progresses using the layer 29 as a seed crystal, and a single-crystal or polycrystalline semiconductor layer 30 with a uniform crystal orientation can be formed over the entire surface of the substrate 70. More specifically, the crystal orientation of the layer 29 is <001> If <111> It is possible to form a semiconductor layer 30 containing crystals whose orientation is perpendicular to the upper surface of the substrate 70. In Fig. 14(B), a scribe line 85 is indicated by a dashed line. The layer 29 is preferably provided at a position overlapping the scribe line 85.

[0290] A silicon wafer can typically be used as the substrate 70. Other examples include insulating substrates such as glass substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (yttria-stabilized zirconia substrates), and semiconductor substrates such as germanium substrates, silicon carbide substrates, silicon germanium substrates, gallium arsenide substrates, indium phosphide substrates, zinc oxide substrates, and gallium oxide substrates. The substrate 70 may have a diameter of, for example, 3 inches, 5 inches, 8 inches, or 12 inches. Even when a large substrate such as a 12-inch substrate is used, a semiconductor layer 30 with good crystallinity can be obtained, thereby improving productivity.

[0291] Thereafter, transistors having the semiconductor layer 30, wiring, electrodes, and the like are formed, thereby forming a plurality of semiconductor chips 81. Subsequently, as shown in Fig. 14(D), the substrate 70 on which the semiconductor chips 81 have been formed is cut along scribe lines 85, thereby separating the plurality of semiconductor chips 81. At this time, by arranging the layer 29 in a position overlapping the scribe lines 85, it is possible to configure the semiconductor chips 81 so that the layer 29 does not remain in the semiconductor chips 81.

[0292] The layer 29 may be provided outside the scribe line 85. The number of layers 29 is not limited to one, and two or more layers 29 may be provided. For example, a plurality of layers 29 may be provided at equal intervals, and each of the plurality of layers 29 may be arranged to overlap the scribe line 85.

[0293] 14(C) shows a schematic cross-sectional view of the semiconductor layer 30 shown in FIG. 14(B) at the stage after formation. Layer 29 is provided at a position overlapping with scribe line 85, and semiconductor layer 30 is formed to cover layer 29. Semiconductor layer 30 is formed along the side and bottom surfaces of opening 91 provided in insulating layer 20. Semiconductor layer 30 is also provided to cover structure 83 formed on insulating layer 20. In this way, even when semiconductor layer 30 is provided to cover the uneven shape on substrate 70, it can be a single-crystal or polycrystalline film with a uniform crystal orientation as described above.

[0294] Examples of the structure 83 include a wiring, an electrode, and a convex portion of the insulating layer 20. The structure 83 may also be a component of a transistor having a different structure from the transistor provided in the opening 91.

[0295] This embodiment mode can be combined with other embodiments or examples as appropriate. In addition, in this specification, when multiple configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0296] (Embodiment 2) In this embodiment, a semiconductor device to which the configuration described in the first embodiment is applied will be described.

[0297] <Configuration Example 1 of Semiconductor Device> Structural examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0298] FIG. 15(A) is a plan view of a semiconductor device having a transistor 200. FIG. 15(B) is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 15(A), and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 15(C) is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 15(A), and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 15(D) is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 15(A). Note that some elements are omitted in the plan view of FIG. 15(A) for clarity. Some elements may also be omitted in the subsequent plan views.

[0299] The transistor 200 includes a conductive layer 205, an insulating layer 221 on the conductive layer 205, an insulating layer 222 on the insulating layer 221, an insulating layer 224 on the insulating layer 222, a layer 229 on the insulating layer 224, a semiconductor layer 230 covering the layer 229, conductive layers 242a and 242b on the semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0300] The insulating layer 224, the semiconductor layer 230, the layer 229, the insulating layer 250, and the conductive layer 260 correspond to the insulating layer 20, the semiconductor layer 30, the layer 29, the insulating layer 50, and the conductive layer 60, respectively, described in Embodiment 1. Therefore, the structures (materials, film thicknesses, etc.), formation methods, etc. of the insulating layer 224, the semiconductor layer 230, the layer 229, the insulating layer 250, and the conductive layer 260 can refer to the structures, formation methods, etc. of the insulating layer 20, the semiconductor layer 30, the layer 29, the insulating layer 50, and the conductive layer 60, described in Embodiment 1. The conductive layer 205 corresponds to the conductive layer 15 described in Embodiment 1. The conductive layers 242a and 242b correspond to the conductive layers 40a and 40b, respectively, described in Embodiment 1.

[0301] In the transistor 200, the conductive layer 260 functions as a first gate electrode (which can also be referred to as an upper gate electrode or a top gate electrode), and the insulating layer 250 functions as a first gate insulating layer. The conductive layer 205 functions as a second gate electrode (which can also be referred to as a lower gate electrode or a bottom gate electrode), and the insulating layers 224, 222, and 221 each function as a second gate insulating layer. The conductive layer 242a functions as one of a source electrode and a drain electrode, and the conductive layer 242b functions as the other of the source electrode and the drain electrode.

[0302] An insulating layer 275 is provided on the conductive layer 242a and the conductive layer 242b, and an insulating layer 280 is provided on the insulating layer 275. An opening 289 is formed in the insulating layer 280 and the insulating layer 275, reaching the insulating layer 222 and the semiconductor layer 230, and the opening 289 overlaps the region between the conductive layer 242a and the conductive layer 242b. In a plan view, the side surface of the insulating layer 280 in the opening 289 coincides or substantially coincides with the side surface of the conductive layer 242a and the side surface of the conductive layer 242b. The insulating layer 280 corresponds to the insulating layer 80 described in the first embodiment.

[0303] The insulating layer 250 and the conductive layer 260 are disposed inside the opening 289. An insulating layer 282 is provided in contact with the upper surface of the insulating layer 280, the upper end of the insulating layer 250, and the upper surface of the conductive layer 260. An insulating layer 283 is provided on the insulating layer 282. An insulating layer 216 is provided under the insulating layer 221, an insulating layer 214 is provided under the insulating layer 216 and the conductive layer 205, and an insulating layer 212 is provided under the insulating layer 214. The insulating layer 212 is provided on a substrate (not shown). The substrate corresponds to the substrate 10 described in Embodiment 1. The insulating layer 212, the insulating layer 214, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0304] An opening reaching the conductive layer 242a is formed in the insulating layers 285, 283, 282, 280, and 275, and the conductive layer 243a and the insulating layer 241a are provided in the opening. The insulating layer 241a is provided in contact with the sidewall of the opening, and the conductive layer 243a is provided inside the insulating layer 241a. An opening reaching the conductive layer 242b is formed in the insulating layers 285, 283, 282, 280, and 275, and the conductive layer 243b and the insulating layer 241b are provided in the opening. The insulating layer 241b is provided in contact with the sidewall of the opening, and the conductive layer 243b is provided inside the insulating layer 241b. The conductive layer 243a and the conductive layer 243b function as vias that connect wiring or the like provided on the transistor 200 to the source or drain of the transistor 200.

[0305] The semiconductor layer 230 includes a channel formation region and a source region and a drain region sandwiching the channel formation region, as in the transistor 200. That is, the semiconductor layer 230 has a channel formation region, a source region, and a drain region. At least a part of the channel formation region overlaps with the conductive layer 260. The source region overlaps with the conductive layer 242a, and the drain region overlaps with the conductive layer 242b. Note that the source region and the drain region can be interchanged. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. The semiconductor layer 230 may have a single-layer structure or a stacked structure of two or more layers.

[0306] The semiconductor layer 230 is physically separated between adjacent transistors 200 in the channel length direction. This configuration can prevent the Row Hammer effect and the Passing Gate effect when the transistor 200 is used in a memory cell. The Row Hammer effect refers to a phenomenon in which, in a configuration in which the word lines (conductive layers 260) of two transistors are adjacent and the channel formation regions of the two transistors are connected, accumulated charge leaks to the adjacent word line, causing malfunction. The Passing Gate effect refers to a phenomenon in which charge moves to a floating gate or gate insulating layer, resulting in the formation of an unintended current path or a change in characteristics such as threshold voltage fluctuation.

[0307] 15A to 15D, the opening where the conductive layer 243a is provided is located so as not to overlap with the layer 229. In addition, the conductive layer 243a is provided so as to be located between the layer 229 and the conductive layer 260 in a plan view. With this structure, the shape of the opening can be improved. Therefore, contact defects can be suppressed, and a highly reliable semiconductor device can be provided.

[0308] 15A and 15B show an example in which the layer 229 is located on the line connecting the conductive layers 243a and 243b, but the present invention is not limited to this structure. For example, as shown in FIGS. 16A to 16D, the layer 229 may be located off the line connecting the conductive layers 243a and 243b. Even with this structure, contact failure can be suppressed, and a highly reliable semiconductor device can be provided. Note that FIGS. 16A to 16D are plan views and cross-sectional views of a semiconductor device including a transistor 200, and correspond to the plan views and cross-sectional views shown in FIGS. 15A to 15D, respectively.

[0309] 15A and 15B show an example in which the opening where the conductive layer 243a is provided is provided so as not to overlap with the layer 229, but the present invention is not limited to this structure. For example, as shown in FIGS. 17A to 17D, a structure in which the opening where the conductive layer 243a is provided overlaps with the layer 229 may be used. This structure enables miniaturization and high integration of the semiconductor device. Note that FIGS. 17A to 17D are plan views and cross-sectional views of a semiconductor device including a transistor 200, and correspond to the plan views and cross-sectional views shown in FIGS. 15A to 15D, respectively.

[0310] 18 to 19C are enlarged cross-sectional views of the transistor 200 shown in FIGS. 17A to 17D in the channel length direction.

[0311] By providing an insulating layer containing excess oxygen near the oxide semiconductor layer and performing heat treatment, oxygen can be supplied from the insulating layer to the oxide semiconductor layer, thereby reducing oxygen vacancies. However, excessive oxygen supplied to the source or drain region may reduce the on-state current or field-effect mobility of the transistor 200. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, excessive oxygen supplied from the insulating layer to the oxide semiconductor layer may adversely affect the electrical characteristics and reliability of the transistor. Furthermore, oxygen may diffuse into conductive layers such as the gate electrode, source electrode, and drain electrode, oxidizing the conductive layers and impairing their conductivity.

[0312] First, it is preferable to form at least one of an insulating layer having a barrier property against hydrogen and an insulating layer having a function of capturing or fixing hydrogen near the semiconductor layer 230, thereby reducing the hydrogen concentration in the channel formation region of the semiconductor layer 230 and its vicinity.

[0313] At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against hydrogen. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against impurities. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against oxygen. Note that all of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 do not necessarily have to be provided. As long as the insulating layer has sufficient barrier properties against hydrogen, impurities, oxygen, and the like, the insulating layer can be formed by appropriately selecting from the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283. For example, the insulating layer 214 may not be provided, and the insulating layer 216 and the conductive layer 205 may be formed in contact with the upper surface of the insulating layer 212.

[0314] The insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 preferably have a function of suppressing diffusion of hydrogen. For example, the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 may be formed using silicon nitride, which has a high hydrogen barrier property.

[0315] The insulating layer 214, the insulating layer 222, and the insulating layer 282 preferably have a function of capturing or fixing hydrogen. For example, aluminum oxide may be used for the insulating layer 214 and the insulating layer 282. For example, hafnium oxide, which is a high-k material, is preferably used for the insulating layer 222, which functions as the second gate insulating layer.

[0316] 18, by providing the insulating layer 212 having the function of suppressing hydrogen diffusion under the transistor 200, it is possible to suppress diffusion of hydrogen from the layer below the transistor 200. Furthermore, by providing the insulating layer 214 having the function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 216 or the like can be captured or fixed in the insulating layer 214. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0317] Furthermore, by providing the insulating layer 221 having a function of suppressing hydrogen diffusion under the semiconductor layer 230, it is possible to suppress diffusion of hydrogen from below the semiconductor layer 230. Furthermore, by providing the insulating layer 222 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 224 or the like can be captured or fixed in the insulating layer 222. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0318] Furthermore, by providing an insulating layer 275 having the function of suppressing the diffusion of hydrogen so as to cover the semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc., it is possible to suppress the diffusion of hydrogen from the insulating layer 280 to the semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc.

[0319] Furthermore, by providing the insulating layer 283 having a function of suppressing hydrogen diffusion over the transistor 200, it is possible to suppress diffusion of hydrogen from above the transistor 200. Furthermore, by providing the insulating layer 282 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 280 or the like can be captured or fixed to the insulating layer 282. This allows the hydrogen concentration in the semiconductor layer 230 and its vicinity to be reduced.

[0320] In this manner, by surrounding the transistor 200 from above and below with barrier insulating layers against hydrogen, diffusion of hydrogen into the oxide semiconductor can be reduced, and the hydrogen concentration in the channel formation region can be reduced, thereby improving the electrical characteristics and reliability of the transistor 200.

[0321] Furthermore, excess oxygen is preferably contained in the insulating layer 280. By supplying the oxygen to the semiconductor layer 230 through the insulating layer 250 by heat treatment, oxygen vacancies in the channel formation region can be reduced.

[0322] The insulating layer 282 is preferably formed by a sputtering method in an atmosphere containing oxygen gas, which allows oxygen to be added to the insulating layer 280. The insulating layer 282 may have a single-layer structure or a stacked structure of two or more layers.

[0323] As described above, by performing heat treatment on the insulating layer 280 containing excess oxygen, a suitable amount of oxygen can be supplied to the semiconductor layer 230 through the insulating layer 250. In the heat treatment, the insulating layers 282 and 283, which have a barrier property against oxygen, are formed on the insulating layer 280, so that the oxygen contained in the insulating layer 280 can be prevented from diffusing excessively from the insulating layer 280. Furthermore, the insulating layer 275, which has a barrier property against oxygen, is formed between the insulating layer 280 and the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b, so that the oxygen contained in the insulating layer 280 can be prevented from diffusing excessively from the insulating layer 280. Furthermore, by performing the heat treatment with openings formed in parts of the insulating layer 280, the insulating layer 282, and the insulating layer 283, part of the oxygen contained in the insulating layer 280 can be diffused outward, and the amount of oxygen supplied from the insulating layer 280 to the semiconductor layer 230 can be adjusted.

[0324] FIG. 18 shows an example in which the semiconductor layer 230 has a single-layer structure. The semiconductor layer 230 can have a stacked structure of two or more layers. As shown in FIG. 19(A), the semiconductor layer 230 can have a two-layer structure of a semiconductor layer 230_1 and a semiconductor layer 230_2 on the semiconductor layer 230_1. The semiconductor layer 230_1 and the semiconductor layer 230_2 correspond to the first semiconductor layer and the second semiconductor layer described in Embodiment 1, respectively. Therefore, the structures (materials, film thicknesses, etc.), formation methods, etc. of the semiconductor layer 230_1 and the semiconductor layer 230_2 can refer to the structures, formation methods, etc. of the first semiconductor layer and the second semiconductor layer described in Embodiment 1.

[0325] 19(A) illustrates a configuration in which the insulating layer 250 is in contact with the upper surface of the semiconductor layer 230_2, but the present invention is not limited to this. For example, as shown in FIG. 19(B), it is possible to remove the semiconductor layer 230_2 in a region overlapping with the opening 289, and have the insulating layer 250 in contact with the side surface of the semiconductor layer 230_2 and the upper surface of the semiconductor layer 230_1. With this configuration, the distance between the conductive layer 260 and the semiconductor layer 230_1 can be shortened. Therefore, an electric field from the gate electrode can be suitably applied to the semiconductor layer 230_1.

[0326] The insulating layer 250 preferably has a structure that allows oxygen to diffuse from the insulating layer 280 to the semiconductor layer 230 and prevents the conductive layers 242a, 242b, and 260 from being oxidized.

[0327] Insulating layer 250 is formed within opening 289 in contact with the top surface of insulating layer 222, the side surface of insulating layer 224, the side surface and top surface of semiconductor layer 230, the side surface of conductive layer 242a, the side surface of conductive layer 242b, the side surface of insulating layer 275, and the side surface of insulating layer 280.

[0328] 17B shows an example in which the insulating layer 250 has a single layer structure. Note that the insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed using two or more types of films. By using two or more types of films for the insulating layer 250, the insulating layer 250 can have multiple functions. Examples of the functions of the insulating layer 250 include a function of extracting excess oxygen from the semiconductor layer 230, a function of extracting hydrogen from the semiconductor layer 230, and a function of suppressing diffusion of hydrogen into the semiconductor layer 230.

[0329] For example, as shown in FIG. 18, the insulating layer 250 preferably has a laminated structure of an insulating layer 250_1 in contact with the semiconductor layer 230, an insulating layer 250_2 on the insulating layer 250_1, and an insulating layer 250_3 on the insulating layer 250_2.

[0330] The insulating layer 250_1 can be formed using any of the materials applicable to the insulating layer 50. For example, the insulating layer 250_1, which has regions in contact with the side surfaces of the conductive layer 242a and the conductive layer 242b, has a function of capturing or fixing oxygen, thereby preventing the side surfaces of the conductive layer 242a and the conductive layer 242b from being oxidized and forming an oxide film on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200. Furthermore, this structure can reduce the amount of oxygen in the insulating layer 250_2 absorbed by the conductive layer 242a and the conductive layer 242b. Therefore, an appropriate amount of oxygen can be supplied from the insulating layer 250_2 to the semiconductor layer 230, thereby reducing oxygen vacancies in the channel formation region of the semiconductor layer 230.

[0331] Furthermore, by providing the insulating layer 250_1 between the insulating layer 280 and the insulating layer 250_2 and between the insulating layer 250_2 and the semiconductor layer 230, excessive supply of oxygen from the insulating layer 280 to the semiconductor layer 230 can be suppressed, and an appropriate amount of oxygen can be supplied to the semiconductor layer 230. Therefore, the amount of oxygen in the channel formation region of the semiconductor layer 230 and its vicinity can be controlled to an appropriate amount, which can prevent the transistor 200 from becoming excessively normally off and improve reliability. In addition, excessive oxidation of the source and drain regions can be suppressed, which can cause a decrease in on-state current or a decrease in field-effect mobility of the transistor 200.

[0332] The above-described structure allows the channel formation region to be i-type or substantially i-type, and the source and drain regions to be n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, the above-described structure allows the semiconductor device to have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0333] Furthermore, a high-k material can be used for the insulating layer 250_1. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. By using a high-k material for the insulating layer 250_1, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It is also possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0334] For the above reasons, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulating layer 250_1, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Aluminum oxide having an amorphous structure is preferably used because an amorphous film can be formed relatively easily using the ALD method. Aluminum oxide has the function of capturing or fixing oxygen and hydrogen, and is therefore suitable for the insulating layer 250_1. Alternatively, hafnium oxide has a high function of capturing or fixing oxygen and hydrogen, and is therefore suitable for the insulating layer 250_1.

[0335] For example, the insulating layer 250_2 is preferably formed using a material with a low relative dielectric constant, such as a silicon oxide film or a silicon oxynitride film.

[0336] Silicon oxide or silicon nitride is an insulating material with high dielectric strength. This can reduce the leakage current of a transistor. Furthermore, a silicon oxide film or a silicon oxynitride film is also a film with high hydrogen permeability. Therefore, the insulating layer 250 may have a three-layer structure including an insulating layer 250_2, an insulating layer 250_1 on the insulating layer 250_2, and an insulating layer 250_3 on the insulating layer 250_1. With this structure, hydrogen in the semiconductor layer 230 can diffuse into the insulating layer 250_1 through the insulating layer 250_2 and be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0337] The insulating layer 250_3 preferably has a barrier property against hydrogen. With such a structure, diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Furthermore, the insulating layer 250_3 preferably has a barrier property against oxygen. The insulating layer 250_3 is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260. With such a structure, oxygen contained in the channel formation region of the semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the semiconductor layer 230. Furthermore, oxygen contained in the semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The insulating layer 250_3 is preferably at least less permeable to oxygen than the insulating layer 250_2. Furthermore, the insulating layer 250_3 preferably has a function of suppressing diffusion of hydrogen. This can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230. For example, silicon nitride is preferably used as the insulating layer 250_3.

[0338] The insulating layer 250 can have, for example, a three-layer structure in which a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. The thicknesses of the hafnium oxide film, the silicon oxide film, and the silicon nitride film are 2 nm, 2 nm, and 1 nm, respectively. This configuration allows excess oxygen in the semiconductor layer 230 to be discharged to the insulating layer 250, thereby reducing the amount of excess oxygen in the semiconductor layer 230. Furthermore, hydrogen in the semiconductor layer 230 can be captured or fixed. This improves the electrical characteristics and reliability of the transistor 200. The insulating layer 250 can also have, for example, a three-layer structure in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side.

[0339] 19(C), an insulating layer 250_4 may be provided over the insulating layer 250_2. The insulating layer 250_4 may be formed using an insulating material that can be used for the insulating layer 250_1. For example, by providing the insulating layer 250_4 having a function of capturing or fixing hydrogen between the insulating layer 250_3 and the insulating layer 250_2, hydrogen contained in the insulating layer 250_2 or the like can be captured or fixed.

[0340] Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. With this structure, hydrogen in the semiconductor layer 230 can be diffused into the insulating layer 250_1 or the insulating layer 250_4 and captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0341] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to be 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as the S value) can be reduced. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0342] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0343] Note that the insulating layer 250 having a four-layer structure may not include the insulating layer 250_3. For example, an insulating layer having a function of capturing or fixing oxygen may be used as the insulating layer 250_1, an insulating layer made of a material with a low dielectric constant may be used as the insulating layer 250_2, and an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 250_4. Specifically, the insulating layer 250 may have a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the semiconductor layer 230 side.

[0344] In order to thin the insulating layers 250_1 to 250_4 as described above, it is preferable to form the insulating layers 250_1 to 250_4 by the ALD method. In addition, in order to form the insulating layers 250_1 to 250_4 in the opening 289 with good coverage, it is preferable to form the insulating layers 250_1 to 250_4 by the ALD method.

[0345] It is preferable to use the ALD process two or more times in forming the insulating layer 250 having a stacked structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, for example, it is possible to increase productivity by successively forming two or more types of insulating films using the ALD process.

[0346] Although the insulating layer 250 has been described above as having a three-layer structure or a four-layer structure, the present invention is not limited to this. The insulating layer 250 can have a structure including at least one of the insulating layers 250_1 to 250_4. By configuring the insulating layer 250 as one, two, or three of the insulating layers 250_1 to 250_4, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0347] The conductive layer 205 is disposed so as to overlap with the semiconductor layer 230 and the conductive layer 260. The conductive layer 205 can be formed using a conductive material described in the later section [Conductive Layer]. Here, the conductive layer 205 is provided so as to be embedded in an opening formed in the insulating layer 216. The conductive layer 205 is preferably provided so as to extend in the channel width direction as shown in FIGS. 17(A) and 17(C). With such a structure, the conductive layer 205 functions as a wiring when a plurality of transistors are provided.

[0348] 18, the conductive layer 205 preferably includes a conductive layer 205_1 and a conductive layer 205_2. The conductive layer 205_1 is provided in contact with the bottom surface and sidewall of the opening. The conductive layer 205_2 is provided so as to fill a recess in the conductive layer 205_1 formed along the opening. Here, the height of the upper surface of the conductive layer 205 coincides or substantially coincides with the height of the upper surface of the insulating layer 216.

[0349] Here, the conductive layer 205_1 preferably includes a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it preferably includes a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0350] By using a conductive material that can reduce hydrogen diffusion for the conductive layer 205_1, impurities such as hydrogen contained in the conductive layer 205_2 can be prevented from diffusing into the semiconductor layer 230 via the insulating layer 216 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductive layer 205_1, it is possible to prevent the conductive layer 205_2 from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205_1 can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 205_1 preferably contains titanium nitride.

[0351] The conductive layer 205_2 is preferably made of a conductor with high conductivity. For example, the conductive layer 205_2 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 205_2 preferably contains tungsten.

[0352] The conductive layer 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. In particular, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential applied to the conductive layer 260 is 0 V compared to not applying a negative potential to the conductive layer 205.

[0353] 18 shows a stacked structure of the conductive layer 205_1 and the conductive layer 205_2, the present invention is not limited thereto, and the conductive layer 205 may have a single-layer structure or a stacked structure of three or more layers. For example, the conductive layer 205_1 may have a two-layer structure of a tantalum nitride film and a titanium nitride film on the tantalum nitride film, and the conductive layer 205_2 having a tungsten film may be provided on the conductive layer 205_1. With such a structure, impurities such as hydrogen and metal impurities such as copper contained in the lower layer of the transistor 200 can be prevented from diffusing into the conductive layer 205.

[0354] The insulating layer 224, together with the insulating layer 221 and the insulating layer 222, functions as a second gate insulating layer.

[0355] The insulating layer 224 preferably includes, for example, a silicon oxide film or a silicon oxynitride film. This allows oxygen to be supplied from the insulating layer 224 to the semiconductor layer 230, thereby reducing oxygen vacancies. Note that the insulating layer 224 may have a stacked structure of two or more layers. In this case, the insulating layer 224 is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0356] The insulating layer 224 is preferably processed into an island shape, similar to the semiconductor layer 230. Thus, when a plurality of transistors 200 are provided, each transistor 200 has an insulating layer 224 of approximately the same size. As a result, the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 in each transistor 200 becomes approximately the same. Therefore, variation in the electrical characteristics of the transistors 200 within the substrate surface can be suppressed.

[0357] Furthermore, by providing the insulating layer 224 in an island shape, at least a part of the lower surface of the conductive layer 260 can be provided below the lower surface of the semiconductor layer 230 (see FIG. 17C). This allows the conductive layer 260 to be provided facing the upper surface and side surface of the semiconductor layer 230, and therefore the electric field of the conductive layer 260 can be applied to the upper surface and side surface of the semiconductor layer 230.

[0358] However, the insulating layer 224 does not necessarily have to be processed into an island shape. For example, as shown in Figures 20(A) to 20(D), the insulating layer 224 may not be formed into an island shape, but may have a shape in which an opening is formed in a part of it. Here, Figures 20(A) to 20(D) correspond to Figures 17(A) to 17(D), respectively, and are similar to Figures 17(A) to 17(D) except that the shape of the insulating layer 224 is different.

[0359] 20(A) to 20(D), the thickness of the insulating layer 224 in a region that does not overlap with the semiconductor layer 230 is thinner than the thickness of the region that overlaps with the semiconductor layer 230. In addition, an opening is formed in a region that does not overlap with the semiconductor layer 230 and overlaps with the insulating layer 250. When multiple transistors are provided on the same substrate, by forming the insulating layer 224 in this manner, the semiconductor layer 230 of each transistor is formed on the same insulating layer 224. This can reduce variations in the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 of each transistor. Therefore, variations in the electrical characteristics of each transistor can be reduced.

[0360] In the insulating layer 224 shown in Figures 20(A) to 20(D), an opening is formed in a region that does not overlap with the semiconductor layer 230 and overlaps with the insulating layer 250; however, a structure without such an opening may be used.

[0361] The conductive layers 242a and 242b can be formed using the conductive materials described in the section "Conductive Layer" below. In particular, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion for the conductive layers 242a and 242b. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 242a and 242b.

[0362] For the conductive layers 242a and 242b, it is preferable to use a metal nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. For example, tantalum nitride can be used for the conductive layers 242a and 242b. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, ITO, ITSO, or In-Zn oxide may also be used. These materials are preferable because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0363] Alternatively, each of the conductive layers 242a and 242b may have a stacked structure. In this case, the above-mentioned conductive material may be used for the lower layer (layer having a large contact area with the semiconductor layer 230) of the conductive layer 242a and the conductive layer 242b, and a conductive material with higher conductivity may be used for the upper layer of the conductive layer 242a and the conductive layer 242b. For example, tantalum nitride may be used for the lower layer, and tungsten may be used for the upper layer. Alternatively, ITO or ITSO may be used for the lower layer, and tungsten may be used for the upper layer.

[0364] The conductive layer 260 is provided in the opening 289 so as to cover the upper surface of the insulating layer 222, the side surface of the insulating layer 224, and the side surface and upper surface of the semiconductor layer 230, via the insulating layer 250. The height of the upper surface of the conductive layer 260 is the same as or approximately the same as the height of the upper end of the insulating layer 250 and the height of the upper surface of the insulating layer 280.

[0365] The sidewall of the opening 289 may be perpendicular or approximately perpendicular to the upper surface of the insulating layer 222, or may be tapered. By tapering the sidewall, the coverage of the insulating layer 250 provided in the opening 289 is improved, and defects such as voids can be reduced.

[0366] 17A and 17C, the conductive layer 260 is preferably provided to extend in the channel width direction. With this structure, when a plurality of transistors are provided, the conductive layer 260 functions as a wiring.

[0367] 17(C), in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the semiconductor layer 230 and the top surface of the semiconductor layer 230. In other words, the end of the side surface and the end of the top surface may be curved.

[0368] 18, the conductive layer 260 preferably has a two-layer structure. Here, the conductive layer 260 preferably has a conductive layer 260_1 and a conductive layer 260_2 disposed on the conductive layer 260_1. For example, the conductive layer 260_1 is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 260_2.

[0369] For example, it is preferable to use titanium nitride for the conductive layer 260_1 and tungsten for the conductive layer 260_2. Alternatively, it is preferable to use tantalum nitride for the conductive layer 260_1 and copper for the conductive layer 260_2. With such a structure, the conductivity of the conductive layer 260 can be increased.

[0370] The conductive layer 260 may also have a stacked structure of three or more layers, such as a three-layer structure of a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0371] The insulating layer 216, the insulating layer 280, and the insulating layer 285 preferably have a lower relative dielectric constant than the insulating layer 222. By using a material with a low relative dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced.

[0372] For example, the insulating layer 216, the insulating layer 280, and the insulating layer 285 can each be made of a material with a low dielectric constant, as described in the "Insulating Layer" section below. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are also preferred because they allow for the easy formation of regions containing excess oxygen.

[0373] Furthermore, the upper surfaces of the insulating layer 216 and the insulating layer 280 may each be planarized.

[0374] It is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulating layer 280. For example, it is preferable that the insulating layer 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0375] The conductive layers 243a and 243b can be formed using a conductive material described in the "Conductive Layer" section below. The conductive layers 243a and 243b are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layers 243a and 243b may have a stacked structure.

[0376] 18, the conductive layer 243a and the conductive layer 243b may have a two-layer laminated structure. The conductive layer 243a has a conductive layer 243a1 formed along the opening and a conductive layer 243a2 formed inside the conductive layer 243a1. The conductive layer 243b has a conductive layer 243b1 formed along the opening and a conductive layer 243b2 formed inside the conductive layer 243b1.

[0377] The conductive layer 243a1 and the conductive layer 243b1 can be formed as a single layer or a stacked layer using a conductive material applicable to the conductive layer 205_1. By providing the conductive layer 243a1 and the conductive layer 243b1, impurities such as water and hydrogen can be prevented from entering the semiconductor layer 230 through the conductive layer 243a2 and the conductive layer 243b2. Note that the conductive layer 243a2 and the conductive layer 243b2 may be formed using a conductive material applicable to the conductive layer 243a and the conductive layer 243b.

[0378] 17(B), the height of the upper surfaces of the conductive layers 243a and 243b is the same or substantially the same as the height of the upper surface of the insulating layer 285. Furthermore, as shown in FIG. 18, the conductive layer 243a may be formed so that its lower portion is embedded in the conductive layer 242a. Similarly, the conductive layer 243b may be formed so that its lower portion is embedded in the conductive layer 242b.

[0379] The insulating layer 241a and the insulating layer 241b may be a barrier insulating layer applicable to the insulating layer 275 or the like. For example, silicon nitride may be used for the insulating layer 241a and the insulating layer 241b. The insulating layer 241a and the insulating layer 241b are provided in contact with the insulating layer 285, the insulating layer 283, the insulating layer 282, and the insulating layer 275. This can prevent impurities such as water and hydrogen contained in the insulating layer 280 or the like from being mixed into the semiconductor layer 230 through the conductive layer 243a and the conductive layer 243b. Silicon nitride is particularly suitable because it has a high barrier property against hydrogen. Furthermore, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layer 243a and the conductive layer 243b.

[0380] The insulating layer 241a and the insulating layer 241b may have a stacked structure. In this case, the first insulating layer in contact with the sidewall of the opening such as the insulating layer 280 and the second insulating layer on the inner side thereof preferably use a combination of a barrier insulating layer against oxygen and a barrier insulating layer against hydrogen.

[0381] [Variation 1] 17(B) and the like, the insulating layer 250 is in contact with the side surface of the insulating layer 280 in the opening 289, but the present invention is not limited to this configuration. For example, an insulating layer may be provided between the insulating layer 250 and the insulating layer 280 in the opening 289.

[0382] 21A to 22C will be used to describe modifications of the semiconductor device described with reference to FIGS. 17A to 17D. FIGS. 21A to 21D are plan views and cross-sectional views of a semiconductor device including a transistor 200, and correspond to the plan views and cross-sectional views shown in FIGS. 17A to 17D, respectively. FIGS. 22A to 22C are enlarged cross-sectional views of the transistor 200 in the channel length direction.

[0383] 21(A) to 21(D) differs from the transistor 200 shown in Figures 17(A) to 17(D) mainly in that it includes an insulating layer 254. Hereinafter, differences from the above description will be mainly described, and overlapping portions will be referred to and may not be described again.

[0384] 21(A) to 21(D), the conductive layer 242a and the conductive layer 242b are each shown as a two-layer structure. The conductive layer 242a has a stacked structure of a conductive layer 242a1 and a conductive layer 242a2 on the conductive layer 242a1. The conductive layer 242b has a stacked structure of a conductive layer 242b1 and a conductive layer 242b2 on the conductive layer 242b1. The conductive layers 242a1 and 242b1 correspond to the lower layers of the above-mentioned conductive layers 242a and 242b, respectively, and the conductive layers 242a2 and 242b2 correspond to the upper layers of the above-mentioned conductive layers 242a and 242b, respectively.

[0385] 21(B) and 21(C), the insulating layer 254 is disposed inside the opening 289 and contacts the side surface of the insulating layer 280, the side surface of the conductive layer 242a2, the side surface of the conductive layer 242b2, the top surface of the conductive layer 242a1, the top surface of the conductive layer 242b1, and the top surface of the insulating layer 222 in the opening 289. In other words, the insulating layer 254 can be said to be formed in the shape of a sidewall in contact with the side wall of the opening 289. Here, the side wall of the opening 289 corresponds to, for example, the side surface of the insulating layer 280, etc. in the opening 289.

[0386] The insulating layer 254 preferably has a barrier property against oxygen. The insulating layer 254 having a barrier property against oxygen can prevent the side surfaces of the conductive layers 242a and 242b from being oxidized and oxide films from being formed on the side surfaces. This can prevent a decrease in on-state current or a decrease in field-effect mobility of the transistor 200. An oxygen barrier insulating layer can be used as the insulating layer 254. For example, silicon nitride can be used as the insulating layer 254.

[0387] The opening 289 overlaps the region between the conductive layer 242a2 and the conductive layer 242b2. In a plan view, the side surfaces of the insulating layer 280 in the opening 289 coincide or substantially coincide with the side surfaces of the conductive layer 242a2 and the conductive layer 242b2. Furthermore, portions of the conductive layers 242a1 and 242b1 are formed to protrude into the opening 289. In other words, the portion of the conductive layer 242a1 on which the insulating layer 254 is formed (hereinafter, sometimes referred to as the protruding portion of the conductive layer 242a1) protrudes toward the conductive layer 260 more than the conductive layer 242a2. Similarly, the portion of the conductive layer 242b1 on which the insulating layer 254 is formed (hereinafter, sometimes referred to as the protruding portion of the conductive layer 242b1) protrudes toward the conductive layer 260 more than the conductive layer 242b2.

[0388] Here, a portion of the upper surface of conductive layer 242a1 contacts conductive layer 242a2, and a portion of the upper surface of conductive layer 242b1 contacts conductive layer 242b2. Therefore, inside opening 289, insulating layer 254 contacts another portion of the upper surface of conductive layer 242a1, another portion of the upper surface of conductive layer 242b1, a side surface of conductive layer 242a2, and a side surface of conductive layer 242b2. Furthermore, insulating layer 250 contacts the upper surface of semiconductor layer 230, the side surface of conductive layer 242a1, the side surface of conductive layer 242b1, and the side surface of insulating layer 254.

[0389] The insulating layer 254 is formed by anisotropic etching to have a sidewall shape in contact with the side wall of the opening 289. The insulating layer 254 is formed in contact with the side surface of the conductive layer 242a2 and the side surface of the conductive layer 242b2, and has a function of protecting the conductive layer 242a2 and the conductive layer 242b2.

[0390] 22A, in a cross-sectional view of the transistor 200, the side edges of the insulating layer 254 coincide with or substantially coincide with the side edges of the conductive layer 242a1 and the conductive layer 242b1.

[0391] Note that after the conductive layer 242a1 and the conductive layer 242b1 are separated, heat treatment is preferably performed in an atmosphere containing oxygen before the insulating layer 250 is formed. At this time, by forming the insulating layer 254 in contact with the side surfaces of the conductive layer 242a2 and the conductive layer 242b2, excessive oxidation of the conductive layer 242a2 and the conductive layer 242b2 can be prevented. Furthermore, even when microwave plasma treatment is performed after the conductive layer 242a1 and the conductive layer 242b1 are separated, formation of an oxide film on the side surfaces of the conductive layer 242a and the conductive layer 242b can be suppressed.

[0392] The insulating layer 254, the insulating layer 250, and the conductive layer 260 are provided to reflect the shape of the opening 289. Therefore, the insulating layer 254 is provided so as to cover the sidewall of the opening 289, the insulating layer 250 is provided so as to cover the bottom of the opening 289 and the insulating layer 254, and the conductive layer 260 is provided so as to fill the recess of the insulating layer 250.

[0393] As described above, the insulating layer 250 may have a stacked structure. For example, as shown in FIG. 22A, the insulating layer 250 may have a three-layer structure of insulating layers 250_1 to 250_3. Alternatively, as shown in FIG. 22B, the insulating layer 250 may have a four-layer structure of insulating layers 250_1 to 250_4.

[0394] The thickness of the insulating layer 254 is preferably 0.5 nm to 20 nm, more preferably 0.5 nm to 10 nm, and even more preferably 0.5 nm to 3 nm. By setting the insulating layer 254 to the above thickness, excessive oxidation of the conductive layer 242a2 and the conductive layer 242b2 can be suppressed. It is sufficient that at least a portion of the insulating layer 254 has a region with the above thickness. Furthermore, since the insulating layer 254 is provided in contact with the sidewall of the opening 289, it is preferable to form the insulating layer 254 using an ALD method or the like, which has good coverage. If the insulating layer 254 is too thick, the time required to form the insulating layer 254 by the ALD method increases, reducing productivity. Therefore, it is preferable to set the thickness of the insulating layer 254 to within the above range. The insulating layer 254 preferably has a thickness that does not excessively hinder the diffusion of excess oxygen from the insulating layer 280 to the insulating layer 250_2 and from the insulating layer 250_2 to the semiconductor layer 230.

[0395] As shown in FIG. 22A, in a cross-sectional view of the transistor 200 in the channel length direction, the distance L1 between the conductive layer 242a1 and the conductive layer 242b1 is smaller than the distance L2 between the conductive layer 242a2 and the conductive layer 242b2. Here, the distance L1 refers to the shortest distance between the conductive layer 242a1 and the conductive layer 242b1, and the distance L2 refers to the shortest distance between the conductive layer 242a2 and the conductive layer 242b2. This configuration allows for a shorter source-drain distance and a correspondingly shorter channel length. This improves the frequency characteristics of the transistor 200. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0396] 22A, the difference between distance L2 and distance L1 is equal to twice the film thickness of insulating layer 254. In other words, distance L2 is equal to or approximately equal to distance L1 obtained by adding twice the film thickness of insulating layer 254. Here, the film thickness of insulating layer 254 refers to the width of at least a portion of insulating layer 254 in the A1-A2 direction.

[0397] The insulating layer 254 may also have a stacked structure of two or more layers. In this case, at least one layer can be the inorganic insulating layer that is resistant to oxidation. For example, the first insulating layer of the insulating layer 254 may be the inorganic insulating layer that is resistant to oxidation, and the second insulating layer on the first insulating layer of the insulating layer 254 may be made of an insulating material (e.g., silicon oxide) that is applicable to the insulating layer 250_2. The second insulating layer of the insulating layer 254 preferably has a lower dielectric constant than the first insulating layer of the insulating layer 254. In this way, by forming the insulating layer 254 into a two-layer structure and increasing its film thickness, the distance between the conductive layer 260 and the conductive layer 242a or 242b can be increased, thereby reducing parasitic capacitance.

[0398] Although the above describes an example in which the insulating layer 254 is formed into a sidewall shape by anisotropic etching, the present invention is not limited to this. As shown in FIG. 22(C), the insulating layer 254 may have an opening inside the opening 289. In this case, the opening in the insulating layer 254 can be formed by removing a part of the insulating film that will become the insulating layer 254 by lithography. The opening in the insulating layer 254 preferably overlaps with the region between the conductive layer 242a1 and the conductive layer 242b1.

[0399] 22C, in a cross-sectional view, a protruding portion is formed at the lower portion of the insulating layer 254. The protruding portion of the insulating layer 254 overlaps with the protruding portion of the conductive layer 242a1 and the protruding portion of the conductive layer 242b1.

[0400] [Variation 2] In the first modification, the insulating layer 254 is provided in contact with the sidewall of the opening 289. However, the present invention is not limited to this configuration. For example, the insulating layer 254 may not be provided in the opening 289.

[0401] 23A to 24 will be used to describe modifications of the semiconductor device described in Modification 1. FIGS. 23A to 23D are plan views and cross-sectional views of a semiconductor device including a transistor 200, and correspond to the plan views and cross-sectional views shown in FIGS. 21A to 21D, respectively. FIG. 24 is an enlarged cross-sectional view of the transistor 200 in the channel length direction, and corresponds to the enlarged cross-sectional view shown in FIG.

[0402] 23(A) to 23(D) differs from the transistor 200 shown in Figures 21(A) to 21(D) mainly in that it does not have an insulating layer 254. Hereinafter, differences from the above description will be mainly described, and overlapping portions will be referred to and may not be described again.

[0403] 24, in a configuration in which the insulating layer 254 is not provided, a portion of the insulating layer 250 is disposed so as to overlap the protruding portions of the conductive layer 242a1 and the conductive layer 242b1. Also, a portion of the conductive layer 260 may be disposed so as to overlap the protruding portions of the conductive layer 242a1 and the conductive layer 242b1. Here, the protruding portions of the conductive layer 242a1 and the conductive layer 242b1 contact the insulating layer 250. Also, the side surface of the insulating layer 250 contacts the side surface of the insulating layer 280, the side surface of the insulating layer 275, the side surface of the conductive layer 242a2, and the side surface of the conductive layer 242b2.

[0404] The insulating layer 250 is formed to reflect the shape of the opening 289. Therefore, the insulating layer 250 is formed to reflect the shapes of the conductive layer 242a1 and the conductive layer 242b1 that protrude into the opening 289.

[0405] As shown in FIG. 24, in a cross-sectional view of the transistor 200 in the channel length direction, the distance L1 between the conductive layer 242a1 and the conductive layer 242b1 is smaller than the distance L2 between the conductive layer 242a2 and the conductive layer 242b2. This configuration allows the distance between the source and the drain to be shortened, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200. By miniaturizing the semiconductor device in this way, it is possible to provide a semiconductor device with improved operating speed.

[0406] 24, the width of the upper part of the conductive layer 260 can be made larger than the distance L1, thereby reducing the wiring resistance of the conductive layer 260. As a result, the power consumption of the semiconductor device can be reduced.

[0407] <Configuration Example 2 of Semiconductor Device> Structural examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0408] Fig. 25(A) is a plan view of a semiconductor device including a transistor 200A. Fig. 25(B) is a cross-sectional view of the portion indicated by the dashed line A1-A2 in Fig. 25(A) and is also a cross-sectional view of the transistor 200A in the channel length direction. Fig. 25(C) is a cross-sectional view of the portion indicated by the dashed line A3-A4 in Fig. 25(A) and is also a cross-sectional view of the transistor 200A in the channel width direction. Fig. 25(D) is a cross-sectional view of the portion indicated by the dashed line A5-A6 in Fig. 25(A).

[0409] 17(A) to 17(D) in that the side edges of the conductive layer 242a and the semiconductor layer 230 coincide or substantially coincide with each other, that the side edges of the conductive layer 242b and the semiconductor layer 230 coincide or substantially coincide with each other, that the transistor 200A includes the insulating layers 271a and 271b, and that the transistor 200A does not include the layer 229. Hereinafter, differences from the above description will be mainly described, and overlapping portions will be referred to and may not be described again.

[0410] The insulating layer 271a is provided over the conductive layer 242a, and the insulating layer 271b is provided over the conductive layer 242b.

[0411] The transistor 200A can be manufactured by, for example, the manufacturing method described with reference to FIGS. 11E to 11H. Specifically, a crystalline semiconductor layer 30 is formed, a conductive film that will become the conductive layers 242a and 242b is formed on the semiconductor layer 30, an insulating layer that will become the insulating layers 271a and 271b is formed on the conductive film, the conductive film is processed using the insulating layer as a mask to form a conductive layer that overlaps with the insulating layer, and the semiconductor layer 30 is further processed. This allows an island-shaped structure of an insulating layer, a conductive layer, and the semiconductor layer 30 to be manufactured. In this case, the two-layer structure of the island-shaped insulating layer and the conductive layer corresponds to the island-shaped layer 35 described in Embodiment 1.

[0412] Furthermore, insulating layer 271a and insulating layer 271b can be formed by removing the portions of the island-shaped insulating layer that overlap with opening 289. Furthermore, conductive layer 242a and conductive layer 242b can be formed by removing the portions of the island-shaped conductive layer that overlap with opening 289. As described above, the side edge of conductive layer 242a coincides or nearly coincides with the side edge of semiconductor layer 230, and the side edge of conductive layer 242b coincides or nearly coincides with the side edge of semiconductor layer 230. Therefore, miniaturization and high integration of semiconductor devices can be achieved.

[0413] Because the insulating layer functions as a mask for the conductive layers, the conductive layers 242a and 242b do not have curved surfaces between their side surfaces and top surfaces. As a result, the conductive layers 242a and 242b have angular ends where their side surfaces and top surfaces intersect. Because the angular ends where their side surfaces and top surfaces intersect are angular, the cross-sectional areas of the conductive layers 242a and 242b are larger than when the ends have curved surfaces. As a result, the resistance of the conductive layers 242a and 242b is reduced, and the on-current of the transistor can be increased.

[0414] At least one of the configurations described in the above-mentioned <Configuration Example 1 of Semiconductor Device> can also be applied to the transistor 200A.

[0415] <Configuration Example 3 of Semiconductor Device> Structural examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0416] Fig. 26(A) is a plan view of a semiconductor device having a transistor 200B. Fig. 26(B) is a cross-sectional view taken along dashed line A1-A2 in Fig. 26(A). Fig. 26(C) is a cross-sectional view taken along dashed line A3-A4 in Fig. 26(A). Fig. 26(D) is a cross-sectional view taken along dashed line A5-A6 in Fig. 26(B).

[0417] The transistor 200B includes a conductive layer 220, a conductive layer 240, a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0418] The conductive layer 220 is provided on the insulating layer 210, an insulating layer 280 is provided on the conductive layer 220, and a conductive layer 240 is provided on the insulating layer 280. An opening 290 reaching the conductive layer 220 is formed in the conductive layer 240 and the insulating layer 280, and the semiconductor layer 230 is provided along the bottom and sidewalls of the opening 290. The semiconductor layer 230 has a portion in contact with the conductive layer 240 and a portion in contact with the conductive layer 220.

[0419] In the transistor 200B, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, and the conductive layer 240 functions as the other of the source electrode and the drain electrode.

[0420] The semiconductor layer 230 has a region that overlaps with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least a part of this region functions as a channel formation region of the transistor 200B. One of the region of the semiconductor layer 230 near the conductive layer 220 and the region of the semiconductor layer 230 near the conductive layer 240 functions as a source region, and the other functions as a drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0421] The semiconductor layer 230 is provided inside the opening 290. The transistor 200B has a configuration in which one of the source and drain electrodes (here, the conductive layer 220) is located below and the other of the source and drain electrodes (here, the conductive layer 240) is located above, allowing current to flow vertically. That is, a channel is formed along the side surface of the opening 290. This allows the transistor 200B to occupy a smaller area than a planar transistor in which the channel formation region, source region, and drain region are separately provided on the XY plane. This allows for a higher integration of the semiconductor device. Furthermore, when the transistor 200B is used in a memory device, the memory capacity per unit area can be increased. Since the channel length direction of the transistor 200B can be said to have a component in the height direction (vertical direction), the transistor 200B can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0422] The transistor 200B corresponds to the transistor provided in the opening 91 described in the first embodiment.

[0423] 26(D), by forming the opening 290 so as to have a circular shape in a plan view, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided concentrically. Therefore, the distance between the conductive layer 260 and the semiconductor layer 230 becomes approximately uniform, and therefore, a gate electric field can be applied to the semiconductor layer 230 approximately uniformly.

[0424] In addition, in this embodiment, an example is shown in which the opening 290 is circular in plan view. By making the opening circular, the processing accuracy when forming the opening can be improved, and openings of a fine size can be formed. However, the present invention is not limited to this. In plan view, the opening 290 can be, for example, a circle or a substantially circle such as an oval, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, a star-shaped polygon, or any of these polygons with rounded corners.

[0425] The structures (materials, film thickness, etc.) of the semiconductor layer 230, the insulating layer 250, the conductive layer 260, and the insulating layer 280 can refer to the structures of the semiconductor layer 230, the insulating layer 250, the conductive layer 260, and the insulating layer 280 described in the above-mentioned <Structural Example 1 of Semiconductor Device>, etc.

[0426] The conductive materials described later in [Conductive Layer] can be used for the conductive layer 220 and the conductive layer 240. In addition, the above-described materials applicable to the conductive layer 242a and the conductive layer 242b can be used.

[0427] <Materials for semiconductor devices> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked-layer structure.

[0428] [Oxide semiconductor layer] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one embodiment of the present invention, the description in <Structure of semiconductor device> can be referred to.

[0429] The carrier concentration in the channel formation region is 1×10 19 cm -3 Less than 1×10 18 cm -3 Less than 5 x 10 17 cm -3 Less than 1×10 17 cm -3 Less than 1×10 16 cm -3 Less than 1×10 15 cm -3 Less than 1×10 14 cm -3 Less than 1×10 13 cm -3 Less than 1×10 12 cm -3 Less than 1×10 11 cm -3 Less than or equal to 1 x 10 10 cm -3The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 -7 cm -3 It can be said that:

[0430] As described above, in an OS transistor, oxygen vacancies (V O ) and impurities may cause fluctuations in electrical characteristics and reduce reliability. Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of an OS transistor. To reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, carbon, and nitrogen.

[0431] When nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of a transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 5 × 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following applies.

[0432] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states are formed, which may cause unstable electrical characteristics of the transistor. Therefore, the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0433] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0434] [Insulating layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 212, insulating layer 214, insulating layer 216, insulating layer 221, insulating layer 222, insulating layer 224, insulating layer 241a, insulating layer 241b, insulating layer 250, insulating layer 254, insulating layer 271a, insulating layer 271b, insulating layer 275, insulating layer 280, insulating layer 283, insulating layer 285, etc.) included in the semiconductor device. Examples of the inorganic insulating film include an insulating oxide film, an insulating nitride film, an insulating oxynitride film, and an insulating nitride oxide film. Examples of the insulating oxide film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of nitride oxide insulating films include silicon nitride oxide films and aluminum nitride oxide films. An organic insulating film may also be used for an insulating layer included in a semiconductor device.

[0435] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current can arise due to thinner gate insulating layers. Using high-k materials for the gate insulating layer allows for lower voltages during transistor operation while maintaining the physical film thickness. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Materials with a low dielectric constant also have high dielectric strength.

[0436] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0437] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0438] Furthermore, a material that can exhibit ferroelectricity may be used for an insulating layer of a semiconductor device. As the material that can exhibit ferroelectricity, an oxide containing one or both of hafnium and zirconium is preferably used. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Furthermore, as the material that can exhibit ferroelectricity, a material obtained by adding an element J1 (here, the element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to a metal oxide containing one of hafnium and zirconium may be used.

[0439] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in an oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0440] Examples of materials that may exhibit ferroelectricity include metal nitrides containing nitrogen and at least one of elements M1 and M2. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Examples of materials that may exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc.

[0441] Examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure. Examples of materials that can have ferroelectricity include lead titanate (PbTiO X Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0442] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0443] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material capable of exhibiting ferroelectricity.

[0444] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0445] The ferroelectric layer preferably contains crystals having an orthorhombic crystal structure, since this allows ferroelectricity to be exhibited. The crystal structure of the crystals contained in the ferroelectric layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The ferroelectric layer may also have an amorphous structure. In this case, the ferroelectric layer may have a composite structure having an amorphous structure and a crystalline structure.

[0446] A metal oxide containing either or both of hafnium and zirconium is also an insulating material capable of capturing or fixing hydrogen. Therefore, by using a metal oxide containing either or both of hafnium and zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor having the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0447] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0448] Specifically, examples of materials for the insulating layer that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Other examples include nitrides such as aluminum nitride, aluminum titanium nitride, and silicon nitride. Other examples include nitride oxides such as silicon nitride oxide. Other examples of materials for the insulating layer that have the function of suppressing the permeation of oxygen include gallium oxide.

[0449] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer preferably has a region containing excess oxygen. For example, when an insulating layer that has a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. For an insulating layer in which a region containing excess oxygen is easily formed, see the description in <Structure of Semiconductor Device>.

[0450] An insulating layer provided in contact with or near an oxide semiconductor layer is preferably a barrier insulating layer against hydrogen. When the insulating layer has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer can be suppressed. The barrier insulating layer against hydrogen can also be said to have a function of suppressing diffusion of hydrogen.

[0451] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), hafnium silicate, etc. These metal oxides may further contain zirconium, and examples thereof include oxides containing hafnium and zirconium.

[0452] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced.

[0453] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0454] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0455] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are defined as a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. - Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and refer to at least one of, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Furthermore, oxygen when described as corresponding substances refers to at least one of, for example, oxygen atoms and oxygen molecules, etc.

[0456] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, and silicon nitride oxide.

[0457] The inorganic insulating layers cited as insulating layers having the function of capturing or fixing hydrogen and insulating layers having the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for oxygen barrier insulating layers include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0458] [Conductive layer] The conductive layers (conductive layer 205, conductive layer 220, conductive layer 240, conductive layer 242a, conductive layer 242b, conductive layer 243a, conductive layer 243b, conductive layer 260, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements. The alloy containing any of the above metal elements may be a nitride of the alloy or an oxide of the alloy. For example, it is preferable to use tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0459] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In-Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification and elsewhere, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0460] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0461] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0462] [substrate] Substrates on which transistors are formed can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate, are also available. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having metal nitrides and substrates having metal oxides. Other examples include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0463] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0464] This embodiment mode can be combined with other embodiments or examples as appropriate. In addition, in this specification, when multiple configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0465] (Embodiment 3) In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0466] Fig. 27 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 27 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 27 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0467] The semiconductor device described in Embodiment 2 (the transistor 200, the transistor 200A, or the transistor 200B) can be applied to the memory cell 950. By using the transistor described in Embodiment 2, the operation speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. Furthermore, the capacitance per area of ​​the memory device can be increased.

[0468] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0469] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0470] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0471] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0472] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0473] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0474] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cell 950, the function of reading data from the memory cell 950, the function of retaining the read data, etc.

[0475] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0476] PSW931 is the V to the peripheral circuit 915 DD The PSW 932 has the function of controlling the supply of V to the row driver 923. HM Here, the high power supply potential of the semiconductor device 900 is V DD The low power supply potential is GND (ground potential). HM is the high power supply potential used to drive the word line high, and V DD 27, in the peripheral circuit 915, V DD Although the number of power domains to which power is supplied is set to one, it is also possible to set multiple power domains. In this case, a power switch should be provided for each power domain.

[0477] An example of a configuration of a memory cell that can be applied to the memory cell 950 will be described with reference to FIGS.

[0478] [DOSRAM] 28A shows an example of a circuit configuration of a memory cell of a dynamic random access memory (DRAM). In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0479] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected to each other.

[0480] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. A second terminal of the capacitance element CA is connected to the wiring CAL.

[0481] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.

[0482] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0483] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 28B may be used. The memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0484] In the memory cell 952, the potential written via the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0485] Note that an OS transistor is preferably used as the transistor M1. Use of an OS transistor can improve the operating speed of the memory device. Furthermore, an OS transistor has a characteristic of having an extremely small off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely small. That is, written data can be held by the transistor M1 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0486] An example of the structure of a DOSRAM will now be described with reference to Fig. 29. In Fig. 29, the X direction is parallel to the channel width direction of the transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X and Y directions.

[0487] As shown in FIG. 29, a memory cell 951 includes a transistor M1 and a capacitor CA. An insulating layer 284 is provided over the transistor M1. The insulating layer 284 can be formed using an insulator that can be used for the insulating layer 216. The transistor M1 has a similar structure to that of the transistor 200A described in Embodiment 2, and the same components are denoted by the same reference numerals. For details of the transistor 200A, refer to Embodiment 2. A conductive layer 240b (conductive layer 240b1 and conductive layer 240b2) is provided in contact with one of the source electrode and drain electrode (conductive layer 242b) of the transistor M1. The conductive layer 240b extends in the Z direction and functions as a wiring BIL. The conductive layer 260 of the transistor M1 extends in the X direction and functions as a wiring WOL.

[0488] The capacitor CA includes a conductive layer 453 over the conductive layer 242a, an insulating layer 454 over the conductive layer 453, and a conductive layer 460 (a conductive layer 460a and a conductive layer 460b) over the insulating layer 454.

[0489] At least a portion of the conductive layer 453, the insulating layer 454, and the conductive layer 460 is disposed inside openings formed in the insulating layer 271a, the insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285, respectively. Ends of the conductive layer 453, the insulating layer 454, and the conductive layer 460 are located at least on the insulating layer 283, and preferably on the insulating layer 285. The insulating layer 454 is provided to cover an end of the conductive layer 453. This allows the conductive layer 453 and the conductive layer 460 to be electrically insulated from each other.

[0490] The deeper the openings provided in the insulating layers 271a, 275, 280, 282, 283, and 285 (i.e., the thicker one or more of the insulating layers 271a, 275, 280, 282, 283, and 285), the larger the capacitance of the capacitor CA. Increasing the capacitance per unit area of ​​the capacitor CA allows for miniaturization or high integration of memory devices. For example, the capacitance of the capacitor CA can be set by adjusting the film thickness of the insulating layer 285. Specifically, the film thickness of the insulating layer 285 can be set in the range of 50 nm to 250 nm, and the depth of the openings can be set to approximately 150 nm to 350 nm. Forming the capacitor CA within such a range allows the capacitor CA to have sufficient capacitance and prevents the height of one layer from becoming excessively high in a semiconductor device in which multiple memory cell layers are stacked. Note that the capacitance of the capacitor provided in each memory cell may be different in each of the layers of the memory cells by, for example, varying the thickness of the insulating layer 285 provided in each memory cell layer.

[0491] In the capacitor CA, the conductive layer 453 has a region that functions as one electrode (lower electrode), the insulating layer 454 has a region that functions as a dielectric, and the conductive layer 460 has a region that functions as the other electrode (upper electrode). The upper part of the conductive layer 460 can be extended to function as a wiring CAL. The capacitor CA constitutes an MIM (Metal-Insulator-Metal) capacitor.

[0492] The conductive layer 242a provided over and overlapping with the semiconductor layer 230 functions as an electrode electrically connected to the lower electrode of the capacitor CA.

[0493] The conductive layer 453 and the conductive layer 460 can be formed using a conductor applicable to the conductive layer 205 or the conductive layer 260, respectively. The conductive layer 453 and the conductive layer 460 are preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method. For example, the conductive layer 453 can be formed using titanium nitride or tantalum nitride formed by an ALD method or a CVD method.

[0494] The top surface of the conductive layer 242a is in contact with the bottom surface of the conductive layer 453. Here, by using a conductive material with good conductivity for the conductive layer 242a, contact resistance between the conductive layer 453 and the conductive layer 242a can be reduced.

[0495] Alternatively, the conductive layer 460a may be made of titanium nitride formed by an ALD method or a CVD method, and the conductive layer 460b may be made of tungsten formed by a CVD method. Note that if the adhesiveness of tungsten to the insulating layer 454 is sufficiently high, the conductive layer 460 may have a single layer structure of tungsten formed by a CVD method.

[0496] The insulating layer 454 of the capacitor CA is preferably formed using the high-k material described in the above embodiment. By using such a high-k material, the insulating layer 454 can be thick enough to suppress leakage current and ensure sufficient capacitance of the capacitor CA. In addition, the insulating layer 454 is preferably formed using a film formation method with good coverage, such as an ALD method or a CVD method.

[0497] Furthermore, it is preferable to use a laminated insulating layer made of the above materials, and it is preferable to use a laminated structure of a high-k material and a material having a higher dielectric strength than the high-k material. For example, the insulating layer 454 can be an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order. Alternatively, it can be an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order. Alternatively, it can be an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order. By using a laminated insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element CA can be suppressed.

[0498] Alternatively, the insulating layer 454 may be made of the material having ferroelectricity described in the [Insulating Layer] of Embodiment 2.

[0499] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM) or a ferroelectric memory. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitance element CA, the memory device described in this embodiment functions as a ferroelectric memory.

[0500] Note that the sidewall of the opening where the capacitor element CA is disposed may be perpendicular or approximately perpendicular to the top surface of the insulating layer 222, or may be tapered. By tapering the sidewall, coverage of the conductive layer 453 or the like provided in the opening can be improved, and defects such as voids can be reduced.

[0501] Furthermore, the conductive layer 242b provided so as to overlap the semiconductor layer 230 functions as wiring that connects to the conductive layer 240b. For example, in Fig. 29, the upper surface and side end portions of the conductive layer 242b are connected to the conductive layer 240b that extends in the Z direction.

[0502] By having the conductive layer 240b directly contact at least one of the upper surface and side edge of the conductive layer 242b, there is no need to provide a separate connection electrode, thereby reducing the area occupied by the memory array. Furthermore, the integration density of memory cells is improved, allowing the storage capacity of the storage device to be increased. It is preferable that the conductive layer 240b contacts a portion of the upper surface and side edge of the conductive layer 242b. By having the conductive layer 240b contact multiple surfaces of the conductive layer 242b, the contact resistance between the conductive layer 240b and the conductive layer 242b can be reduced.

[0503] Conductive layer 240b is provided in openings formed in insulating layer 216, insulating layer 221, insulating layer 222, insulating layer 271b, insulating layer 275, insulating layer 280, insulating layer 282, insulating layer 283, insulating layer 285, and insulating layer 284.

[0504] 29, an insulating layer 241b is preferably provided in contact with the side surface of the conductive layer 240b. Specifically, the insulating layer 241b is provided in contact with the inner walls of the openings of the insulating layer 216, the insulating layer 221, the insulating layer 222, the insulating layer 224, the insulating layer 271b, the insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, the insulating layer 285, and the insulating layer 284. The insulating layer 241b is also formed on the side surface of the semiconductor layer 230, which is formed to protrude into the opening. Here, at least a portion of the conductive layer 242b is exposed from the insulating layer 241b and is in contact with the conductive layer 240b. In other words, the conductive layer 240b is provided so as to fill the interior of the opening via the insulating layer 241b.

[0505] 29, the uppermost portion of the insulating layer 241b formed below the conductive layer 242b is preferably located below the upper surface of the conductive layer 242b. This configuration allows the conductive layer 240b to be in contact with at least a portion of the side edge of the conductive layer 242b. The insulating layer 241b formed below the conductive layer 242b preferably has a region in contact with the side surface of the semiconductor layer 230. This configuration can prevent impurities such as water and hydrogen contained in the insulating layer 280, etc., from being mixed into the semiconductor layer 230 through the conductive layer 240b.

[0506] Furthermore, in the opening where the conductive layer 240b and the insulating layer 241b are disposed, the sidewall of the opening may be perpendicular or approximately perpendicular to the top surface of the insulating layer 222, or may have a tapered shape. By making the sidewall tapered, coverage by the insulating layer 241b or the like provided in the opening is improved.

[0507] [NOSRAM] 28C shows an example of a circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and elsewhere, a memory device having a gain cell type memory cell in which an OS transistor is used as the transistor M2 is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0508] A first terminal of transistor M2 is connected to a first terminal of capacitance element CB, a second terminal of transistor M2 is connected to line WBL, and a gate of transistor M2 is connected to line WOL. A second terminal of capacitance element CB is connected to line CAL. A first terminal of transistor M3 is connected to line RBL, a second terminal of transistor M3 is connected to line SL, and a gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0509] The line WBL functions as a write bit line, the line RBL functions as a read bit line, and the line WOL functions as a word line. The line CAL functions as a line for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the line CAL.

[0510] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. After that, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0511] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0512] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in Figure 28(D). The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured such that the write bit line and the read bit line operate as a single wiring BIL.

[0513] 28E is an example of a memory cell 955 in which the capacitor CB and the wiring CAL are omitted from the memory cell 953. Also, FIG. 28F is an example of a memory cell 956 in which the capacitor CB and the wiring CAL are omitted from the memory cell 954. With this configuration, the degree of integration of the memory cells can be increased.

[0514] Note that it is preferable to use an OS transistor for at least the transistor M2. In particular, it is preferable to use an OS transistor for the transistors M2 and M3. By using an OS transistor as the transistor M2, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cells 953 to 956.

[0515] The memory cells 953 to 956 in which an OS transistor is used as the transistor M2 are one embodiment of NOSRAM.

[0516] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, which increases the degree of freedom in circuit design.

[0517] 28G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 includes transistors M4 to M6 and a capacitor CC.

[0518] A first terminal of the transistor M4 is connected to a first terminal of the capacitor CC, a second terminal of the transistor M4 is connected to the wiring BIL, and a gate of the transistor M4 is connected to the wiring WOL. A second terminal of the capacitor CC is connected to a first terminal of the transistor M5 and the wiring GNDL. A second terminal of the transistor M5 is connected to a first terminal of the transistor M6, and a gate of the transistor M5 is connected to the first terminal of the capacitor CC. A second terminal of the transistor M6 is connected to the wiring BIL, and a gate of the transistor M6 is connected to the wiring RWL.

[0519] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low level potential.

[0520] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0521] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0522] It is preferable to use an OS transistor for at least the transistor M4.

[0523] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0524] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 30(A), the driver circuit 910 and the memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and the memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 30(B), the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0525] Here, an example of the configuration of a semiconductor device 900 in which memory arrays 920 are stacked in multiple layers will be described with reference to FIG.

[0526] 31 includes a driver circuit 910, which is a layer including a transistor 310 and the like, and memory arrays 920[1] to 920[m] over the driver circuit 910. Here, the layer provided in the first layer (bottom) is referred to as memory array 920[1], the layer provided in the second layer is referred to as memory array 920[2], and the layer provided in the m-th layer (top) is referred to as memory array 920[m]. In other words, the memory device of one embodiment of the present invention may have a structure in which multiple layers including memory cells are stacked.

[0527] 31 illustrates a transistor 310 included in a driver circuit 910. The transistor 310 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. An element isolation layer 318 is preferably provided between adjacent transistors 310. The transistor 310 may be either a p-channel transistor or an n-channel transistor. The substrate 311 may be, for example, a single-crystal silicon substrate.

[0528] Here, in the transistor 310, a semiconductor region 313 (a part of the substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a FIN transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Although the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0529] Note that the transistor 310 illustrated in FIG. 31 is just an example, and the structure is not limited thereto, and an appropriate transistor can be used depending on the circuit configuration or driving method.

[0530] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer having the function of a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0531] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 310. A conductive layer 328 or the like is embedded in the insulating layer 320 and the insulating layer 322. A conductive layer 330 or the like is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0532] The insulating layer serving as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by CMP processing to enhance flatness.

[0533] Insulators that can be used as the interlayer film include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, which have insulating properties.

[0534] For example, by using a material with a low dielectric constant for the insulating layer that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is preferable to select a material depending on the function of the insulating layer.

[0535] An insulating layer 208 is provided on the driver circuit 910, and a conductive layer 207 is provided in an opening formed in the insulating layer 208. Furthermore, an insulating layer 210 is provided on the insulating layer 208, and a conductive layer 209 is provided in an opening formed in the insulating layer 210. Furthermore, an insulating layer 212 is provided on the insulating layer 210, and an insulating layer 214 is provided on the insulating layer 212. Part of the conductive layer 240b provided in the memory array 920[1] is buried in the openings formed in the insulating layer 212 and the insulating layer 214. Here, the insulating layer 208 and the insulating layer 210 can be made of an insulator that is applicable to the insulating layer 216.

[0536] The conductive layer 207 functions as a wiring electrically connected to the driver circuit 910. The upper surface of the conductive layer 207 is provided in contact with the lower surface of the conductive layer 209. The upper surface of the conductive layer 209 is provided in contact with the lower surface of the conductive layer 240b provided in the memory array 920[1]. With this structure, the conductive layer 240b corresponding to the wiring BIL can be electrically connected to the driver circuit 910.

[0537] Each of the memory arrays 920[1] to 920[m] includes a plurality of memory cells 951. The conductive layer 240b of each memory cell 951 is electrically connected to the conductive layer 240b in the upper layer and the conductive layer 240b in the lower layer.

[0538] 31, the conductive layer 240b is shared by adjacent memory cells 951. In addition, in the adjacent memory cells 951, the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductive layer 240b.

[0539] In the above-described memory array 920, a plurality of memory arrays 920[1] to 920[m] can be stacked. The memory arrays 920[1] to 920[m] included in the memory array 920 can be arranged in the vertical direction of the substrate surface on which the driver circuit 910 is provided, thereby improving the memory density of the memory cells 951. Furthermore, the memory array 920 can be manufactured by repeatedly using the same manufacturing process in the vertical direction. The semiconductor device 900 can reduce the manufacturing cost of the memory array 920.

[0540] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0541] Fig. 32 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in Fig. 32 can be applied to, for example, a CPU. The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0542] 32 includes an ALU 962 (Arithmetic logic unit, arithmetic circuit), an ALU controller 962c, an instruction decoder 963, an interrupt controller 964, a timing controller 965, a register 966, a register controller 967, a bus interface 968, a cache 969, and a cache interface 969i on a substrate 961. The substrate 961 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. A rewritable ROM and a ROM interface may be included. The cache 969 and the cache interface 969i may be provided on separate chips.

[0543] The cache 969 is connected to a main memory provided on a separate chip via a cache interface 969i. The cache interface 969i has a function of supplying part of the data held in the main memory to the cache 969. The cache interface 969i also has a function of outputting part of the data held in the cache 969 to the ALU 962, register 966, etc. via the bus interface 968.

[0544] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 969i may have a function of supplying data held in the memory array 920 to the cache 969. In this case, it is preferable that a drive circuit 910 be provided as part of the cache interface 969i.

[0545] It is also possible to use only the memory array 920 as a cache without providing the cache 969.

[0546] The arithmetic device 960 shown in FIG. 32 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 32 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle via its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0547] An instruction input to the arithmetic unit 960 via the bus interface 968 is input to the instruction decoder 963, decoded, and then input to the ALU controller 962c, the interrupt controller 964, the register controller 967, and the timing controller 965.

[0548] The ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965 perform various controls based on the decoded instructions. Specifically, the ALU controller 962c generates signals for controlling the operation of the ALU 962. Furthermore, the interrupt controller 964 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 967 generates an address for the register 966 and reads and writes data from and to the register 966 depending on the state of the arithmetic unit 960.

[0549] Furthermore, the timing controller 965 generates signals that control the timing of the operations of the ALU 962, the ALU controller 962c, the instruction decoder 963, the interrupt controller 964, and the register controller 967. For example, the timing controller 965 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0550] In the arithmetic unit 960 shown in FIG. 32, the register controller 967 selects a holding operation in the register 966 in accordance with an instruction from the ALU 962. That is, it selects whether to hold data in a flip-flop or a capacitor in the memory cell of the register 966. If holding data in a flip-flop is selected, a power supply potential is supplied to the memory cell in the register 966. If holding data in a capacitor is selected, the data is rewritten to the capacitor, and the supply of the power supply potential to the memory cell in the register 966 can be stopped.

[0551] The memory array 920 and the arithmetic device 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in FIGS. 33A and 33B. The semiconductor device 970A has a layer 930 on which memory arrays are provided, on an arithmetic device 960. The layer 930 is provided with a memory array 920L1, a memory array 920L2, and a memory array 920L3. The arithmetic device 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic device 960 and the layer 930 are shown separately in FIG. 33B.

[0552] By stacking the memory array layer 930 and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0553] The layer 930 having the memory array and the arithmetic device 960 may be stacked by stacking the layer 930 having the memory array directly on the arithmetic device 960 (also called monolithic stacking), or by forming the arithmetic device 960 and the layer 930 on different substrates, bonding the two substrates together, and connecting them using through-vias or conductive film bonding technology (such as Cu-Cu bonding). The former method does not require consideration of misalignment during bonding, and therefore not only can it reduce the chip size but also the manufacturing cost.

[0554] Here, the arithmetic unit 960 does not have a cache 969, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also called a level 1 cache), the memory array 920L2 can be used as an L2 cache (also called a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and is accessed least frequently. Furthermore, the memory array 920L1 has the smallest capacity and is accessed most frequently.

[0555] When the cache 969 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0556] 33(B), a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0557] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0558] When the memory array 920L1 is used as a cache, the driver circuit 910L1 may function as part of the cache interface 969i, or may be configured to be connected to the cache interface 969i. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 969i, or may be configured to be connected to it.

[0559] Whether the memory array 920 functions as a cache or a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0560] The semiconductor device 900 can cause some of the multiple memory cells 950 to function as a cache and the other part to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one aspect of the present invention can function as, for example, a universal memory.

[0561] Furthermore, a layer 930 having one memory array 920 may be provided overlapping the arithmetic device 960. Figure 34A shows a perspective view of a semiconductor device 970B.

[0562] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Figure 34(A) shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0563] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if you want to increase the capacity of the L1 cache, you can achieve this by increasing the area of ​​the area L1. This configuration makes it possible to improve the efficiency of calculation processing and increase the processing speed.

[0564] Moreover, a plurality of memory arrays may be stacked. Figure 34(B) shows a perspective view of a semiconductor device 970C.

[0565] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0566] This embodiment mode can be combined with other embodiments or examples as appropriate. In addition, in this specification, when multiple configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0567] (Fourth embodiment) In this embodiment, an example of the applicability of a semiconductor device of one embodiment of the present invention will be described with reference to FIG. 35. A transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a capacitor are used in a memory device of one embodiment of the present invention. Since the ...

Claims

1. a first step of forming a crystalline portion; a second step of forming a crystalline metal oxide layer using the crystal portion as a nucleus, The method for producing a metal oxide layer, wherein the metal oxide layer contains indium.

2. In claim 1, In the first step, the crystalline portion is formed from one of the grains of a polycrystalline film.

3. In claim 1, a third step of forming an amorphous metal oxide film before the first step; In the first step, the crystalline portion is formed on the amorphous metal oxide film; In the second step, the amorphous metal oxide film is crystallized to form the metal oxide layer.

4. In claim 1, forming the metal oxide layer using atomic layer deposition; The method for forming a metal oxide layer, wherein the substrate is heated to a temperature of 100° C. or higher and 300° C. or lower.

5. In claim 1, forming the metal oxide layer using atomic layer deposition; The method for forming a metal oxide layer, wherein the substrate is heated to a temperature of 150° C. or higher and 250° C. or lower.

6. a first step of forming a crystalline portion on an insulating layer; a second step of forming a crystalline metal oxide layer on the crystal portion, the metal oxide layer comprises indium; A method for manufacturing a metal oxide layer, wherein, prior to the second step, the upper surface of the insulating layer is planarized using a chemical mechanical polishing method so that the average surface roughness of the upper surface of the insulating layer is 0 nm or more and less than 3 nm.

7. In claim 6, The method for producing a metal oxide layer, wherein in the second step and thereafter, crystals of the metal oxide layer are grown laterally.

8. In claim 6, In the first step, a film that will become the crystalline portion is formed, and the film is processed using a wet etching method to form the crystalline portion.

9. In claim 1 or claim 6, The method for manufacturing a metal oxide layer, wherein the crystal grains of the metal oxide layer have a crystal orientation of <111>.

10. In claim 9, The method for producing a metal oxide layer, wherein the crystal orientation of the crystal portion is <001>.

11. In claim 9, the crystal portion contains indium, gallium, and zinc; the crystalline portion has a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition therearound, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition therearound.

12. In claim 1 or claim 6, The method for manufacturing a metal oxide layer, wherein the crystal orientation of the crystal grains of the metal oxide layer coincides or substantially coincides with the crystal orientation of the crystalline portion.

13. In claim 12, The method for producing a metal oxide layer, wherein the crystalline portion contains indium.

14. a first step of forming a crystalline portion on a first insulating layer; a second step of forming a crystalline metal oxide layer using the crystal portion as a nucleus; a third step of processing the metal oxide layer into islands; a fourth step of forming a second insulating layer overlying the metal oxide layer; a fifth step of forming an opening in the second insulating layer that overlaps the metal oxide layer; a sixth step of forming a third insulating layer in the opening; a seventh step of forming a conductive layer on the third insulating layer, The method for manufacturing a semiconductor device, wherein the metal oxide layer contains indium.

15. In claim 14, In the first step, the crystalline portion is formed from one of grains of a polycrystalline film.

16. In claim 14, forming the metal oxide layer using atomic layer deposition; A method for manufacturing a semiconductor device, wherein a substrate heating temperature is 100° C. or higher and 300° C. or lower.

17. In claim 14, forming the metal oxide layer using atomic layer deposition; A method for manufacturing a semiconductor device, wherein a substrate heating temperature is 150° C. or higher and 250° C. or lower.

18. In claim 14, The method for manufacturing a semiconductor device, wherein the metal oxide layer has crystal grains with a crystal orientation of <111>.

19. In claim 18, The method for manufacturing a semiconductor device, wherein the crystal orientation of the crystal portion is <001>.

20. In claim 18, the crystal portion contains indium, gallium, and zinc; The method for manufacturing a semiconductor device, wherein the crystalline portion has a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition therearound, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition therearound.

21. In claim 14, A method for manufacturing a semiconductor device, wherein a crystal orientation of crystal grains in the metal oxide layer and a crystal orientation of the crystalline portion are identical or substantially identical.

22. In claim 21, The method for manufacturing a semiconductor device, wherein the crystal portion contains indium.

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