Display device

Abstract

To provide a semiconductor device for high electric power that uses a novel semiconductor material high in productivity.SOLUTION: For reduction of impurities such as moisture, hydrogen, etc., in an oxide semiconductor film, first heating processing is performed with the oxide semiconductor film exposed after the oxide semiconductor film is formed. For further reduction of impurities such as moisture, hydrogen, etc., second heating processing is performed again with the oxide semiconductor film exposed after oxygen is added to the oxide semiconductor film by an ion injection method, an ion doping method, etc.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof. [Background technology]

[0002] A transistor using a semiconductor film formed on an insulating surface is indispensable for a semiconductor device. The manufacturing of transistors is limited by the heat resistance temperature of the substrate. Amorphous silicon, which can be formed at a relatively low temperature, and silicon, which is formed using laser light or catalytic elements. A transistor having an active layer made of polysilicon or the like obtained by crystallization is used in a semiconductor display device. It has become the mainstream transistor used in

[0003] In recent years, the high mobility achieved by polysilicon and the high mobility achieved by amorphous silicon have been As a new semiconductor material that combines these properties with uniform device characteristics, oxide semiconductors have been developed. Metal oxides that exhibit semiconducting properties are attracting attention. For example, indium oxide, a well-known metal oxide, is used in liquid crystal displays and other devices. Metal oxides that exhibit semiconducting properties include, for example, , tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Transistors using metal oxides that exhibit these characteristics in the channel formation region are already known ( Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0005] The transistors used in semiconductor devices are required to have small variations in threshold voltage due to deterioration over time. Also, low off-state current is desirable. Variation in threshold voltage due to degradation over time is small. By using small transistors, the reliability of the semiconductor device can be improved. By using a transistor with a low current, power consumption of a semiconductor device can be reduced. .

[0006] An object of the present invention is to provide a method for manufacturing a highly reliable semiconductor device. Another object of the present invention is to provide a method for manufacturing a semiconductor device with low power consumption. Another object of the present invention is to provide a semiconductor device with high reliability. One of the objects is to provide a semiconductor device.

[0007] Also, there are semiconductor devices called power devices that have high breakdown voltage and are used to control large currents. Currently, silicon is the main semiconductor material used in semiconductor devices. It is said that the physical properties of semiconductor elements that have been used up to now are reaching the theoretical limit. To realize a power device that can control a high voltage and a large current, it is necessary to improve the characteristics. New semiconductor materials with high breakdown voltage, high conversion efficiency, high-speed switching, etc. are required. Examples of semiconductor materials that may improve various properties include silicon carbide and gallium nitride. The band gap of silicon carbide is 3.26 The band gap of gallium nitride is 3.39 eV, and that of silicon is about three times that of silicon. It has a large band gap, which is advantageous for improving the breakdown voltage of semiconductor devices and reducing power loss. It is known that:

[0008] However, compound semiconductors such as silicon carbide and gallium nitride require high processing temperatures. The process temperature for silicon carbide is about 1500°C, and the process temperature for gallium nitride is about 1500°C. The temperature is approximately 1100°C, and it is impossible to form a film on a glass substrate, which has a low heat resistance temperature. Therefore, it is not possible to use inexpensive glass substrates and it is not possible to accommodate larger substrates. Semiconductor devices using compound semiconductors such as silicon nitride and gallium nitride are not suitable for mass production. This is a hindrance to practical application.

[0009] In view of the above-mentioned problems, we have developed a semiconductor device for high power use that uses a new semiconductor material that is highly mass-producible. One of the purposes is to provide [Means for solving the problem]

[0010] The present inventors have found that impurities such as hydrogen and water present in an oxide semiconductor film cause a shift in the threshold voltage. We focused on the fact that this is a factor that causes deterioration over time in transistors. The oxide semiconductor film contains a large amount of hydrogen or water as impurities. Therefore, in one embodiment of the present invention, a method for removing moisture, hydrogen, or the like in an oxide semiconductor film is In order to reduce impurities, an oxide semiconductor film is formed, and then the oxide semiconductor film is exposed. In a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or rare gas, an oxygen gas atmosphere, or an ultra Dry air (measured using a CRDS (cavity ring-down laser spectroscopy) type dew point meter) When measured, the moisture content is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less The first heat treatment is carried out in an atmosphere of 10 ppb or less of air. To further reduce impurities such as moisture or hydrogen in the semiconductor film, ion implantation or In the method, oxygen is added to the oxide semiconductor film by an ion doping method or the like, and then the oxide semiconductor film is again With the semiconductor film exposed, it is heated in a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or rare gas, or an acid atmosphere. Under nitrogen gas atmosphere or ultra-dry air (CRDS (Cavity Ring-Down Laser Spectroscopy) When measured using a dew point meter, the moisture content is 20 ppm (-55°C in dew point equivalent) or less. The second heat treatment is carried out under an atmosphere of preferably 1 ppm or less, preferably 10 ppb or less (air). Do the following.

[0011] By the first heat treatment, impurities such as moisture or hydrogen in the oxide semiconductor film are reduced. However, this problem has not been completely eliminated, and there is still room for improvement. This is thought to be due to hydrogen or hydroxyl groups bonded to the constituent metals. In the method, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like. By doing so, a bond between a metal constituting the oxide semiconductor and hydrogen or a bond between the metal and a hydroxyl group can be formed. The bond between these atoms is broken, and these hydrogen or hydroxyl groups react with oxygen to produce water. Then, by performing a second heat treatment after adding oxygen, the strongly remaining hydrogen Furthermore, impurities such as hydroxyl groups can be easily eliminated as water.

[0012] By removing impurities such as moisture and hydrogen, the i-type (intrinsic semiconductor) or an oxide as close to i-type as possible is formed. If it is possible to obtain a compound semiconductor, it will be possible to realize transistors in which the threshold voltage is shifted by the above impurities. This prevents the deterioration of the characteristics of the transistor from progressing and reduces the off-state current. impurities such as hydrogen or water contained in the oxide semiconductor are removed, and the oxide semiconductor is subjected to secondary ion mass spectrometry. (SIMS: Secondary Ion Mass Spectroscopy) The measured hydrogen concentration in the oxide semiconductor is 5×10 19 / cm 3 Below, preferably 5×10 18 / cm 3 Less than or equal to 5 × 10 17 / cm 3 The following is more preferably is 1 x 10 16 / cm 3 In addition, oxide semiconductors that can be measured by Hall effect measurement The carrier density of the membrane is 1×10 14 cm -3 Less than 1 x 10 12 cm -3 Not yet less than 1 × 10 11 cm -3 That is, the oxide semi-conductor The carrier density of the conductive film is close to zero. The band gap is preferably 2 eV or more. The potential is preferably 2.5 eV or more, and more preferably 3 eV or more. By using an oxide semiconductor film that has been highly purified by the above method, the off-state current of a transistor can be reduced. It is possible.

[0013] The two heat treatments are performed at temperatures between 500°C and 850°C (or below the strain point of the glass substrate). It is preferable to carry out the heating process at a temperature in the range of 550°C to 750°C. The temperature must not exceed the heat resistance temperature of the substrate used. The effect of TDS (Thermal Desorption Spectroscopy) This has been confirmed by thermal desorption analysis.

[0014] The heat treatment is performed in a furnace or by rapid thermal annealing (RTA). The RTA method uses a lamp light source, and moves the substrate through a heated gas for a short time. There is a method for performing heat treatment. When the RTA method is used, the time required for heat treatment is reduced to less than 0.1 hours. It can also be time.

[0015] Specifically, a transistor using a highly purified oxide semiconductor film as described above can be used, for example, For example, the channel width W is 1×10 4 Even if the device has a channel length L of 3 μm, the off-current is 10 -13 A or less, subthreshold swing value (S value) is about 0.1V / dec. Therefore, the characteristics of the gate electrode and the source electrode (gate insulating film thickness 100 nm) can be obtained. The off-state current when the voltage is below 0 V, that is, the leakage current, is This is significantly lower than that of a transistor using

[0016] In addition, transistors using highly purified oxide semiconductors (purified OS) The temperature dependence of the off-state current is almost nonexistent. This is because the electron donor (donor) in the oxide semiconductor By removing impurities that act as a nucleator and purifying the oxide semiconductor, the conductivity type can be determined This is because the Fermi level is located in the center of the forbidden band. This is because the energy gap of oxide semiconductors is 3 eV or more, and thermally excited carriers are extremely In addition, the source electrode and the drain electrode are in a degenerated state. This is also the reason why temperature dependence does not appear. Most of the carriers are injected from the electrode into the oxide semiconductor, and the carrier density The lack of temperature dependence can explain the above characteristics (no temperature dependence of off-current). do.

[0017] In the first heat treatment, RTA (Rapid Thermal Anneal) Rapid thermal annealing is used to dehydrate or dehydrogenate the oxide semiconductor film at high temperature for a short time. By performing this process, the surface layer of the oxide semiconductor film is formed into a so-called It has crystalline regions containing nanocrystals (also written as nanocrystals), and other Some parts are amorphous, or a mixture of amorphous and microcrystalline with microcrystalline interspersed among the amorphous regions. The size of the nanocrystals is merely an example, and the invention should not be interpreted as being limited to the above numerical range. It's not that.

[0018] Note that the crystalline region formed in the surface layer portion of the oxide semiconductor film is formed by ion implantation or ion doping. However, the oxide semiconductor film is damaged by the addition of oxygen using a ping method or the like. The heat treatment in step 1 removes water or hydrogen and generates oxygen vacancies. The oxygen vacancy is generated by adding oxygen using the oxygen doping method or the ion doping method. The first heat treatment can supply oxygen to the oxide semiconductor film. The removed hydrogen or water is not a constituent element of the oxide semiconductor, but is a so-called impurity. The added oxygen is one of the constituent elements of the oxide semiconductor, and therefore satisfies the stoichiometric composition ratio. Therefore, after the first heat treatment and the addition of oxygen, A second heat treatment is then performed to repair the damaged crystalline regions and to remove the oxide. Promotes crystal growth from the surface of the semiconductor film to the interior of the semiconductor film, expanding the crystalline region. In the second heat treatment, the crystal growth rate can be increased more than in the first heat treatment. The growth is further promoted, so that the crystal grains are adjacent to each other in the crystalline region and the oxide The metal elements that make up the compound semiconductor are connected between adjacent crystal grains, that is, Therefore, the transistor having the above-mentioned crystalline region in the channel forming region In transistors, the potential barrier at the grain boundaries is low, resulting in high mobility and high breakdown voltage. Such excellent characteristics can be obtained.

[0019] Oxide semiconductors include In-Sn-Ga-Zn-O-based oxide semiconductors, which are quaternary metal oxides. , ternary metal oxide In-Ga-Zn-O oxide semiconductor, In-Sn-Zn-O In-Al-Zn-O oxide semiconductors, In-Al-Zn-O oxide semiconductors, Sn-Ga-Zn-O oxides Semiconductors, Al-Ga-Zn-O oxide semiconductors, Sn-Al-Zn-O oxide semiconductors, , binary metal oxides such as In-Zn-O oxide semiconductors and Sn-Zn-O oxide semiconductors body, Al-Zn-O oxide semiconductor, Zn-Mg-O oxide semiconductor, Sn-Mg-O Oxide semiconductors, In-Mg-O based oxide semiconductors, In-Ga-O based oxide semiconductors, -O-based oxide semiconductors, Sn-O-based oxide semiconductors, Zn-O-based oxide semiconductors, etc. In this specification, for example, an In—Sn—Ga—Zn—O-based oxide is used. Semiconductors are those containing indium (In), tin (Sn), gallium (Ga), and zinc (Zn). The stoichiometric composition ratio of the metal oxide is not particularly important. The compound semiconductor may contain silicon.

[0020] Alternatively, the oxide semiconductor may have the chemical formula InMO3(ZnO) m (m>0) Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. vinegar.

[0021] Here, analysis of the hydrogen concentration in the oxide semiconductor film and the conductive film will be described. The hydrogen concentration in semiconductor and conductive films is measured by secondary ion mass spectrometry (SIMS). SIMS analysis is performed using standard ion mass spectroscopy (SIMS). In principle, it is possible to obtain accurate data near the sample surface and near the interface between layers of different materials. Therefore, the distribution of hydrogen concentration in the film in the thickness direction is known to be difficult. When analyzing with SIMS, there is no extreme fluctuation in the values ​​within the range where the target film exists. The average value in the region where a nearly constant value is obtained is used as the hydrogen concentration. When the thickness of the film to be measured is thin, it is affected by the hydrogen concentration in the adjacent film and remains almost constant. In this case, it may be impossible to find an area where the value of The maximum or minimum value of the hydrogen concentration is adopted as the hydrogen concentration in the film. In the region where If not present, the value at the inflection point is taken as the hydrogen concentration.

[0022] The transistor may be a bottom gate type or a top gate type, A bottom-gate transistor is a transistor in which the gate is on an insulating surface. a gate electrode, a gate insulating film on the gate electrode, and a gate insulating film overlapping the gate electrode. An oxide semiconductor film, a source electrode and a drain electrode on the oxide semiconductor film, and The top-gate transistor has an insulating film over the oxide semiconductor film and an insulating film over the oxide semiconductor film. an oxide semiconductor film on the edge surface; a gate insulating film on the oxide semiconductor film; a gate electrode and a source electrode which overlap with the oxide semiconductor film and function as a conductive film; a drain electrode; and an insulating film on the source electrode, the drain electrode, and the oxide semiconductor film. A bottom-contact transistor has a gate electrode on an insulating surface and a gate electrode on the gate electrode. a gate insulating film, a source electrode and a drain electrode on the gate insulating film, and a source electrode and a drain electrode on the gate insulating film. an oxide semiconductor film that is on the electrode and overlaps with the gate electrode on the gate insulating film; The gate insulating film includes a source electrode, a drain electrode, and an insulating film over the oxide semiconductor film.

[0023] In addition, the oxide semiconductor film is formed by sputtering or the like, and the oxide semiconductor film is formed by sputtering or the like. The hydrogen or water present around the semiconductor film is easily incorporated into the film. Water or hydrogen is a donor. Therefore, the oxide semiconductor itself is an impurity. In one embodiment, after forming the source electrode and the drain electrode, the source electrode, the drain electrode and An insulating film using an insulating material with high barrier properties may be formed to cover the oxide semiconductor film. It is desirable to use an insulating material with high barrier properties for the insulating film. As a high insulating film, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or a nitride oxide film An aluminum film or the like can be used. When a plurality of laminated insulating films are used, Silicon oxide films and silicon oxynitride films, which contain a lower ratio of nitrogen than insulating films with high barrier properties, are The insulating film having a low nitrogen content is formed on the side closer to the oxide semiconductor film. The source electrode, the drain electrode, and the oxide semiconductor film are sandwiched between the insulating film and the insulating film. By using an insulating film having a barrier property, Moisture or other substances may be present in the gate insulating film or in the interface between the oxide semiconductor film and other insulating films or in the vicinity thereof. can prevent impurities such as hydrogen from entering.

[0024] In addition, an insulating film using a material with high barrier properties may be formed between the gate electrode and the oxide semiconductor film. It has a structure in which an insulating film such as a silicon oxide film or a silicon oxynitride film, which has a low ratio of nitrogen contained therein, is laminated. An insulating film such as a silicon oxide film or a silicon oxynitride film may be formed on the surface of the semiconductor substrate. is formed between the insulating film having a barrier property and the oxide semiconductor film. By using this, impurities in the atmosphere such as moisture or hydrogen, or arsenic contained in the substrate can be removed. Impurities such as alkali metals and heavy metals may be trapped in the oxide semiconductor film, the gate insulating film, or the oxide Therefore, it is possible to prevent the semiconductor from penetrating into the interface between the semiconductor film and other insulating film and its vicinity. [Effects of the Invention]

[0025] It is possible to provide a method for manufacturing a highly reliable semiconductor device. Furthermore, a highly reliable semiconductor device can be provided. In addition, a semiconductor device with low power consumption can be provided.

[0026] Furthermore, since high-voltage semiconductor elements can be fabricated at low film-forming temperatures, large-scale production is possible. A semiconductor device for power applications can be provided. [Brief explanation of the drawings]

[0027] [Figure 1] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 2] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 3] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 4] FIG. [Figure 5] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 6] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 7] FIG. [Figure 8] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 9] FIG. [Figure 10] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 11] FIG. 1 is a cross-sectional view of a transistor. [Figure 12] FIG. 1 is a cross-sectional view of a transistor. [Figure 13] 1A and 1B are a top view and a cross-sectional view of an electronic paper. [Figure 14] FIG. 1 is a block diagram of a semiconductor display device. [Figure 15] FIG. 2 illustrates a configuration of a signal line driver circuit. [Figure 16] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 17] 1A and 1B are a diagram illustrating one embodiment of a shift register and a timing chart illustrating the operation of the shift register; [Figure 18] FIG. [Figure 19] FIG. 1 is a diagram showing a configuration of a module of a liquid crystal display device. [Figure 20] FIG. [Figure 21] 1A to 1C are diagrams illustrating electronic devices using semiconductor devices. [Figure 22] FIG. 10 is a longitudinal cross-sectional view of an inverted staggered transistor including an oxide semiconductor. [Figure 23] 23 is an energy band diagram (schematic diagram) taken along the line AA' in FIG. 22. [Figure 24] (A) shows the state where a positive voltage (VG>0) is applied to the gate electrode (GE), and (B) shows the state where a negative voltage (VG<0) is applied to the gate electrode (GE). [Figure 25] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and the embodiments and aspects thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0029] The present invention is applicable to integrated circuits such as microprocessors and image processing circuits, RF tags, semiconductors, etc. The semiconductor device can be used to manufacture various semiconductor devices such as display devices. It refers to all devices that can function by utilizing semiconductor characteristics, including semiconductor display devices, semiconductor circuits, etc. All electronic devices are semiconductor devices. Semiconductor display devices include liquid crystal display devices, organic light-emitting devices, Light-emitting devices with light-emitting elements, such as OLEDs, in each pixel, electronic paper, and DMDs (Digital Micromirror Device), PDP (Plasma Display Panel), FED(Field Emission Display) y) and other semiconductor display devices having circuit elements using semiconductor films in their drive circuits. It falls into that category.

[0030] (Embodiment 1) A bottom-gate transistor with a channel-etched structure will be taken as an example of a transistor according to one embodiment of the present invention. A structure of a transistor included in a semiconductor device and a manufacturing method thereof will be described.

[0031] As shown in FIG. 1(A), a gate electrode 101 is formed on a substrate 100 .

[0032] There is no significant limitation on the substrate that can be used as the substrate 100 having an insulating surface. At the very least, it is necessary for the material to have heat resistance sufficient to withstand subsequent heat treatment. A glass substrate manufactured by a fusion method or a float method can be used. If the temperature of the subsequent heat treatment is high, use a plate with a strain point of 730°C or higher. The glass substrate may be made of, for example, aluminosilicate glass or aluminoborosilicate glass. Glass materials such as acid glass and barium borosilicate glass are used. By containing more barium oxide (BaO) than boron oxide, more practical resistance is achieved. Thermal glass is obtained. For this reason, a glass substrate containing more BaO than B2O3 is used. is preferred.

[0033] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, a substrate made of an insulating material may be used. Alternatively, a substrate made of a crystallized glass may be used. A substrate in which an insulating film is provided on the surface of a metal substrate such as a stainless alloy may also be used.

[0034] In addition, substrates made of flexible synthetic resins such as plastic generally have a low heat resistance temperature. However, if it can withstand the processing temperatures in the subsequent manufacturing steps, it is possible to use a material such as a silicon dioxide film as the substrate 100. As a plastic substrate, polyethylene terephthalate (P Polyesters such as polyethersulfone (PES), polyethylene naphtha (PEP), Polyethylene terephthalate (PEN), Polycarbonate (PC), Polyether ether ketone (PEE K), polysulfone (PSF), polyetherimide (PEI), polyarylate (PA R), polybutylene terephthalate (PBT), polyimide, acrylonitrile butadiene Polystyrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, etc. Examples include:

[0035] An insulating film serving as a base film may be formed between the substrate 100 and the gate electrode 101. Examples of the base film include a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, and a nitride film. Either a single layer of aluminum film or aluminum nitride oxide film, or multiple layers In particular, an insulating film with high barrier properties, such as silicon nitride, can be used as the base film. A bare film, a silicon nitride oxide film, an aluminum nitride film, an aluminum nitride oxide film, or the like is used. By this, impurities in the atmosphere such as moisture or hydrogen, or alkali contained in the substrate 100 can be removed. Impurities such as alkali metals and heavy metals may be trapped in the oxide semiconductor film, the gate insulating film, or the oxide Therefore, it is possible to prevent the semiconductor from penetrating into the interface between the semiconductor film and other insulating film and its vicinity.

[0036] In this specification, an oxynitride is a compound having a composition in which oxygen is contained more than nitrogen. Nitrogen oxide is a substance that contains more nitrogen than oxygen. It refers to a substance.

[0037] The material of the gate electrode 101 is molybdenum, titanium, chromium, tantalum, tungsten, or nickel. Conductors made of metal materials such as chromium and scandium, and alloy materials whose main components are these metal materials. The conductive film or nitride of these metals can be used as a single layer or a laminate. If it can withstand the temperature of the heat treatment performed in the process, aluminum is used as the metal material. Aluminum or copper can be used. Aluminum or copper can avoid the problems of heat resistance and corrosion. To avoid this, it is recommended to use it in combination with high melting point metal materials. Molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. You can be there.

[0038] For example, a gate electrode 101 having a two-layer laminated structure may be formed by depositing molybdenum on an aluminum film. a two-layer structure with a molybdenum film laminated on a copper film, or a two-layer structure with a molybdenum film laminated on a copper film, or a two-layer structure in which a titanium nitride film or a tantalum nitride film is laminated on a copper film; It is preferable to have a two-layer structure in which a molybdenum film is laminated. The electrode 101 may be an aluminum film, an aluminum-silicon alloy film, or an aluminum The intermediate layer is an alloy film of aluminum and titanium or an alloy film of aluminum and neodymium, and the The structure is a laminate of a tungsten nitride film, a titanium nitride film, or a titanium film as upper and lower layers. It is preferable that

[0039] The gate electrode 101 may be made of indium oxide, an indium oxide tin oxide alloy, or zinc oxide alloy, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, or oxide By using a transparent oxide conductive film such as zinc gallium oxide, the aperture ratio of the pixel area can be improved. It can be done.

[0040] The thickness of the gate electrode 101 is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, a 150 nm film is formed by sputtering using a tungsten target. After forming a conductive film for the gate electrode of m, the conductive film is etched into a desired shape. The gate electrode 101 is formed by patterning. If the end of the electrode is tapered, the coverage of the gate insulating film laminated thereon is improved, which is preferable. The resist mask may be formed by an ink-jet method. When formed by the ink jet method, no photomask is used, which reduces manufacturing costs.

[0041] Next, a gate insulating film 102 is formed on the gate electrode 101. The gate insulating film 102 is , a silicon oxide film, a silicon nitride film, a silicon nitride film, a silicon nitride film, a silicon nitride film, a silicon nitride film, a silicon oxide ... silicon oxide film, silicon nitride oxide film, aluminum oxide film, aluminum nitride film, aluminum oxynitride film Aluminum nitride film, aluminum oxide nitride film, hafnium oxide film or tantalum oxide film in a single layer or The gate insulating film 102 can be formed by stacking layers. When forming a silicon oxide film by sputtering, it is desirable to minimize the content of A silicon target or a quartz target is used as the target, and a sputtering gas is Oxygen or a mixed gas of oxygen and argon is used.

[0042] By removing impurities, an oxide semiconductor that has been made i-type or substantially i-type (highly purified) Since the gate insulating film (oxide semiconductor) is extremely sensitive to the interface state and the interface charge, The interface with the gate insulating film 102 is important. The membrane (GI) is required to be of high quality.

[0043] For example, high density plasma CVD using microwaves (2.45 GHz) produces dense, high dielectric strength films. This is preferable because it allows the formation of a high-quality insulating film. By closely contacting the insulating film, the interface state is reduced and the interface characteristics are improved. Because it is possible.

[0044] Of course, if a good quality insulating film can be formed as a gate insulating film, sputtering is also possible. Other film formation methods such as the plasma CVD method and the like can also be applied. Even if the insulating film is one in which the film quality of the gate insulating film and the interface characteristics with the oxide semiconductor are modified by In any case, it is important that the quality of the gate insulating film is good, and that the oxidation Any material may be used as long as it can reduce the interface state density with the compound semiconductor and form a good interface.

[0045] Insulating films made of materials with high barrier properties, silicon oxide films with a low nitrogen content, and oxynitride films The gate insulating film 102 may have a structure in which an insulating film such as a silicon film is laminated. In this case, the insulating film such as a silicon oxide film or a silicon oxynitride film has a barrier property and an oxidizing property. The insulating film with high barrier properties is formed between the semiconductor film, for example, silicon nitride film, nitride oxide film, etc. Examples of the barrier include a silicon film, an aluminum nitride film, and an aluminum nitride oxide film. By using an insulating film with this property, impurities in the atmosphere such as moisture or hydrogen, or Impurities such as alkali metals and heavy metals contained in the oxide semiconductor film and the gate insulating film 1 02, or to the interface between the oxide semiconductor film and other insulating films and its vicinity. In addition, a silicon oxide film or an oxynitride film having a low nitrogen ratio that is in contact with the oxide semiconductor film can be formed. By forming an insulating film such as a silicon film, the insulating film made of a material with high barrier properties can be directly oxidized. This can prevent contact with the semiconductor film.

[0046] For example, the first gate insulating film is formed by sputtering to a thickness of 50 nm to 200 nm. The following silicon nitride films (SiN y (y>0)), and a second gate insulating film is formed on the first gate insulating film. As the insulating film, a silicon oxide film (SiO x (x>0) The gate insulating film 102 may be formed by layering the gate insulating film 102 with a thickness of 100 nm. can be set appropriately depending on the characteristics required for the transistor, and is in the range of 350 nm to 400 nm. It can be about m.

[0047] In this embodiment, a silicon nitride film having a thickness of 50 nm is formed by sputtering. A gate insulating film 10 having a structure in which a silicon oxide film having a thickness of 100 nm formed by Form 2.

[0048] In order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the gate insulating film 102 as much as possible, As a pre-treatment for film formation, a gate electrode 101 is formed in a pre-heating chamber of a sputtering device. The substrate 100 is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 100. The preheating temperature is preferably 100°C or higher and 400°C or lower. The temperature is preferably 150°C or higher and 300°C or lower. A pump is preferred. However, this preheating step can be omitted.

[0049] Next, a film having a thickness of 2 nm to 200 nm, preferably 3 nm, is deposited on the gate insulating film 102. The oxide semiconductor film 10 has a thickness of 3 nm to 20 nm, and more preferably has a thickness of 50 nm to 100 nm. The oxide semiconductor film 103 is formed by sputtering using an oxide semiconductor as a target. The oxide semiconductor film 103 is formed in a rare gas (for example, argon) atmosphere. Sputtering method under an oxygen atmosphere or a rare gas (e.g., argon) and oxygen atmosphere It can be formed by:

[0050] Note that before the oxide semiconductor film 103 was formed by a sputtering method, argon gas was introduced. Reverse sputtering is performed to generate plasma, and dust adhering to the surface of the gate insulating film 102 is removed. It is preferable to remove the target. In a nitrogen atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. It is also possible to use nitrogen or helium instead of argon atmosphere. Alternatively, the treatment may be carried out in an argon atmosphere to which oxygen, nitrous oxide, etc. have been added. Alternatively, the treatment may be carried out in an argon atmosphere to which chlorine, carbon tetrafluoride, or the like has been added.

[0051] The oxide semiconductor film 103 can be formed using any of the above-described oxide semiconductors.

[0052] In this embodiment, an acid containing In (indium), Ga (gallium), and Zn (zinc) is used. 30 nm thick In-Ga-Z obtained by sputtering using an In-Ga-Zr nitride semiconductor target An nO-based non-single-crystal film is used as the oxide semiconductor film 103. For example, the atomic ratio of each metal is In:Ga:Zn=1:1:0.5, In:Ga:Zn=1:1 :1, or an oxide semiconductor target having a composition ratio of In:Ga:Zn=1:1:2 The oxide semiconductor film 103 can be grown in a rare gas (typically, argon) atmosphere. In air, oxygen, or a rare gas (typically argon) and oxygen atmosphere, It can be formed by sputtering. The film may be formed using a target containing 2% by weight or more and 10% by weight or less of iO2. The filling rate of the oxide semiconductor target containing In, Ga, and Zn is 90% or more and 100% or more. The filling rate of the oxide semiconductor target is preferably 95% or more and 99.9% or less. By using the above, the formed oxide semiconductor film becomes a dense film.

[0053] The substrate is held in a processing chamber maintained in a reduced pressure state, and hydrogen and A sputtering gas from which moisture and oxygen have been removed is introduced, and a metal oxide is used as a target to deposit a metal oxide on the substrate 100. During the deposition, the substrate temperature is preferably 100° C. or higher and 600° C. or lower. Preferably, the temperature may be 200° C. or higher and 400° C. or lower. This allows the concentration of impurities contained in the formed oxide semiconductor film to be reduced. Damage caused by tarring is reduced. To remove residual moisture in the processing chamber, an adsorption type It is preferable to use a vacuum pump. For example, a cryopump, an ion pump, a titanium sa It is preferable to use a displacement pump. Also, a turbo pump is used as the exhaust means. A cold trap may be added to the chamber. The chamber may contain, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (HO), etc. (more preferably, carbon Since the exhaust gas contains the oxide semiconductor film formed in the deposition chamber, This reduces the concentration of impurities.

[0054] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. When a pulsed direct current (DC) power supply is used, particles that are generated during film formation are The oxide semiconductor film is preferable because it can reduce dust particles and make the film thickness distribution uniform. The thickness is set to 5 nm or more and 30 nm or less. The appropriate thickness depends on the oxide semiconductor material used. The thickness may be selected appropriately depending on the material.

[0055] Note that in order to prevent hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor film 103 as much as possible, In order to do this, as a pre-treatment for film formation, the gate insulating film 102 is formed in the pre-heating chamber of the sputtering device. The substrate 100 on which the film is formed is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 100. It is preferable to desorb and exhaust the gas. The preheating temperature is 100°C or higher and 400°C or lower. The temperature is preferably 150°C or higher and 300°C or lower. A cryopump is preferable. However, this preheating process can be omitted. The preheating is performed up to the source electrode 111 and the drain electrode 112 before the insulating film 113 is formed. The same process may be carried out on the formed substrate 100 .

[0056] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply, and D There is also the pulsed DC sputtering method, which applies a bias in a pulsed manner. The RF sputtering method is mainly used to form insulating films, while the DC sputtering method The tarring method is mainly used when forming a metal film.

[0057] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0058] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. The ECR device uses a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the sputtering method.

[0059] In addition, as a film formation method using a sputtering method, a target material and a sputtering gas are mixed during film formation. Reactive sputtering method to form compound thin films by chemically reacting the silicon dioxide and silicon dioxide components. There is also a bias sputtering method in which a voltage is applied to the substrate during film formation.

[0060] The gate insulating film 102 and the oxide semiconductor film 103 are successively formed without being exposed to the air. By continuously forming the film without exposing it to the air, the interface is free from water and hydrochloric acid. Each layer interface is free from contamination by atmospheric components and impurities floating in the air, such as carbon. Therefore, variations in transistor characteristics can be reduced.

[0061] Next, as shown in FIG. 1B, the oxide semiconductor film 103 is removed by etching or the like to form a desired The gate insulating film is formed at a position where it overlaps with the gate electrode 101. An island-shaped oxide semiconductor film 104 is formed over the oxide semiconductor film 102 .

[0062] A resist mask for forming the island-shaped oxide semiconductor film 104 is formed by an inkjet method. If the resist mask is formed by the inkjet method, a photomask is not required. Therefore, the manufacturing cost can be reduced.

[0063] In addition, when forming a contact hole in the gate insulating film 102, the process is performed by forming an island-shaped oxide film. This can be done when the semiconductor film 104 is formed.

[0064] Note that the etching for forming the island-shaped oxide semiconductor film 104 is dry etching. Dry etching can be performed by wet etching, or both can be used. The gas may be a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron trichloride ( Preferred are silicon tetrachloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc. In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur hexafluoride (SF 6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HB r), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas containing , etc. can be used.

[0065] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0066] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid, Organic acids such as enoic acid and oxalic acid can be used. The etching solution used after wet etching may be The etching solution containing the removed material is then washed away. The liquid may be purified and the materials contained therein may be reused. By recovering and reusing materials such as indium contained in the membrane, resources can be used effectively. Costs can be reduced.

[0067] Note that reverse sputtering is performed before forming a conductive film in the next step, and the island-shaped oxide semiconductor film 104 and It is also preferable to remove resist residues adhering to the surface of the gate insulating film 102. .

[0068] Next, the mixture is heated under a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or The dew point was measured using an ultra-dry air (CRDS (Cavity Ring Down Laser Spectroscopy)) dew point meter. The moisture content measured by the method is 20 ppm or less (-55°C in dew point equivalent), preferably 1 ppm The oxide semiconductor film 10 is subjected to a fluorine-containing treatment under an atmosphere of 10 ppb or less (more preferably, air). The oxide semiconductor film 104 is subjected to first heat treatment. By performing heat treatment on the oxide semiconductor film 104, the oxide semiconductor film 104 is As shown in FIG. 1, the oxide semiconductor film 105 from which moisture and hydrogen are released is formed. Specifically, 500°C or higher and 850°C or lower (or a temperature below the strain point of the glass substrate), preferably 550 For example, the heat treatment may be performed at 600°C for 3 to 6 minutes. The RTA method allows dehydration or dehydrogenation in a short time, so glass In this embodiment, the heat treatment device can be used even at a temperature exceeding the distortion point of the substrate. The oxide semiconductor film 104 was heated in a nitrogen atmosphere using an electric furnace, which is one of the furnaces. After the plate temperature reached 600°C and the heat treatment was carried out for 6 minutes, The oxide semiconductor film 105 is obtained while preventing re-entry of water or hydrogen.

[0069] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gases are used.

[0070] For example, as the first heat treatment, a base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate is moved and placed in the oven, heated for several minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. GRTA can be used to heat the food at high temperatures in a short time. become.

[0071] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain hydrogen or the like. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. Preferably, the concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable that the concentration is 0.1 ppm or less.

[0072] Then, as shown in FIG. 1C, the island-shaped oxide semiconductor film 105 The crystalline region 106 is formed in the surface layer of the crystalline region 106. The crystalline region 106 has a particle size of 1 nm. It contains so-called nanocrystals (also written as nanocrystals) with a size of 20 nm or less. The island-shaped oxide semiconductor film 105 is amorphous or It contains a mixture of amorphous and microcrystalline regions, with microcrystalline regions scattered throughout the amorphous regions. The above values ​​are merely examples, and the present invention should not be interpreted as being limited to the above numerical ranges. The target was formed by sputtering with an atomic ratio of In:Ga:Zn=1:1:1. In the case of an In-Ga-Zn-O oxide semiconductor film formed using a target with a different atomic ratio, The crystallization of the surface layer of the oxide semiconductor film is more likely to proceed than when a SiO 2 film is used. Therefore, the crystalline region 106 is likely to form in a deeper region.

[0073] Next, as shown in FIG. 1D, the oxide semiconductor film having a crystalline region in the surface layer portion is subjected to ion implantation. Oxygen is added by using an implantation method or an ion doping method. By adding oxygen to the oxide semiconductor film 105 by a doping method or the like, the excess oxygen The oxide semiconductor film 107 is formed by adding oxygen. The bond between the metal and hydrogen or the bond between the metal and hydroxyl group is broken, and These hydrogen or hydroxyl groups react with oxygen to produce water. The second heat treatment makes it easier to eliminate impurities such as hydrogen or hydroxyl groups as water. It can be easily done.

[0074] The ion implantation method converts a source gas into plasma and extracts ion species contained in this plasma. The ion species having a predetermined mass are accelerated and then separated into an ion beam. The ion doping method is a method of injecting ions into a material. Ion species are extracted from the plasma by the action of a predetermined electric field, and the extracted ion species are analyzed by mass spectrometry. This method involves accelerating the ions without separating them and injecting them into the object to be treated as an ion beam. By adding oxygen using ion implantation, impurities such as metal elements are converted into oxides together with oxygen. The ion doping method can prevent ions from being added to the semiconductor film. The area irradiated with the ion beam can be made larger than that of the implantation method, so the ion doping By adding oxygen using the doping method, the tact time can be shortened.

[0075] When oxygen gas is used to add oxygen by ion implantation, the acceleration voltage should be set to 5 kV or more and 100 kV or less, dose of 1×10 13 ions / cm 2 More than 1×10 16 ions / cm 2 The following would suffice.

[0076] In addition to the addition of oxygen to the oxide semiconductor film 105 by ion implantation, The substrate on which the semiconductor film 105 is formed is heated to 500° C. or higher and 850° C. or lower (or glass The heat treatment is carried out at a temperature below the strain point of the substrate, preferably in the range of 550°C to 750°C. It is also possible to do so.

[0077] The crystals contained in the crystalline region 106 formed in the surface layer of the oxide semiconductor film 105 The damage is caused by the addition of oxygen using ion implantation or ion doping. Therefore, the surface portion of the oxide semiconductor film 107 has the same structure as the oxide semiconductor film 105 before oxygen is added. The crystallinity of the crystalline region 106 is lower than that of the crystalline region 106. The amorphous region has the same structure as that of the amorphous region of the nitride semiconductor film 105 .

[0078] Next, a second heat treatment is carried out under the same conditions as the first heat treatment. Specifically, it can be performed under a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, or an acid atmosphere. Under nitrogen gas atmosphere or ultra-dry air (CRDS (Cavity Ring-Down Laser Spectroscopy) When measured using a dew point meter, the moisture content is 20 ppm (-55°C in dew point equivalent) or less. In an atmosphere of preferably 1 ppm or less, more preferably 10 ppb or less (air), 500°C or higher and 850°C or lower (or a temperature below the strain point of the glass substrate), preferably 550 The heat treatment can be performed at temperatures between 750°C and 750°C. When heat treatment is performed using the anneal process, for example, at 600°C for 3 to 6 minutes. The RTA method allows dehydration or dehydrogenation in a short time, so the glass The substrate can be treated at a temperature exceeding the distortion point. Using an electric furnace, the substrate temperature reached 600°C under a nitrogen atmosphere. After the heating process for 1 minute, the material is kept away from the atmosphere, preventing the re-incorporation of water and hydrogen. 1(E), an oxide semiconductor film 108 is obtained. Note that the heat treatment This may be performed multiple times after the formation of the compound semiconductor film 108.

[0079] In one embodiment of the present invention, oxygen is added to the oxide semiconductor film 105 to form an oxide semiconductor. The bond between the metal and hydrogen or the bond between the metal and hydroxyl group is broken, and These hydrogen or hydroxyl groups react with oxygen to produce water. By carrying out the second heat treatment, impurities such as hydrogen or hydroxyl groups that have remained strongly are removed by heating. Therefore, the islands formed by the heat treatment can be easily removed. The oxide semiconductor film 108 has moisture that is not removed by the first heat treatment. Since impurities such as hydrogen and the like are removed, the oxide semiconductor film 105 is Furthermore, it becomes an i-type (intrinsic semiconductor) or as close to i-type as possible. The impurities mentioned above cause the semiconductor to desorb and become i-type (intrinsic semiconductor) or very close to i-type. This prevents the deterioration of transistor characteristics, such as a shift in the value voltage, and reduces the off-state current. It can be reduced.

[0080] Also, at 85°C, 2 x 10 6 V / cm, 12-hour gate bias thermal stress test (BT In the test, when impurities are added to the oxide semiconductor, the The bond to the main component is broken by a strong electric field (B: bias) and high temperature (T: temperature), and The resulting dangling bonds induce a drift in the threshold voltage (Vth). As described above, the interface characteristics between the gate insulating film and the oxide semiconductor film are improved, and the oxide semiconductor film is also By removing impurities, especially hydrogen and water, from the semiconductor film as much as possible, Therefore, a more stable transistor can be obtained.

[0081] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gases are used.

[0082] For example, as the second heat treatment, the substrate is heated to a high temperature of 650°C to 700°C in an inert gas. The plate is moved and placed in the oven, heated for several minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. GRTA can be used to heat the food at high temperatures in a short time. become.

[0083] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain hydrogen or the like. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. Preferably, the concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable that the concentration is 0.1 ppm or less.

[0084] In the oxide semiconductor film 105, water or hydrogen is removed and oxygen is removed by the first heat treatment. Although oxygen deficiency occurs, the addition of oxygen using ion implantation or ion doping This allows sufficient oxygen to be supplied to the oxide semiconductor film in which oxygen vacancies have occurred. The hydrogen or water removed by the first heat treatment is not a constituent element of the oxide semiconductor. The oxygen added later is one of the constituent elements of the oxide semiconductor. Therefore, the stoichiometric composition ratio can be satisfied. After the addition of oxygen, the second heat treatment is carried out to remove the damage. The crystalline region 106 is repaired, and the surface of the oxide semiconductor film 108 is further removed. The crystal growth is further promoted to the inside, and an oxide semiconductor film 108 is formed as shown in FIG. This second heating step allows the formation of a crystalline region 109 that extends to a deeper portion. In the second heat treatment, crystal growth is further promoted than in the first heat treatment, so that In this case, the crystal grains are adjacent to each other, and the metal elements constituting the oxide semiconductor are The adjacent crystal grains are connected, that is, connected.

[0085] The crystalline region 109 will be described in more detail below. The crystals in the crystalline region 109 at the surface layer are The c-axis is oriented in a direction substantially perpendicular to the surface of the oxide semiconductor film 108. The crystals are adjacent to each other. For example, an In-Ga-Zn-O oxide semiconductor When using a material, the crystal of the crystalline region 109 is an InGaZnO4 crystal whose c-axis is an oxide The semiconductor film 108 is oriented in a direction substantially perpendicular to its surface.

[0086] The InGaZnO4 crystal contains either In, Ga, or Zn and has an a-axis (a-ax It can be seen as a stack of layers parallel to the is and b-axes. That is, the InGaZnO4 crystal has a first layer containing In and a second layer containing In. A structure in which a second layer having a ZnO atom and a third layer containing In are stacked in the c-axis direction. Equipped with.

[0087] The electrical conductivity of InGaZnO4 crystals is mainly controlled by In. The electrical characteristics of the first to third layers in the directions parallel to the a-axis and b-axis are This is because the first to third layers containing In have good electrical conductivity. In one or more cases, the 5s orbital of one In atom overlaps with the 5s orbital of an adjacent In atom. This is because it helps shape career paths.

[0088] Such crystal orientation affects the electrical characteristics of the oxide semiconductor film 108. Specifically, for example, the electrical characteristics in a direction parallel to the surface of the oxide semiconductor film 108 are improved. This is because the c-axis of the InGaZnO4 crystal is approximately perpendicular to the surface of the oxide semiconductor film 108. In the InGaZnO4 crystal, the electrons are oriented in the directions parallel to the a-axis and b-axis. This is because the current flows.

[0089] In one embodiment of the present invention, crystal grains are adjacent to each other in the crystalline region, and the oxide The metal elements that make up the compound semiconductor are connected between adjacent crystal grains, that is, Therefore, as shown in Figure 4, the a-axis and A current easily flows in a direction parallel to the b-axis, and a current easily flows in a direction parallel to the surface of the oxide semiconductor film 108. The electrical characteristics are further improved. Note that the oxide semiconductor film 108 shown in FIG. The amorphous region 110 as the main component and the crystalline region formed in the surface layer portion of the oxide semiconductor film 108 and region 109.

[0090] The crystal structure of the crystalline region 109 is not limited to the above, and may include crystals of other crystal structures. For example, when an In-Ga-Zn-O oxide semiconductor material is used, InG In addition to ZnO4 crystals, crystals such as In2Ga2ZnO7 and InGaZn5O8 are also included. Of course, the crystal region 109 may have InGaZnO4 crystals throughout. It is more effective and preferable to do so.

[0091] As described above, the oxide semiconductor film 108 has the crystalline region 109 in the surface layer portion. In particular, the crystalline region 109 is made of InGaZnO4 The c-axis of the crystal is oriented in a direction substantially perpendicular to the surface of the oxide semiconductor film 108. In this case, the oxide semiconductor film 108 is formed by the electrical properties of the InGaZnO 4 crystal. Therefore, the carrier mobility in the surface layer portion is increased. The field-effect mobility of the resulting transistor increases, and favorable electrical characteristics can be achieved.

[0092] Furthermore, the crystalline region 109 is more stable than the amorphous region 110 other than the crystalline region 109. Therefore, by having this in the surface layer portion of the oxide semiconductor film 108, impurities can be easily introduced into the amorphous region 110. It is possible to reduce the incorporation of hydrogen, water, hydroxyl groups, or hydrides. Therefore, the reliability of the oxide semiconductor film 108 can be improved.

[0093] Through the above steps, the concentration of hydrogen in the oxide semiconductor film can be reduced and the oxide semiconductor film can be highly purified. This makes it possible to stabilize the oxide semiconductor film. By heat treatment, an oxide semiconductor film with extremely low carrier density and a wide band gap is formed. Therefore, a transistor can be fabricated using a large-area substrate. Therefore, mass productivity can be improved. By using a semiconductor film, it is possible to achieve high voltage resistance, low short channel effect, and high on-off ratio. Therefore, it is possible to fabricate a high-performance transistor.

[0094] The amorphous region 110 is mainly composed of an amorphous oxide semiconductor film. "Among the amorphous oxide semiconductors, for example, is 50% or more. This refers to a state in which the membrane occupies 50% or more by volume (or weight). In addition to the crystalline oxide semiconductor film, the oxide semiconductor film may contain crystals. The ratio is preferably less than 50% by volume (or weight), but is not limited to these ranges. There is no need to be.

[0095] When an In-Ga-Zn-O oxide semiconductor film is used as the material for the oxide semiconductor film, The composition of the amorphous region 110 is such that the content (atomic %) of Zn is 0.01% or less than the content of In or Ga. It is preferable that the amount (atomic %) of the SiO2 alloy is equal to or greater than 1. This is because it becomes easier to form the crystalline region 109 with a predetermined composition.

[0096] In this embodiment, the oxide semiconductor film 103 is processed into a desired shape to form an island-shaped oxide semiconductor film. After forming the conductive film 104, a first heat treatment, oxygen addition, and a second heat treatment are performed. However, the present invention is not limited to this structure. The oxide semiconductor film 103 before the formation of the oxide semiconductor film 4 is subjected to first heat treatment, addition of oxygen, and second After the heat treatment, the shape of the oxide semiconductor film is processed to form an island-shaped oxide semiconductor film. Alternatively, the oxide semiconductor film 103 may be subjected to the first heat treatment and then The shape of the conductor film is processed to form an island-shaped oxide semiconductor film, and then the island-shaped oxide semiconductor Oxygen may be added to the film, and second heat treatment may be performed. After the first heat treatment and the addition of oxygen to the film 103, the shape of the oxide semiconductor film is changed. An island-shaped oxide semiconductor film is formed by processing the oxide semiconductor film. The heat treatment may be performed as follows.

[0097] Next, as shown in FIG. 2A, a thin film was formed on the gate insulating film 102 and the oxide semiconductor film 108. A conductive film that becomes a source electrode and a drain electrode (including wiring formed in the same layer as these electrodes) is formed. After the formation, the conductive film is patterned to form a source electrode 111 and a drain electrode 11 The conductive film may be formed by sputtering or vacuum deposition. The materials for the conductive film that will become the inner electrode (including the wiring formed in the same layer) include Al, Elements selected from Cr, Cu, Ta, Ti, Mo, and W, or those containing the above elements as components Examples include alloys of the above elements or alloy films made of a combination of the above elements. A high melting point metal film such as Cr, Ta, Ti, Mo, or W is laminated on the upper or lower side of the metal film. In addition, Si, Ti, Ta, W, Mo, Cr, Nd, Sc, Y, etc. The Al material contains elements that prevent the formation of hillocks and whiskers in the Al film. Use of this material makes it possible to improve heat resistance.

[0098] The conductive film may have a single layer structure or a stacked structure of two or more layers. a single-layer structure of an aluminum film containing titanium; a two-layer structure of a titanium film laminated on an aluminum film; A film is then laminated on top of the Ti film, an aluminum film is then laminated on top of that, and a Ti film is then formed on top of that. Examples include a three-layer structure.

[0099] Also, the conductive layer that becomes the source electrode and the drain electrode (including the wiring formed in the same layer as these) The film may be formed of a conductive metal oxide. In2O3, tin oxide (SnO2), zinc oxide (ZnO), indic oxide Tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium oxide zinc oxide alloy (In2O3-ZnO) or the metal oxide material containing silicon or silicon oxide The mixture can be used.

[0100] When a heat treatment is performed after the conductive film is formed, the conductive film must have heat resistance to withstand this heat treatment. It is preferable that

[0101] Then, a resist mask is formed on the conductive film, and selective etching is performed to form the source electrode 1 11. After forming the drain electrode 112, the resist mask is removed.

[0102] In the photolithography process, ultraviolet light and KrF laser light are used for exposure when forming resist masks. The lower end of the source electrode and the lower end of the source electrode adjacent to each other on the oxide semiconductor film 108 are laser-irradiated. The channel length L of the transistor to be formed later is determined by the gap width between the lower end of the drain electrode. When performing exposure with a channel length L of less than 25 nm, the exposure time is set to several nm to several tens of nm. Extreme ultraviolet light with an extremely short wavelength of 1000m is used. Exposure is performed when forming a resist mask in the photolithography process. Exposure with extreme ultraviolet light is The resolution is high and the depth of focus is large. Therefore, the channel length L of the transistor to be formed later is It is possible to make it 10nm or more and 1000nm or less, which will increase the operating speed of the circuit. Furthermore, the off-state current is extremely small, which contributes to reducing power consumption.

[0103] Note that the conductive film is etched so as not to remove the oxide semiconductor film 108 as much as possible. The materials and etching conditions are adjusted appropriately.

[0104] In this embodiment, a titanium film is used as the conductive film, and a solution containing ammonia and hydrogen peroxide (ammonia) is used. The conductive film is wet-etched using ammonia hydrogen peroxide to form the source electrode 111, The drain electrode 112 is formed. Specifically, the solution containing ammonia hydrogen peroxide is 31% by weight. A mixture of 28% by weight of hydrogen peroxide solution, 28% by weight of ammonia water, and water in a volume ratio of 5:2:2. Using a solution, or using a gas containing chlorine (Cl2), boron chloride (BCl3), etc. Alternatively, the conductive film may be dry-etched.

[0105] When the source electrode 111 and the drain electrode 112 are formed by the above patterning, island-shaped The exposed portion of the oxide semiconductor film 108 is partially etched, whereby an island-shaped oxide semiconductor A groove (a recess) may be formed in the body film 108. A resist mask for forming the electrode 112 may be formed by an ink-jet method. When a photomask is formed by the inkjet method, no photomask is used, reducing manufacturing costs. can be reduced.

[0106] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, A resist mask formed by a multi-tone mask that gives the applied light multiple levels of intensity is used. The resist mask formed using the multi-tone mask may be formed by etching a plurality of resist masks. The shape can be further modified by etching. Therefore, it can be used in multiple etching processes to process different patterns. A single multi-tone mask can be used to create a register that corresponds to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding The photolithography process can also be eliminated, which simplifies the process.

[0107] The source electrode 111 and the drain electrode 112 are formed in the crystalline region 10 of the oxide semiconductor film 108. The highly conductive crystalline region 109 is in contact with the source electrode 111 and the drain electrode 11 2 contacts the source electrode 111 and the drain electrode 112, and the oxide semiconductor film 108 This reduces the contact resistance between the The on-current can be increased.

[0108] Next, plasma treatment is performed using gases such as N2O, N2, or Ar. The annealing process removes adsorbed water and other substances adhering to the exposed surface of the oxide semiconductor film. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0109] After the plasma treatment, as shown in FIG. 2(B), the source electrode 111 and the drain electrode 112 are The insulating film 113 is formed to cover the electrode 112 and the oxide semiconductor film 108. 3 is preferably a single layer insulating film that does not contain impurities such as moisture and hydrogen as much as possible. The insulating film 113 may contain hydrogen or may be formed of a plurality of stacked insulating films. When hydrogen is introduced into the oxide semiconductor film, the hydrogen penetrates into the oxide semiconductor film, or the hydrogen is absorbed by oxygen in the oxide semiconductor film. This causes a loss of resistance in the back channel of the oxide semiconductor film (becoming n-type), resulting in a parasitic Therefore, the insulating film 113 should contain as little hydrogen as possible. It is important that hydrogen is not used in the film formation method so that the insulating film 113 is formed. It is desirable to use a material with high barrier properties. For example, a nitride insulating film with high barrier properties is used. Silicon film, silicon nitride oxide film, aluminum nitride film, aluminum nitride oxide film, etc. When a plurality of laminated insulating films are used, it is possible to use a film having a higher barrier property than the insulating film having a higher barrier property. Insulating films such as silicon oxide films and silicon oxynitride films with a low nitrogen ratio are used instead of oxide semiconductor films. Then, an insulating film with a low nitrogen ratio is sandwiched between the source electrode 1 and the gate electrode 2. 11, a barrier film having a barrier property is formed so as to overlap with the drain electrode 112 and the oxide semiconductor film 108. By using an insulating film having a barrier property, the oxide semiconductor film 108 In the gate insulating film 102, or at the interface between the oxide semiconductor film 108 and other insulating films and in the vicinity thereof In addition, impurities such as moisture and hydrogen can be prevented from entering the oxide semiconductor film. Form an insulating film such as a silicon oxide film or silicon oxynitride film with a low nitrogen ratio in contact with 108. By doing so, the insulating film using a material with a high barrier property is in direct contact with the oxide semiconductor film 108. This can be prevented.

[0110] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering. The insulating film 113 has a structure in which a silicon nitride film having a thickness of 100 nm formed by a method is laminated. The substrate temperature during film formation may be set to a temperature between room temperature and 300° C. Set the temperature to 100°C.

[0111] Note that heat treatment may be performed after the insulating film 113 is formed. In an atmosphere (nitrogen, helium, neon, argon, etc.), preferably at 200°C The heating is performed at a temperature of 250° C. to 350° C., for example. Then, a heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. Before the in-electrode 112 is formed, the oxide semiconductor film is heated to 1000° C. for 1 hour, similar to the heat treatment performed on the oxide semiconductor film. A high-temperature, short-time RTA treatment may be performed. The exposed region of the oxide semiconductor film 108 provided on the insulating film 113 containing oxygen is in contact with the exposed region of the oxide semiconductor film 108. After the oxidation, heat treatment is performed, whereby oxygen is supplied to the oxide semiconductor film 108. Therefore, a region of the oxide semiconductor film 108 in contact with the insulating film 113 is selectively made into an oxygen-excess state. As a result, it is possible to obtain a structure that satisfies the stoichiometric composition ratio. The channel forming region overlapping with the gate electrode 101 becomes an I-type, and the electrical characteristics of the transistor are The timing of this heat treatment can improve the quality and reduce the variations in electrical characteristics. The step of forming the insulating film 113 is not particularly limited as long as it is performed after the insulating film 113 is formed. By combining this with heat treatment to lower the resistance of the transparent conductive film, the number of processes can be increased. This can be done without any hassle.

[0112] Through the above steps, the transistor 114 is formed.

[0113] FIG. 2C shows a top view of the transistor 114 shown in FIG. The cross-sectional view taken along the dashed line A1-A2 corresponds to FIG. 2(B).

[0114] The transistor 114 has a gate electrode 101 formed on a substrate 100 having an insulating surface. , a gate insulating film 102 on the gate electrode 101, and a gate electrode 103 on the gate insulating film 102. The oxide semiconductor film 108 overlapping the electrode 101 and the oxide semiconductor film 108 formed thereon The transistor 1 has a pair of source electrodes 111 and drain electrodes 112. 14 may include an insulating film 113 formed over the oxide semiconductor film 108 as a component. The transistor 114 shown in FIG. 2C has a source electrode 111 and a drain electrode 112. The oxide semiconductor film 108 is partly etched between the first and second electrodes to form a channel-etched structure. do.

[0115] Although the transistor 114 has been described as a single-gate transistor, If necessary, a transistor having a multi-gate structure having a plurality of channel forming regions is also formed. It is possible.

[0116] Note that the transistor 114 formed by the manufacturing method shown in FIGS. The crystalline region 109 located between the electrode 111 and the drain electrode 112 is removed by etching. The amorphous region 110 is exposed by the amorphous region 110. Whether the surface layer 110 is exposed or not depends on whether the surface layer where the crystalline region 109 is present is exposed or not. How deep does it extend from the surface of the When forming the doped electrode 112, how much of the surface of the oxide semiconductor film 108 is etched? It depends on whether

[0117] In FIG. 11A, an oxide semiconductor film 108 includes a crystalline region 109 and an amorphous region 110. Furthermore, the surface layer portion where the crystalline region 109 exists is at a distance (depth) from the surface of the oxide. 10 shows a cross-sectional view of the oxide semiconductor film 108 in the case where the thickness is half or more of the thickness of the semiconductor film 108. 11B shows a structure of a semiconductor device manufactured using the oxide semiconductor film 108 shown in FIG. FIG. 11B shows an example of a cross-sectional view of a channel-etched transistor. The surface layer where the region 109 is present is closer to the surface than the transistor 114 shown in FIGS. Since the junction extends to a deeper region, the junction is located between the source electrode 111 and the drain electrode 112. The crystalline region 109 remains.

[0118] As shown in FIG. 2(B), the present invention provides a method for forming a semiconductor device between a source electrode 111 and a drain electrode 112. The amorphous region 110 may be exposed, or may be formed as shown in FIG. 11(B). However, a structure in which the crystal region 109 remains may be used. In the case of a channel-etch transistor, the gate electrode 101 of the oxide semiconductor film 108 To prevent the formation of a parasitic channel in the back channel area far from the It is desirable that the hole portion be formed of an amorphous region 110 having high resistance. As shown, an amorphous region 110 is exposed between the source electrode 111 and the drain electrode 112. The configuration that exposes the transistors allows for a higher on / off ratio.

[0119] Furthermore, when the crystallization of the oxide semiconductor film 108 reaches a deeper portion, the oxide semiconductor film 108 In some cases, almost the entire area is occupied by the crystalline region 109. When almost the entire oxide semiconductor film 108 is occupied by the crystalline region 109, 12B is a cross-sectional view of the oxide semiconductor film 108 shown in FIG. An example of a cross-sectional view of a channel-etched transistor manufactured using the above method is shown in FIG. In B), the region of the oxide semiconductor film 108 that overlaps with the gate electrode 101, that is, the channel The channel formation region is entirely made up of the crystalline region 109. The carrier mobility in the region increases, which increases the field-effect mobility of the transistor and improves the This allows for excellent electrical characteristics.

[0120] Next, a conductive film is formed on the insulating film 113, and then the conductive film is patterned. As shown in FIG. 3(A), a back gate electrode 115 is formed at a position overlapping with the oxide semiconductor film 108. The back gate electrode 115 may be formed on the gate electrode 101 or the source electrode 11. The gate electrode 112 can be formed using the same material and structure as the gate electrode 112.

[0121] The thickness of the back gate electrode 115 is 10 nm to 400 nm, preferably 100 nm to 20 In this embodiment, a structure in which a titanium film, an aluminum film, and a titanium film are stacked is used. A conductive film having a structure is formed. Then, a resist mask is formed by photolithography. Then, unnecessary portions are removed by etching to process the conductive film into a desired shape (patterning). By performing the above-described process (etching), the back gate electrode 115 is formed.

[0122] Next, as shown in FIG. 3(B), an insulating film 116 is formed to cover the back gate electrode 115. The insulating film 116 is formed by preventing moisture, hydrogen, oxygen, and the like in the atmosphere from damaging the characteristics of the transistor 114. It is desirable to use a material with high barrier properties that can prevent the material from affecting the properties of the product. For example, insulating films with high barrier properties include silicon nitride films, silicon nitride oxide films, and aluminum nitride films. or an aluminum nitride oxide film, etc., by plasma CVD or sputtering method, etc. In order to obtain a barrier effect, the insulating film 11 can be formed as a single layer or a laminated layer. The film 6 is preferably formed to a thickness of, for example, 15 nm to 400 nm.

[0123] In this embodiment, a 300 nm insulating film is formed by plasma CVD. The film formation conditions are as follows: The flow rate of silane gas was 4 sccm, and the flow rate of nitrous oxide (N2O) was 800 sccm. The substrate temperature is set to 400°C.

[0124] 3C shows a top view of the semiconductor device shown in FIG. This corresponds to the cross-sectional view taken along dashed line A1-A2 in FIG.

[0125] Note that in FIG. 3B, the back gate electrode 115 covers the entire oxide semiconductor film 108. However, the present invention is not limited to this configuration. It is sufficient that the insulating film 104 overlaps with at least part of a channel formation region of the oxide semiconductor film 108. stomach.

[0126] The back gate electrode 115 may be in an electrically insulating floating state. In the latter case, the back gate electrode 115 may be in a state where a potential is applied. The potential may be the same as that of the gate electrode 101, or may be a fixed potential such as ground. The level of the potential applied to the back gate electrode 115 can be controlled. Thus, the threshold voltage of the transistor 114 can be controlled.

[0127] As in this embodiment, impurities such as hydrogen and water contained in the oxide semiconductor film are removed as much as possible. How purifying an oxide semiconductor film affects transistor characteristics is explained below.

[0128] FIG. 22 is a longitudinal cross-sectional view of an inverted staggered transistor using an oxide semiconductor. An oxide semiconductor film (OS) is provided on a gate electrode (GE) via a gate insulating film (GI), and A source electrode (S) and a drain electrode (D) are provided on top.

[0129] FIG. 23 shows an energy band diagram (schematic diagram) in the cross section A-A' shown in FIG. In 23, the black circles (●) represent electrons, and the white circles (○) represent holes, each of which has a charge (-q, + When a positive voltage (VD>0) is applied to the drain electrode, the dashed line indicates the gate When no voltage is applied to the electrode (VG=0), the solid line indicates the case where a positive voltage (VG>0) is applied to the gate electrode. When no voltage is applied to the gate electrode, the potential barrier is high. The off state is when no carriers (electrons) are injected from the electrode to the oxide semiconductor, and no current flows. On the other hand, when a positive voltage is applied to the gate electrode, the potential barrier decreases, allowing current to flow. Indicates the on state.

[0130] FIG. 24 is an energy band diagram (schematic diagram) in the cross section taken along line B-B' in FIG. 22. FIG. 24(A) shows the state where a positive potential (VG>0) is applied to the gate electrode (GE), This shows the on-state where carriers (electrons) flow between the source electrode and the drain electrode. FIG. 24(B) shows a state in which a negative potential (VG<0) is applied to the gate electrode (GE). The case where the transistor is in the off state (no minority carriers flow) is shown.

[0131] Figure 25 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor Shows.

[0132] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. Conventional oxide semiconductors are generally n-type, and the Fermi level (Ef) in this case is It is located away from the intrinsic Fermi level (Ei) in the center of the gap and closer to the conduction band (Ec). In the oxide semiconductor, some of the hydrogen atoms act as donors, and the oxide semiconductor It is known that oxygen deficiency is one of the factors that cause n-type formation. It is known that:

[0133] In contrast, the oxide semiconductor according to the present invention can remove hydrogen, which is an n-type impurity, from the oxide semiconductor. The oxide semiconductor is highly purified by removing impurities other than the main component of the oxide semiconductor as much as possible, and By removing oxygen vacancies, oxide semiconductors are made intrinsic (i-type) or intrinsic. That is, instead of adding impurities to make the oxide semiconductor i-type, hydrogen, water, etc. By removing as many impurities and oxygen vacancies as possible and purifying the material, it becomes an i-type (intrinsic semiconductor) or i The feature of this method is to obtain an oxide semiconductor that is as close as possible to an intrinsic semiconductor. Therefore, as shown by the arrow, the Fermi level (Ef) is at the same level as the intrinsic Fermi level (Ei). It can be made as close as possible to the original.

[0134] The band gap (Eg) of the oxide semiconductor is 3.15 eV and the electron affinity (χ) is 4.3 V. It is said that the work function of titanium (Ti) that constitutes the source and drain electrodes is The electron affinity (χ) of the oxide semiconductor is approximately equal to the electron affinity (χ) of the metal-oxide semiconductor interface. In this case, no Schottky barrier is formed for electrons.

[0135] At this time, the electrons are transferred to the gate insulating film and the highly purified oxide semiconductor as shown in FIG. The electrons move through the lowest energetically stable part on the oxide semiconductor side at the interface with the oxide semiconductor.

[0136] In addition, in FIG. 24(B), a negative potential (reverse bias) is applied to the gate electrode (GE). Since the number of holes, which are minority carriers, is essentially zero, the current is close to zero. value.

[0137] In this way, the oxide semiconductor is highly oxidized so that elements other than the main components (impurity elements) are not included as much as possible. By purifying it, it becomes intrinsic (i-type) or substantially intrinsic, so that the gate insulation Therefore, the gate insulating film must have a good interface with the oxide semiconductor. Specifically, for example, the power supply frequency of the VHF band to the microwave band is required. Insulating films produced by CVD using high-density plasma generated at high frequencies, and sputtering It is preferable to use an insulating film manufactured by a coating method.

[0138] For example, if the channel width W of a transistor is 1×10 4 μm and the channel length L is 3 μm. Even if the off-state current is 10 -13 A or less, subthreshold swing value (S value) A voltage of 0.1V / dec. (gate insulating film thickness 100nm) can be obtained.

[0139] In this way, efforts are made to minimize the inclusion of impurities such as water and hydrogen other than the main components of oxide semiconductors. By purifying the oxide semiconductor film, the transistor can operate satisfactorily. This can be done.

[0140] (Embodiment 2) In this embodiment, the present invention is suitable for power devices that can control even higher voltages or currents. The structure and manufacturing method of the transistor will be described. Or, parts and steps having similar functions can be performed in the same manner as in Embodiment 1. , and repeated explanations will be omitted.

[0141] As shown in FIG. 5A, after forming an insulating film 201 as a base film on a substrate 200, a first The electrode 202 is formed.

[0142] The substrate used for the substrate 200 is the same as that described for the substrate 100 in the first embodiment. For the material, structure and film thickness of the insulating film 201, see the description of the embodiment. Please refer to the description of the undercoat film shown in 1.

[0143] The first electrode 202 is made of aluminum, chromium, copper, tantalum, titanium, molybdenum, titanium a metal element selected from the group consisting of tungsten and yttrium, or a compound containing the above-mentioned metal elements It is made of gold, an alloy combining the above metal elements, etc. a metal element selected from one or more of aluminum, zirconium, beryllium, and thorium; The first electrode 202 may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of aluminum film containing silicon, aluminum Two-layer structure in which a titanium film is laminated on a tungsten film, and two-layer structure in which a titanium film is laminated on a tungsten film The structure is a titanium film, an aluminum film is layered on top of the titanium film, and a titanium film is layered on top of that. In addition, titanium, tantalum, and An element selected from tungsten, molybdenum, chromium, neodymium, and scandium, Alternatively, a film made up of a combination of multiple layers, an alloy film, or a nitride film may be used.

[0144] The first electrode 202 may be made of indium tin oxide or indium oxide containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium titanium oxide oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide A light-transmitting conductive material such as doped indium tin oxide can also be used. Alternatively, the conductive material having light-transmitting properties and the metal element may be laminated together.

[0145] The first electrode 202 is formed by depositing a conductive film on the substrate 200 by sputtering, CVD, or vacuum deposition. A resist mask is formed on the conductive film by a photolithography process. The conductive film can be etched using the resist mask. The first electrode 202 is formed by a printing method or an inkjet method without using a photolithography process. By forming the first electrode 202 in a tapered shape, the number of steps can be reduced. This is preferable because it improves the coverage of the gate insulating film that will be formed later. The angle between the end of the electrode 202 and the insulating film 201 is set to 30° or more and 60° or less, preferably 40° or less. By setting the angle to between 100° and 50°, the coverage of the gate insulating film to be formed later can be improved. can be done.

[0146] In this embodiment, a conductive film to be the first electrode 202 is formed by sputtering. A 50 nm titanium film is formed, a 100 nm aluminum film is formed, and a 50 nm Next, a resist mask formed by a photolithography process is used to form a titanium film. The first electrode 202 is formed by etching using a photolithography process. Instead of a resist mask formed by a method using a photoresist, a resist mask was formed by an ink-jet method. By manufacturing the product in this manner, the number of steps can be reduced.

[0147] Next, an island-shaped oxide semiconductor film 203 is formed over the first electrode 202. The film 203 can be formed by a sputtering method, a coating method, a printing method, or the like. In this embodiment, an oxide semiconductor film is formed over the first electrode 202 by a sputtering method, and then The oxide semiconductor film is processed into a desired shape by etching or the like, whereby island-shaped oxide semiconductor films are formed. The conductive film 203 is formed. The oxide semiconductor film is then heated under a rare gas (for example, argon) atmosphere. , or in an atmosphere of rare gas (e.g., argon) and oxygen. It can be formed more easily.

[0148] Note that the etching for forming the island-shaped oxide semiconductor film 203 is the same as that described in Embodiment 1. The etching for forming the island-shaped oxide semiconductor film 203 was performed with reference to the description. However, the edge of the island-shaped oxide semiconductor film 203 formed by etching may be The angle between the first electrode 202 and the second electrode 203 is set to 30° or more and 60° or less, preferably 40° or more and 50° or less. By setting the angle to 0° or less, it is possible to improve the coverage of the gate insulating film to be formed later. Therefore, it is preferable.

[0149] Before forming the oxide semiconductor film by a sputtering method, argon gas was introduced to form a plasma. Inverse sputtering is performed to generate dust, and dust adhering to the surface of the first electrode 202 is removed. Reverse sputtering is a method in which a target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using an RF power supply below, forming plasma near the substrate and modifying the surface. It is to be noted that nitrogen, helium, etc. may be used instead of the argon atmosphere. Alternatively, the heating may be carried out in an argon atmosphere to which oxygen, nitrous oxide, etc. have been added. Alternatively, the treatment may be carried out in an atmosphere containing chlorine, carbon tetrafluoride, or the like added to the fluorine atmosphere.

[0150] The oxide semiconductor film 203 can be formed using any of the above-described oxide semiconductors.

[0151] In this embodiment, an acid containing In (indium), Ga (gallium), and Zn (zinc) is used. 30 nm thick In-Ga-Z obtained by sputtering using an In-Ga-Zr nitride semiconductor target An nO-based non-single-crystal film is used as the oxide semiconductor film 203. For example, the atomic ratio of each metal is In:Ga:Zn=1:1:0.5, In:Ga:Zn=1:1 :1, or an oxide semiconductor target having a composition ratio of In:Ga:Zn=1:1:2 The oxide semiconductor film can be formed under a rare gas (typically, argon) atmosphere. , or in an atmosphere of rare gas (typically argon) and oxygen. When the sputtering method is used, the SiO2 The film may be formed using a target containing 2% by weight or more and 10% by weight or less of In. The filling rate of the oxide semiconductor target containing Ga and Zn is 90% or more and 100% or less, and preferably Preferably, the filling rate is 95% or more and 99.9% or less. As a result, the formed oxide semiconductor film becomes a dense film.

[0152] The substrate is held in a processing chamber maintained in a reduced pressure state, and hydrogen and A sputtering gas from which the moisture and oxygen have been removed is introduced, and a metal oxide is used as a target to deposit a metal oxide on the substrate 200. During the deposition, the substrate temperature is preferably 100° C. or higher and 600° C. or lower. Preferably, the temperature may be 200° C. or higher and 400° C. or lower. This allows the concentration of impurities contained in the formed oxide semiconductor film to be reduced. Damage caused by tarring is reduced. To remove residual moisture in the processing chamber, an adsorption type It is preferable to use a vacuum pump. For example, a cryopump, an ion pump, a titanium sa It is preferable to use a displacement pump. Also, a turbo pump is used as the exhaust means. A cold trap may be added to the chamber. The chamber may contain, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (HO), etc. (more preferably, carbon Since the exhaust gas contains the oxide semiconductor film formed in the deposition chamber, This reduces the concentration of impurities.

[0153] In this embodiment, as an example of the film formation conditions for the oxide semiconductor film, the substrate temperature is room temperature, and the substrate and the substrate are heated. The distance between the getter and the target was 110 mm, the pressure was 0.4 Pa, the direct current (DC) power was 0.5 kW, and oxygen and argon (oxygen flow rate 15 sccm: argon flow rate 30 sccm) atmosphere conditions are suitable. When a pulsed direct current (DC) power supply is used, the particles generated during film formation are This is preferable because it can reduce dust particles, which are called "dust particles," and the film thickness distribution becomes uniform. is 1 μm or more, preferably 3 μm or more, and more preferably 10 μm or more. The appropriate thickness varies depending on the oxide semiconductor film material used, and the thickness should be selected appropriately depending on the material. That's fine.

[0154] Note that in order to prevent hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor film 203 as much as possible, Therefore, as a pre-treatment for film formation, the first electrode 202 is heated in a pre-heating chamber of the sputtering device. The formed substrate 200 is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 200. It is preferable to separate the gas and exhaust the gas. The preheating temperature should be between 100°C and 400°C. The temperature is preferably 150°C or higher and 300°C or lower. The Lyo Pump is preferable. However, this preheating process can be omitted. The preheating is also performed on the substrate 200 on which the gate electrode has been formed before the gate insulating film is formed. It is also possible.

[0155] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply, and D There is also the pulsed DC sputtering method, which applies a bias in a pulsed manner. The RF sputtering method is mainly used to form insulating films, while the DC sputtering method The tarring method is mainly used when forming a metal film.

[0156] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0157] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. The ECR device uses a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the sputtering method.

[0158] In addition, as a film formation method using a sputtering method, a target material and a sputtering gas are mixed during film formation. Reactive sputtering method to form compound thin films by chemically reacting the silicon dioxide and silicon dioxide components. There is also a bias sputtering method in which a voltage is applied to the substrate during film formation.

[0159] Next, the mixture is heated under a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or The dew point was measured using an ultra-dry air (CRDS (Cavity Ring Down Laser Spectroscopy)) dew point meter. The moisture content measured by the method is 20 ppm or less (-55°C in dew point equivalent), preferably 1 ppm The oxide semiconductor film 203 is then heated to a temperature of 1000 K or less in an air atmosphere (preferably 10 ppb or less). By performing the heat treatment on the oxide semiconductor film 203, the oxide semiconductor film 203 is transformed into the oxide semiconductor film 203 shown in FIG. In this manner, the oxide semiconductor film 205 from which moisture and hydrogen are released is formed. °C or higher and 850 °C or lower (or a temperature lower than the strain point of the glass substrate), preferably 550 °C or higher Heat treatment can be performed at 750°C or less. For example, at 600°C for 3 to 6 minutes. The RTA method allows dehydration or dehydrogenation in a short time, so the glass The substrate can be treated at a temperature exceeding the distortion point. The oxide semiconductor film 203 was heated in a nitrogen atmosphere using an electric furnace. After heating for 6 minutes at a temperature of 600°C, the sample was placed in a water bath without contact with the air. The oxide semiconductor film 205 is obtained by preventing re-contamination of oxygen and hydrogen.

[0160] For a detailed explanation of the heat treatment device used in the first heat treatment, This has already been described in form 1, so it will be omitted here.

[0161] In addition, in the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain hydrogen or the like. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. Preferably, the concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable that the concentration is 0.1 ppm or less.

[0162] Then, as shown in FIG. 5B, the island-shaped oxide semiconductor film 205 The crystalline region 206 is formed in the surface layer of the crystalline region 206. The crystalline region 206 has a grain size of 1 nm. It contains so-called nanocrystals (also written as nanocrystals) with a size of 20 nm or less. The island-shaped oxide semiconductor film 205 is amorphous or It contains a mixture of amorphous and microcrystalline regions, with microcrystalline regions scattered throughout the amorphous regions. The above values ​​are merely examples, and the present invention should not be interpreted as being limited to the above numerical ranges. The target was formed by sputtering with an atomic ratio of In:Ga:Zn=1:1:1. In the case of an In-Ga-Zn-O oxide semiconductor film formed using a target with a different atomic ratio, The crystallization of the surface layer of the oxide semiconductor film is more likely to proceed than when a SiO 2 film is used. Therefore, the crystalline region 206 is likely to form in a deeper region.

[0163] Next, as shown in FIG. 5C, the oxide semiconductor film 20 having the crystalline region 206 in the surface layer portion is Oxygen is added to the silicon dioxide film 5 by ion implantation or ion doping. Alternatively, oxygen is added to the oxide semiconductor film 205 by an ion doping method or the like. The oxide semiconductor film 207 to which excess oxygen is added is formed. Breaking the bond between the metal and hydrogen that constitutes the semiconductor, or the bond between the metal and hydroxyl groups At the same time, these hydrogen or hydroxyl groups react with oxygen to produce water. Then, the second heat treatment carried out later removes the impurity hydrogen or hydroxyl group as water. It can make it easier to let go.

[0164] When oxygen gas is used to add oxygen by ion implantation, the acceleration voltage should be set to 5 kV or more and 100 kV or less, dose of 1×10 13 ions / cm 2 More than 1×10 16 ions / cm 2 The following would suffice.

[0165] In addition to the addition of oxygen to the oxide semiconductor film 205 by ion implantation, The substrate on which the semiconductor film 205 is formed is heated to 500° C. or higher and 850° C. or lower (or glass The heat treatment is carried out at a temperature below the strain point of the substrate, preferably in the range of 550°C to 750°C. It is also possible to do so.

[0166] The crystals contained in the crystalline region 206 formed in the surface layer of the oxide semiconductor film 205 The damage is caused by the addition of oxygen using ion implantation or ion doping. Therefore, the surface portion of the oxide semiconductor film 207 has the same structure as the oxide semiconductor film 205 before oxygen is added. The crystallinity of the crystalline region 206 is lower than that of the crystalline region 206. The amorphous region has the same structure as that of the amorphous region of the nitride semiconductor film 205 .

[0167] Next, a second heat treatment is carried out under the same conditions as the first heat treatment. Specifically, it can be performed under a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, or an acid atmosphere. Under nitrogen gas atmosphere or ultra-dry air (CRDS (Cavity Ring-Down Laser Spectroscopy) When measured using a dew point meter, the moisture content is 20 ppm (-55°C in dew point equivalent) or less. In an atmosphere of preferably 1 ppm or less, preferably 10 ppb or less, °C or higher and 850 °C or lower (or a temperature lower than the strain point of the glass substrate), preferably 550 °C or higher Heat treatment can be performed at 750°C or less. RTA (Rapid Thermal Anneal) When heat treatment is performed in the a) treatment, for example, it is performed at 600°C for 3 to 6 minutes. The RTA method allows dehydration or dehydrogenation in a short time, so the glass substrate The heat treatment can be performed at a temperature exceeding the strain point of the plate. Using an electric furnace, the substrate temperature was raised to 600°C in a nitrogen atmosphere for 6 minutes. After the heat treatment, the oxide semiconductor is kept in a state where it is not exposed to the air and water or hydrogen is not re-mixed. The oxide semiconductor film 208 is obtained. Note that the heat treatment is repeated multiple times after the formation of the island-shaped oxide semiconductor film 208. You can go.

[0168] In one embodiment of the present invention, oxygen is added to the oxide semiconductor film 205 to form an oxide semiconductor. The bond between the metal and hydrogen or the bond between the metal and hydroxyl group is broken, and These hydrogen or hydroxyl groups react with oxygen to produce water. By carrying out the second heat treatment, impurities such as hydrogen or hydroxyl groups that have remained strongly are removed by heating. Therefore, the islands formed by the heat treatment can be easily removed. The oxide semiconductor film 208 has moisture that is not removed by the first heat treatment. Since impurities such as hydrogen and the like are removed, the oxide semiconductor film 205 is Furthermore, it becomes an i-type (intrinsic semiconductor) or as close to i-type as possible. The impurities mentioned above cause the semiconductor to desorb and become i-type (intrinsic semiconductor) or very close to i-type. This prevents the deterioration of transistor characteristics, such as a shift in the value voltage, and reduces the off-state current. It can be reduced.

[0169] Also, at 85°C, 2 x 10 6 V / cm, 12-hour gate bias thermal stress test (BT In the test, when impurities are added to the oxide semiconductor, the The bond to the main component is broken by a strong electric field (B: bias) and high temperature (T: temperature), and The resulting dangling bonds induce a drift in the threshold voltage (Vth). As described above, the interface characteristics between the gate insulating film and the oxide semiconductor film are improved, and the oxide semiconductor film is also By removing impurities, especially hydrogen and water, from the semiconductor film as much as possible, Therefore, a more stable transistor can be obtained.

[0170] For a detailed explanation of the heat treatment device used in the second heat treatment, This has already been described in form 1, so it will be omitted here.

[0171] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain hydrogen or the like. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. Preferably, the concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable that the concentration is 0.1 ppm or less.

[0172] In the oxide semiconductor film 205, water or hydrogen is removed and oxygen is removed by the first heat treatment. Although oxygen deficiency occurs, the addition of oxygen using ion implantation or ion doping This allows sufficient oxygen to be supplied to the oxide semiconductor film in which oxygen vacancies have occurred. The hydrogen or water removed by the first heat treatment is not a constituent element of the oxide semiconductor. The oxygen added later is one of the constituent elements of the oxide semiconductor. Therefore, the stoichiometric composition ratio can be satisfied. After the addition of oxygen, the second heat treatment is carried out to remove the damage. The crystalline region 206 is repaired, and the surface of the oxide semiconductor film 208 is further removed. The crystal growth is further promoted to the inside, and the crystalline region is expanded to the deeper part of the oxide semiconductor film. In this second heat treatment, the thickness of the film 209 can be increased by more than that of the first heat treatment. Since the crystal growth is further promoted, the crystal grains are adjacent to each other in the crystalline region 209. Furthermore, the metal elements constituting the oxide semiconductor are connected between adjacent crystal grains. Therefore, the crystal region is called a channel forming region. In a transistor with a high mobility region, the potential barrier at the grain boundary is low. It is possible to obtain good characteristics such as high mobility and high breakdown voltage.

[0173] Note that the oxide semiconductor film 208 shown in FIG. 5D has an amorphous region mainly composed of an amorphous material. 210 and a crystalline region 209 formed in a surface portion of the oxide semiconductor film 208.

[0174] Furthermore, the crystalline region 209 is more stable than the amorphous region 210 other than the crystalline region 209. Therefore, by having this in the surface layer portion of the oxide semiconductor film 208, impurities can be easily formed in the amorphous region 210. It is possible to reduce the incorporation of hydrogen, water, hydroxyl groups, or hydrides. Therefore, the reliability of the oxide semiconductor film 208 can be improved.

[0175] In this embodiment, the oxide semiconductor film 208 is divided into a crystalline region 209 and an amorphous region 210. Although the oxide semiconductor film 208 is almost entirely occupied by the crystalline region 209, In addition, the oxide semiconductor film 208 has a crystalline region 209 and an amorphous region 210. Even in this case, how deep does the crystalline region 209 occupy from the surface of the oxide semiconductor film 208? The configurations shown in FIGS. 5 and 6 are not limited to those shown in FIGS.

[0176] Through the above steps, the concentration of hydrogen in the oxide semiconductor film can be reduced and the oxide semiconductor film can be highly purified. This makes it possible to stabilize the oxide semiconductor film. By heat treatment, an oxide semiconductor film with extremely low carrier density and a wide band gap is formed. Therefore, a transistor can be fabricated using a large-area substrate. Therefore, mass productivity can be improved. By using a semiconductor film, it is possible to achieve high voltage resistance, low short channel effect, and high on-off ratio. Therefore, it is possible to fabricate a high-performance transistor.

[0177] The amorphous region 210 is mainly composed of an amorphous oxide semiconductor film. "Among the amorphous oxide semiconductors, for example, is 50% or more. This refers to a state in which the membrane occupies 50% or more by volume (or weight). In addition to the crystalline oxide semiconductor film, the oxide semiconductor film may contain crystals. The ratio is preferably less than 50% by volume (or weight), but is not limited to these ranges. There is no need to be.

[0178] When an In-Ga-Zn-O oxide semiconductor film is used as the material for the oxide semiconductor film, The composition of the amorphous region 210 is such that the content (atomic %) of Zn is 0.01% or less than the content of In or Ga. It is preferable that the amount (atomic %) of the SiO2 alloy is equal to or greater than 1. This is because it becomes easier to form the crystalline region 209 with a predetermined composition.

[0179] Next, as shown in FIG. 5E, a second electrode 211 is formed over the oxide semiconductor film 208. The material and structure of the conductive film used for the second electrode 211 are the same as those of the first electrode 202. The second electrode 211 can be fabricated in the same manner as described above. It can be implemented in the same manner as the first electrode 202.

[0180] In this embodiment, a photolithography process is performed to form a pattern on a conductive film that will become the second electrode 211. A resist mask is formed, and the conductive film is etched using the resist mask to form a second conductive film. Here, a conductive film having a thickness of 50 nm is used as the second electrode 211. A titanium film, an aluminum film with a thickness of 100 nm, and a titanium film with a thickness of 50 nm are stacked in this order. The angle between the edge of the second electrode 211 and the oxide semiconductor film 208 is set to be 30° or more and 60° or less. 50° or less, preferably 40° to 50°, This is preferable because it can improve the coverage. The second electrode 202 is formed at a position spaced apart from the first electrode 202 without contacting the first electrode 202 .

[0181] One of the first electrode 202 and the second electrode 211 is a source electrode of the transistor, and the other is a The other electrode functions as the drain electrode.

[0182] After the second electrode 211 is formed, heat treatment may be performed. The temperature for the heat treatment is 400° C. The temperature is set to 850° C. or lower, preferably 400° C. or higher but lower than the strain point of the substrate. The substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and nitrogen is applied to the oxide semiconductor film 208. The heat treatment was carried out at 450°C for 1 hour under an inert gas atmosphere such as a rare gas. After that, by not exposing the oxide semiconductor film to the air, hydrogen, water, a hydroxyl group, hydride, or the like is prevented from being added to the oxide semiconductor film. By preventing re-entry of hydrogen, the hydrogen concentration is further reduced and the hydrogen is highly purified, resulting in i-type or substantially Therefore, an i-type oxide semiconductor film can be obtained.

[0183] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the heat treatment does not contain hydrogen, water, hydroxyl groups, hydrides, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the treatment equipment must be 6N or less. (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurities It is preferable to set the concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0184] FIG. 7A shows the first electrode 202, the oxide semiconductor film 208, and the second electrode 21 in FIG. 7A shows a top view of the semiconductor device 1. The cross section taken along the dashed line B1-B2 in FIG. 7A corresponds to the cross section in FIG. 5E. Equivalent.

[0185] Next, as shown in FIG. 6(A), the first electrode 202, the oxide semiconductor film 208, the second electrode 204, and the oxide semiconductor film 208 are stacked. A gate insulating film 212 is formed so as to cover the electrode 211, and a gate electrode is formed on the gate insulating film 212. The electrode 213 is formed on the gate insulating film 212 by plasma CVD, sputtering, or the like. Using the above, silicon oxide film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film Aluminum film, aluminum nitride film, aluminum oxynitride film, aluminum nitride oxide film, aluminum oxide film The tantalum oxide film or the tantalum oxide film can be formed as a single layer or a stacked layer.

[0186] The gate insulating film 212 is made of hafnium silicate (HfSiO x ), N is added HfSi x O y , nitrogen-doped hafnium aluminate (HfAlO x ), oxidation Use of high-k materials such as hafnium and yttrium oxide reduces gate leakage. Furthermore, high-k materials and silicon oxide films, silicon nitride films, and oxynitride films can be used. A laminate of at least one of a silicon film, a silicon nitride oxide film, and an aluminum oxide film The thickness of the gate insulating film 212 is set to 50 nm or more and 500 nm or less. By increasing the thickness of the gate insulating film 212, the gate leakage current can be reduced. It is possible.

[0187] It is desirable that the gate insulating film 212 contains as little impurities as possible, such as moisture and hydrogen. When forming a silicon oxide film by the tar- ping method, a silicon target is used as the target. A quartz or silica target is used, and oxygen or a mixture of oxygen and argon is used as the sputtering gas. This is done using a

[0188] By removing impurities, an oxide semiconductor that has been made i-type or substantially i-type (highly purified) Since the gate insulating film (oxide semiconductor) is extremely sensitive to the interface state and the interface charge, The interface with the gate insulating film 212 is important. The membrane (GI) is required to be of high quality.

[0189] For example, high density plasma CVD using microwaves (2.45 GHz) produces dense, high dielectric strength films. This is preferable because it allows the formation of a high-quality insulating film. By closely contacting the insulating film, the interface state is reduced and the interface characteristics are improved. Because it is possible.

[0190] Of course, if a good insulating film can be formed as the gate insulating film 212, sputtering is also possible. Other film formation methods such as the ring method and plasma CVD method can be applied. The insulating film 212 and the interface characteristics with the oxide semiconductor are modified by heat treatment. In any case, it is of course important that the film quality as a gate insulating film is good. If the interface state density with the oxide semiconductor can be reduced and a good interface can be formed, good.

[0191] Insulating films made of materials with high barrier properties, silicon oxide films with a low nitrogen content, and oxynitride films The gate insulating film 212 may be formed to have a structure in which an insulating film such as a silicon film is laminated. In this case, the insulating film such as a silicon oxide film or a silicon oxynitride film has a barrier property and an oxidizing property. The insulating film with high barrier properties is formed between the semiconductor film, for example, silicon nitride film, nitride oxide film, etc. Examples of the barrier include a silicon film, an aluminum nitride film, and an aluminum nitride oxide film. By using an insulating film with this property, impurities in the atmosphere such as moisture or hydrogen, or Impurities such as alkali metals and heavy metals contained in the oxide semiconductor film and the gate insulating film 2 12, or the interface between the oxide semiconductor film and other insulating films and its vicinity. In addition, a silicon oxide film or an oxynitride film having a low nitrogen ratio that is in contact with the oxide semiconductor film can be formed. By forming an insulating film such as a silicon film, the insulating film made of a material with high barrier properties can be directly oxidized. This can prevent contact with the semiconductor film.

[0192] For example, a silicon oxide film (S) having a thickness of 5 nm to 300 nm is used as the first gate insulating film. iO x (x>0)) is formed on the first gate insulating film, and a second gate insulating film is sputtered on the first gate insulating film. Silicon nitride film (SiN) with a thickness of 50 nm to 200 nm is formed by the deposition method. y (y>0 )) may be stacked to form a gate insulating film with a thickness of 100 nm. 0.4 Pa, high frequency power supply 1.5 kW, oxygen and argon (oxygen flow rate 25 sccm: argon A 100 nm thick film was deposited by RF sputtering under an atmosphere with a flow rate of 25 sccm (1:1). A silicon oxide film is formed.

[0193] In order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the gate insulating film 212 as much as possible, As a pretreatment for film formation, the first electrode 202, the oxide The substrate 200 on which the semiconductor film 208 and the second electrode 211 are formed is preheated. It is preferable to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the surface of the substrate. The temperature is 100°C or higher and 400°C or lower, preferably 150°C or higher and 300°C or lower. The evacuation means provided in the preheating chamber is preferably a cryopump. The process can also be omitted.

[0194] Note that heat treatment may be performed after the gate insulating film 212 is formed. In an atmosphere of reactive gas (nitrogen, helium, neon, argon, etc.), preferably 2 The heating temperature is 00°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. The compound semiconductor film 208 is heated in contact with the silicon oxide that constitutes the gate insulating film 212. Therefore, even if oxygen vacancies occur in the second heat treatment, oxygen is supplied from silicon oxide. By supplying oxygen, the oxygen vacancies that act as donors are reduced, and the stoichiometric composition ratio is satisfied. Therefore, the oxide semiconductor film 208 can be made i-type or substantially i-type. The timing of this heat treatment is not particularly limited as long as it is performed after the gate insulating film 212 is formed. The gate electrode 213, the insulating film 214, or the wiring 215 to be formed later may be omitted. This may be performed after forming any one of the transparent conductive film 215, the wiring 216, and the wiring 217. By combining this with other heat treatments, such as heat treatments to reduce the resistance of conductive films, the number of processes can be increased. It can be done without any hassle.

[0195] The material of the gate electrode 213 is molybdenum, titanium, chromium, tantalum, tungsten, nickel, or the like. Conductors made of metal materials such as chromium and scandium, and alloy materials whose main components are these metal materials. The conductive film or nitride of these metals can be used as a single layer or a laminate. If it can withstand the temperature of the heat treatment performed in the process, aluminum is used as the metal material. Aluminum or copper can be used. Aluminum or copper can avoid the problems of heat resistance and corrosion. To avoid this, it is recommended to use it in combination with high melting point metal materials. Molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. You can be there.

[0196] For example, the gate electrode 213 having a two-layer laminated structure may be formed by depositing molybdenum on an aluminum film. a two-layer structure with a molybdenum film laminated on a copper film, or a two-layer structure with a molybdenum film laminated on a copper film, or a two-layer structure in which a titanium nitride film or a tantalum nitride film is laminated on a copper film; It is preferable to have a two-layer structure in which a molybdenum film is laminated. The electrode 213 may be an aluminum film, an aluminum-silicon alloy film, or an aluminum The intermediate layer is an alloy film of aluminum and titanium or an alloy film of aluminum and neodymium, and the The structure is a laminate of a tungsten nitride film, a titanium nitride film, or a titanium film as upper and lower layers. It is preferable that

[0197] The gate electrode 213 may be made of indium oxide, an indium oxide tin oxide alloy, or zinc oxide alloy, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, or oxide By using a light-transmitting conductive oxide film such as zinc gallium oxide for the gate electrode 213, The aperture ratio of the element portion can be improved.

[0198] The thickness of the gate electrode 213 is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, a 150 nm film is formed by sputtering using a tungsten target. After forming a conductive film for the gate electrode of m, the conductive film is etched into a desired shape. The gate electrode 213 is formed by patterning. At least, the gate insulating film 212 is formed at a position overlapping with an end portion of the oxide semiconductor film 208, with the gate insulating film 212 interposed therebetween. At the end of the oxide semiconductor film 208, the gate insulating film 212 is formed. A channel forming region is formed in a portion 218 that overlaps with the gate electrode 213. If the end of the formed gate electrode 213 is tapered, the insulating film laminated thereon may be damaged. This is preferable because it improves the coverage of 214. If the resist mask is formed by an inkjet method, a photomask is not required. Therefore, the manufacturing cost can be reduced.

[0199] Next, as shown in FIG. 6B, the first electrode 202, the oxide semiconductor film 208, and the second electrode 204 are An insulating film 214 is formed so as to cover the electrode 211, the gate insulating film 212 and the gate electrode 213. After that, contact holes 221, 222, and 223 are It is desirable that the insulating film 214 contains as little impurities as possible, such as moisture and hydrogen. It may be a single layer insulating film, or may be made up of a plurality of laminated insulating films. The film 214 may be, for example, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an oxynitride film. oxide insulating films such as aluminum nitride films, silicon nitride films, silicon nitride oxide films, aluminum nitride films A nitride insulating film such as an aluminum nitride oxide film or an oxide insulating film is used. The insulating film 214 may be a laminate of an insulating film having a high barrier property and a nitride insulating film. Films, such as silicon nitride films, silicon oxynitride films, aluminum nitride films, or aluminum oxynitride films By using a silicon dioxide film or the like, the oxide semiconductor film 208, the gate insulating film 212, or the like can be formed. Impurities such as moisture or hydrogen are present at the interface between the oxide semiconductor film 208 and other insulating films and in the vicinity thereof. can be prevented from entering.

[0200] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering. The insulating film 214 has a structure in which a silicon nitride film having a thickness of 100 nm formed by a method is laminated. When the insulating film 214 is formed by sputtering, the substrate 200 is High purity, heated to temperatures between ℃ and 400℃, with hydrogen, water, hydroxyl groups, hydrides, etc. removed Nitrogen-containing sputtering gas is introduced and an insulating film 214 is formed using a silicon semiconductor target. In this case, hydrogen, water, hydroxyl groups, or hydrogenated carbon atoms remaining in the processing chamber may be removed. It is preferable to form the insulating film while removing the materials.

[0201] Note that heat treatment may be performed after the insulating film 214 is formed. In an atmosphere (nitrogen, helium, neon, argon, etc.), preferably at 200°C The heating is carried out at a temperature of 250°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower.

[0202] The contact holes 221, 222, and 223 are photoresist holes. A resist mask is formed by a lithography process, and the gate insulating film 212 and the insulating film 214 are formed. The contact hole 221 can be formed by selectively removing a part of the This exposes a part of the gate electrode 213. The contact hole 222 allows the second A part of the electrode 211 is exposed. When these contact holes are formed, the gate electrode of the first electrode 202 is exposed. In the area not covered by the electrode 213, the first electrode 202 is exposed. A hole may be formed.

[0203] Next, as shown in FIG. 6(C), the contact holes 221, 222, and A conductive film is formed on the insulating film 214 so as to cover the contact hole 223, and then etching is performed. The conductive film is processed into a desired shape by the above-mentioned methods, and wiring 215, wiring 216, and wiring 217 are formed. The resist mask used for etching may be formed by an ink-jet method. When a resist mask is formed by the inkjet method, a photomask is not used, so the manufacturing process is simple. This reduces manufacturing costs.

[0204] The wiring 215 is connected to the gate electrode 213 via a contact hole 221. The wire 216 is connected to the second electrode 211 through a contact hole 222. 217 is connected to the gate electrode 213 via a contact hole 223. When forming these wirings, the wirings connected to the first electrode 202 through the contact holes are It may be formed.

[0205] The wiring 215, the wiring 216, and the wiring 217 have the same structure and material as the first electrode 202. The conductive film can be used to form the insulating film by a similar manufacturing method.

[0206] Through the above steps, the transistor 220 is formed.

[0207] 7B shows a top view of the transistor 220 shown in FIG. The cross section taken along the dashed line B1-B2 corresponds to FIG. 6(C). 230 is a wiring formed simultaneously with the wiring 215, wiring 216, and wiring 217. It is connected to the first electrode 202 via a contact hole 231 .

[0208] As described above, the concentration of hydrogen in the oxide semiconductor film can be reduced, and the oxide semiconductor film can be highly purified. The oxide semiconductor film can be stabilized by the heat treatment at a temperature equal to or lower than the glass transition temperature. This method allows the formation of an oxide semiconductor film with an extremely low carrier density and a wide band gap. Therefore, a transistor can be manufactured using a large-area substrate. In addition, the hydrogen concentration is reduced and the oxide semiconductor is highly purified. By using a thin film, the transistor has high voltage resistance, low short channel effect, and high on-off ratio. A transistor can be fabricated.

[0209] In this embodiment, a region of the oxide semiconductor film 208 that is different from the second electrode 211 is The entire portion formed in the region is covered with the gate electrode 213. The second electrode 211 may be formed in a region of the oxide semiconductor film 208 that is different from the region of the second electrode 211. At least a part of the exposed portion is covered with the gate electrode 213. The electrode that functions as the drain electrode out of the first electrode 202 and the second electrode 211 is The electrode that functions as the drain electrode may be connected to the gate electrode 213. 213, the transistor can function as a diode. can.

[0210] The source electrode and the drain electrode of the transistor are determined by the polarity and the voltage of the transistor. The name changes depending on the difference in potential applied to the electrodes. Generally, n-channel In a transistor with a low potential, the electrode to which a high potential is applied is called the source electrode. The electrode that is connected to the drain electrode is called the drain electrode. The electrode to which a low potential is applied is called the drain electrode, and the electrode to which a high potential is applied is called the source electrode. In this specification, for convenience, it is assumed that the source electrode and the drain electrode are fixed. In this paper, the connection relationship of the transistor is explained by setting the potentials as shown above. The names of the source electrode and the drain electrode are interchanged.

[0211] In this specification, connection means an electrical connection, and means a connection through which current or voltage can be transmitted. This corresponds to a state in which the

[0212] Here, the drain breakdown voltage of the transistor described in this embodiment will be described.

[0213] When the electric field in the semiconductor reaches a certain threshold, impact ionization occurs, and the high electric field causes electrons to be generated in the depletion layer. The accelerated carriers collide with the crystal lattice, generating electron-hole pairs. As the electron-hole pairs generated by impact ionization are further accelerated by the electric field, Repeated collision ionization leads to an avalanche breakdown, where the current increases exponentially. Ionization occurs when carriers (electrons, holes) gain kinetic energy greater than the band gap of a semiconductor. Therefore, the larger the band gap, the more likely it is that impact ionization will occur. The electric field generated becomes stronger.

[0214] The band gap of oxide semiconductors is 3.15 eV, which is 1 / 2 the band gap of silicon. Since this is larger than 0.74 eV, avalanche breakdown is unlikely to occur. Transistors using semiconductors have a high drain breakdown voltage, and even when a high electric field is applied, the on-current This makes it less likely that an exponential rise will occur.

[0215] Next, hot carrier degradation of a transistor including an oxide semiconductor will be described.

[0216] Hot carrier degradation occurs when electrons accelerated to high speeds penetrate the gate insulating film near the drain in the channel. The charge is injected into the insulating film and becomes a fixed charge, or a trap level is formed at the gate insulating film interface. This can cause deterioration of transistor characteristics such as threshold voltage fluctuations and gate leakage. The cause of hot carrier degradation is channel hot electron injection (CHE). injection) and drain avalanche hot carrier injection (DAHC injection).

[0217] Since silicon has a narrow band gap, electrons are generated in an avalanche manner due to avalanche breakdown. The number of electrons accelerated to a high enough speed to overcome the potential barrier to the gate insulating film is However, since the oxide semiconductor described in this embodiment has a wide band gap, Therefore, avalanche breakdown is less likely to occur and resistance to hot carrier degradation is higher than that of silicon. In addition, the band gap of silicon carbide, which is one of the high-voltage materials, and the band gap of oxide semiconductor Although the band gap is the same, the mobility of oxide semiconductors is about two orders of magnitude smaller, so electrons is less likely to be accelerated, and hot carrier degradation is less likely to occur than with silicon carbide. It can be said that the pressure resistance is high.

[0218] From the above, a transistor using an oxide semiconductor has a high drain breakdown voltage. A drain breakdown voltage of 100 V or more, preferably 500 V or more, more preferably 1 kV or more It is possible.

[0219] Here, we compare silicon carbide, a typical example of a transistor, with oxide semiconductors. The following shows how 4H-SiC is used as silicon carbide.

[0220] Oxide semiconductors and 4H-SiC have several things in common. The intrinsic carrier density is For example, according to the Fermi-Dirac distribution, the intrinsic carrier density of an oxide semiconductor is 1 0 -7 cm -3 This is estimated to be about 6.7 × 10 in 4H-SiC. -1 1 cm -3 Similarly, this is an extremely low value.

[0221] The energy band gap of oxide semiconductors is 3.0 eV to 3.5 eV, and 4H -The energy band gap of SiC is 3.26 eV, making it a wide-gap semiconductor In this respect, oxide semiconductors and silicon carbide have something in common.

[0222] However, the manufacturing temperatures for oxide semiconductors and silicon carbide are significantly different. Silicon carbide generally requires heat treatment at 1500 to 2000°C. Compound semiconductors are heated to temperatures between 300°C and 500°C (below the glass transition temperature, up to about 700°C). It can be fabricated by processing, and transistors can be fabricated on large-area substrates. In addition, the throughput can be increased.

[0223] In addition, silicon carbide transistors use PN junctions, so donor or Because a doping process of impurities (phosphorus, boron, etc.) that can act as acceptors is required, On the other hand, a transistor using an oxide semiconductor does not have a PN junction. This allows for a reduction in manufacturing processes and an improvement in throughput, and also makes it possible to manufacture large-area substrates. It is possible to use.

[0224] In an oxide semiconductor, the DOS (density of scattering) in the band gap Although many studies have been conducted on the physical properties of the DOS, these studies have not fully investigated the DOS itself. In this embodiment, the idea of ​​oxidizing water and hydrogen, which can be the cause of DOS, is not included. By removing the oxide from the semiconductor, a highly purified oxide semiconductor is produced. This is based on the idea of ​​reducing the amount of waste as much as possible. This enables the production of industrial products that meet these requirements.

[0225] Furthermore, oxygen is supplied to the dangling bonds of the metal that are generated due to oxygen deficiency, and oxygen vacancies are formed. By reducing the DOS, a more highly purified (i-type) oxide semiconductor can be obtained. For example, it is possible to form an oxide film with excess oxygen in close proximity to the channel formation region. By supplying oxygen from the oxide film, it is possible to reduce DOS due to oxygen defects. .

[0226] Defects in oxide semiconductors are caused by excess hydrogen at shallow levels 0.1 to 0.2 eV below the conduction band, or by oxide These defects are thought to be caused by deep levels due to a lack of elements. The technical idea of ​​thoroughly removing hydrogen and providing sufficient oxygen is correct. cormorant.

[0227] In addition, although oxide semiconductors are generally n-type, in this embodiment, impurities, particularly water and By removing hydrogen, the i-type structure is realized. It is not just an i-type system that has been added, but rather it contains a technological concept that has never been seen before.

[0228] In addition, by making the oxide semiconductor i-type, the temperature characteristics of the transistor are good. Generally speaking, the current-voltage characteristics of a transistor in the temperature range from -25°C to 150°C In this case, the on-current, off-current, field-effect mobility, S value, and threshold voltage fluctuate little. There is almost no deterioration in the current-voltage characteristics due to temperature.

[0229] Note that the transistor including an oxide semiconductor described in this embodiment is a transistor including an oxide semiconductor. Although the mobility is about two orders of magnitude lower than that of the transistors used, the Increasing the channel width (W) increases the transistor current value and improves device characteristics. It can be done.

[0230] The technical idea of ​​this embodiment is to reverse the oxide semiconductor without adding any impurities to the oxide semiconductor. By intentionally removing impurities such as water and hydrogen that are unintentionally present in the oxide semiconductor, The purpose is to purify the material itself. In other words, to remove water or hydrogen that constitutes the donor level. Furthermore, oxygen vacancies are reduced, and oxygen is sufficiently supplied to the main component material constituting the oxide semiconductor. This results in a highly purified oxide semiconductor.

[0231] By forming an oxide semiconductor film, 20 cm -3 The hydrogen level is measured by SIMS (secondary ion This is measured by mass spectrometry. The water or hydrogen that causes this donor level is intentionally removed, Furthermore, oxygen (one of the components of oxide semiconductors) is also reduced when water or hydrogen is removed. ) to the oxide semiconductor, the oxide semiconductor is highly purified and becomes electrically i-type (intrinsic ) semiconductor.

[0232] In this embodiment, the smaller the amount of water and hydrogen in the oxide semiconductor, the better. The fewer carriers, the better. That is, the carrier density is 1×10 1 4 cm -3 Less than 1 x 10 12 cm -3 less than, more preferably below the measurement limit 1 x 10 11 cm -3 Furthermore, in the technical concept of this embodiment, Ideally, the carrier density should be close to or zero. By doing so, the oxide semiconductor becomes a path for carriers to pass through in the transistor. As a result, the oxide semiconductor is a highly purified i-type (intrinsic) semiconductor, By making the carriers zero or very few, the transistor is in the off state. The technical idea of ​​this embodiment is to be able to make Ioff extremely low.

[0233] In addition, the oxide semiconductor functions as a path, and the oxide semiconductor itself does not have carriers. If the i-type (intrinsic) is highly purified so that there is no or very little carriers, the carriers The source electrode is supplied by the drain electrode.

[0234] Note that the transistor having the structure described in this embodiment can be used in the same manner as in Embodiment 1. In contrast to a lateral transistor in which the channel is formed approximately parallel to the substrate, The occupied area can be reduced, which allows for miniaturization of transistors.

[0235] In this way, impurities other than the main components of the oxide semiconductor film, typically hydrogen, water, a hydroxyl group, or By purifying the material to minimize the amount of hydrides contained, the transistors can function properly. In particular, it is possible to improve the breakdown voltage, reduce the short channel effect, and The turn-off ratio can be increased.

[0236] Similarly to the crystalline region 109 in the first embodiment, the crystals in the crystalline region 209 in the surface layer are oxidized. The crystals are oriented with their c-axis in a direction approximately perpendicular to the surface of the compound semiconductor film 208. Therefore, as explained in the first embodiment, the crystal region 2 By including the oxide semiconductor film 208, the electrical characteristics of the oxide semiconductor film 208 in a direction parallel to the surface thereof are improved. In one embodiment of the present invention, crystal grains are adjacent to each other within the crystalline region. and a state in which metal elements constituting the oxide semiconductor are connected between adjacent crystal grains. That is, the oxide semiconductor film 208 is in a connected state. Therefore, the electrical characteristics in the direction of the carrier concentration in the surface layer of the oxide semiconductor film 208 are further improved. Since the electron mobility is increased, the field-effect transition of the transistor including the oxide semiconductor film 208 is improved. The mobility increases and good electrical properties can be achieved.

[0237] The crystal structure of the crystalline region 209 is not limited to the above, and may include crystals of other crystal structures. For example, when an In-Ga-Zn-O oxide semiconductor material is used, InG In addition to ZnO4 crystals, crystals such as In2Ga2ZnO7 and InGaZn5O8 are also included. Of course, it is also possible for InGaZnO4 crystals to exist throughout the entire crystalline region 209. It is more effective and preferable to do so.

[0238] Furthermore, the crystalline region 209 is more stable than the amorphous region 210 other than the crystalline region 209. Therefore, by having this in the surface layer portion of the oxide semiconductor film 208, impurities can be easily formed in the amorphous region 210. It is possible to reduce the incorporation of hydrogen, water, hydroxyl groups, or hydrides. Therefore, the reliability of the oxide semiconductor film 208 can be improved.

[0239] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0240] (Embodiment 3) In this embodiment, a bottom-gate transistor with a channel protection structure is taken as an example. The structure and manufacturing method of the body device will be described. The functional parts and steps can be performed in the same manner as in the first embodiment, so that the The explanation will be omitted.

[0241] As shown in FIG. 1(E) of the first embodiment, the steps up to the second heat treatment are carried out in the same manner. As shown in FIG. 8A, the region of the oxide semiconductor film 108 that overlaps with the gate electrode 101 That is, a channel protective film is formed on the oxide semiconductor film 108 so as to overlap with the channel formation region. By providing the channel protective film 130, the oxide semiconductor film 108 Damage to the channel formation region during subsequent processes (during etching) This prevents the film from being thinned by plasma or etching agents. Reliability can be improved.

[0242] The channel protection film 130 is made of an inorganic material containing oxygen (silicon oxide, silicon oxynitride, silicon nitride oxide, etc.). The channel protection film 130 can be formed by plasma CVD or thermal CVD. The channel protection film can be formed by a vapor deposition method such as a sputtering method. After the film is formed, the shape of 130 is processed by etching. A base film is formed and then etched using a photolithography mask to create a chalcogenide film. A protective film 130 is formed on the substrate.

[0243] After forming the channel protective film 130, a heat treatment may be performed. Preferably, the reaction is carried out under an inert gas atmosphere (nitrogen, helium, neon, argon, etc.). The temperature is 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. For example, heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour. The channel forming region of the silicon nitride film is connected to the channel protective film 130, which is an insulating film containing oxygen. After the oxide semiconductor film 108 is formed, heat treatment is performed, whereby oxygen is introduced into the oxide semiconductor film 108. Therefore, the region of the oxide semiconductor film 108 in contact with the channel protective film 130 is selectively As a result, at least the carbon dioxide of the oxide semiconductor film 108 can be reduced. In the region in contact with the protective film 130, oxygen deficiency was generated by the second heat treatment. However, it is possible to reduce the oxygen vacancies that act as donors and achieve a structure that satisfies the stoichiometric composition ratio. The channel forming region overlapping with the gate electrode 101 is made i-type or substantially i-type. This makes it possible to improve the electrical characteristics of the transistor and reduce the variations in the electrical characteristics. There is no particular limitation on the timing of this heat treatment, as long as it is after the channel protection film 130 is formed. It is not limited to this, and other processes, such as heat treatment during resin film formation and processes for reducing the resistance of the transparent conductive film, may be used. By combining this with the heat treatment for the purpose of heating, it can be performed without increasing the number of steps.

[0244] Next, as shown in FIG. 8B, a source electrode and a drain electrode are formed on the oxide semiconductor film 108. After forming a conductive film that will become an electrode (including wiring formed in the same layer), the conductive film is The source electrode 131 and the drain electrode 132 are formed by etching or the like into a desired shape. The material, film thickness and structure of the source electrode 131 and the drain electrode 132, and the manufacturing method thereof Regarding the source electrode 111 and the drain electrode 112 shown in the first embodiment, Please refer to the above.

[0245] The source electrode 131 and the drain electrode 132 are formed in the crystalline region 10 of the oxide semiconductor film 108. The highly conductive crystalline region 109 is in contact with the source electrode 131 and the drain electrode 13. 2 contacts the source electrode 131 and the drain electrode 132 with the oxide semiconductor film 108 This reduces the contact resistance between the The on-current can be increased.

[0246] Next, plasma treatment is performed using gases such as N2O, N2, or Ar. The annealing process removes adsorbed water and other substances adhering to the exposed surface of the oxide semiconductor film. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0247] After the plasma treatment, as shown in FIG. 8(C), the source electrode 131 and the drain electrode An insulating film 13 is formed to cover the electrode 132, the channel protective film 130, and the oxide semiconductor film 108. The material, film thickness, structure, and manufacturing method of the insulating film 133 are described in the embodiment. 1. The description of the insulating film 113 can be referred to.

[0248] Note that heat treatment may be performed after the insulating film 133 is formed. In an atmosphere (nitrogen, helium, neon, argon, etc.), preferably at 200°C In this embodiment, the heating is performed at a temperature of 250°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. For example, heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.

[0249] Through the above steps, the transistor 140 is formed.

[0250] In this embodiment, the oxide semiconductor film 108 is divided into a crystalline region 109 and an amorphous region 110. Although the oxide semiconductor film 108 is almost entirely occupied by the crystalline region 109, In addition, the oxide semiconductor film 108 has a crystalline region 109 and an amorphous region 110. Even in this case, how deep does the crystalline region 109 extend from the surface of the oxide semiconductor film 108? The configuration is not limited to that shown in FIG.

[0251] 9 is a top view of the transistor 140 shown in FIG. The cross-sectional view at C2 corresponds to FIG. 8(C).

[0252] The transistor 140 formed according to the above manufacturing method includes a gate electrode 101 and a gate electrode a gate insulating film 102 on the electrode 101; an oxide semiconductor film 108 on the gate insulating film 102; The channel protection film 130 on the oxide semiconductor film 108 and the source electrode 130 on the oxide semiconductor film 108 The transistor 140 further comprises an oxide semiconductor. The conductive film 108, the source electrode 131, the drain electrode 132, and the insulating film on the channel protective film 130 It may also have a velum 133 .

[0253] Although the transistor 140 has been described as a single-gate transistor, If necessary, a transistor having a multi-gate structure having a plurality of channel forming regions is also formed. It is possible.

[0254] Next, a conductive film is formed on the insulating film 133, and then the conductive film is patterned. As shown in FIG. 10(A), a back gate electrode 145 is disposed at a position overlapping with the oxide semiconductor film 108. The back gate electrode 145 may be formed on the gate electrode 101 or the source electrode 102. The drain electrode 31 and the drain electrode 132 can be formed using the same material and structure.

[0255] The thickness of the back gate electrode 145 is 10 nm to 400 nm, preferably 100 nm to 20 In this embodiment, a structure in which a titanium film, an aluminum film, and a titanium film are stacked is used. A conductive film having a structure is formed. Then, a resist mask is formed by photolithography. Then, unnecessary portions are removed by etching to process the conductive film into a desired shape (patterning). By performing the process of (etching), the back gate electrode 145 is formed.

[0256] Next, as shown in FIG. 10(B), an insulating film 146 is formed to cover the back gate electrode 145. The insulating film 146 prevents moisture, hydrogen, oxygen, and the like from being present in the atmosphere. It is desirable to use a material with high barrier properties that can prevent the properties from being affected. For example, insulating films with high barrier properties include silicon nitride films, silicon nitride oxide films, and aluminum nitride films. film, or aluminum nitride oxide film, etc., by plasma CVD method or sputtering method, etc. In order to obtain a barrier effect, the insulating film 1 can be formed as a single layer or as a laminate. It is preferable that the film 46 be formed to a thickness of, for example, 15 nm to 400 nm.

[0257] In this embodiment, a 300 nm insulating film is formed by plasma CVD. The film formation conditions are as follows: The flow rate of silane gas was 4 sccm, the flow rate of nitrous oxide was 800 sccm, and the substrate temperature was 4 Let's assume it's 00℃.

[0258] 10C shows a top view of the semiconductor device shown in FIG. This corresponds to the cross-sectional view taken along dashed line C1-C2 in FIG.

[0259] Note that in FIG. 10B, the back gate electrode 145 covers the entire oxide semiconductor film 108. However, the present invention is not limited to this configuration. overlaps with at least a part of a channel formation region of the oxide semiconductor film 108. good.

[0260] The back gate electrode 145 may be in an electrically insulating floating state. In the latter case, the back gate electrode 145 may be in a state where a potential is applied. The potential may be the same as that of the gate electrode 101, or may be a fixed potential such as ground. The level of the potential applied to the back gate electrode 145 can be controlled. Thus, the threshold voltage of the transistor 140 can be controlled.

[0261] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0262] (Fourth embodiment) In this embodiment, a semiconductor display device formed by the manufacturing method of the present invention will be described. The structure of a semiconductor display device called electronic paper or digital paper will be explained. .

[0263] Electronic paper can control the gradation by applying voltage and has memory properties. Specifically, the display element used in the electronic paper is a non-aqueous electrophoretic display element. A dynamic display element, in which liquid crystal droplets are dispersed in a polymer material between two electrodes. LC (polymer dispersed liquid crystal) method table Display element, display having chiral nematic liquid crystal or cholesteric liquid crystal between two electrodes The element has charged particles between two electrodes, and the particles are moved through the powder by an electric field. A powder migration type display element can be used. Also, a non-aqueous electrophoretic type display element can be used. is a display element in which a dispersion liquid in which charged particles are dispersed is sandwiched between two electrodes, and A display element having a dispersion liquid in which fine particles are dispersed on two electrodes sandwiching an insulating film, A twisting ball with two differently charged hemispheres is placed between two electrodes. a display element in which charged particles are dispersed in a solvent, a micro-element in which charged particles are dispersed in a solution, This includes a display element having a chlorocapsule between two electrodes.

[0264] FIG. 13A shows a pixel portion 700 of electronic paper, a signal line driver circuit 701, and a scanning line driver circuit 702. A top view of the circuit 702 is shown.

[0265] The pixel portion 700 has a plurality of pixels 703. A signal line driver circuit 701 outputs a plurality of A signal line 707 is routed to the inside of the pixel portion 700. The scanning lines 708 are routed to the inside of the pixel section 700 .

[0266] Each pixel 703 has a transistor 704, a display element 705, and a storage capacitor 706. The gate electrode of the transistor 704 is connected to one of the scanning lines 708. The source electrode and the drain electrode of the transistor 704 are connected to one of the signal lines 707 and the other to It is connected to the pixel electrode of the display element 705 .

[0267] In FIG. 13A, the voltage applied between the pixel electrode and the counter electrode of the display element 705 is maintained. A storage capacitor 706 is connected in parallel to the display element 705 to maintain the If the memory capacity of 05 is high enough to maintain the display, then the retention capacity of 70 It is not necessary to provide 6.

[0268] In FIG. 13A, each pixel has one transistor functioning as a switching element. The structure of the active matrix pixel portion provided with the pixel electrode has been described. The electronic paper is not limited to this configuration. In addition to the transistor, elements such as capacitors, resistors, and coils may be connected. stomach.

[0269] FIG. 13(B) shows an example of electrophoretic electronic paper with microcapsules, 7 shows a cross-sectional view of a display element 705 provided on a substrate 703.

[0270] The display element 705 includes a pixel electrode 710, a counter electrode 711, and a pair of the pixel electrode 710 and the counter electrode The microcapsule 712 has a voltage applied thereto by the transistor 711. One of the four source or drain electrodes 713 is connected to the pixel electrode 710 .

[0271] The microcapsules 712 contain a positively charged white pigment such as titanium oxide and carbon dioxide. Negatively charged black pigments such as lanthanum black are enclosed together with a dispersion medium such as oil. The voltage of the pixel electrode and the counter electrode changes in accordance with the voltage of the video signal applied to the pixel electrode 710. By applying a voltage between them, the black pigment is attracted to the positive electrode side and the white pigment to the negative electrode side. , and gradation display can be performed.

[0272] In FIG. 13B, the microcapsules 712 are disposed between the pixel electrode 710 and the counter electrode 711. However, the present invention uses this structure. The structure is not limited to the microcapsules 712, the pixel electrodes 710, and the counter electrodes 711. The space formed may be filled with a gas such as air or an inert gas. In this case, the microcapsules 712 are attached to the pixel electrodes 710 and the counter electrodes 711 by adhesive or the like. It is desirable to fix both or either one of them.

[0273] The number of microcapsules 712 included in the display element 705 is as shown in FIG. It is not necessarily the case that one display element 705 has a plurality of microcapsules 712. Alternatively, a plurality of display elements 705 may have one microcapsule 712. For example, two display elements 705 may share one microcapsule 712, and one A positive voltage is applied to the pixel electrode 710 of the display element 705, and a negative voltage is applied to the pixel electrode 710 of the other display element 705. In this case, a positive voltage is applied to the pixel electrode 710. In the area overlapping with the applied pixel electrode 710, a black face is formed within the microcapsule 712. The white pigment is attracted to the pixel electrode 710 side, and the white pigment is attracted to the counter electrode 711 side. Conversely, in the area overlapping with the pixel electrode 710 to which a negative voltage is applied, the microcapsules In the cell 712, the white pigment is attracted to the pixel electrode 710 side, and the black pigment is attracted to the counter electrode 71 It is drawn to one side.

[0274] Next, regarding the specific driving method of the electronic paper, the electrophoretic electronic paper described above will be Let me explain with an example.

[0275] The operation of electronic paper can be explained by dividing it into an initialization period, a writing period, and a retention period. Yes, it is possible.

[0276] Before switching the image to be displayed, the grayscale of each pixel in the pixel section is first reset during the initialization period. By unifying the display elements, the display elements are initialized. By initializing the display elements, afterimages are prevented from remaining. Specifically, in the electrophoretic type, each pixel is displayed in either white or black. The gray scale displayed by the microcapsules 712 of the display element 705 is adjusted.

[0277] In this embodiment, after inputting an initialization video signal to display black to the pixel, a video signal to display white is input. The initialization operation when an initialization video signal such as the one shown in the figure is input to the pixel will be explained. For example, in the case of an electrophoretic electronic paper in which an image is displayed facing the counter electrode 711 side, In this case, first, the black pigment in the microcapsules 712 is applied to the counter electrode 711 side, and the white pigment is applied to the image side. A voltage is applied to the display element 705 so that it faces the base electrode 710. The white pigment in the cell 712 faces the counter electrode 711 side, and the black pigment faces the pixel electrode 710 side. Then, a voltage is applied to the display element 705 .

[0278] Also, if the initialization video signal is input to the pixel only once, the image displayed before the initialization period will Depending on the gradation, the movement of the white pigment and the black pigment in the microcapsule 712 may be incomplete. Even after the initialization period has ended, the gray scale displayed between the pixels remains the same. Therefore, a negative voltage - Vp is applied to the pixel electrode 710 multiple times to display black, and It is desired to display white by applying a positive voltage Vp to the pixel electrode 710 multiple times. Desirable.

[0279] If the gray scale displayed by the display element of each pixel before the initialization period is different, The minimum number of times that the video signal must be input varies depending on the display. The number of times the initialization video signal is input between pixels is changed according to the gradation that has been set. In this case, the pixels that no longer need to input the initialization video signal may be It is a good idea to input the supply voltage Vcom.

[0280] It should be noted that the voltage Vp or voltage −Vp of the initialization video signal is applied to the pixel electrode 710 multiple times. In order to do this, during the period when the pulse of the selection signal is given to each scanning line, the scanning line is A series of operations of inputting an initialization video signal to the pixels of the line having the By applying the voltage Vp or voltage −Vp of the initialization video signal to the pixel electrode 710 multiple times, This converges the movement of the white pigment and black pigment within the microcapsules 712, thereby reducing the distance between pixels. This can prevent a difference in gray level from occurring in the pixel portion and initialize the pixels in the pixel portion.

[0281] During the initialization period, each pixel does not display black and then white. Alternatively, in the initialization period, the pixels may be configured to display black after the initial state. It is also possible to display white, then black, and then white again.

[0282] The timing at which the initialization period starts is the same for all pixels in the pixel section. For example, it is not necessary to do it for each pixel, or for each pixel that belongs to the same line. The timing at which the initialization period starts may be varied.

[0283] Next, in the writing period, a video signal having image information is input to the pixels.

[0284] When an image is displayed on the entire pixel area, power is applied to all the scanning lines in sequence during one frame period. A selection signal with a shifted voltage pulse is input. Then, a pulse appears in the selection signal. During one line period, video signals containing image information are input to all signal lines. do.

[0285] The white light in the microcapsules 712 changes in response to the voltage of the video signal applied to the pixel electrode 710. The color pigment and the black pigment move to the pixel electrode 710 side or the counter electrode 711 side, thereby forming a display element. The child 705 displays the gray scale.

[0286] In the writing period, as in the initialization period, the voltage of the video signal is applied to the pixel electrode 710 multiple times. Therefore, during the period when the pulse of the selection signal is applied to each scanning line, In this case, a series of operations of inputting a video signal to pixels of a line having the scanning line is performed as follows: Do this multiple times.

[0287] Next, in the holding period, a common voltage Vcom is input to all pixels via the signal line, and then the scanning No selection signal is input to the line or a video signal is input to the signal line. The white pigment and the black pigment in the microcapsule 712 of 705 are opposite to the pixel electrode 710. The arrangement is maintained unless a positive or negative voltage is applied between the opposing electrodes 711. Therefore, the gray scale displayed by the display element 705 is maintained. The displayed image is maintained during the retention period.

[0288] The display element used in electronic paper requires a voltage to change the gradation, which is the same as that of a liquid crystal display. For light emitting elements such as liquid crystal elements used in display devices and organic light emitting elements used in light emitting devices Therefore, the transistors in the pixels used as switching elements tend to be During the writing period, the potential difference between the source electrode and the drain electrode of the transistor 704 becomes large. Therefore, the off current becomes high, which causes the potential of the pixel electrode 710 to fluctuate, causing display disturbance. The potential of the pixel electrode 710 can be prevented from fluctuating due to the off-state current of the transistor 704. In order to prevent this, it is effective to increase the capacitance of the storage capacitor 706. 707 and the counter electrode 711. When a voltage is applied to the microcapsules 712, noise is generated in the display of the display element 705. In order to prevent this noise from occurring, the area of ​​the pixel electrode 710 should be made large. The voltage generated between the signal line 707 and the counter electrode 711 is applied to the microcapsule 712. However, as mentioned above, if the potential of the pixel electrode 710 changes, To prevent this, the capacitance of the holding capacitor 706 is increased, or noise appears in the display. In order to prevent this, if the area of ​​the pixel electrode 710 is increased, the amount of current that should be supplied to the pixel during the writing period can be increased. This results in a high current value, and it takes time to input the video signal. In the electronic paper related to the above, transistors are used in the pixels as switching elements. In 704, a crystalline region of the oxide semiconductor film is connected to a source electrode or a drain electrode. Therefore, the contact resistance between the oxide semiconductor film and the source electrode or the drain electrode is reduced. Therefore, the capacitance of the storage capacitor 706 can be increased. Even if the pixel electrode 710 is enlarged, the input of the video signal to the pixel Therefore, the length of the writing period can be reduced, and the display You can switch between images smoothly.

[0289] In one embodiment of the present invention, an oxide semiconductor film with an extremely low impurity concentration is used as the Therefore, the transistor 704 has a gate electrode and a source electrode. The off-state current, i.e., the leakage current, is extremely low when the voltage is almost zero. During the writing period, the potential difference between the source electrode and the drain electrode of the transistor 704 is large. Even if the OFF current is reduced, the display disturbance caused by the fluctuation of the potential of the pixel electrode 710 is prevented. In addition, the transistor of the pixel used as a switching element can be prevented from 704, during the writing period, the potential difference between the source electrode and the drain electrode becomes large. However, in one embodiment of the present invention, the transistor 704 is easily deteriorated due to deterioration over time. The variation in threshold voltage can be kept small, which improves the reliability of electronic paper. This can be done.

[0290] This embodiment mode can be implemented in combination with the above embodiment modes.

[0291] (Embodiment 5) FIG. 14A shows an example of a block diagram of an active matrix semiconductor display device. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a first scanning line driver circuit 5304, a second scanning line driver circuit 5305, a second scanning line driver circuit 5306, a second scanning line driver circuit 5307, a second scanning line driver circuit 5308, a second scanning line driver circuit 5309, a second scanning line driver circuit 5310, a second scanning line driver circuit 531 The pixel portion 5301 includes a scanning line driver circuit 5303 and a signal line driver circuit 5304. The signal lines are arranged extending from the signal line driver circuit 5304, and a plurality of scanning lines are arranged as first scanning lines. The driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. At the intersections of the scanning lines and the signal lines, pixels each having a display element are arranged in a matrix. The substrate 5300 of the display device is made of an FPC (Flexible Printed Circuit). d Circuit) and other connections to the timing control circuit 5305 (controller , also called a control IC).

[0292] In FIG. 14A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The signal line driver circuit 5304 is formed on one substrate 5300 together with the pixel portion 5301. Therefore, the number of external components such as drive circuits can be reduced, which not only reduces the size of the display device, but also Cost reduction can be achieved by reducing the assembly process and inspection process. When a driving circuit is provided externally, it becomes necessary to extend the wiring, which increases the number of connections between the wiring. When a driver circuit is provided on the same substrate 5300, the number of connections between the wirings can be reduced. This prevents a decrease in yield due to poor connections between the driver circuit and the pixel section, and improves the connection points. This can prevent a decrease in reliability due to low mechanical strength caused by the wiring.

[0293] The timing control circuit 5305 controls the first scanning line driver circuit 5302 as follows: The first scanning line driving circuit start signal (GSP1), the scanning line driving circuit clock signal (GCK1). The timing control circuit 5305 also supplies the second scanning line driving circuit For example, the second scanning line driver circuit start signal (GSP2) (start The signal line supplies the clock signal (GCK2) for the scanning line driver circuit. The driver circuit 5304 is provided with a start signal (SSP) for the signal line driver circuit, a clock for the signal line driver circuit, and a Clock signal (SCK), video signal data (DATA) (also simply called video signal), The first scanning line driving circuit 5302 and the second scanning line driving circuit 5303 are connected to each other. It is possible to omit either the scanning line driver circuit 5302 or the scanning line driver circuit 5303 .

[0294] In FIG. 14B, circuits with low driving frequencies (for example, the first scanning line driving circuit 5302, the 2) a scanning line driver circuit 5303) is formed on one substrate 5300 together with a pixel portion 5301. 5 shows a structure in which the signal line driver circuit 5304 is formed on a substrate different from that of the pixel portion 5301. In addition, the analog signal line driver circuit 5304 used in the sampling circuit is A circuit with a low driving frequency such as a log switch is partially mounted on one substrate together with the pixel portion 5301. It is also possible to form the system on a plate 5300. By adopting this, the yield reduction caused by the above-mentioned connection failure and the mechanical strength of the connection part can be reduced. This system aims to reduce costs by eliminating assembly and inspection processes, thereby avoiding low quality. The advantages of the system on the panel can be enjoyed to some extent. Furthermore, the pixel part 5301, the scanning line drive A circuit 5302, a scanning line driver circuit 5303, and a signal line driver circuit 5304 are all formed on one substrate. Compared to a system-on-panel consisting of a LCD panel, the performance of the circuit with a high drive frequency can be improved. Furthermore, it is difficult to realize a large pixel area when using a single crystal semiconductor. It can be formed.

[0295] Next, the configuration of a signal line driver circuit using n-channel transistors will be described.

[0296] The signal line driver circuit shown in FIG. 15A includes a shift register 5601 and a sampling circuit The sampling circuit 5602 includes a plurality of switching circuits 5602_1 5602_1 to 5602_N (N is a natural number). are each a plurality of n-channel transistors 5603_1 to 5603_k (k is a natural number). It has.

[0297] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. Note that either the source electrode or the drain electrode of the transistor is connected to the first The other terminal will be referred to as the first terminal.

[0298] The first terminals of the transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. The wirings 5604_1 to 5604_k are connected to the video signals. The second terminals of the transistors 5603_1 to 5603_k are connected to the signal line S1. The gate electrodes of the transistors 5603_1 to 5603_k are connected to the It is connected to a soft register 5601.

[0299] The shift register 5601 supplies voltages of increasing levels to the wirings 5605_1 to 5605_N in order. (H level), and the switching circuits 5602_1 to 560 It has the function of selecting 2_N in order.

[0300] The switching circuit 5602_1 is a switch for transistors 5603_1 to 5603_k. By this, the wirings 5604_1 to 5604_k and the signal lines S1 to Sk are in a conductive state (first terminal The function of controlling the conduction between the first terminal and the second terminal, that is, the function of controlling the conduction between the first terminal and the second terminal of the wiring 5604_1 to 5604_k. The control circuit has a function of controlling whether or not the voltage is supplied to the signal lines S1 to Sk.

[0301] Next, the operation of the signal line driver circuit of FIG. 15(A) will be explained with reference to the timing chart of FIG. 15(B). 15B, a wiring 5605 is connected from the shift register 5601 to the Timing signals Sout_1 to Sout_N input to input terminals 1 to 5605_N, respectively; Video signals Vdata_1 to Vd input to wirings 5604_1 to 5604_k, respectively The timing chart of ata_k is shown as an example.

[0302] One operation period of the signal line driver circuit corresponds to one line period in the display device. 5(B) illustrates an example in which one line period is divided into periods T1 to TN. T1 to TN are periods for writing a video signal to one pixel belonging to a selected row. is.

[0303] During the period T1 to the period TN, the shift register 5601 outputs a timing signal of H level. For example, in the period T1, the shift The register 5601 outputs a high-level signal to the wiring 5605_1. The transistors 5603_1 to 5603_k included in the switching circuit 5602_1 are turned on. Then, the wirings 5604_1 to 5604_k and the signal lines S1 to Sk are brought into a conductive state. Then, Data(S1) to Data(Sk) are input to the wiring 5604_1 to 5604_k. Data(S1) to Data(Sk) are respectively connected to transistors 5603_1 to 5603_5. 603_k, writing is performed on the pixels in the first to kth columns among the pixels belonging to the selected row. In this way, in the periods T1 to TN, pixels belonging to the selected row are sequentially shifted by k columns. The video signal is written in the order.

[0304] As described above, the video signal is written to the pixels in multiple columns. This reduces the number of connections to external circuits such as controllers. In addition, the video signal is written to the pixels in multiple columns, Therefore, the write time can be extended, and insufficient writing of the video signal can be prevented. can be done.

[0305] Next, one mode of a shift register used in a signal line driver circuit or a scanning line driver circuit will be described. 16 and 17.

[0306] The shift register includes the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N ( N is a natural number of 3 or more (see FIG. 16(A)). The first to N-th pulse output circuits 10_N are supplied with a first clock signal CK 1, a second clock signal CK2 is transmitted from the second wiring 12, and a third clock signal CK3 is transmitted from the third wiring 13. A signal CK3 is supplied through the first wiring 14, and a fourth clock signal CK4 is supplied through the fourth wiring 14. In the pulse output circuit 10_1, a start pulse SP1 (first start pulse) is output from the fifth wiring 15. In addition, the n-th pulse output circuit 10_n (n is 2 or more) from the second stage onwards is input. In the upper N (a natural number less than N), the signal from the pulse output circuit 10_n-1 in the previous stage (previous stage signal OUT(n-1)) is input. In addition, in the first pulse output circuit 10_1, two stages A signal from the third pulse output circuit 10_3 at the subsequent stage is input. In the nth pulse output circuit 10_n, the (n+2)th pulse output circuit 10_(n A signal from the next stage (called the next stage signal OUT(n+2)) is input. The pulse output circuit outputs a first pulse for input to the pulse output circuit of the next stage and / or the second stage before. The output signals (OUT(1)(SR) to OUT(N)(SR)) and the signals input to other circuits, etc. The second output signals (OUT(1) to OUT(N)) are output. As shown in the figure, the last two stages of the shift register receive the next stage signal OUT(n+2). Therefore, for example, the second start pulse SP2 and the third start pulse SP3 are separately generated. The configuration may be such that the signal SP3 is input to each of the devices.

[0307] The clock signal (CK) alternates between H level and L level (low level voltage) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal ( CK4) are sequentially delayed by 1 / 4 cycle. The fourth clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit. conduct.

[0308] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to It is electrically connected to any one of the fourth wirings 14. For example, in FIG. The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is The second pulse output circuit 10_2 is electrically connected to the third wiring 13. The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring The third input terminal 23 is electrically connected to the fourth wiring 14. There are.

[0309] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 16B, the input terminal 25, the first output terminal 26, and the second output terminal 27. In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A third clock signal CK3 is input to the input terminal 23 of the clock generator 10, and a start signal CK4 is input to the fourth input terminal 24 of the clock generator 10. A pulse is input, the subsequent signal OUT(3) is input to the fifth input terminal 25, and the first output The first output signal OUT(1)(SR) is output from the terminal 26, and the second output signal OUT(1)(SR) is output from the second output terminal 27. The second output signal OUT(1) is output.

[0310] Next, an example of a specific circuit configuration of the pulse output circuit is shown in FIG.

[0311] Each pulse output circuit has a first transistor 31 to a thirteenth transistor 43. (See FIG. 17(A)). In addition, the first input terminal 21 to the fifth input terminal 25, In addition to the first output terminal 26 and the second output terminal 27, a first high power supply potential VDD is supplied. A power supply line 51, a power supply line 52 to which a second high power supply potential VCC is supplied, and a power supply line 53 to which a low power supply potential VSS is supplied. A signal is supplied to the first transistor 31 to the thirteenth transistor 43 from the power supply line 53 connected to the Here, the relationship between the levels of the power supply potentials of the power supply lines in FIG. 17(A) is as follows: The first power supply potential VDD is set to a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is set to The potential is set to be higher than the third power supply potential VSS. The clock signal 4 (CK4) is a signal that alternates between high and low levels at regular intervals. When the voltage is at H level, it is VDD, and when it is at L level, it is VSS. By making VDD higher than the potential VCC of the power supply line 52, the operation can be prevented from being affected. Therefore, the potential applied to the gate electrode of the transistor can be kept low, and the transistor This reduces the shift in threshold voltage and suppresses degradation.

[0312] In FIG. 17A, the first terminal of the first transistor 31 is electrically connected to the power supply line 51. the second terminal of the ninth transistor 39 is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode of the The second transistor 32 has a first terminal electrically connected to the fourth input terminal 24. The second terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. and a gate electrode electrically connected to the gate electrode of the fourth transistor 34. The third transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the The second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 One terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the power supply line 53. The two terminals are the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrode is electrically connected to the fourth input terminal 24. The transistor 36 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the second transistor 36. The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. The seventh transistor 3 has a gate electrode electrically connected to the fifth input terminal 25. The first terminal of the transistor 7 is electrically connected to the power supply line 52, and the second terminal of the transistor 38 is electrically connected to the power supply line 52. The gate electrode is electrically connected to the second terminal and the gate electrode is electrically connected to the third input terminal 23. The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and a second terminal connected to the gate electrode of the second transistor 32. 4, and the gate electrode is electrically connected to the second input terminal 2 The ninth transistor 39 has a first terminal electrically connected to the first transistor 2. The second terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are supplied with a voltage. The gate electrode is electrically connected to the power supply line 52. The first terminal of the sigma 40 is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the second output terminal 22. the gate electrode of the ninth transistor 39 is electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has a first terminal electrically connected to the power supply line 53. The second terminal is electrically connected to the second output terminal 27, and the gate electrode is The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. The twelfth transistor 42 has a first terminal electrically connected to the power supply line 53 and a second terminal is electrically connected to the second output terminal 27, and the gate electrode is connected to the gate of the seventh transistor 37. The first terminal of the thirteenth transistor 43 is electrically connected to the power supply line 53. , the second terminal is electrically connected to the first output terminal 26, and the gate electrode is It is electrically connected to the gate electrode of the seventh transistor 37 .

[0313] In FIG. 17A, the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 4 The connection point of the gate electrode of the ninth transistor 30 and the second terminal of the ninth transistor 39 is referred to as node A. The gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the eleventh transistor 38 and the gate electrode of the eleventh transistor 41 is node B. (See FIG. 17(A)).

[0314] The timing chart of the shift register having a plurality of pulse output circuits shown in FIG. The above is shown in FIG. 17(B).

[0315] As shown in FIG. 17A, the ninth power supply voltage Vcc is applied to the gate electrode. By providing the transistor 39, the following occurs before and after the bootstrap operation: The advantages are as follows:

[0316] If the ninth transistor 39 having the second potential VCC applied to its gate electrode is not present, the boot When the potential at node A rises due to the strapping operation, the second terminal of the first transistor 31 The potential of the source electrode, which is at VDD, rises and becomes higher than the first power supply potential VDD. The source electrode of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, the gate electrode and the source electrode are A large bias voltage is applied between the gate and drain electrodes, which causes a large stress. Therefore, the gate electrode is supplied with a second power supply potential VC By providing a ninth transistor 39 to which C is applied, bootstrap operation Although the potential of the node A rises due to this, the potential of the second terminal of the first transistor 31 does not rise. In other words, by providing the ninth transistor 39, As a result, a negative bias voltage is applied between the gate electrode and the source electrode of the first transistor 31. Therefore, by using the circuit configuration of this embodiment, , a negative bias voltage applied between the gate electrode and the source electrode of the first transistor 31 Since the resistance can be reduced, deterioration of the first transistor 31 due to stress can be suppressed. Cut.

[0317] The ninth transistor 39 is provided at a location corresponding to the second gate of the first transistor 31. and a gate electrode of the third transistor 33 via a first terminal and a second terminal. In this embodiment, a plurality of pulse output circuits may be provided. In the case of a shift register, the signal line driver circuit has more stages than the scanning line driver circuit. The transistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0318] The active layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a material, the off-state current of a transistor is reduced, and the on-state current and the field effect This can increase the effective mobility and reduce the degree of degradation, making it possible to In addition, a transistor using an oxide semiconductor can be Compared to transistors using silicon, a high potential is applied to the gate electrode. The degree of deterioration of the transistor is small. Therefore, the power supply line that supplies the second power supply potential VCC The same operation can be obtained by supplying the first power supply potential VDD to the Since the number of lines can be reduced, the circuit can be made smaller.

[0319] The gate electrode of the seventh transistor 37 is connected to the clock signal supplied from the third input terminal 23. A lock signal, supplied by the second input terminal 22 to the gate electrode of the eighth transistor 38 The clock signal to be input is provided by the second input terminal 22 to the gate electrode of the seventh transistor. The clock signal supplied to the eighth gate electrode is supplied by the third input terminal 23. The same effect can be achieved by changing the wiring relationship so that the clock signal is generated. In the shift register shown in (A), the seventh transistor 37 and the eighth transistor The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. On, then the seventh transistor 37 is off, and the eighth transistor 38 is off. By setting the input terminal 22 to the ON state, the potentials of the second input terminal 22 and the third input terminal 23 are reduced. The potential drop at node B is a drop at the gate electrode of the seventh transistor 37. , and the potential of the gate electrode of the eighth transistor 38 decreases. On the other hand, in the shift register shown in FIG. The seventh transistor 37 is turned on, and the eighth transistor 38 is turned on. The seventh transistor 37 is turned off, and the eighth transistor 38 is turned off. By turning off the input terminal 38, the second input terminal 22 and the third input terminal 23 The voltage drop at node B caused by the voltage drop at node B is absorbed by the gate of the eighth transistor 38. Therefore, the number of times the seventh transistor is turned on can be reduced to one time by the decrease in the potential of the seventh transistor. The clock signal CK3 is supplied to the gate electrode of the third input terminal 23. As a result of the clock signal CK2 being supplied to the gate electrode of the transistor 38 from the second input terminal 22, The linear relationship is preferable because it reduces the number of fluctuations in the potential of node B. This is because noise can be reduced.

[0320] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during this period, the pulse output This can suppress malfunction of the power circuit.

[0321] This embodiment mode can be implemented in combination with the above embodiment modes.

[0322] (Embodiment 6) A liquid crystal display device according to one embodiment of the present invention includes a transistor having a low off-state current and high reliability. Since the display is made of a metal, the display has high visibility and high reliability. The configuration of the liquid crystal display device according to the present invention will be described below.

[0323] FIG. 18 illustrates an example of a cross-sectional view of a pixel in a liquid crystal display device according to one embodiment of the present invention. The transistor 1401 shown in FIG. 8 has a gate electrode 1402 formed on an insulating surface and a gate A gate insulating film 1403 on the gate electrode 1402 and a gate electrode on the gate insulating film 1403 The oxide semiconductor film 1404 overlapping with the electrode 1402 and the oxide semiconductor film 1404 are A conductive film 1406 formed to be stacked and functioning as a source electrode or a drain electrode The transistor 1401 further includes an oxide semiconductor film The insulating film 1407 formed on the insulating film 1404 may be included in the components. 7 includes a gate electrode 1402, a gate insulating film 1403, an oxide semiconductor film 1404, and a conductive film. The oxide semiconductor film 1406 is formed to cover the conductive film 1406a and the conductive film 1406b. The film 1404 has an amorphous region 1430 and a crystalline region 1431 on the amorphous region 1430. The crystalline region 1431 is in contact with the conductive film 1406a and the conductive film 1406b.

[0324] An insulating film 1408 is formed on the insulating film 1407. An opening is provided in a part of 8, and the opening is made to be in contact with the conductive film 1406b. A pixel electrode 1410 is formed on the substrate.

[0325] Moreover, on the insulating film 1408, a spacer 141 for controlling the cell gap of the liquid crystal element is formed. The spacer 1417 is formed by etching the insulating film into a desired shape. However, by dispersing filler on the insulating film 1408, the cell gap can be reduced. The loop may be controlled.

[0326] An alignment film 1411 is formed on the pixel electrode 1410. A counter electrode 1413 is provided at a position facing the pixel 10. An alignment film 1414 is formed on the side closer to the electrode 1410. 414 can be formed using organic resin such as polyimide or polyvinyl alcohol. The surface is subjected to orientation treatment such as rubbing to align the liquid crystal molecules in a certain direction. Rubbing is done by applying pressure to the alignment film while wrapping it in a cloth such as nylon. This can be done by rotating the roller and rubbing the surface of the alignment film in a certain direction. It uses inorganic materials such as silicon oxide and has alignment properties by evaporation without alignment treatment. It is also possible to form the alignment film 1411 and the alignment film 1414 directly.

[0327] The pixel electrode 1410 and the counter electrode 1413 are surrounded by a sealant 1416. The liquid crystal 1415 is provided in the area. The liquid crystal 1415 is injected by a dispenser ( A dripping method or a dip method (pumping method) may be used. Filler may be mixed into the material 1416 .

[0328] A liquid crystal element formed by a pixel electrode 1410, a counter electrode 1413, and a liquid crystal 1415 The color filter may be overlapped with a color filter that can transmit light in a specific wavelength range. The filter is formed on a substrate (counter substrate) 1420 on which the counter electrode 1413 is formed. The color filter is made by applying an organic resin, such as an acrylic resin, in which a pigment is dispersed, to a substrate. After coating on 420, it can be selectively formed using photolithography. In addition, after coating the substrate 1420 with polyimide resin in which a pigment is dispersed, etching is performed. Alternatively, a droplet ejection method such as ink jetting may be used. This allows selective formation of color filters.

[0329] In addition, disclination caused by the disturbance of the alignment of the liquid crystal 1415 between pixels is visible. To prevent this, a light-shielding film capable of blocking light may be formed between the pixels. The shielding film uses an organic resin containing black pigments such as carbon black and low-order titanium oxide. Alternatively, the shielding film can be formed of a film using chromium.

[0330] The pixel electrode 1410 and the counter electrode 1413 are made of, for example, indium oxide containing silicon oxide. Indium tin oxide (ITSO), indium tin oxide (ITO), zinc oxide (ZnO), indium oxide By using transparent conductive materials such as zinc oxide (IZO) and gallium-doped zinc oxide (GZO), In this embodiment mode, the pixel electrode 1410 and the counter electrode 1413 are made of a material that transmits light. An example of fabricating a transmissive liquid crystal element using a transparent conductive film is shown, but the present invention is not limited to this configuration. The liquid crystal display device according to one aspect of the present invention may be a semi-transmissive type or a reflective type. .

[0331] In this embodiment, the liquid crystal display device is a TN (Twisted Nematic) ) type, but VA (Vertical Alignment) type, OCB (Opti cally Compensated Birefringence) type, IPS(In The transistor of the present invention can also be applied to other liquid crystal display devices such as a two-plane switching type. A transistor can be used.

[0332] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal 1415. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 10 μsec. It is optically isotropic, so alignment processing is not required. The field angle dependency is small.

[0333] 19 is a perspective view showing an example of the structure of a liquid crystal display device of the present invention. The display device includes a liquid crystal panel 1601 having a liquid crystal element formed between a pair of substrates, and a first diffusion plate 1602. 602, a prism sheet 1603, a second diffusion plate 1604, a light guide plate 1605, and a reflector. It has a reflector 1606 , a light source 1607 , and a circuit board 1608 .

[0334] A liquid crystal panel 1601, a first diffusion plate 1602, a prism sheet 1603, and a second diffusion plate 1604 are included. The scattering plate 1604, the light guide plate 1605, and the reflector 1606 are stacked in this order. 607 is provided at the end of the light guide plate 1605, and is a light source diffused inside the light guide plate 1605. The light from 1607 passes through the first diffusion plate 1602, the prism sheet 1603 and the second diffusion plate The liquid crystal panel 1601 is uniformly illuminated by the light 1604 .

[0335] In this embodiment, a first diffusion plate 1602 and a second diffusion plate 1604 are used. However, the number of the diffusion plates is not limited to this, and may be one or three or more. The scattering plate may be provided between the light guide plate 1605 and the liquid crystal panel 1601. Even if the diffusion plate is provided only on the side closer to the liquid crystal panel 1601 than the reflective sheet 1603, The diffusing plate is provided only on the side closer to the light guide plate 1605 than the prism sheet 1603. It's okay to have it.

[0336] The cross section of the prism sheet 1603 is not limited to the sawtooth shape shown in FIG. It is sufficient if the shape can condense the light from the plate 1605 onto the liquid crystal panel 1601 side.

[0337] The circuit board 1608 includes a circuit for generating various signals to be input to the liquid crystal panel 1601, The circuit board 16 is provided with circuits for processing these signals. 08 and the LCD panel 1601 are connected by FPC (Flexible Printed Circuit) The above circuit is connected via a COG (Chip On Ground) 1609. The liquid crystal panel 1601 may be connected using the glass method, or one of the above circuits may be connected using the glass method. Even if the part is connected to FPC1609 using the COF (Chip on Film) method, good.

[0338] In FIG. 19, a control circuit for controlling the driving of a light source 1607 is provided on a circuit board 1608. The control circuit and the light source 1607 are connected via an FPC 1610. However, the control circuit may be formed on the liquid crystal panel 1601. In this case, the liquid crystal panel 1601 and the light source 1607 are connected by an FPC or the like. do.

[0339] 19 shows an edge-light type light source in which a light source 1607 is arranged at the edge of a liquid crystal panel 1601. In the liquid crystal display device of the present invention, the light source 1607 is located directly below the liquid crystal panel 1601. It may also be a direct type that is placed in the

[0340] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0341] (Embodiment 7) In this embodiment, a structure of a light-emitting device in which a transistor according to one embodiment of the present invention is used in a pixel is described. In this embodiment, a transistor for driving a light-emitting element is an n-type The cross-sectional structure of the pixel in this case will be described with reference to FIG. The case where the first electrode is a cathode and the second electrode is an anode will be described. The second electrode may be a cathode.

[0342] In FIG. 20A, a transistor 6031 is an n-type transistor, and light emitted from a light emitting element 6033 is A cross-sectional view of the pixel when taken out from the first electrode 6034 side is shown. The insulating film 6037 is covered with a partition wall 6038 having an opening. The first electrode 6034 is partially exposed at the opening of the partition wall 6038. In the opening, a first electrode 6034, an electroluminescent layer 6035, and a second electrode 6036 are arranged in this order. are stacked on top of each other.

[0343] The first electrode 6034 is formed of a material or a film thickness that transmits light and has a small work function. The conductive material can be formed of a metal, an alloy, an electrically conductive compound, or a mixture thereof. Specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr metals, alloys containing these (Mg:Ag, Al:Li, Mg:In, etc.), and their compounds In addition to compounds (calcium fluoride, calcium nitride), rare earth metals such as Yb and Er can also be used. When an electron injection layer is provided, other conductive films such as aluminum may be used. The first electrode 6034 is formed to a thickness that allows light to pass through (preferably 5 Furthermore, the conductive film is formed to a thickness of about 100 nm to 300 nm. A light-transmitting conductive film is formed using a light-transmitting oxide conductive material so as to be in contact with the upper or lower surface of the substrate. In this case, the sheet resistance of the first electrode 6034 may be reduced. Oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium-added Only conductive films using other transparent oxide conductive materials such as zinc oxide (GZO) are used. It is also possible to use ITSO or indium oxide containing silicon oxide. A mixture of 20% zinc oxide (ZnO) may also be used. When an electron injection layer is used, it is desirable to provide the electroluminescent layer 6035 with an electron injection layer.

[0344] The second electrode 6036 is formed of a material and a film thickness that reflects or blocks light. It is made of a material suitable for use as an anode, such as titanium nitride, zirconium nitride, One or more of titanium, tungsten, nickel, platinum, chromium, silver, aluminum, etc. In addition to the single layer film, titanium nitride and aluminum-based films are also available. The three-layer structure of the film, the film mainly composed of aluminum, and the titanium nitride film is formed as the second electrode 6036. It can be used for.

[0345] The electroluminescent layer 6035 is composed of one or more layers. In this case, these layers are classified into a hole injection layer, a hole transport layer, a light emitting layer, and a It can be classified into an electron transport layer, an electron injection layer, etc. The electroluminescent layer 6035 is a light-emitting layer as well as When the layer has any one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, From the first electrode 6034, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are formed in this order. The boundaries between the layers do not necessarily need to be clear, and the layers that make up each other may be stacked one on top of the other. In some cases, the materials are mixed together and the interface is unclear. Organic materials can be used. It is possible to use any material of molecular type. The number of repeats (degree of polymerization) corresponds to a low polymer of about 2 to 20. The distinction between these is not necessarily strict, and these are the types in which hole transport properties (hole mobility) are particularly important. For convenience, the hole injection layer is the layer that contacts the anode, and the The layer in contact with the hole injection layer is called the hole transport layer to distinguish it from the electron transport layer and electron injection layer. Similarly, the layer in contact with the cathode is called the electron injection layer, and the layer in contact with the electron injection layer is called the electron transport layer. The light-emitting layer may also function as an electron transport layer, and is therefore also called a light-emitting electron transport layer.

[0346] In the case of the pixel shown in FIG. 20(A), light emitted from the light emitting element 6033 is indicated by a white arrow. As shown, it can be taken out from the first electrode 6034 side.

[0347] Next, in FIG. 20B, a transistor 6041 is an n-type transistor, and a light emitting element 6043 emits light. 10 is a cross-sectional view of a pixel in the case where light is extracted from the second electrode 6046 side. 41 is covered with an insulating film 6047, and a partition wall 604 having an opening is formed on the insulating film 6047. 8 is formed. The first electrode 6044 is partially exposed at the opening of the partition wall 6048. In the opening, a first electrode 6044, an electroluminescent layer 6045, and a second electrode 6046 are disposed. are stacked in order.

[0348] The first electrode 6044 is formed of a material and a film thickness that reflects or blocks light and has a workability. Formation of low-function metals, alloys, electrically conductive compounds, and mixtures thereof Specifically, alkali metals such as Li and Cs, and aluminum metals such as Mg, Ca, and Sr can be used. Potassium earth metals and alloys containing them (Mg:Ag, Al:Li, Mg:In, etc.), and In addition to these compounds (calcium fluoride, calcium nitride), rare earth metals such as Yb and Er When an electron injection layer is provided, other conductive films such as aluminum can be used. It is also possible to use

[0349] The second electrode 6046 is formed of a material or a film thickness that transmits light and also serves as an anode. The substrate is made of a material suitable for use. For example, indium tin oxide (ITO), zinc oxide ( ZnO), indium zinc oxide (IZO), gallium-doped zinc oxide (GZO), etc. Other transparent conductive oxide materials can be used for the second electrode 6046. TSO and indium oxide containing silicon oxide, plus 2-20% zinc oxide (ZnO) A mixture of the above may be used for the second electrode 6046. Other examples include titanium nitride, zirconium nitride, titanium, tungsten, nickel, platinum, In addition to single layer films made of one or more of chromium, silver, aluminum, etc., titanium nitride and aluminum a titanium nitride film and a film mainly composed of aluminum; A three-layer structure with a titanium film can also be used for the second electrode 6046. When using a material other than a conductive material, the thickness should be such that light can pass through (preferably 5 nm to 3 The second electrode 6046 is formed with a thickness of about 100 nm.

[0350] The electroluminescent layer 6045 can be formed in the same manner as the electroluminescent layer 6035 in FIG. 20(A). do.

[0351] In the case of the pixel shown in FIG. 20B, light emitted from the light emitting element 6043 is indicated by a white arrow. As shown, it can be taken out from the second electrode 6046 side.

[0352] Next, in FIG. 20(C), a transistor 6051 is an n-type transistor, and a light emitting element 6053 emits light. 6 is a cross-sectional view of a pixel when light is extracted from the first electrode 6054 side and the second electrode 6056 side. The transistor 6051 is covered with an insulating film 6057. A partition wall 6058 having an opening is formed. The first electrode The first electrode 6054 is partially exposed through the opening, and the electroluminescent layer 60 55 and a second electrode 6056 are laminated in this order.

[0353] The first electrode 6054 can be formed in the same manner as the first electrode 6034 in FIG. 20(A). The second electrode 6056 is formed in the same manner as the second electrode 6046 in FIG. The electroluminescent layer 6055 can be formed in the same manner as the electroluminescent layer 6035 in FIG. It is possible.

[0354] In the case of the pixel shown in FIG. 20C, light emitted from the light emitting element 6053 is indicated by a white arrow. As shown in FIG. 6, the light can be extracted from the first electrode 6054 side and the second electrode 6056 side. .

[0355] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Example]

[0356] By using a semiconductor device according to one embodiment of the present invention, highly reliable electronic devices and low power consumption devices can be realized. It is possible to provide electronic devices with low power consumption and high-speed operation. By using such a semiconductor display device, it is possible to provide electronic devices with high reliability, electronic devices with high visibility, and electronic devices with high power consumption. It is possible to provide electronic devices with low power consumption. In the case of portable electronic devices, which are difficult to use, a semiconductor device with low power consumption according to one embodiment of the present invention or By adding a semiconductor display device to the components, the continuous use time can be extended. In addition, by using a transistor with low off-state current, This eliminates the need for redundant circuit design to cover the large size of semiconductor devices. The degree of integration of the integrated circuit can be increased, and the semiconductor device can have higher functionality.

[0357] In addition, in the semiconductor device of the present invention, the temperature of the heat treatment in the manufacturing process can be suppressed. Therefore, the substrate is made of flexible synthetic resin such as plastic, which has lower heat resistance than glass. It is possible to fabricate highly reliable transistors with excellent characteristics even on substrates. Therefore, by using the manufacturing method according to one embodiment of the present invention, a highly reliable, lightweight, and It is possible to provide a flexible semiconductor device. Polyesters, such as ethylene terephthalate (PET), polyethersulfone ( PES), polyethylene naphthalate (PEN), polycarbonate (PC), polyethylene Polyether ketone (PEEK), polysulfone (PSF), polyetherimide (PE I), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide , acrylonitrile butadiene styrene resin, polyvinyl chloride, polypropylene, polyacetic acid vinyl acid, acrylic resin, etc.

[0358] The semiconductor device according to one embodiment of the present invention can be used in a display device, a notebook personal computer, a recording medium, Image playback device equipped with a medium (typically DVD: Digital Versatile (Devices with a display that can play back recording media such as discs and display the images) In addition, a semiconductor device according to one embodiment of the present invention can be used in an electric device. Sub-devices include mobile phones, portable game consoles, personal digital assistants, e-books, video cameras, Digital still camera, goggle-type display (head-mounted display), navigation audio systems, audio playback devices (car audio, digital audio players, etc.) , copiers, facsimiles, printers, printer-combined machines, automated teller machines (A TM), vending machines, etc. Specific examples of these electronic devices are shown in Figure 21.

[0359] FIG. 21A shows an electronic book having a housing 7001, a display portion 7002, and the like. The semiconductor display device according to this embodiment can be used in the display portion 7002. By using a semiconductor display device according to one embodiment of the present invention, it is possible to read e-books with high reliability and high visibility. It is possible to provide electronic books with high display quality and low power consumption. The semiconductor device according to one embodiment of the present invention can be used in an integrated circuit for controlling the operation of an electronic book. The semiconductor device according to one aspect of the present invention can be used in an integrated circuit for controlling the operation of an electronic book. By using this device, it is possible to develop highly reliable e-books, e-books with low power consumption, and e-books with high speed operation. It is possible to provide electronic books with high functionality. This allows the semiconductor device and the semiconductor display device to have flexibility, so that they can be used in flexible It is possible to provide a lightweight and user-friendly e-book.

[0360] FIG. 21B shows a display device, which includes a housing 7011, a display portion 7012, a support base 7013, and the like. The semiconductor display device according to one embodiment of the present invention can be used in the display portion 7012. By using a semiconductor display device according to one embodiment of the present invention for the display portion 7012, a highly reliable display can be obtained. It is possible to provide a display device, a display device capable of displaying with high visibility, and a display device with low power consumption. Furthermore, the semiconductor device according to one embodiment of the present invention can be implemented by a centralized control circuit for controlling the driving of a display device. The present invention can be applied to an integrated circuit for controlling the driving of a display device. By using the semiconductor device, a highly reliable display device, a display device with low power consumption, It is possible to provide a high-speed driving display device and a high-performance display device. All information display devices for personal computers, TV broadcast reception, advertising displays, etc. This includes placement.

[0361] FIG. 21C shows a display device, which includes a housing 7021, a display portion 7022, and the like. The semiconductor display device according to this embodiment can be used in the display portion 7022. By using a semiconductor display device according to one embodiment of the present invention, a display device with high reliability and high visibility can be realized. It is possible to provide a display device capable of high quality display and a display device with low power consumption. The semiconductor device according to one embodiment of the present invention can be used in an integrated circuit for controlling the driving of a display device. The semiconductor device according to one aspect of the present invention can be used in an integrated circuit for controlling the driving of a display device. By using this device, it is possible to produce highly reliable display devices, display devices with low power consumption, and display devices with high speed operation. In addition, a flexible substrate can be used to provide a high-performance display device. This allows the semiconductor device and the semiconductor display device to have flexibility, so that they can be used in flexible Therefore, a display device that is light, easy to use, and simple to use can be provided. In this way, the display device can be fixed to fabric or the like and used, which increases the range of applications of the display device. Spreads in stages.

[0362] FIG. 21D shows a portable game machine, which includes a housing 7031, a housing 7032, a display portion 7033, Display unit 7034, microphone 7035, speaker 7036, operation keys 7037, The semiconductor display device according to one embodiment of the present invention includes a display portion 7033, a display area 7038, and the like. It can be used for the display portion 7034. The display portion 7033 and the display portion 7034 can be used as one embodiment of the present invention. By using the semiconductor display device, a highly reliable portable game machine and a highly visible display can be manufactured. It is possible to provide a portable game machine that can display a variety of images and consumes low power. In addition, the semiconductor device according to one embodiment of the present invention is an integrated circuit for controlling the operation of a portable game machine. The present invention can be applied to an integrated circuit for controlling the operation of a portable game machine. By using the semiconductor device according to the embodiment, a highly reliable portable game machine and a portable game machine with low power consumption can be realized. We can provide handheld game machines, high-speed portable game machines, and highly functional portable game machines. The portable game machine shown in FIG. 21(D) has two display units 7033 and 7043. 034, the number of display units that the portable game machine has is not limited to this.

[0363] FIG. 21E shows a mobile phone, which includes a housing 7041, a display portion 7042, an audio input portion 7043, It has an audio output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received in the sensor into an electrical signal, an external image can be captured. The semiconductor display device according to one embodiment of the present invention can be used for the display portion 7042. By using a semiconductor display device according to one embodiment of the present invention, a highly reliable mobile phone, It is possible to provide a mobile phone capable of displaying with high visibility and a mobile phone with low power consumption. Further, the semiconductor device according to one embodiment of the present invention may be applied to an integrated circuit for controlling the driving of a mobile phone. The present invention can be applied to an integrated circuit for controlling the operation of a mobile phone. By using the semiconductor device, it is possible to provide a highly reliable mobile phone, a mobile phone with low power consumption, and a mobile phone with high speed operation. We can provide mobile phones with high functionality.

[0364] FIG. 21(F) shows a portable information terminal, which includes a housing 7051, a display unit 7052, and operation keys 7053. The portable information terminal shown in FIG. 21(F) has a modem built in a housing 7051. The semiconductor display device according to one embodiment of the present invention can be used in the display portion 7052. By using the semiconductor display device according to one embodiment of the present invention for the display portion 7052, reliability can be improved. portable information terminals with low power consumption, portable information terminals with highly visible displays, portable information terminals with low power consumption Furthermore, the semiconductor device according to one embodiment of the present invention can be used for driving a portable information terminal. It can be used in integrated circuits for controlling the operation of mobile information terminals. By using a semiconductor device according to one embodiment of the present invention for an integrated circuit, a highly reliable portable information terminal can be realized. Eventually, we will provide low-power portable information terminals, high-speed portable information terminals, and highly functional portable information terminals. It can be provided.

[0365] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. [Explanation of symbols]

[0366] 10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 input terminals 25 Input terminals 26 Output terminal 27 Output terminal 31 Transistor 32 transistors 33 Transistor 34 transistors 35 transistors 36 transistors 37 Transistor 38 transistors 39 Transistor 40 transistors 41 Transistor 42 transistors 43 Transistor 51 Power line 52 Power line 53 Power line 100 boards 101 gate electrode 102 Gate insulating film 103 Oxide semiconductor film 104 Oxide semiconductor film 105 Oxide semiconductor film 106 Crystal region 107 Oxide semiconductor film 108 Oxide semiconductor film 109 Crystal region 110 Amorphous region 111 Source electrode 112 Drain electrode 113 Insulating film 114 transistors 115 Back gate electrode 116 Insulating film 130 Channel protection film 131 Source electrode 132 Drain electrode 133 Insulating Film 140 transistors 145 Back gate electrode 146 Insulating Film 200 boards 201 Insulating film 202 Electrode 203 Oxide semiconductor film 205 Oxide semiconductor film 206 Crystal region 207 Oxide semiconductor film 208 Oxide semiconductor film 209 Crystal region 210 Amorphous region 211 Electrode 212 Gate insulating film 213 Gate electrode 214 insulating film 215 Wiring 216 Wiring 217 Wiring 218 parts 220 transistors 221 Contact Hole 222 Contact Hole 223 Contact Hole 230 Wiring 231 Contact Hole 700 pixel unit 701 Signal line driver circuit 702 Scanning line driving circuit 703 pixels 704 Transistor 705 Display element 706 Holding capacity 707 Signal Line 708 scan lines 710 pixel electrode 711 Counter electrode 712 Microcapsules 713 Source or drain electrode 714 Resin 1401 Transistor 1402 gate electrode 1403 Gate insulating film 1404 Oxide semiconductor film 1406a Conductive film 1406b Conductive film 1407 Insulating film 1408 insulating film 1410 pixel electrode 1411 Alignment film 1413 Counter electrode 1414 Alignment film 1415 LCD 1416 Sealing material 1417 Spacer 1420 PCB 1430 Amorphous region 1431 Crystal region 1601 LCD panel 1602 Diffuser 1603 Prism Sheet 1604 Diffuser 1605 Light guide plate 1606 Reflector 1607 Light source 1608 Circuit Board 1609 FPC 1610 FPC 5300 board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing control circuit 5601 Shift Register 5602 Sampling Circuit 5603 Transistor 5604 Wiring 5605 Wiring 6031 Transistor 6033 Light-emitting element 6034 Electrode 6035 Electroluminescent layer 6036 Electrode 6037 Insulating film 6038 Bulkhead 6041 Transistor 6043 Light-emitting element 6044 Electrode 6045 Electroluminescent layer 6046 Electrode 6047 Insulating film 6048 Bulkhead 6051 transistor 6053 Light-emitting element 6054 Electrode 6055 Electroluminescent layer 6056 Electrode 6057 Insulating film 6058 Bulkhead 7001 Case 7002 Display section 7011 Case 7012 Display section 7013 Support stand 7021 Housing 7022 Display section 7031 Housing 7032 chassis 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Key 7038 Stylus 7041 Housing 7042 Display section 7043 Audio Input Unit 7044 Audio output section 7045 Operation Key 7046 Light receiving section 7051 Housing 7052 Display section 7053 Operation Key

Claims

[Claim 1] A semiconductor device having a transistor, A gate electrode; a gate insulating film on the gate electrode; an oxide semiconductor film provided on the gate insulating film and overlapping with the gate electrode; a source electrode and a drain electrode electrically connected to the oxide semiconductor film; a first insulating film provided on the source electrode and the drain electrode and having a region in contact with the oxide semiconductor film; the oxide semiconductor film contains In, Ga, and Zn, the first insulating film contains silicon and oxygen, the oxide semiconductor film has a crystalline region whose c-axis is oriented in a direction substantially perpendicular to a surface of the oxide semiconductor film, The semiconductor device, wherein the oxide semiconductor film has a thickness of 5 nm or more and less than 30 nm.

Images