Driving circuit and semiconductor device

Abstract

To provide a driving circuit that can prevent the occurrence of undershoot in the driving voltage of a transistor, and a semiconductor device including such a driving circuit.SOLUTION: A driving circuit of an embodiment is a driving circuit that performs normally-off driving of a transistor circuit in which a normally-on type first transistor and a normally-off type second transistor are connected in series. The driving circuit of the embodiment has: a clamp transistor arranged between wiring connected between the first transistor and the second transistor and a driving terminal of the first transistor, and functioning as a clamp element; and a capacitor arranged between the clamp transistor and the wiring and connected in series to the clamp transistor.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a drive circuit and a semiconductor device. [Background technology]

[0002] A known technique involves connecting a normally-off transistor in series with a normally-on transistor to form a transistor circuit and operating the transistor circuit in a normally-off mode. For example, when two such transistor circuits are connected to form a half-bridge circuit and the half-bridge circuit is operated in a switching mode, there is a problem that undershoot occurs in the drive voltage of the transistor included in the high-side transistor circuit when the low-side transistor circuit is turned off. To address this problem, a Zener diode is known to be used to suppress undershoot in the drive voltage. However, the Zener diode has a limited response time, making it difficult to sufficiently suppress undershoot. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-118630 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a drive circuit capable of suppressing undershoot in the drive voltage of a transistor, and a semiconductor device including such a drive circuit. [Means for solving the problem]

[0005] A drive circuit according to an embodiment is a drive circuit that normally-off drives a transistor circuit configured by connecting a normally-on first transistor and a normally-off second transistor in series. The drive circuit according to an embodiment includes a clamp transistor that functions as a clamp element and is arranged between a wiring that is connected between the first transistor and the second transistor and a drive terminal of the first transistor, and a capacitor that is arranged between the clamp transistor and the wiring and is connected in series with the clamp transistor. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 1 is a circuit diagram showing a semiconductor package according to a first embodiment. [Figure 3] 10 is a diagram showing a current flowing through an external load when a transistor circuit in a high-side semiconductor package is in an OFF state and a transistor circuit in a low-side semiconductor package is in an ON state in the first embodiment. FIG. [Figure 4] 10 is a diagram showing a current flowing through an external load when a transistor circuit in a high-side semiconductor package is in an ON state and a transistor circuit in a low-side semiconductor package is in an OFF state in the first embodiment. FIG. [Figure 5] 4 is a timing chart showing an example of the relationship between the power supply voltage and the gate voltage of each transistor when the transistor circuit of the first embodiment is switched between an ON state and an OFF state. [Figure 6] 10 is a diagram showing a current that flows when the high-side transistor circuit of the first embodiment is in an OFF state and the low-side transistor circuit is switched from an OFF state to an ON state. FIG. [Figure 7] 10 is a diagram showing a current that flows when the high-side transistor circuit of the first embodiment is in the OFF state and the low-side transistor circuit is switched from the ON state to the OFF state. FIG. [Figure 8]10 is a timing chart showing an example of the relationship between the power supply voltage and the gate voltage of each transistor when the transistor circuit of the second embodiment is switched between an ON state and an OFF state. [Figure 9] FIG. 10 is a circuit diagram showing a part of a semiconductor device according to a third embodiment. [Figure 10] FIG. 10 is a circuit diagram showing a part of a semiconductor device according to a fourth embodiment. [Figure 11] FIG. 10 is a circuit diagram showing a part of a semiconductor device according to a fifth embodiment. [Figure 12] FIG. 10 is a circuit diagram showing a part of a semiconductor device according to a sixth embodiment. [Figure 13] FIG. 13 is a circuit diagram showing a boost converter according to a seventh embodiment. [Figure 14] FIG. 13 is a circuit diagram showing a step-down converter according to an eighth embodiment. [Figure 15] 10 is a graph showing an example of an induced voltage generated in a semiconductor device of a comparative example. [Figure 16] 10 is a graph showing an example of undershoot occurring in a semiconductor device of a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, a driving circuit and a semiconductor device according to an embodiment will be described with reference to the drawings.

[0008] (First embodiment) FIG. 1 is a circuit diagram showing a semiconductor device 100 according to a first embodiment. The semiconductor device 100 shown in FIG. 1 is a semiconductor device for supplying power to an external load 60. The semiconductor device 100 is used as a power conversion circuit such as a power supply circuit or an inverter circuit by connecting a power source, the external load 60, and a coil 70. The method of connecting the external load 60 and the coil 70 is not limited to the method shown in FIG. 1. The semiconductor device 100 is controlled by a controller 80. Pulse signals PSA and PSB are input to the semiconductor device 100 from the controller 80 via an insulating transmission circuit unit 81.

[0009] As shown in FIG. 1, in the first embodiment, the semiconductor device 100 includes two semiconductor packages 10A and 10B. The semiconductor packages 10A and 10B are connected in series between a power supply VDC that supplies power to an external load 60 and ground GND. The semiconductor package 10A is a high-side semiconductor package connected to the power supply VDC. The semiconductor package 10B is a low-side semiconductor package connected to ground GND. In the first embodiment, the external load 60 is connected in parallel to the semiconductor package 10A with respect to the power supply VDC. A coil 70 is disposed between a wiring portion 71 that connects the semiconductor packages 10A and 10B and the external load 60. The wiring portion 71 connects a transistor circuit 30A to a transistor circuit 30B, which will be described later.

[0010] In the circuits disclosed herein, "another element is disposed between a certain element and another element" means that the other element is disposed on the circuit between the certain element and the other element, leading from one to the other.

[0011] In the first embodiment, the semiconductor package 10A and the semiconductor package 10B have the same structure, although they differ in the timing of operation of the semiconductor device 100. Therefore, in the following description, the configuration of the high-side semiconductor package 10A will be described as a representative, and a description of the configuration of the low-side semiconductor package 10B may be omitted.

[0012] The semiconductor package 10A includes a transistor circuit 30A and a drive circuit 40A. The semiconductor package 10B includes a transistor circuit 30B and a drive circuit 40B. The semiconductor packages 10A and 10B are configured by encapsulating drive circuits 40A and 40B and transistor circuits 30A and 30B, respectively, in a single package. The drive circuit 40A and the transistor circuit 30A do not necessarily have to be encapsulated in a single package, and the drive circuit 40B and the transistor circuit 30B do not necessarily have to be encapsulated in a single package. The two transistor circuits 30A and 30B are connected in series. The two transistor circuits 30A and 30B form a half-bridge circuit 30H. The transistor circuit 30A and the transistor circuit 30B are connected to each other by a wiring portion 71.

[0013] FIG. 2 is a circuit diagram illustrating a semiconductor package 10A. As shown in FIG. 2, the transistor circuit 30A is configured by connecting a first transistor 31A and a second transistor 32A in series. The first transistor 31A is a normally-on transistor. The first transistor 31A is a field effect transistor (FET). The first transistor 31A is, for example, a high electron mobility transistor (HEMT) using gallium nitride (GaN). The first transistor 31A is a high-voltage element having a withstand voltage of, for example, about 600 V or more. A drain terminal 31d of the first transistor 31A is connected to a power supply VDC. A source terminal 31s of the first transistor 31A is connected to a source terminal 32s of the second transistor 32A. The first transistor 31A is in an ON state when the potential difference between the gate terminal 31g and the source terminal 31s is 0 V. The threshold voltage of the first transistor 31A is a negative voltage value. In the following description, the threshold voltage of the first transistor 31A is −Vth, and the absolute value of the threshold voltage of the first transistor 31A is Vth. The first transistor 31A is turned off when the gate voltage becomes smaller than −Vth with respect to the source terminal 31s.

[0014] The second transistor 32A is a normally-off transistor. The second transistor 32A is a field-effect transistor. In the first embodiment, the second transistor 32A is a P-channel field-effect transistor. More specifically, the second transistor 32A is a P-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The withstand voltage of the second transistor 32A is lower than the withstand voltage of the first transistor 31A. The second transistor 32A is a low-voltage MOSFET with a withstand voltage of, for example, about 60 V or less. A source terminal 32s of the second transistor 32A is connected to a source terminal 31s of the first transistor 31A. A drain terminal 32d of the second transistor 32A is connected to a wiring portion 71 that connects the two transistor circuits 30A and 30B.

[0015] The transistor circuit 30A, which is composed of the first transistor 31A and the second transistor 32A, can be regarded as a single normally-off field-effect transistor. When the transistor circuit 30A is regarded as a single field-effect transistor, the gate terminal G of the field-effect transistor is the gate terminal 31g of the first transistor 31A, the drain terminal D of the field-effect transistor is the drain terminal 31d of the first transistor 31A, and the source terminal S of the field-effect transistor is the drain terminal 32d of the second transistor 32A.

[0016] In this disclosure, the gate terminal of a field-effect transistor corresponds to the "drive terminal." The drive terminal of a transistor is a terminal to which a voltage is applied to drive the transistor. Of the drain terminal and source terminal of a field-effect transistor, the terminal from which current flows when the field-effect transistor is turned on corresponds to the "output terminal." In other words, in a P-channel field-effect transistor, the drain terminal corresponds to the "output terminal," and in an N-channel field-effect transistor, the source terminal corresponds to the "output terminal."

[0017] The drive circuit 40A is a drive circuit that drives the transistor circuit 30A in a normally-off mode. The drive circuit 40A is a gate drive circuit that applies a voltage to the gate terminal G of the transistor circuit 30A, i.e., the gate terminal 31g of the first transistor 31A. The drive circuit 40A includes a semiconductor chip 20A, a resistive element 43, a first capacitor 44, a second capacitor 47, and a second ground 92. The semiconductor chip 20A includes a power supply voltage terminal 41A, a ground terminal 42A, connection terminals 21, 22, 23, 24, 25, 26, and 27, a power supply voltage wiring 48, a first ground 91, a third transistor 33A, a fourth transistor 34A, a fifth transistor 35A, a first diode 45, a second diode 46, and a control circuit unit 50A.

[0018] The power supply voltage terminal 41A is exposed to the outside of the semiconductor chip 20A. A power supply that drives the drive circuit 40A is connected to the power supply voltage terminal 41A. A power supply voltage VDDA is applied to the power supply voltage terminal 41A. A power supply voltage wiring 48 is connected to the power supply voltage terminal 41A. The power supply voltage VDDA is applied to the power supply voltage wiring 48. The power supply voltage wiring 48 is connected between the first transistor 31A and the second transistor 32A. The power supply voltage wiring 48 is connected to the source terminal 31s of the first transistor 31A and the source terminal 32s of the second transistor 32A.

[0019] The ground terminal 42A is exposed to the outside of the semiconductor chip 20A. A ground having a reference potential VSSA that serves as a reference for the power supply voltage VDDA is connected to the ground terminal 42A. The reference potential VSSA is a potential that serves as a reference when the drive circuit 40A operates. As a result, the potential of the first ground 91 of the drive circuit 40A that is connected to the ground terminal 42A becomes the reference potential VSSA. There are no particular limitations on the reference potential VSSA, as long as it is a potential that serves as a reference for the power supply voltage VDDA.

[0020] The connection terminals 21, 22, 23, 24, 25, 26, and 27 are exposed to the outside of the semiconductor chip 20A. A resistive element 43 is connected to the connection terminal 21. A gate terminal 31g of the first transistor 31A is connected to the connection terminals 22 and 25. The connection terminals 22 and 25 may be combined into one common terminal. A gate terminal 32g of the second transistor 32A is connected to the connection terminal 23. A drain terminal 32d of the second transistor 32A is connected to the connection terminal 24. One electrode of the second capacitor 47 and a second ground 92 are connected to the connection terminal 26. The other electrode of the second capacitor 47 is connected to the connection terminal 27.

[0021] The third transistor 33A and the fourth transistor 34A are normally-off field effect transistors. In the first embodiment, the third transistor 33A is a P-channel MOSFET. In the first embodiment, the fourth transistor 34A is an N-channel MOSFET. The third transistor 33A and the fourth transistor 34A are connected in series to each other and disposed between the power supply voltage wiring 48 and the first ground 91. A source terminal 33s of the third transistor 33A is connected to the power supply voltage wiring 48. A drain terminal 33d of the third transistor 33A is connected to the drain terminal 34d of the fourth transistor 34A. A source terminal 34s of the fourth transistor 34A is connected to the first ground 91.

[0022] The gate terminal 31g of the first transistor 31A is connected between the third transistor 33A and the fourth transistor 34A via the resistive element 43. As a result, the third transistor 33A is disposed between the power supply voltage wiring 48 and the gate terminal 31g of the first transistor 31A. The fourth transistor 34A is disposed between the first ground 91 and the gate terminal 31g of the first transistor 31A. The resistive element 43 is disposed between the gate terminal 31g of the first transistor 31A and the third transistor 33A. One end of the resistive element 43 is connected to the gate terminal 31g of the first transistor 31A. The other end of the resistive element 43 is connected to the drain terminal 33d of the third transistor 33A.

[0023] The fifth transistor 35A is a normally-off field-effect transistor. In the first embodiment, the fifth transistor 35A is an N-channel MOSFET. In the first embodiment, the fifth transistor 35A corresponds to a "clamp transistor" that functions as a clamp element. The fifth transistor 35A constitutes an active Miller clamp circuit. The fifth transistor 35A is disposed on a wiring connected between the first transistor 31A and the second transistor 32A, i.e., between a power supply voltage wiring 48 and a gate terminal 31g of the first transistor 31A. A second capacitor 47 is disposed between the fifth transistor 35A and the power supply voltage wiring 48. A drain terminal 35d of the fifth transistor 35A is connected to the gate terminal 31g of the first transistor 31A. A source terminal 35s of the fifth transistor 35A is an output terminal of the fifth transistor 35A and is connected to one electrode of the second capacitor 47 and a second ground 92. A gate terminal 35g of the fifth transistor 35A is connected to a switching circuit unit 51A (described later) of the control circuit unit 50A.

[0024] The output capacitance Coss of the fifth transistor 35A is one-tenth or less of the input capacitance Ciss of the first transistor 31A. The output capacitance Coss of the fifth transistor 35A is the sum of the drain-source capacitance Cds and gate-drain capacitance Cgd of the fifth transistor 35A. The input capacitance Ciss of the first transistor 31A is the sum of the gate-source capacitance Cgs and gate-drain capacitance Cgd of the first transistor 31A.

[0025] The anode of the first diode 45 is connected to the gate terminal 31g of the first transistor 31A and the drain terminal 35d of the fifth transistor 35A, and the cathode of the first diode 45 is connected to the drain terminal 32d of the second transistor 32A.

[0026] The anode of the second diode 46 is connected to the gate terminal 31g of the first transistor 31A and the drain terminal 35d of the fifth transistor 35A. The anode of the second diode 46 is connected to the anode of the first diode 45. The cathode of the second diode 46 is connected to the drain terminal 34d of the fourth transistor 34A.

[0027] The first capacitor 44 is disposed between the power supply voltage wiring 48 and the first ground 91. One electrode of the first capacitor 44 is connected to the power supply voltage wiring 48. The other electrode of the first capacitor 44 is connected to the first ground 91.

[0028] The second capacitor 47 is disposed between the fifth transistor 35A and the power supply voltage wiring 48. The second capacitor 47 is connected in series with the fifth transistor 35A. One electrode of the second capacitor 47 is connected to the source terminal 35s of the fifth transistor 35A and the second ground 92. The other electrode of the second capacitor 47 is connected to the power supply voltage wiring 48. The capacitance of the second capacitor 47 is 10 times or more the input capacitance Ciss of the first transistor 31A. It is more preferable that the capacitance of the second capacitor 47 is approximately 100 times the input capacitance Ciss of the first transistor 31A.

[0029] The second ground 92 is a ground provided separately from the first ground 91. The voltage of the second ground 92 is lower than the power supply voltage VDD. The second ground 92 has a reference potential VG that serves as a reference when the fifth transistor 35A operates. In the first embodiment, the reference potential VG of the second ground 92 is the same as the reference potential VSSA of the first ground 91. That is, in the first embodiment, the voltage of the second ground 92 is the same as the voltage of the first ground 91. Note that the reference potential VG of the second ground 92 may be different from the reference potential VSSA of the first ground 91, and the voltage of the second ground 92 may be different from the voltage of the first ground 91.

[0030] The second ground 92 is insulated from the first ground 91 or is indirectly connected to the first ground 91 via an element having a relatively high impedance with respect to a current flowing from the second ground 92 to the first ground 91. The element having a relatively high impedance is, for example, an element having an impedance higher than the impedance of the body diode of the fifth transistor 35A. The element may be, for example, a resistor element or a diode having an anode connected to the first ground 91 and a cathode connected to the second ground 92.

[0031] The control circuit unit 50A is a circuit unit that switches each of the second transistor 32A, the third transistor 33A, the fourth transistor 34A, and the fifth transistor 35A between an ON state and an OFF state. The control circuit unit 50A is disposed between the power supply voltage wiring 48 and the first ground 91. A power supply voltage VDDA is input to the control circuit unit 50A. The reference potential in the control circuit unit 50A is the reference potential VSSA. The control circuit unit 50A has a switching circuit unit 51A and a voltage comparison circuit unit 52A.

[0032] The switching circuit unit 51A is disposed between the power supply voltage wiring 48 and the first ground 91. A power supply voltage VDDA is input to the switching circuit unit 51A. The reference potential of the switching circuit unit 51A is the reference potential VSSA. A pulse signal PSA for switching the state of the transistor circuit 30A is input to the switching circuit unit 51A from the controller 80 via the isolation transmission circuit unit 81. In the first embodiment, a pulse signal PSB for switching the state of the low-side transistor circuit 30B is input to the switching circuit unit 51A from the controller 80 via the isolation transmission circuit unit 81. An output from the voltage comparison circuit unit 52A is input to the switching circuit unit 51A. A gate terminal 33g of the third transistor 33A, a gate terminal 34g of the fourth transistor 34A, and a gate terminal 35g of the fifth transistor 35A are connected to the switching circuit unit 51A.

[0033] In the first embodiment, the switching circuit unit 51A switches each of the third transistor 33A, the fourth transistor 34A, and the fifth transistor 35A between an ON state and an OFF state based on the pulse signals PSA and PSB and the output from the voltage comparison circuit unit 52A. More specifically, the switching circuit unit 51A applies voltages to the gate terminal 33g of the third transistor 33A and the gate terminal 34g of the fourth transistor 34A based on the pulse signal PSA and the output from the voltage comparison circuit unit 52A to switch the state of each transistor. The switching circuit unit 51A applies voltage to the gate terminal 35g of the fifth transistor 35A based on the pulse signal PSB to switch the state of the fifth transistor 35A.

[0034] The voltage comparison circuit unit 52A is disposed between the power supply voltage wiring 48 and the first ground 91. The power supply voltage VDDA is input to the voltage comparison circuit unit 52A. The reference potential of the voltage comparison circuit unit 52A is the reference potential VSSA. The gate terminal 32g of the second transistor 32A is connected to the voltage comparison circuit unit 52A. The voltage comparison circuit unit 52A is a circuit unit that compares the voltage of the power supply voltage wiring 48, i.e., the power supply voltage VDDA, with a voltage higher than the absolute value Vth of the threshold voltage of the first transistor 31A, and outputs the comparison result. The threshold voltage of the normally-on first transistor 31A is a negative value. The comparison result of the voltage comparison circuit unit 52A is output as a voltage value. The comparison result of the voltage comparison circuit unit 52A is output to the switching circuit unit 51A and the gate terminal 32g of the second transistor 32A.

[0035] As shown in FIG. 1, the transistor circuit 30B in the low-side semiconductor package 10B is configured by connecting a first transistor 31B and a second transistor 32B in series. The first transistor 31B is a transistor similar to the first transistor 31A in the high-side semiconductor package 10A. The second transistor 32B is a transistor similar to the second transistor 32A in the high-side semiconductor package 10A. The drain terminal 31d of the first transistor 31B is connected to the drain terminal 32d of the high-side second transistor 32A. The drain terminal 32d of the second transistor 32B is connected to ground GND.

[0036] The drive circuit 40B is a drive circuit that drives the transistor circuit 30B in a normally-off mode. The drive circuit 40B is a gate drive circuit that applies a voltage to the gate terminal of the transistor circuit 30B, i.e., the gate terminal of the first transistor 31B. The drive circuit 40B includes a semiconductor chip 20B, a resistive element 43, a first capacitor 44, and a second capacitor 47. The semiconductor chip 20B includes a power supply voltage terminal 41B, a ground terminal 42B, a third transistor 33B, a fourth transistor 34B, a fifth transistor 35B, and a control circuit unit 50B. The control circuit unit 50B includes a switching circuit unit 51B and a voltage comparison circuit unit 52B. A pulse signal PSB is input to the switching circuit unit 51B from the controller 80 via the insulating transmission circuit unit 81. A pulse signal PSA for switching the state of the high-side transistor circuit 30A may also be input to the switching circuit unit 51B from the controller 80.

[0037] A power supply for driving the drive circuit 40 B is connected to the power supply voltage terminal 41 B. A power supply voltage VDDB is applied to the power supply voltage terminal 41 B and a power supply voltage wiring 48 connected to the power supply voltage terminal 41 B.

[0038] A ground having a reference potential VSSB, which is the reference for the power supply voltage VDDB, is connected to the ground terminal 42B. The reference potential VSSB is a potential that serves as a reference when the drive circuit 40B operates. As a result, the potential of the first ground 91 of the drive circuit 40B, which is connected to the ground terminal 42B, becomes the reference potential VSSB.

[0039] Next, the operation of the semiconductor device 100 will be described. The semiconductor device 100 is controlled based on pulse signals PSA and PSB input from the controller 80. The semiconductor device 100 is controlled so that the ON / OFF state of the transistor circuit 30A in the high-side semiconductor package 10A and the ON / OFF state of the transistor circuit 30B in the low-side semiconductor package 10B are alternately switched. FIG. 3 is a diagram showing the current Ie1 flowing through the external load 60 when the transistor circuit 30A in the high-side semiconductor package 10A is in the OFF state and the transistor circuit 30B in the low-side semiconductor package 10B is in the ON state. FIG. 4 is a diagram showing the current Ie2 flowing through the external load 60 when the transistor circuit 30A in the high-side semiconductor package 10A is in the ON state and the transistor circuit 30B in the low-side semiconductor package 10B is in the OFF state.

[0040] 3, when the high-side transistor circuit 30A is in the OFF state and the low-side transistor circuit 30B is in the ON state, a current Ie1 flows from the power supply VDC to ground GND. The current Ie1 flows from the power supply VDC through the external load 60, the coil 70, and the transistor circuit 30B in that order, and then to ground GND. In this case, energy is stored in the coil 70.

[0041] 4, when the high-side transistor circuit 30A is in the ON state and the low-side transistor circuit 30B is in the OFF state, a current Ie2 flows circulating through a closed circuit formed by the external load 60, the coil 70, and the transistor circuit 30A. At this time, the current Ie2 flows through the external load 60, the coil 70, and the transistor circuit 30A in this order. At this time, the stored energy is released from the coil 70.

[0042] FIG. 5 is a timing chart showing an example of the relationship between the power supply voltages VDDA and VDDB and the gate voltages of the transistors when the transistor circuits 30A and 30B are switched between the ON state and the OFF state. In the following description, the power supply voltages VDDA and VDDB may be collectively referred to as the power supply voltage VDD. Furthermore, the reference potentials VSSA and VSSB may be collectively referred to as the reference potential VSS. VG1A is the gate voltage of the first transistor 31A. VG2A is the gate voltage of the second transistor 32A. VG3A is the gate voltage of the third transistor 33A. VG4A is the gate voltage of the fourth transistor 34A. VG5A is the gate voltage of the fifth transistor 35A. VG1B is the gate voltage of the first transistor 31B. VG2B is the gate voltage of the second transistor 32B. VG3B is the gate voltage of the third transistor 33B. VG4B is the gate voltage of the fourth transistor 34B. The gate voltage is the voltage of the gate terminal when the potential of the source terminal is used as a reference. The gate voltage corresponds to the "drive voltage" for driving a field effect transistor. In the first embodiment, the low-side fifth transistor 35B is always in the OFF state and its state is not switched.

[0043] The horizontal axis in FIG. 5 represents time t. FIG. 5 illustrates an example in which the semiconductor device 100 is powered on at time t1. When the semiconductor device 100 is powered off, the potential of the power supply voltage wiring 48 is the same as the reference potential VSS, so the power supply voltage VDD is 0 V. When the semiconductor device 100 is powered off, the potential of the gate terminals 31g of the first transistors 31A and 31B is the reference potential VSS, and the potential of the source terminals 31s of the first transistors 31A and 31B is also the potential of the power supply voltage wiring 48, i.e., the reference potential VSS. Therefore, when the semiconductor device 100 is powered off, the normally-on first transistors 31A and 31B are in the ON state. When the semiconductor device 100 is powered off, the other normally-off transistors are in the OFF state. Note that the circuit may be configured so that the fourth transistors 34A and 34B are in the ON state when the semiconductor device 100 is powered off.

[0044] When the semiconductor device 100 is powered on, the power supply voltage VDD rises from 0V to a constant voltage Vd. As the power supply voltage VDD rises, the potential of the source terminal 31s of the first transistors 31A and 31B connected to the power supply voltage line 48 rises. Therefore, the gate voltages VG1A and VG1B of the first transistors 31A and 31B fall by the amount of the rise in the potential of the source terminal 31s. At time t2, after time t1, the value of the power supply voltage VDD becomes equal to the absolute value Vth of the threshold voltage of the first transistors 31A and 31B. At time t2, the gate voltages VG1A and VG1B become the threshold voltage of the first transistors 31A and 31B, i.e., −Vth. After time t2, when the gate voltages VG1A and VG1B become smaller than −Vth, the first transistors 31A and 31B are turned off. At time t4, which is later than time t2, the power supply voltage VDD becomes the constant voltage Vd, and the gate voltages VG1A and VG1B become negative values ​​whose absolute values ​​are the same as the constant voltage Vd, that is, −Vd.

[0045] The voltage comparison circuit units 52A and 52B apply the same voltage as that applied to the source terminal 32s to the gate terminals 32g of the second transistors 32A and 32B to set the gate voltages VG2A and VG2B to 0 V and keep the second transistors 32A and 32B in the OFF state until the power supply voltage VDD exceeds the absolute value Vth of the threshold voltages of the first transistors 31A and 31B. In the first embodiment, the voltage comparison circuit units 52A and 52B short-circuit the power supply voltage wiring 48 and the gate terminals 32g of the second transistors 32A and 32B to set the gate voltages VG2A and VG2B to 0 V until the power supply voltage VDD exceeds the absolute value Vth of the threshold voltages of the first transistors 31A and 31B.

[0046] When the power supply voltage VDD reaches or exceeds a value Vh, which is higher than the absolute value Vth of the threshold voltage of the first transistors 31A and 31B, the voltage comparator circuits 52A and 52B lower the voltage applied to the gate terminals 32g of the second transistors 32A and 32B, turning on the P-channel second transistors 32A and 32B. In the example of FIG. 5, at time t3 between times t2 and t4, the power supply voltage VDD reaches a value Vh. When the power supply voltage VDD reaches or exceeds Vh, the voltage comparator circuits 52A and 52B connect the gate terminals 32g of the second transistors 32A and 32B to the first ground 91, for example. This causes the gate voltages VG2A and VG2B of the second transistors 32A and 32B to drop by the absolute value of the power supply voltage VDD. When the power supply voltage VDD reaches a constant voltage Vd, the gate voltages VG2A and VG2B of the second transistors 32A and 32B become −Vd. The threshold voltages of the second transistors 32A and 32B are higher than −Vd. Therefore, in the first embodiment, the P-channel second transistors 32A and 32B are turned on when the gate voltages VG2A and VG2B reach −Vd. The second transistors 32A and 32B are always maintained in the on state when the power supply voltage VDD is at a constant voltage Vd. In this way, the control circuit 50A turns on the second transistor 32A when the voltage of the power supply voltage line 48 is higher than the absolute value Vth of the threshold voltage of the first transistor 31A.

[0047] When the switching circuits 51A and 51B determine based on the output from the voltage comparator circuits 52A and 52B that the power supply voltage VDD exceeds the absolute value Vth of the threshold voltage of the first transistors 31A and 31B, they apply a voltage equal to or greater than the threshold voltage of each transistor to the gate terminals 34g of the fourth transistors 34A and 34B, thereby turning on the fourth transistors 34A and 34B. In the example of FIG. 5, when the power supply voltage VDD reaches a value Vh higher than the absolute value Vth at time t3, the switching circuits 51A and 51B set the gate voltages VG4A and VG4B of the fourth transistors 34A and 34B to Vb, thereby turning on the fourth transistors 34A and 34B. The value Vb is not particularly limited as long as it is a gate voltage value that can turn each transistor on. The value Vb may be the same as the constant voltage Vd.

[0048] When the power supply voltage VDD reaches the constant voltage Vd at time t4, the semiconductor device 100 enters an operable state. At time t4, when the semiconductor device 100 enters an operable state, the first transistors 31A and 31B, the third transistors 33A and 33B, and the fifth transistor 35A are in the OFF state, and the second transistors 32A and 32B and the fourth transistors 34A and 34B are in the ON state. At time t4, the same voltage as the power supply voltage VDD is applied to the gate terminals 33g of the third transistors 33A and 33B from the switching circuit units 51A and 51B. As a result, the gate voltages VG3A and VG3B of the third transistors 33A and 33B are 0V at time t4, and the normally-off third transistors 33A and 33B are in the OFF state. When the third transistors 33A and 33B are turned off, the switching circuit sections 51A and 51B short-circuit the gate terminals 33g and source terminals 33s of the third transistors 33A and 33B via the power supply voltage wiring 48, for example.

[0049] The transistor circuit 30A, which can be considered as a single normally-off transistor, is in the ON state when both the first transistor 31A and the second transistor 32A are in the ON state, and is in the OFF state when at least one of the first transistor 31A and the second transistor 32A is in the OFF state. The same applies to the transistor circuit 30B. Therefore, at time t4 when the semiconductor device 100 is in an operable state, each of the transistor circuits 30A and 30B is in the OFF state. While the semiconductor device 100 is supplied with the constant voltage Vd and in an operable state, the second transistors 32A and 32B are always in the ON state. Therefore, the transistor circuits 30A and 30B can be turned ON and OFF by turning the first transistors 31A and 31B ON and OFF, respectively.

[0050] When the semiconductor device 100 enters an operable state, the semiconductor device 100 starts a switching operation that alternates between the ON and OFF states of the transistor circuits 30A and 30B based on pulse signals PSA and PSB input from the controller 80. In the example of FIG. 5 , at time t5, which is after time t4, a pulse signal PSB is input to the low-side switching circuit unit 51B to turn the low-side transistor circuit 30B ON. At time t5, a pulse signal PSB is also input to the high-side switching circuit unit 51A to turn the low-side transistor circuit 30B ON. Based on the pulse signal PSB, the switching circuit unit 51B turns the third transistor 33B ON and the fourth transistor 34B OFF. Specifically, the switching circuit unit 51B applies a voltage to the gate terminal 33g of the third transistor 33B to turn the third transistor 33B ON, and a voltage to the gate terminal 34g of the fourth transistor 34B to turn the fourth transistor 34B OFF. In the example of Figure 5, at time t5, the switching circuit unit 51B sets the value of the gate voltage VG3B of the P-channel third transistor 33B to -Va to turn the third transistor 33B on, and sets the value of the gate voltage VG4B of the N-channel fourth transistor 34B to 0V to turn the fourth transistor 34B off.

[0051] When the third transistor 33B is turned on and the fourth transistor 34B is turned off, the gate terminal 31g of the first transistor 31B is shorted to the power supply voltage line 48 via the third transistor 33B, and the gate voltage VG1B of the first transistor 31B becomes 0 V. This turns the first transistor 31B on. When the first transistor 31B is turned on, the low-side transistor circuit 30B is turned on, and a current Ie1 flows as shown in FIG. 3.

[0052] The control circuit 50A of the high-side drive circuit 40A switches the fifth transistor 35A in the high-side drive circuit 40A between the ON state and the OFF state based on the state of the low-side drive circuit 40B. In the first embodiment, the switching circuit 51A in the high-side control circuit 50A switches the fifth transistor 35A to the ON state when a pulse signal PSB for switching the low-side transistor circuit 30B to the ON state is input. As a result, in the first embodiment, the high-side control circuit 50A switches the fifth transistor 35A to the ON state before the first transistor 31B switches to the ON state. Specifically, the switching circuit 51A applies a voltage to the gate terminal 35g of the fifth transistor 35A to switch the fifth transistor 35A to the ON state. In the example of FIG. 5, at time t5 when the low-side third transistor 33B switches to the ON state, the switching circuit 51A sets the gate voltage VG5A of the N-channel fifth transistor 35A to a value Vc, switching the fifth transistor 35A to the ON state. The value Vc is not particularly limited as long as it is a gate voltage value that can turn on the fifth transistor 35A. The value Vc may be the same value as the constant voltage Vd.

[0053] The high-side control circuit 50A turns off the fifth transistor 35A when a first predetermined time ta has elapsed since the first low-side transistor 31B was turned on after the pulse signal PSB for turning on the low-side transistor circuit 30B is input. That is, in the first embodiment, the control circuit 50A of the high-side drive circuit 40A keeps the fifth transistor 35A of the high-side drive circuit 40A in the ON state for at least the first predetermined time ta from the time the first transistor 31B of the low-side drive circuit 40B is switched from the OFF state to the ON state. The first predetermined time ta is equal to or longer than the time from the time the first transistor 31B is switched from the OFF state to the ON state until the current Is1 shown in FIG. 6 stops flowing. The current Is1 will be described in detail later.

[0054] In the first embodiment, the high-side control circuit 50A switches the fifth transistor 35A to the OFF state when a third predetermined time tc has elapsed since the pulse signal PSB for switching the low-side transistor circuit 30B to the ON state is input to switch the fifth transistor 35A to the ON state. The third predetermined time tc is equal to or longer than the time from when the third transistor 33B is switched from the OFF state to the ON state until the current Is1 shown in FIG. 6 stops flowing. The third predetermined time tc is longer than the first predetermined time ta.

[0055] At time t6, a predetermined time after the low-side transistor circuit 30B is turned on, the controller 80 inputs a pulse signal PSB to the switching circuit unit 51B to instruct the low-side transistor circuit 30B to be turned off. At time t6, the switching circuit unit 51B turns the third transistor 33B off and the fourth transistor 34B on based on the pulse signal PSB. This causes the first transistor 31B to be turned off again, and the transistor circuit 30B to be turned off.

[0056] In the first embodiment, the switching circuit 51A in the high-side control circuit 50A turns the fifth transistor 35A ON when the pulse signal PSB for turning the low-side transistor circuit 30B OFF is input. As a result, in the first embodiment, the high-side control circuit 50A turns the fifth transistor 35A ON before the first transistor 31B switches OFF. After the pulse signal PSB for turning the low-side transistor circuit 30B OFF is input, the high-side control circuit 50A turns the fifth transistor 35A ON. Then, when the second predetermined time tb has elapsed since the first low-side transistor 31B switched OFF, the high-side control circuit 50A turns the fifth transistor 35A OFF. In other words, the high-side control circuit 50A keeps the fifth transistor 35A in the high-side drive circuit 40A ON until the second predetermined time tb has elapsed since the first transistor 31B in the low-side drive circuit 40B switched from ON to OFF. The second predetermined time tb is equal to or longer than the time from when the first transistor 31B is switched from the ON state to the OFF state until the current Is2 shown in FIG. 7 stops flowing. The current Is2 will be described in detail later. The second predetermined time tb is shorter than the time from when the first transistor 31B is switched from the ON state to the OFF state until the high-side first transistor 31A is switched to the ON state.

[0057] In the first embodiment, the high-side control circuit 50A turns the fifth transistor 35A off when a fourth predetermined time td has elapsed since the fifth transistor 35A was turned on in response to the input of a pulse signal PSB for turning the low-side transistor circuit 30B off. The fourth predetermined time td is equal to or longer than the time from when the third transistor 33B is switched from the on state to the off state until the current Is2 shown in FIG. 7 stops flowing. The fourth predetermined time td is longer than the second predetermined time tb.

[0058] At time t6, the controller 80 turns the transistor circuit 30B to the OFF state, and then, after a predetermined dead time, outputs a pulse signal PSA at time t7 to turn the high-side transistor circuit 30A to the ON state. The pulse signal PSA is input to the high-side switching circuit 51A, which turns the high-side transistor circuit 30A to the ON state in the same manner as the switching circuit 51B described above. This causes the current Ie2 to flow, as shown in FIG. 4. Thereafter, the state of the transistor circuit 30A and the state of the transistor circuit 30B are alternately switched in the same manner.

[0059] When the semiconductor device 100 is powered off, the power supply voltage VDD drops from the constant voltage Vd to 0 V. The example in FIG. 5 shows a case where the semiconductor device 100 is powered off at time t8. When the semiconductor device 100 is powered off, the power supply voltage VDD drops, and the gate voltages VG1A and VG1B of the first transistors 31A and 31B rise by the amount of the drop in the power supply voltage VDD. At time t9, which is after time t8, the value of the power supply voltage VDD reaches a value Vh that is higher than the absolute value Vth of the threshold voltages of the first transistors 31A and 31B. The voltage comparator circuits 52A and 52B apply a voltage to the gate terminals 32g of the second transistors 32A and 32B to turn the second transistors 32A and 32B off. The voltage comparison circuit units 52A, 52B, for example, short-circuit the gate terminal 32g and the source terminal 32s via the power supply voltage wiring 48 to set the gate voltages VG2A, VG2B of the second transistors 32A, 32B to 0 V, thereby turning the second transistors 32A, 32B to the OFF state. When the power supply of the semiconductor device 100 is turned off, the second transistors 32A, 32B turn off before the power supply voltage VDD becomes equal to the absolute value Vth of the threshold voltages of the first transistors 31A, 31B.

[0060] As described above, when the semiconductor device 100 is powered on, the control circuit units 50A, 50B turn on the second transistors 32A, 32B after the power supply voltage VDD exceeds the absolute value Vth of the threshold voltages of the first transistors 31A, 31B, and when the semiconductor device 100 is powered off, they turn off the second transistors 32A, 32B before the power supply voltage VDD becomes equal to or lower than the absolute value Vth of the threshold voltages of the first transistors 31A, 31B. This prevents the transistor circuits 30A, 30B from being turned on when the semiconductor device 100 is powered on and when the semiconductor device 100 is powered off, thereby preventing unintended current from flowing through the external load 60.

[0061] When the power supply voltage VDD drops to Vh when the semiconductor device 100 is powered off, the switching circuit units 51A and 51B turn the fourth transistors 34A and 34B off. At this time, the switching circuit units 51A and 51B may keep the fourth transistors 34A and 34B on.

[0062] At time t10, which is later than time t9, the power supply voltage VDD drops to the absolute value Vth of the threshold voltage of the first transistors 31A and 31B. When the power supply voltage VDD falls below the absolute value Vth of the threshold voltage of the first transistors 31A and 31B, the gate voltages VG1A and VG1B of the first transistors 31A and 31B rise above the threshold voltage, and the first transistors 31A and 31B turn on. As described above, because the second transistors 32A and 32B are in the off state before the power supply voltage VDD reaches the absolute value Vth, the transistor circuits 30A and 30B remain in the off state even when the first transistors 31A and 31B turn on. When the power supply voltage VDD falls to 0 V at time t11, the semiconductor device 100 stops operating.

[0063] Next, a description will be given of the current Is1 that flows when the high-side transistor circuit 30A is in the OFF state and the low-side transistor circuit 30B is switched from the OFF state to the ON state during the switching operation of the semiconductor device 100. Fig. 6 is a diagram showing the current Is1 that flows when the high-side transistor circuit 30A is in the OFF state and the low-side transistor circuit 30B is switched from the OFF state to the ON state.

[0064] 6, when the low-side transistor circuit 30B is switched to the ON state, a current Is1 flows from the drain terminal D of the transistor circuit 30A to the first transistor 31A. The current Is1 flows from the drain terminal 31d of the first transistor 31A to the gate terminal 31g of the first transistor 31A via the gate-drain capacitance of the first transistor 31A. The current Is1 that flows to the gate terminal 31g flows, for example, through the first diode 45 and then to the source terminal S of the transistor circuit 30A, i.e., the drain terminal 32d of the second transistor 32A. The current Is1 is generated, for example, until the gate-drain capacitance of the first transistor 31A is charged.

[0065] In a conventional drive circuit, when current Is1 flows through gate terminal 31g, charge accumulates in gate terminal 31g, causing a rise in gate voltage VG1A of first transistor 31A. This can result in an induced voltage PV, which causes the gate voltage VG1A of first transistor 31A to rise in a positive direction. FIG. 15 is a graph showing an example of the induced voltage PV generated in a comparative semiconductor device that does not include fifth transistor 35A and second capacitor 47. VG1C, shown by a solid line in FIG. 15, is the gate voltage of the high-side first transistor of the comparative example. VG1D, shown by a dashed-dotted line in FIG. 15, is the gate voltage of the low-side first transistor of the comparative example. As shown in FIG. 15, in the comparative example, when the gate voltage VG1D of the low-side first transistor rises and turns on the low-side first transistor, an induced voltage PV is generated, which momentarily causes the gate voltage VG1C of the high-side first transistor to rise. 15, at time t1a, the low-side third transistor is turned on and the gate voltage VG1D starts to rise. At time t2a, which is later than time t1a, the low-side first transistor is turned on.

[0066] In the first embodiment, when the low-side third transistor 33B is turned on, the high-side fifth transistor 35A is turned on and maintained in the on state for the third predetermined time tc. As described above, the third predetermined time tc is equal to or longer than the time from when the third transistor 33B is switched from the off state to the on state until the current Is1 shown in FIG. 6 stops flowing. Therefore, in the comparative example, the fifth transistor 35A is maintained in the on state from when the current Is1 starts flowing and the induced voltage PV is generated until the induced voltage PV disappears. By turning the fifth transistor 35A on, the gate terminal 31g of the first transistor 31A and the second ground 92 are short-circuited via the fifth transistor 35A, thereby suppressing a rise in the voltage at the gate terminal 31g of the first transistor 31A. This suppresses the generation of the induced voltage PV in the gate voltage VG1A of the first transistor 31A. In the example of FIG. 15, the fifth transistor 35A is turned on at time t1a, and is turned off at time t3a, which is the first predetermined time ta after time t2a.

[0067] Next, a description will be given of the current Is2 that flows when the high-side transistor circuit 30A is in the OFF state and the low-side transistor circuit 30B is switched from the ON state to the OFF state during the switching operation of the semiconductor device 100. Fig. 7 is a diagram showing the current Is2 that flows when the high-side transistor circuit 30A is in the OFF state and the low-side transistor circuit 30B is switched from the ON state to the OFF state.

[0068] 7, when the low-side transistor circuit 30B is switched to the OFF state, a current Is2 flows from the source terminal S of the transistor circuit 30A to the second transistor 32A. The current Is2 flows from the drain terminal 32d to the source terminal 32s of the second transistor 32A. The current Is2 that has flowed through the second transistor 32A flows from the source terminal 32s through the first capacitor 44, the fourth transistor 34A, the resistive element 43, and the gate-drain capacitance of the first transistor 31A, in that order, to the drain terminal D of the transistor circuit 30A. The current Is2 is generated until the first capacitor 44 and the gate-drain capacitance of the first transistor 31A are charged.

[0069] Before the first capacitor 44 is charged by the voltage applied between the drain terminal D and the source terminal S, a potential difference occurs between the electrodes of the first capacitor 44, and a current Is2 flows through the first capacitor 44.

[0070] In a conventional drive circuit, when current Is2 flows through resistive element 43, a voltage drop occurs, which may cause an undershoot US in the voltage at gate terminal 31g of first transistor 31A. FIG. 16 is a graph showing an example of undershoot US that occurs in a comparative semiconductor device that does not include fifth transistor 35A and second capacitor 47. As shown in FIG. 16, in the comparative example, after the gate voltage VG1D of the low-side first transistor drops and turns off, the gate voltage VG1C of the high-side transistor circuit momentarily drops, causing an undershoot US. In the example of FIG. 16, at time t1b, the low-side third transistor turns off, and the gate voltage VG1D begins to drop. At time t2b, which is later than time t1b, the low-side first transistor turns off.

[0071] In the first embodiment, when the low-side third transistor 33B is turned OFF, the high-side fifth transistor 35A is turned ON and maintained in the ON state for a fourth predetermined time td. As described above, the fourth predetermined time td is equal to or longer than the time from when the third transistor 33B is switched from ON to OFF until the current Is2 shown in FIG. 7 stops flowing. Therefore, in the comparative example, the fifth transistor 35A is maintained in the ON state from when the current Is2 starts flowing, causing an undershoot US, until the undershoot US disappears. By turning the fifth transistor 35A ON, the gate terminal 31g of the first transistor 31A and the second ground 92 are short-circuited via the fifth transistor 35A, thereby suppressing a voltage drop at the gate terminal 31g of the first transistor 31A. This suppresses the occurrence of undershoot US.

[0072] In the example of FIG. 16, the fifth transistor 35A is turned ON at time t1b and turned OFF at time t3b, which is a second predetermined time tb after time t2b. Time t3b is before the pulse signal PSA is input to the high-side control circuit 50A and the high-side third transistor 33A is turned ON. That is, in the first embodiment, the control circuit 50A of the high-side drive circuit 40A turns OFF the fifth transistor 35A after the first transistor 31A in the low-side drive circuit 40B is switched from ON to OFF, but before control to turn ON the first transistor 31A in the high-side drive circuit 40A is initiated. At time t4b, which is later than time t3b, the first transistor 31A is turned ON.

[0073] A conventional technique for suppressing the above-described undershoot US involves placing a Zener diode between the power supply voltage wiring and the gate terminal of the first transistor. In this case, the anode of the Zener diode is connected to the gate terminal of the first transistor. The cathode of the Zener diode is connected to the power supply voltage wiring. However, the Zener diode has a limited response time, and therefore its effectiveness in suppressing undershoot is limited. Therefore, there is a problem in that the undershoot US occurring in the gate voltage of the first transistor on the high side cannot be sufficiently suppressed. Furthermore, even if such a Zener diode is provided, there is a problem in that the induced voltage PV occurring in the gate voltage of the first transistor cannot be suppressed.

[0074] To address the above problem, according to the first embodiment, the drive circuit 40A is a drive circuit 40A that normally drives a transistor circuit 30A configured by connecting a normally-on first transistor 31A and a normally-off second transistor 32A in series. The drive circuit 40A includes a fifth transistor 35A (clamp transistor) that functions as a clamp element and is disposed between a power supply voltage wiring 48 (wiring) connected between the first transistor 31A and the second transistor 32A and a gate terminal 31g (drive terminal) of the first transistor 31A. The fifth transistor 35A also includes a second capacitor 47 that is disposed between the fifth transistor 35A and the power supply voltage wiring 48 and is connected in series with the fifth transistor 35A. Therefore, by turning on the fifth transistor 35A when an undershoot US occurs, a drop in the voltage at the gate terminal 31g can be suppressed even if the current Is2 flows through the resistor element 43 as described above. This suppresses undershoot US from occurring in the gate voltage VG1A (drive voltage) of the first transistor 31A. Furthermore, by turning on the fifth transistor 35A at the timing when the induced voltage PV occurs, even if the current Is1 flows as described above, it is possible to prevent the voltage at the gate terminal 31g from increasing, thereby preventing the induced voltage PV from occurring in the gate voltage VG1A of the first transistor 31A.

[0075] Furthermore, if the first transistor 31A were a normally-off transistor, the occurrence of undershoot US and induced voltage PV could be suppressed in the same manner as described above, even without providing the second capacitor 47. However, if the first transistor 31A were a normally-on transistor as in the first embodiment, the absence of the second capacitor 47 would cause a short circuit between the gate terminal 31g and the source terminal 31s of the first transistor 31A via the fifth transistor 35A, causing the normally-on first transistor 31A to enter an ON state. Therefore, in a transistor circuit 30A configured by connecting a normally-on first transistor 31A and a normally-off second transistor 32A in series, simply providing the fifth transistor 35A is not enough to suppress the occurrence of undershoot US and induced voltage PV. In contrast, in the first embodiment, a second capacitor 47 connected in series to the fifth transistor 35A is provided between the fifth transistor 35A and the power supply voltage line 48, thereby preventing the gate terminal 31g and source terminal 31s of the first transistor 31A from being short-circuited via the fifth transistor 35A. This makes it possible to use the fifth transistor 35A to prevent the undershoot US and the induced voltage PV from occurring in the transistor circuit 30A configured by connecting a normally-on first transistor 31A and a normally-off second transistor 32A in series.

[0076] Furthermore, if the fifth transistor 35A is disposed between the fifth transistor 35A and the power supply voltage wiring 48 without providing the second capacitor 47, the source terminal 35s of the fifth transistor 35A is connected to the power supply voltage wiring 48. Therefore, to turn the fifth transistor 35A on, a voltage higher than the power supply voltage VDD must be applied to the gate terminal 35g. Furthermore, because the voltage of the source terminal 35s becomes the power supply voltage VDD, there is a problem that, when the fifth transistor 35A is turned on, current flows back through the fifth transistor 35A, causing the voltage of the gate terminal 31g of the first transistor 31A to rise. In contrast, according to the first embodiment, by providing the second capacitor 47, the voltage of the source terminal 35s of the fifth transistor 35A can be made lower than the power supply voltage VDD, thereby preventing the above-described problem from occurring.

[0077] According to the first embodiment, the capacitance of the second capacitor 47 is 10 times or more the input capacitance Ciss of the first transistor 31A. Therefore, when the above-described current Is1 flows and the voltage of the gate terminal 31g is about to rise, charge can be efficiently released from the gate terminal 31g of the first transistor 31A to the second capacitor 47. Furthermore, when the above-described current Is2 flows and the voltage of the gate terminal 31g is about to fall, charge can be efficiently released from the second capacitor 47 to the gate terminal 31g. As a result, when the currents Is1 and Is2 flow, fluctuations in the gate voltage VG1A of the first transistor 31A can be efficiently suppressed, and the occurrence of undershoot US and induced voltage PV in the gate voltage VG1A can be suppressed. This effect is significantly more pronounced when the capacitance of the second capacitor 47 is 10 times or more the input capacitance Ciss of the first transistor 31A than when the capacitance of the second capacitor 47 is less than 10 times the input capacitance Ciss of the first transistor 31A. The value of 10 times was confirmed through simulation. By setting the capacitance of the second capacitor 47 to about 100 times the input capacitance Ciss of the first transistor 31A, it is possible to more effectively suppress the occurrence of undershoot US and induced voltage PV in the gate voltage VG1A of the first transistor 31A.

[0078] According to the first embodiment, the output capacitance Coss of the fifth transistor 35A (clamp transistor) is less than one-tenth the input capacitance Ciss of the first transistor 31A. Therefore, the capacitance of the fifth transistor 35A in the OFF state can be suitably reduced, and the total capacitance of the fifth transistor 35A and the second capacitor 47 connected in series can be suitably reduced. This allows the amount of charge required to charge the fifth transistor 35A and the second capacitor 47 connected in series when the first transistor 31A is turned ON to be sufficiently smaller than the amount of charge required to charge the gate terminal 31g to turn the first transistor 31A ON. This prevents the first transistor 31A from taking too long to turn ON. Similarly, it also prevents the first transistor 31A from taking too long to turn OFF. Therefore, even if the fifth transistor 35A and the second capacitor 47 are provided, the switching speed does not slow down. This effect is significantly more effective when the output capacitance Coss of the fifth transistor 35A is equal to or less than one-tenth of the input capacitance Ciss of the first transistor 31A than when the output capacitance Coss of the fifth transistor 35A is greater than one-tenth of the input capacitance Ciss of the first transistor 31A. The value one-tenth of the value was confirmed by simulation.

[0079] According to the first embodiment, the wiring connected between the first transistor 31A and the second transistor 32A is the power supply voltage wiring 48 to which the power supply voltage VDD is applied. Therefore, the power supply voltage VDD can be applied to the source terminal 31s of the first transistor 31A. This allows changes in the gate voltage VG1A of the first transistor 31A to be detected by detecting changes in the power supply voltage VDD. Therefore, by detecting changes in the power supply voltage VDD, changes in the ON / OFF state of the first transistor 31A can be detected, making it easier to appropriately switch the state of the second transistor 32A in response to changes in the state of the first transistor 31A. Specifically, as described above, when the power supply voltage VDD rises, the second transistor 32A can be switched to the ON state after the first transistor 31A turns OFF. Furthermore, when the power supply voltage VDD drops, the second transistor 32A can be switched to the OFF state before the first transistor 31A turns ON.

[0080] According to the first embodiment, the drive circuit 40A includes a third transistor 33A disposed between the power supply voltage line 48 and the gate terminal 31g (drive terminal) of the first transistor 31A, a fourth transistor 34A disposed between the first ground 91 and the gate terminal 31g of the first transistor 31A, and a control circuit 50A that switches the second transistor 32A, the third transistor 33A, the fourth transistor 34A, and the fifth transistor 35A (clamp transistor) between an ON state and an OFF state. Therefore, the control circuit 50A can switch the state of the transistor circuit 30A by switching the states of the second transistor 32A, the third transistor 33A, and the fourth transistor 34A. Furthermore, by switching the state of the fifth transistor 35A to the ON state using the control circuit 50A, the occurrence of undershoot US and induced voltage PV can be suppressed as described above. Furthermore, when the undershoot US and the induced voltage PV do not occur, the control circuit 50A switches the fifth transistor 35A to the OFF state, thereby reducing the parasitic capacitance of the fifth transistor 35A. This reduces the total capacitance of the fifth transistor 35A and the second capacitor 47, which are connected in series. Therefore, even if the second capacitor 47 is provided, it is possible to prevent the time required for the gate terminal 31g of the first transistor 31A to be charged from increasing.

[0081] According to the first embodiment, the source terminal 35s (output terminal) of the fifth transistor 35A (clamp transistor) is connected to a second ground 92 that is provided separately from the first ground 91. Therefore, when a voltage is applied between the drain terminal D and the source terminal S of the high-side transistor circuit 30A before the semiconductor device 100 is powered on, even if a current that has flowed through the first transistor 31A flows from the source terminal 31s to the first ground 91 through the first capacitor 44, the current can be prevented from flowing from the first ground 91 to the second ground 92. This prevents the current from flowing from the second ground 92 through the body diode of the fifth transistor 35A, and allows the current to flow from the first ground 91 through the body diode of the fourth transistor 34A, the resistor element 43, and the first diode 45 in this order. Therefore, the magnitude of the current can be reduced by the resistor element 43, thereby preventing an inrush current from occurring. Furthermore, when the first ground 91 and the second ground 92 are connected by an element with a relatively high impedance, the magnitude of the current can be reduced by the current flowing from the first ground 91 to the second ground 92. This makes it possible to suppress the occurrence of an inrush current.

[0082] According to the first embodiment, the control circuit unit 50A has a voltage comparison circuit unit 52A that switches the state of the second transistor 32A based on the comparison result between the power supply voltage VDD and the absolute value Vth of the threshold voltage of the first transistor 31A. The fifth transistor 35A (clamp transistor) and the voltage comparison circuit unit 52A are mounted on the same semiconductor chip 20A. Therefore, compared to when the fifth transistor 35A and the voltage comparison circuit unit 52A are mounted on separate semiconductor chips, the wiring length of the circuit portion including the fifth transistor 35A and the voltage comparison circuit unit 52A can be shortened, and the impedance of the circuit portion can be reduced.

[0083] According to the first embodiment, the fifth transistor 35A (clamp transistor), the third transistor 33A, the fourth transistor 34A, and the control circuit unit 50A are mounted on the same semiconductor chip 20A. Therefore, compared to when the fifth transistor 35A (clamp transistor), the third transistor 33A, the fourth transistor 34A, and the control circuit unit 50A are mounted on separate semiconductor chips, the wiring length of the circuit portion including these parts can be shortened, and the impedance of the circuit portion can be more suitably reduced.

[0084] According to the first embodiment, the semiconductor device 100 includes two drive circuits 40A and 40B and two transistor circuits 30A and 30B that are normally-off driven by the drive circuits 40A and 40B. The two drive circuits 40A and 40B drive the two transistor circuits 30A and 30B, respectively. The two transistor circuits 30A and 30B are connected in series to form a half-bridge circuit 30H. A control circuit 50A of one drive circuit 40A switches a fifth transistor 35A (clamp transistor) in one drive circuit 40A between an ON state and an OFF state based on the state of the other drive circuit 40B. Therefore, when the other drive circuit 40B turns the transistor circuit 30B on and when the other drive circuit 40B turns the transistor circuit 30B off, the fifth transistor 35A can be turned on by one drive circuit 40A. This makes it possible to suppress changes in the gate voltage VG1A of the first transistor 31A, and to suppress the occurrence of undershoot US and induced voltage PV in the gate voltage VG1A of the first transistor 31A.

[0085] According to the first embodiment, the control circuit 50A of one drive circuit 40A keeps the fifth transistor 35A (clamp transistor) of one drive circuit 40A in the ON state for at least the first predetermined time ta from the time when the first transistor 31B in the other drive circuit 40B is switched from the OFF state to the ON state. Therefore, by appropriately setting the first predetermined time ta, the fifth transistor 35A can be turned ON at the timing when the induced voltage PV occurs after the first transistor 31B is turned ON. This further suppresses the generation of the induced voltage PV in the gate voltage VG1A of the first transistor 31A.

[0086] According to the first embodiment, the control circuit 50A of one drive circuit 40A keeps the fifth transistor 35A (clamp transistor) of the one drive circuit 40A in the ON state for at least the second predetermined time tb after the first transistor 31A of the other drive circuit 40A is switched from the ON state to the OFF state. Therefore, by appropriately setting the second predetermined time tb, the fifth transistor 35A can be turned ON at the timing when an undershoot US occurs after the first transistor 31B is switched OFF. This further reduces the occurrence of an undershoot US in the gate voltage VG1A of the first transistor 31A. Furthermore, after the first transistor 31A of the other drive circuit 40B is switched from the ON state to the OFF state, the control circuit 50A of the one drive circuit 40A turns the fifth transistor 35A OFF before control to turn the first transistor 31A of the one drive circuit 40A ON is initiated. Therefore, when the drive circuit 40A attempts to turn on the first transistor 31A by turning on the third transistor 33A based on the pulse signal PSA, the fifth transistor 35A is in the OFF state. This makes it possible to reduce the total capacitance of the fifth transistor 35A and the second capacitor 47, which are connected in series, when attempting to turn on the first transistor 31A, thereby preventing the first transistor 31A from taking a long time to turn on.

[0087] According to the first embodiment, the control circuit 50A of one drive circuit 40A turns the fifth transistor 35A (clamp transistor) to the OFF state when the second predetermined time tb has elapsed since the first transistor 31A in the other drive circuit 40B was switched from the ON state to the OFF state. Therefore, by appropriately setting the second predetermined time tb, the fifth transistor 35A can be turned to the OFF state after the timing at which the undershoot US occurs has passed and before control to turn the first transistor 31A to the ON state is started.

[0088] According to the first embodiment, the semiconductor device 100 includes a half-bridge circuit 30H configured by two transistor circuits 30A and 30B connected in series. Therefore, regardless of whether an operator configuring a circuit using the semiconductor device 100 uses the transistor circuit 30A or the transistor circuit 30B as the high-side transistor circuit, the occurrence of undershoot US and induced voltage PV in the gate voltage VG1A of the first transistor 31A can be suppressed as described above. Also, even in a circuit in which the transistor circuit 30A and the transistor circuit 30B are switched between the high side and the low side, the occurrence of undershoot US and induced voltage PV in the gate voltage VG1A of the first transistor 31A can be suppressed as described above regardless of whether the transistor circuit 30A or the transistor circuit 30B is the high-side transistor circuit.

[0089] In the present disclosure, "the control circuit unit 50A keeps a certain fifth transistor 35A in an ON state from a certain point in time to another point in time" means that the control circuit unit 50A keeps the fifth transistor 35A in an ON state from a certain point in time to another point in time, and the state of the fifth transistor 35A before the certain point in time and after the other point in time is not particularly limited.

[0090] (Second embodiment) The second embodiment differs from the first embodiment in the control procedure in the control circuit unit 50A. In the following description, the same components as those in the above-described embodiments may be denoted by the same reference numerals as appropriate and the description thereof may be omitted.

[0091] FIG. 8 is a timing chart showing an example of the relationship between the power supply voltage VDD and the gate voltage of each transistor when the transistor circuits 30A and 30B of the second embodiment are switched between the ON state and the OFF state. As shown in FIG. 8, in the second embodiment, the control circuit 50A of the high-side drive circuit 40A turns on the fifth transistor 35A at time t5 when the low-side third transistor 33B is turned on, and maintains the fifth transistor 35A in the ON state while the third transistor 33B is on. The control circuit 50A turns off the fifth transistor 35A when a fourth predetermined time td has elapsed since the third transistor 33B was turned off. As in the first embodiment, the control circuit 50A turns off the fifth transistor 35A when a second predetermined time tb has elapsed since the first transistor 31B was turned off after the third transistor 33B was turned off. Other control procedures of the control circuit section 50A in the second embodiment are similar to other control procedures of the control circuit section 50A in the first embodiment.

[0092] According to the second embodiment, the control circuit 50A of one drive circuit 40A keeps the fifth transistor 35A (clamp transistor) of one drive circuit 40A in the ON state from the time when the first transistor 31B in the other drive circuit 40B is switched from the OFF state to the ON state until the second predetermined time tb has elapsed since the first transistor 31B was switched back to the OFF state. Therefore, even if a factor that causes an unintended voltage fluctuation occurs at the gate terminal 31g of the high-side first transistor 31A while the low-side first transistor 31B is in the ON state, the fifth transistor 35A can suppress fluctuations in the voltage at the gate terminal 31g. This can more effectively suppress fluctuations in the gate voltage VG1A of the first transistor 31A.

[0093] (Third embodiment) The third embodiment differs from the first embodiment in that the second transistor 332A is an N-channel transistor. In the following description, the same components as those in the above-described embodiments may be denoted by the same reference numerals as appropriate and the description thereof may be omitted.

[0094] 9 is a circuit diagram showing a portion of a semiconductor device 300 according to the third embodiment. As shown in FIG. 9, in a drive circuit 340A according to the third embodiment, a second transistor 332A of a transistor circuit 330A is an N-channel field-effect transistor. A drain terminal 332d of the second transistor 332A is connected to a source terminal 31s of the first transistor 31A. A source terminal 332s of the second transistor 332A is connected to a wiring portion 71. A cathode of a first diode 45 is connected to the source terminal 332s of the second transistor 332A. In the third embodiment, the source terminal 332s of the second transistor 332A is the source terminal S of the transistor circuit 330A.

[0095] The drive circuit 340A has a level shifter circuit section 390. The level shifter circuit section 390 is connected to the gate terminal 332g and the source terminal 332s of the second transistor 332A. A second power supply voltage VDD2 is applied to the level shifter circuit section 390. The second power supply voltage VDD2 is a voltage higher than the power supply voltage VDD. In the third embodiment, a voltage comparison circuit section 352A of the control circuit section 350A outputs a comparison result of the power supply voltage VDD to the switching circuit section 51A and the level shifter circuit section 390.

[0096] When the level shifter circuit unit 390 receives a signal from the voltage comparison circuit unit 352A indicating that the power supply voltage VDD has exceeded the absolute value Vth of the threshold voltage of the first transistor 31A, the level shifter circuit unit 390 applies the second power supply voltage VDD2 to the gate terminal 332g of the second transistor 332A. This switches the second transistor 332A to an ON state. In the third embodiment, when the level shifter circuit unit 390 receives a signal from the voltage comparison circuit unit 352A indicating that the power supply voltage VDD has reached or exceeded a value Vh that is higher than the absolute value Vth of the threshold voltage of the first transistor 31A, the level shifter circuit unit 390 applies the second power supply voltage VDD2 to the gate terminal 332g of the second transistor 332A, switching the second transistor 332A to an ON state. When the power supply voltage VDD is lower than the value Vh, the level shifter circuit unit 390 short-circuits the gate terminal 332g and source terminal 332s of the second transistor 332A, for example, to switch the second transistor 332A to an OFF state.

[0097] During the switching operation of the semiconductor device 300, the timing at which the state of the second transistor 332A is switched is the same as the timing at which the state of the second transistor 32A is switched in the first embodiment. In the third embodiment, as in the first embodiment, the fifth transistor 35A is driven, thereby making it possible to suppress the occurrence of an undershoot US and an induced voltage PV in the gate voltage VG1A of the first transistor 31A.

[0098] Other configurations of the drive circuit 340A are similar to other configurations of the drive circuit 40A in Embodiment 1. Other configurations of the semiconductor device 300 are similar to other configurations of the semiconductor device 100 in Embodiment 1.

[0099] (Fourth embodiment) The fourth embodiment is different from the first embodiment in the configuration of the chip that constitutes the semiconductor device 400. In the following description, the same configurations as those in the above-described embodiments may be appropriately denoted by the same reference numerals and description thereof may be omitted.

[0100] Figure 10 is a circuit diagram showing a portion of a semiconductor device 400 according to the fourth embodiment. The circuit configuration of the semiconductor device 400 shown in Figure 10 is similar to that of the semiconductor device 100 according to the first embodiment, although the representation in the figure is different. Parts of the circuit configuration of the semiconductor device 400 are omitted as appropriate in Figure 10. The multiple portions enclosed by dashed double-dashed lines in Figure 10 are each mounted on separate chips.

[0101] 10 , in the fourth embodiment, the first transistor 31A, the second transistor 32A, the fifth transistor 35A, and the second capacitor 47 are mounted on different chips. The voltage comparison circuit unit 52A and the first diode 45 are mounted on the same chip. The chip on which the voltage comparison circuit unit 52A and the first diode 45 are mounted is different from the chip on which the first transistor 31A, the second transistor 32A, the fifth transistor 35A, and the second capacitor 47 are mounted. The other configurations of the semiconductor device 400 are similar to the other configurations of the semiconductor device 100 in the first embodiment.

[0102] (Fifth embodiment) The fifth embodiment differs from the first embodiment in the configuration of the chips that make up the semiconductor device 500. In the following description, the same configurations as those in the above-described embodiments may be appropriately denoted by the same reference numerals and description thereof may be omitted.

[0103] Fig. 11 is a circuit diagram showing a portion of a semiconductor device 500 according to the fifth embodiment. The circuit configuration of the semiconductor device 500 shown in Fig. 11 is similar to that of the semiconductor device 100 according to the first embodiment, although the representation in the figure is different. Parts of the circuit configuration of the semiconductor device 500 are omitted as appropriate in Fig. 11. The multiple portions enclosed by dashed-dotted lines in Fig. 11 are each mounted on separate chips.

[0104] 11, in the fifth embodiment, the fifth transistor 35A and the first transistor 31A are mounted on the same semiconductor chip 500a. Therefore, compared to when the fifth transistor 35A and the first transistor 31A are mounted on separate semiconductor chips, the wiring length of the circuit portion including the fifth transistor 35A and the first transistor 31A can be shortened, and the impedance of the circuit portion can be reduced.

[0105] The second transistor 32A, the second capacitor 47, the voltage comparison circuit unit 52A, and the first diode 45 are the same as those in the fourth embodiment. The other configurations of the semiconductor device 500 are the same as those of the semiconductor device 100 in the first embodiment.

[0106] (Sixth embodiment) The sixth embodiment is different from the first embodiment in the configuration of the chip that constitutes the semiconductor device 600. In the following description, the same configurations as those in the above-described embodiments may be appropriately denoted by the same reference numerals and description thereof may be omitted.

[0107] Fig. 12 is a circuit diagram showing a portion of a semiconductor device 600 according to the sixth embodiment. The circuit configuration of the semiconductor device 600 shown in Fig. 12 is similar to that of the semiconductor device 100 according to the first embodiment, although the representation in the figure is different. Parts of the circuit configuration of the semiconductor device 600 are omitted as appropriate in Fig. 12. The multiple portions enclosed by dashed double-dashed lines in Fig. 12 are mounted on separate chips.

[0108] 12, in the sixth embodiment, the fifth transistor 35A, the voltage comparison circuit unit 52A, and the first diode 45 are mounted on the same semiconductor chip 600a. Therefore, compared to when the fifth transistor 35A, the voltage comparison circuit unit 52A, and the first diode 45 are mounted on separate semiconductor chips, the wiring length of the circuit portion including the fifth transistor 35A, the voltage comparison circuit unit 52A, and the first diode 45 can be shortened, thereby reducing the impedance of the circuit portion. For example, the third transistor 33A, the fourth transistor 34A, and the switching circuit unit 51A are not mounted on the semiconductor chip 600a. The third transistor 33A, the fourth transistor 34A, and the switching circuit unit 51A are mounted on a semiconductor chip other than the semiconductor chip 600a.

[0109] The first transistor 31A, the second transistor 32A, and the second capacitor 47 are the same as those in the fourth embodiment. The other configurations of the semiconductor device 600 are the same as those of the semiconductor device 100 in the first embodiment.

[0110] (Seventh embodiment) The seventh embodiment is an embodiment of a boost converter equipped with a semiconductor device 700. In the following description, the same components as those in the above-described embodiments may be denoted by the same reference numerals as appropriate, and the description thereof may be omitted.

[0111] 13 is a circuit diagram showing a boost converter 1000 of the seventh embodiment. The boost converter 1000 includes a semiconductor device 700, a coil 1100, a third capacitor 1200, and a resistive element 1300. The structure of the semiconductor device 700 is similar to the structure of the semiconductor device 100 of the first embodiment. The semiconductor device 700 has two semiconductor packages 10A and 10B.

[0112] The semiconductor package 10A and the semiconductor package 10B are connected in series to each other. One end of a coil 1100 is connected between the semiconductor package 10A and the semiconductor package 10B. One end of the coil 1100 is connected to a source terminal S of the semiconductor package 10A and a drain terminal D of the semiconductor package 10B. The other end of the coil 1100 is connected in series to a power supply Vin. The positive terminal of the power supply Vin is connected to the coil 1100. The negative terminal of the power supply Vin is connected to the source terminal S of the semiconductor package 10B.

[0113] One electrode of the third capacitor 1200 is connected to the drain terminal D of the semiconductor package 10A. The other electrode of the third capacitor 1200 is connected to the source terminal S of the semiconductor package 10B. The resistive element 1300 is connected in parallel with the third capacitor 1200. One end of the resistive element 1300 is connected to the drain terminal D of the semiconductor package 10A. The other end of the resistive element 1300 is connected to the source terminal S of the semiconductor package 10B.

[0114] In a circuit configured like the boost converter 1000 of the seventh embodiment, when the state of the transistor circuit 30B in the low-side semiconductor package 10B is switched, an undershoot US and an induced voltage PV may occur in the gate voltage VG1A of the first transistor 31A of the transistor circuit 30A in the high-side semiconductor package 10A. In response to this, as in the first embodiment, by operating the fifth transistor 35A in the high-side semiconductor package 10A, it is possible to suppress the occurrence of the undershoot US and the induced voltage PV in the gate voltage VG1A of the first transistor 31A.

[0115] (Eighth embodiment) The eighth embodiment is an embodiment of a step-down converter equipped with a semiconductor device 800. In the following description, the same components as those in the above-described embodiments may be appropriately denoted by the same reference numerals and description thereof may be omitted.

[0116] 14 is a circuit diagram showing a step-down converter 2000 according to the eighth embodiment. The step-down converter 2000 includes a semiconductor device 800, a coil 2100, a fourth capacitor 2200, and a resistive element 2300. The structure of the semiconductor device 800 is similar to the structure of the semiconductor device 100 according to the first embodiment. The semiconductor device 800 includes two semiconductor packages 10A and 10B.

[0117] The semiconductor package 10A and the semiconductor package 10B are connected in series to each other. One end of the coil 2100 is connected between the semiconductor package 10A and the semiconductor package 10B. One end of the coil 2100 is connected to the source terminal S of the semiconductor package 10A and the drain terminal D of the semiconductor package 10B. The other end of the coil 2100 is connected to one electrode of the fourth capacitor 2200 and one end of the resistor element 2300. The fourth capacitor 2200 and the resistor element 2300 are connected in parallel to each other. The other electrode of the fourth capacitor 2200 and the other end of the resistor element 2300 are connected to the source terminal S of the semiconductor package 10B. The drain terminal D of the semiconductor package 10A is connected to the positive electrode of the power supply Vin. The source terminal S of the semiconductor package 10B is connected to the negative electrode of the power supply Vin.

[0118] In a circuit configured like the step-down converter 2000 of the eighth embodiment, when the state of the transistor circuit 30A in the high-side semiconductor package 10A is switched, an undershoot US and an induced voltage PV may occur in the gate voltage VG1B of the first transistor 31B of the transistor circuit 30B in the low-side semiconductor package 10B. By operating the fifth transistor 35B in the low-side semiconductor package 10B in the same manner as the high-side fifth transistor 35A in the first embodiment, it is possible to prevent the undershoot US and the induced voltage PV from occurring in the gate voltage VG1B of the first transistor 31B.

[0119] According to at least one of the above-described embodiments, the drive circuit is a drive circuit that normally-off drives a transistor circuit configured by connecting a normally-on first transistor and a normally-off second transistor in series. The drive circuit includes a clamp transistor that functions as a clamp element and is arranged between a wiring connected between the first transistor and the second transistor and a drive terminal of the first transistor, and a capacitor that is arranged between the clamp transistor and the wiring and is connected in series with the clamp transistor. This makes it possible to suppress undershoot in the drive voltage of the first transistor.

[0120] The first transistor may be any transistor as long as it is a normally-on type transistor. The second transistor may be any transistor as long as it is a normally-off type transistor. The third transistor may be any transistor that is arranged between the power supply voltage wiring and the drive terminal of the first transistor and that can be switched on / off by the control circuit unit. The fourth transistor may be any transistor that is arranged between the first ground and the drive terminal of the first transistor and that can be switched on / off by the control circuit unit. The clamp transistor (fifth transistor) may be any transistor that is arranged between the wiring connected between the first transistor and the second transistor and the drive terminal of the first transistor and that can function as a clamp element.

[0121] The wiring connected between the first transistor and the second transistor may be wiring other than the power supply voltage wiring. The control circuit unit may be configured in any manner. The control circuit unit may be configured to switch the voltages applied to the second transistor, the third transistor, the fourth transistor, and the fifth transistor by a switching element such as a transistor, or may be configured to include a microprocessor or the like. The elements included in the semiconductor chip provided in the drive circuit are not particularly limited. The elements included in the semiconductor package provided in the semiconductor device are not particularly limited. The semiconductor device may be configured from only one semiconductor package.

[0122] The drive circuit and semiconductor device of the embodiments may be applied to any circuit. For example, the drive circuit and semiconductor device of the embodiments may be applied to a full-bridge circuit. In this case, undershoot US and induced voltage PV may occur in both the gate voltage of the high-side first transistor and the gate voltage of the low-side first transistor. In this case, by driving the high-side clamp transistor and the low-side clamp transistor as in the above-described embodiment, the occurrence of undershoot US and induced voltage PV can be suppressed in both the gate voltage of the high-side first transistor and the gate voltage of the low-side first transistor.

[0123] The driving circuit and the semiconductor device according to the embodiment include the following additional aspects. (Appendix 1) A drive circuit for normally-off driving a transistor circuit configured by connecting a normally-on first transistor and a normally-off second transistor in series, a clamp transistor that is disposed between a wiring connected between the first transistor and the second transistor and a drive terminal of the first transistor and functions as a clamp element; a capacitor disposed between the clamp transistor and the wiring and connected in series with the clamp transistor; A drive circuit comprising: (Appendix 2) 2. The driving circuit of claim 1, wherein the capacitance of the capacitor is 10 times or more the input capacitance of the first transistor. (Appendix 3) 3. The drive circuit of claim 1, wherein the output capacitance of the clamp transistor is equal to or less than one-tenth of the input capacitance of the first transistor. (Appendix 4) 4. The drive circuit according to claim 1, wherein the wiring is a power supply voltage wiring to which a power supply voltage is applied. (Appendix 5) a third transistor disposed between the power supply voltage wiring and a drive terminal of the first transistor; a fourth transistor disposed between a first ground and the drive terminal of the first transistor; a control circuit unit that switches each of the second transistor, the third transistor, the fourth transistor, and the clamp transistor between an ON state and an OFF state; 5. The drive circuit of claim 4, comprising: (Appendix 6) 6. The drive circuit according to claim 5, wherein the output terminal of the clamp transistor is connected to a second ground provided separately from the first ground. (Appendix 7) the control circuit unit has a voltage comparison circuit unit that switches the state of the second transistor based on a comparison result between the power supply voltage and an absolute value of a threshold voltage of the first transistor, 7. The drive circuit according to claim 5, wherein the clamp transistor and the voltage comparison circuit unit are mounted on the same semiconductor chip. (Appendix 8) 8. The drive circuit according to claim 7, wherein the clamp transistor, the third transistor, the fourth transistor, and the control circuit unit are mounted on a single semiconductor chip. (Appendix 9) A drive circuit according to any one of Supplementary Note 5 to Supplementary Note 8; the transistor circuit being driven in a normally-off state by the drive circuit; Two of each are provided. the two drive circuits respectively drive the two transistor circuits; the two transistor circuits are connected in series to each other to form a half-bridge circuit; The control circuit of one of the drive circuits switches the clamp transistor in one of the drive circuits between an ON state and an OFF state based on the state of the other of the drive circuits. (Appendix 10) 10. The semiconductor device according to claim 9, wherein the control circuit unit of one of the drive circuits keeps the clamp transistor in one of the drive circuits in an ON state for at least a first predetermined time from the time the first transistor in the other of the drive circuits is switched from an OFF state to an ON state. (Appendix 11) The control circuit unit of one of the drive circuits includes: the clamp transistor in one of the drive circuits is kept in an ON state until at least a second predetermined time has elapsed since the first transistor in the other of the drive circuits is switched from an ON state to an OFF state; 11. The semiconductor device according to claim 9, wherein after the first transistor in the other of the drive circuits is switched from an ON state to an OFF state, the clamp transistor is turned OFF before control to turn the first transistor in one of the drive circuits ON is started. (Appendix 12) 12. The semiconductor device according to claim 11, wherein the control circuit unit of one of the drive circuits turns the clamp transistor to an OFF state when the second predetermined time has elapsed since the first transistor in the other drive circuit was switched from an ON state to an OFF state. (Appendix 13) 13. The semiconductor device according to claim 11, wherein the control circuit unit of one of the drive circuits keeps the clamp transistor in one of the drive circuits in an ON state from the time when the first transistor in the other of the drive circuits is switched from an OFF state to an ON state until the first transistor is switched back to an OFF state and the second predetermined time has elapsed. (Appendix 14) A drive circuit according to any one of Supplementary Note 1 to Supplementary Note 8; the transistor circuit being driven in a normally-off state by the drive circuit; A semiconductor device comprising: (Appendix 15) 15. The semiconductor device according to claim 9, wherein the clamp transistor and the first transistor are mounted on a same semiconductor chip.

[0124] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0125] 20A, 20B, 500a, 600a... semiconductor chips, 30A, 30B, 330A... transistor circuits, 30H... half-bridge circuits, 31A, 31B... first transistors, 32A, 32B, 332A... second transistors, 33A, 33B... third transistors, 34A, 34B... fourth transistors, 35A... fifth transistor (clamp transistor), 40A, 40B, 340A... drive circuits, 47... second capacitor (capacitor), 48... power supply voltage wiring, 50A, 50B, 350A... control circuit sections, 52A, 52B, 352A... voltage comparison circuit sections, 91... first ground, 92... second ground, 100, 300, 400, 500, 600, 700, 800... semiconductor devices, Ciss... input capacitance, Coss... output capacitance, ta... first predetermined time, tb... second predetermined time, VDD, VDDA, VDDB... power supply voltages, Vth... absolute value of threshold voltage

Claims

1. A drive circuit for normally-off driving a transistor circuit configured by serially connecting a normally-on first transistor and a normally-off second transistor, a clamp transistor that is disposed between a wiring connected between the first transistor and the second transistor and a drive terminal of the first transistor and functions as a clamp element; a capacitor disposed between the clamp transistor and the wiring and connected in series with the clamp transistor; A drive circuit comprising:

2. 2. The drive circuit according to claim 1, wherein the capacitance of the capacitor is 10 times or more the input capacitance of the first transistor.

3. 2. The drive circuit according to claim 1, wherein the output capacitance of said clamp transistor is equal to or less than one-tenth of the input capacitance of said first transistor.

4. 2. The drive circuit according to claim 1, wherein the wiring is a power supply voltage wiring to which a power supply voltage is applied.

5. a third transistor disposed between the power supply voltage wiring and a drive terminal of the first transistor; a fourth transistor disposed between a first ground and the drive terminal of the first transistor; a control circuit unit that switches each of the second transistor, the third transistor, the fourth transistor, and the clamp transistor between an ON state and an OFF state; The drive circuit of claim 4 , comprising:

6. 6. The drive circuit according to claim 5, wherein the output terminal of the clamp transistor is connected to a second ground provided separately from the first ground.

7. the control circuit unit has a voltage comparison circuit unit that switches the state of the second transistor based on a comparison result between the power supply voltage and an absolute value of a threshold voltage of the first transistor, 6. The drive circuit according to claim 5, wherein the clamp transistor and the voltage comparison circuit section are mounted on the same semiconductor chip.

8. 8. The drive circuit according to claim 7, wherein the clamp transistor, the third transistor, the fourth transistor, and the control circuit unit are mounted on a single semiconductor chip.

9. A drive circuit according to any one of claims 5 to 8; the transistor circuit being driven in a normally-off state by the drive circuit; Two of each are provided. the two drive circuits respectively drive the two transistor circuits; the two transistor circuits are connected in series to each other to form a half-bridge circuit; The semiconductor device, wherein the control circuit of one of the drive circuits switches the clamp transistor in one of the drive circuits between an ON state and an OFF state based on the state of the other of the drive circuits.

10. 10. The semiconductor device according to claim 9, wherein the control circuit of one of the drive circuits keeps the clamp transistor in one of the drive circuits in an ON state for at least a first predetermined time from the time when the first transistor in the other of the drive circuits is switched from an OFF state to an ON state.

11. The control circuit unit of one of the drive circuits includes: the clamp transistor in one of the drive circuits is kept in an ON state until at least a second predetermined time has elapsed since the first transistor in the other of the drive circuits is switched from an ON state to an OFF state; 10. The semiconductor device according to claim 9, wherein after the first transistor in the other of the drive circuits is switched from an ON state to an OFF state, the clamp transistor is turned OFF before control for turning the first transistor in one of the drive circuits ON is started.

12. 12. The semiconductor device according to claim 11, wherein the control circuit of one of the drive circuits turns the clamp transistor to the OFF state when the second predetermined time has elapsed since the first transistor in the other drive circuit was switched from the ON state to the OFF state.

13. 12. The semiconductor device according to claim 11, wherein the control circuit unit of one of the drive circuits keeps the clamp transistor in one of the drive circuits in an ON state from the time when the first transistor in the other of the drive circuits is switched from an OFF state to an ON state until the first transistor is switched back to an OFF state and the second predetermined time has elapsed.

14. A drive circuit according to any one of claims 1 to 8; the transistor circuit being driven in a normally-off state by the drive circuit; A semiconductor device comprising:

15. 10. The semiconductor device according to claim 9, wherein said clamp transistor and said first transistor are mounted on the same semiconductor chip.

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