MANUFACTURING METHOD FOR SiGe SUBSTRATE

Abstract

To provide a manufacturing method for a SiGe substrate for forming a SiGe layer on a Si substrate, by which a surface of the SiGe layer is homogenized efficiently and a high-quality SiGe substrate is manufactured.SOLUTION: A manufacturing method for a SiGe substrate includes the steps of: epitaxially growing a SiGe layer on a main front surface of a Si substrate; polishing the main front surface and a main back surface of the Si substrate having the SiGe layer while having the surfaces held by a pad; and cleaning the Si substrate including the SiGe layer after the polishing.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a SiGe substrate. [Background technology]

[0002] SiGe is a material that is widely used in various devices, including electronic, optical, and RF devices. Recently, instead of the fin structure currently used in logic ICs, GAA (Gate All Around) and CFET (Complementary Field Effect Transistor), which stacks NMOS and CMOS, have been proposed for next-generation semiconductors, and SiGe plays an important role in the manufacturing process of these devices (Non-Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-109901 [Patent Document 2] Japanese Patent Application Laid-Open No. 2003-158102 [Non-patent literature]

[0004] [Non-Patent Document 1] The 1st Workshop of the Industry-Academia Collaboration Committee on Crystal Growth, Processing, and Evaluation of Semiconductors of the Japan Society of Applied Physics: "Crystal Technology Supporting the Revival of Semiconductors" [Non-patent document 2] Yonenaga, "Growth of high-quality SiGe crystals and elucidation of their fundamental properties," Material, 47(1), 3(2008) [Non-patent document 3] Sato, "Fundamentals and Challenges of Heteroepitaxy: 1st Workshop on 3C-SiC Technology for IoT in Harsh Environments" (2019) [Non-patent document 4] Wong, LH “Strain relaxation in SiGe / Si heteroepitaxy.” Doctoral thesis, Nanyang Technological University, Singapore, (2007). [Non-Patent Document 5] EAFitgerald, et.al., “Totally relaxed GexSi1-x layers with low threading dislocation densities grows on Si substrares”, App. Phys. Lett., 59, 811 (1991). [Non-patent document 6] FKLeGeues, et.al., “Mechanism and conditions for anomalous strain relaxation in graded thin films and superlattices”, App.Phys.Lett., 71, 4230 (1992). [Non-Patent Document 7] T.Taniguchi,et.al.,Abst.of SAP Spring Meeting.,17a-F102-9(2018). [Non-patent document 8] T.Taniguchi,et.al.,Abst.of JSAP Autumn Meeting.,20p-234-10(2018). Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the equilibrium phase diagram, the liquidus and solidus of SiGe are far apart, and the distribution coefficient is 2 to 5, which is greater than 1, making it known that it is prone to polycrystallization. Even if single crystals can be grown, the growth rate is slow and it is difficult to grow them consistently (Non-Patent Document 2).

[0006] Therefore, for semiconductor devices, SiGe is grown on Si substrates, sometimes referred to as virtual SiGe substrates. In this SiGe growth (heteroepitaxial), the key issue is how to mitigate the difference in lattice constants between Si and Ge. The lattice constant of Si crystals is 0.5431 nm, while that of Ge crystals is 0.56754 nm, resulting in a difference of approximately 4.5%. To mitigate this difference in lattice constants, SiGe uses a SiGe alloy. If the Ge composition ratio is x, the lattice constant of the SiGe alloy is 0.5431 nm + x × 0.02 nm + x squared × 0.0027 nm. For example, if x is 0.3, the lattice constant is 0.5493 ​​nm, resulting in a minimal lattice mismatch of 0.14%. This lattice mismatch can cause dislocations and defects to develop in the subsequently grown epitaxial layer, resulting in degradation of quality. However, it is believed that there is a critical thickness, and even if there is lattice mismatch, defects will not occur unless the critical thickness is exceeded (Non-Patent Document 3).

[0007] Therefore, various intermediate layers have been proposed that utilize this critical thickness to form a buffer layer. For example, there is a method in which the Ge concentration is varied from the silicon substrate to a SiGe layer with a predetermined Ge concentration, which is called a graded buffer layer (Non-Patent Documents 4, 5, 6). Another method has been proposed, which involves stacking multiple layers with thicknesses below the critical thickness, called a superlattice buffer layer (Non-Patent Documents 6, 7, 8).

[0008] In addition to these film formation techniques, proposals have been made to improve the quality of the surface of a SiGe film grown on a silicon substrate. Patent Document 1 describes a method in which a SiGe layer is epitaxially grown on a Si substrate, and after the epitaxial process, the top surface of the SiGe layer is oxidized to form an oxide film, and after the oxide film formation process, the oxide film is removed by polishing or etching, thereby removing crosshatching on the surface of the SiGe layer and improving surface roughness.

[0009] Patent Document 2 describes a method for producing a semiconductor substrate having a SiGe layer with higher flatness by polishing the surface of the SiGe layer of a semiconductor substrate having a SiGe layer formed on a Si substrate with a polishing solution containing colloidal silica having an average particle size of 40 to 50 nm and having a pH of 10.0 to 11.0.

[0010] Various methods have been investigated. The polishing technique disclosed in Patent Document 1 involves oxidizing the surface of the SiGe layer before polishing. The reason for this is that the unevenness caused by crosshatching on the SiGe surface cannot be removed by polishing, so it is considered effective to oxidize the surface to flatten it before polishing. However, this oxidation is considered to be pyrogenic oxidation at temperatures between 800 and 1300°C. It has been found that at such high temperatures, the Ge composition of the graded buffer layer and superlattice buffer layer formed for SiGe growth collapses, making it difficult to obtain a good SiGe layer.

[0011] The present invention has been made to solve the above problems, and aims to provide a method for manufacturing a SiGe substrate by forming a SiGe layer on a Si substrate, which method efficiently homogenizes the surface of the SiGe layer and manufactures a high-quality SiGe substrate. [Means for solving the problem]

[0012] The present invention has been made to achieve the above-mentioned object, and provides a method for manufacturing a SiGe substrate, comprising the steps of: epitaxially growing a SiGe layer on a main surface of a Si substrate; polishing the SiGe layer while sandwiching the main surface and main back surface of the Si substrate provided with the SiGe layer between pads; and cleaning the Si substrate provided with the SiGe layer after polishing.

[0013] According to such a method for manufacturing a SiGe substrate, the surface of the SiGe layer can be efficiently homogenized, and a high-quality SiGe substrate can be manufactured.

[0014] In this case, the pH value of the polishing agent used for the polishing can be set to 10 or less.

[0015] This effectively prevents the high concentration Ge from peeling off from the SiGe layer.

[0016] In this case, the pH value of the polishing agent used for the polishing can be set to 9 to 9.7.

[0017] This makes it possible to more effectively suppress peeling of the high-concentration Ge in the SiGe layer.

[0018] In this case, the pH value of the cleaning solution used for the cleaning can be set to 10 or less.

[0019] This effectively prevents the high concentration Ge from peeling off from the SiGe layer.

[0020] In this case, the pH value of the cleaning solution used for the cleaning can be set to 9 to 9.7.

[0021] This makes it possible to more effectively suppress peeling of the high-concentration Ge in the SiGe layer.

[0022] At this time, the edge portion of the Si substrate having the SiGe layer thereon can be polished.

[0023] This makes it possible to homogenize the edge portion of the SiGe substrate as well.

[0024] At this time, after the polishing of the SiGe layer, the main surface can be further subjected to finish polishing.

[0025] This allows the surface of the SiGe layer to be more uniform. [Effects of the Invention]

[0026] As described above, according to the method for manufacturing a SiGe substrate of the present invention, it is possible to efficiently homogenize the surface of the SiGe layer and manufacture a high-quality SiGe substrate. [Brief explanation of the drawings]

[0027] [Figure 1] 1 shows an example of an embodiment flow of a method for manufacturing a SiGe substrate according to the present invention. [Figure 2] 1 is a schematic diagram of a SiGe substrate obtained by a method for manufacturing a SiGe substrate according to the present invention; [Figure 3] 1A and 1B show observations of the surface of a SiGe layer before and after polishing according to the present invention ((a) before polishing, (b) after polishing). DETAILED DESCRIPTION OF THE INVENTION

[0028] The present invention will be described in detail below, but the present invention is not limited thereto.

[0029] As described above, there has been a demand for a method for manufacturing a SiGe substrate by forming a SiGe layer on a Si substrate, which method can efficiently homogenize the surface of the SiGe layer and manufacture a high-quality SiGe substrate.

[0030] Therefore, in order to solve the above problem, the inventors investigated a method of directly polishing a SiGe layer without oxidizing the deposited SiGe layer. Regarding this polishing, Patent Document 1 states that direct polishing is not possible due to the large unevenness, but the inventors discovered that this problem can be avoided by polishing the substrate while absorbing the waviness of the substrate by sandwiching it between pads on both sides, rather than by using an adhesive to fix the backside of the substrate.

[0031] That is, as a result of intensive research into the above-mentioned problems, the inventors have found that a method for manufacturing a SiGe substrate, comprising the steps of epitaxially growing a SiGe layer on a main surface of a Si substrate, polishing the SiGe layer while sandwiching the main surface and the main back surface of the Si substrate provided with the SiGe layer between pads, and cleaning the Si substrate provided with the SiGe layer after polishing, can efficiently homogenize the surface of the SiGe layer and produce a high-quality SiGe substrate, and have completed the present invention.

[0032] In other words, the method for manufacturing a SiGe substrate of the present invention makes it possible to polish the surface of the SiGe substrate without pretreatment such as oxidation, and to obtain a high-quality virtual SiGe substrate.

[0033] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 2 is a schematic diagram of a SiGe substrate obtained by the SiGe substrate manufacturing method according to the present invention. A SiGe substrate 1 in which a SiGe layer 3 is formed on a silicon single crystal substrate 2 is sometimes called a virtual SiGe substrate. The composition of the SiGe layer 3 is not particularly limited, but the Ge content can be 10 to 35 atomic %.

[0034] An example of an embodiment flow of a method for manufacturing a SiGe substrate according to the present invention is shown in Fig. 1. As shown in Fig. 1, the method for manufacturing a SiGe substrate according to the present invention includes a step of epitaxially growing a SiGe layer on a main surface of a Si substrate (epitaxial step), a step of polishing the SiGe layer while sandwiching the main surface and back surface of the Si substrate provided with the SiGe layer between pads (polishing step), and a step of cleaning the Si substrate provided with the SiGe layer after polishing (cleaning step).

[0035] [Epitaxial process] A SiGe layer is epitaxially grown on the main surface of a Si substrate. A CVD apparatus is often used to grow the SiGe layer, and the present invention does not limit the manufacturing method. Regardless of the method selected, crosshatch defects caused by dislocations will exist on the surface of the SiGe layer grown on the Si substrate, although to varying degrees.

[0036] [Polishing process] After the epitaxial process, as shown in the "polishing process" in Figure 1, the SiGe layer is polished by sandwiching the main surface and the main back surface of the Si substrate with the SiGe layer between polishing pads 4. The polishing pad 4 can be made of suede or nonwoven fabric, but this is selected appropriately depending on the actual polishing equipment. This type of polishing can be performed as double-sided polishing. In this case, the back surface is also polished, which is preferable.

[0037] Furthermore, as a polishing device, a device using a general pad and slurry can be used.

[0038] The purpose of backside polishing is to remove damage around the edge when edge processing is performed, as well as to remove the SiGe layer grown on the backside by epitaxial growth. Note that there are no crosshatch-shaped defects on the backside, so there are no particular restrictions on the polishing method.

[0039] In this way, when polishing the front surface, it is necessary to perform polishing by sandwiching the substrate from above and below with polishing pads 4, rather than fixing the back surface to a surface plate.

[0040] The pH value of the polishing agent is preferably 10 or less, more preferably less than 10, and even more preferably 9 to 9.7.

[0041] The pH of the polishing solution specified in Patent Document 2, 10.0 to 11.0, poses the problem of peeling from the high-concentration Ge layer at the periphery, particularly when the Ge concentration in the SiGe layer is high. If the pH value of the abrasive containing colloidal silica or the like is within the above range, the etching of the high Ge concentration areas at the periphery of the substrate, which occurs when the alkaline component becomes strong, resulting in dust generation and film peeling, can be effectively suppressed while maintaining the polishing rate. In other words, damage to the SiGe exposed at the edge by the slurry used during processing can be effectively prevented.

[0042] [Cleaning process] After the polishing step, the Si substrate with the SiGe layer is cleaned. The pH value of the cleaning solution used for cleaning is preferably 10 or less, more preferably less than 10, and even more preferably 9 to 9.7. For example, the cleaning solution may be SC1 (Standard Cleaning 1) cleaning solution, which is a general mixture of ammonia, hydrogen peroxide, and water.

[0043] This makes it possible to more effectively suppress peeling of the high-concentration Ge in the SiGe layer.

[0044] In the method for manufacturing a SiGe substrate of the present invention, in consideration of the recent advances in miniaturization of semiconductor elements and the subsequent lithography process, the edge portions (end faces and notch portions) of the Si substrate having a SiGe layer can be further polished (mirror-shape chamfered) as shown in "(Edge Polishing)" in Figure 1.

[0045] This makes it possible to homogenize the edge portion of the SiGe substrate as well.

[0046] The specific method of chamfering is not particularly limited, but the edge shape at this time can be adjusted to be suitable for the subsequent process, such as epitaxial growth or lithography.

[0047] When using a chemical solution such as a slurry, as described above, the pH value of the polishing agent is preferably 10 or less, more preferably less than 10, and even more preferably 9 to 9.7. In addition, examples of types of slurry include polishing slurries mainly composed of silica and ceria.

[0048] Furthermore, after polishing the SiGe layer, the main surface can be further subjected to finish polishing. This allows the surface of the SiGe layer to be more uniform. [Example]

[0049] The present invention will be specifically explained below with reference to examples, but the present invention is not limited to these examples.

[0050] (Example) A boron-doped single-crystal silicon substrate with a surface crystal orientation of (110), a diameter of 300 mm, and a resistivity of 10 Ω·cm was prepared and placed in a reactor for epitaxial growth.

[0051] SiH2Cl2 gas and GeH4 gas were used as raw materials and introduced at 1000 sccm each into an epitaxial growth reactor evacuated to 1333 Pa (10 Torr). Film formation was carried out on a silicon substrate at a growth temperature (substrate temperature) of 610°C for 60 minutes to grow a SiGe layer (Ge concentration = 30 atomic %), producing a SiGe substrate.

[0052] After that, the edges of the substrate were mirror-chamfered, and then the main surface of the SiGe layer was polished (double-sided polishing by DSP), followed by finish polishing of the main surface (surface finishing processing by CMP). Finally, SC1 cleaning was performed.

[0053] The pH of the polishing solution containing colloidal silica used in polishing and the cleaning solution for SC1 cleaning were adjusted to 9, and the temperature of the SC1 cleaning solution was set to 50°C, rather than the 70°C or higher temperature normally used in cleaning silicon wafers.

[0054] Figure 3 shows images of the surface of the SiGe layer before and after the polishing, taken with an optical microscope ((a) before polishing, (b) after polishing). As shown in Figure 3, the roughness and depth of the crosshatch defects on the surface after polishing (b) were improved compared to (a) before polishing, indicating that the crosshatch defects had been reduced.

[0055] As described above, according to the examples of the present invention, by carrying out the polishing process according to the present invention, it was possible to reduce crosshatch defects on the surface of the SiGe layer.

[0056] The present specification includes the following aspects. [1]: A method for manufacturing a SiGe substrate, comprising: a step of epitaxially growing a SiGe layer on a main surface of a Si substrate; a step of polishing the SiGe layer while sandwiching the main surface and main back surface of the Si substrate with the SiGe layer between pads; and a step of cleaning the Si substrate with the SiGe layer after polishing. [2]: The method for producing a SiGe substrate according to [1] above, which comprises adjusting the pH value of the polishing agent used in the polishing to 10 or less. [3]: The method for producing a SiGe substrate according to [1] or [2] above, which comprises adjusting the pH value of the polishing agent used in the polishing to 9 to 9.7. [4]: The method for producing a SiGe substrate according to [1], [2] or [3] above, which comprises adjusting the pH value of the cleaning solution used for the cleaning to 10 or less. [5]: The method for producing a SiGe substrate according to [1], [2], [3] or [4] above, which comprises adjusting the pH value of the cleaning solution used for the cleaning to 9 to 9.7. [6]: The method for manufacturing a SiGe substrate according to [1], [2], [3], [4] or [5], further comprising polishing an edge portion of the Si substrate provided with the SiGe layer. [7]: The method for manufacturing a SiGe substrate according to [1], [2], [3], [4], [5] or [6], further comprising finish-polishing the main surface after polishing the SiGe layer.

[0057] The present invention is not limited to the above-described embodiments. The above-described embodiments are merely examples, and anything that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits similar effects is included within the technical scope of the present invention. [Explanation of symbols]

[0058] 1...SiGe substrate (virtual SiGe substrate), 2...silicon single crystal substrate, 3...SiGe layer, 4...polishing pad.

Claims

1. A method for manufacturing a SiGe substrate, comprising: a step of epitaxially growing a SiGe layer on a main surface of a Si substrate; a step of polishing the SiGe layer while sandwiching the main surface and main back surface of the Si substrate with the SiGe layer between pads; and a step of cleaning the Si substrate with the SiGe layer after polishing.

2. 2. The method for manufacturing a SiGe substrate according to claim 1, wherein the pH value of the polishing agent used for said polishing is set to 10 or less.

3. 2. The method for manufacturing a SiGe substrate according to claim 1, wherein the pH value of the polishing agent used for said polishing is set to 9 to 9.

7.

4. 2. The method for manufacturing a SiGe substrate according to claim 1, wherein the pH value of the cleaning solution used for the cleaning is set to 10 or less.

5. 2. The method for manufacturing a SiGe substrate according to claim 1, wherein the pH value of the cleaning solution used for the cleaning is set to 9 to 9.

7.

6. 2. The method for manufacturing a SiGe substrate according to claim 1, further comprising polishing an edge portion of the Si substrate provided with the SiGe layer.

7. 7. The method for manufacturing a SiGe substrate according to claim 1, further comprising the step of polishing the main surface after polishing the SiGe layer.

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