Photoelectric conversion device, method for driving photoelectric conversion device, and apparatus

Abstract

To provide a photoelectric conversion device that has improved the accuracy of AD conversion.SOLUTION: Provided is a method for driving a photoelectric conversion device comprising pixels that generate pixel signals through photoelectric conversion, output lines that can be electrically connected to the pixels, and comparators that each have a first input node to which a reference signal is input and a second input node to which the pixel signal is input through the output line. In a reset period of the comparator, first voltage is input to the second input node, and a direction in which the voltage of the output line changes when the pixel signal is input to the second input node is different from a direction in which the voltage of the output line changes when the first voltage is input to the second input node.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device, a method for driving a photoelectric conversion device, and an apparatus. [Background technology]

[0002] Patent Document 1 discloses a photoelectric conversion device having an analog-to-digital (AD) conversion circuit that converts pixel signals output from pixels into digital signals. In the configuration disclosed in Patent Document 1, pixel signals output from multiple pixels arranged in different rows are AD converted sequentially for each row using the AD conversion circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-111095 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the configuration disclosed in Patent Document 1, the accuracy of AD conversion of pixel signals output from pixels arranged in a row may be reduced due to the influence of AD conversion of pixel signals output from pixels arranged in a row other than the row. This point is not taken into consideration in Patent Document 1.

[0005] An object of the present invention is to provide a photoelectric conversion device with improved accuracy of AD conversion. [Means for solving the problem]

[0006] According to one disclosure of this specification, there is provided a method for driving a photoelectric conversion device comprising a pixel that generates a pixel signal by photoelectric conversion, an output line electrically connectable to the pixel, and a comparator having a first input node to which a reference signal is input and a second input node to which the pixel signal is input via the output line, wherein during a reset period of the comparator, a first voltage is input to the second input node, and the direction in which the voltage of the output line changes when the pixel signal is input to the second input node is different from the direction in which the voltage of the output line changes when the first voltage is input to the second input node. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a photoelectric conversion device with improved accuracy of AD conversion. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram illustrating a photoelectric conversion device according to a first embodiment. [Figure 2] 1 is a circuit diagram illustrating a photoelectric conversion device according to a first embodiment; [Figure 3] 1 is a circuit diagram illustrating a photoelectric conversion device according to a first embodiment; [Figure 4] 1 is a circuit diagram illustrating a photoelectric conversion device according to a first embodiment; [Figure 5] 10 is a driving timing chart illustrating a photoelectric conversion device according to a reference example. [Figure 6] 10 is a driving timing chart illustrating a photoelectric conversion device according to a reference example. [Figure 7] 1 is a driving timing chart illustrating a photoelectric conversion device according to a first embodiment; [Figure 8] FIG. 10 is a circuit diagram illustrating a photoelectric conversion device according to a second embodiment. [Figure 9] 10 is a driving timing chart illustrating a photoelectric conversion device according to a second embodiment. [Figure 10] FIG. 10 is a circuit diagram illustrating a photoelectric conversion device according to a third embodiment. [Figure 11]10 is a driving timing chart illustrating a photoelectric conversion device according to a third embodiment. [Figure 12] FIG. 10 is a circuit diagram illustrating a photoelectric conversion device according to a fourth embodiment. [Figure 13] FIG. 10 is a circuit diagram illustrating a photoelectric conversion device according to a fifth embodiment. [Figure 14] FIG. 10 is a circuit diagram illustrating a photoelectric conversion device according to a fifth embodiment. [Figure 15] 10 is a driving timing chart illustrating a photoelectric conversion device according to a fifth embodiment. [Figure 16] FIG. 13 is a schematic diagram illustrating a device according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Each embodiment will be described below with reference to the drawings. Note that the following embodiments do not limit the scope of the claimed invention. Although multiple features are described in the embodiments, not all of these features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same or similar components are given the same reference numerals, and redundant description will be omitted. Also, in the following embodiments, an imaging sensor will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to an imaging sensor and can be applied to other examples of photoelectric conversion devices. Examples include an imaging device, a range finder (a device for measuring distance using focus detection or TOF (Time Of Flight)), and a photometric device (a device for measuring the amount of incident light).

[0010] In this specification, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms including these terms) are used as necessary. The use of these terms is for the purpose of facilitating understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0011] In this specification, the phrase "electrically connecting component A and component B" does not necessarily mean that component A and component B are directly connected. For example, even if another component C is connected between component A and component B, it is acceptable as long as they are electrically connected.

[0012] In this specification, "plane" refers to a surface parallel to the main surface of a substrate. The main surface of a substrate may be the light incident surface of a substrate including a photoelectric conversion element, a surface on which multiple ADCs are repeatedly arranged, or a bonding surface between substrates in a stacked photoelectric conversion device. Furthermore, "planar view" refers to a view from a direction perpendicular to the main surface of the substrate. Furthermore, "cross section" refers to a surface perpendicular to the light incident surface of a semiconductor layer. Furthermore, "cross section" refers to a view from a direction parallel to the main surface of the substrate.

[0013] Metallic components such as wiring and pads described herein may be composed of a single metal element or a mixture (alloy). For example, wiring described as copper wiring may be composed of copper alone or may be composed primarily of copper with other components. Furthermore, for example, pads connected to external terminals may be composed of aluminum alone or may be composed primarily of aluminum with other components. The copper wiring and aluminum pads shown here are merely examples and can be replaced with various metals. Furthermore, the wiring and pads shown here are merely examples of metallic components used in photoelectric conversion devices and may also be applied to other metallic components.

[0014] The relationship between "substantially equal" and "substantially identical" in the present invention will be explained. Although they are designed to be equal, slight differences may occur due to manufacturing errors. The terms "substantially equal" and "substantially identical" include such slight differences caused by manufacturing errors.

[0015] First Embodiment A photoelectric conversion device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 4 and 7. FIG.

[0016] FIG. 1 is an example of a block diagram of a photoelectric conversion device 1 according to this embodiment.

[0017] 1, the photoelectric conversion device 1 includes a pixel array 11, a row selection circuit 12, a signal processing circuit 13, a reference signal output circuit 14, a counter circuit 15, a column selection circuit 16, an output circuit 17, and a control circuit 18. The photoelectric conversion device 1 also includes a control line 19, a vertical output line 20, and a horizontal output line 22.

[0018] The pixel array 11 has a plurality of pixels 10 that perform photoelectric conversion, and the plurality of pixels 10 are arranged across a plurality of rows and a plurality of columns within the pixel array 11. The pixels 10 generate pixel signals through photoelectric conversion. The pixel signals output from the pixels 10 are analog signals. In this specification, the horizontal direction in the drawings is referred to as the row direction, and the vertical direction is referred to as the column direction. The number of rows and columns of the plurality of pixels 10 arranged in the pixel array 11 is not particularly limited. The plurality of pixels 10 may include effective pixels that output pixel signals according to the amount of incident light, as well as optical black pixels in which the photoelectric conversion elements are shielded from light, dummy pixels that do not output signals, etc.

[0019] Additionally, a plurality of control lines 19 are arranged in each row of the pixel array 11, extending in the row direction. Each of the control lines 19 is electrically connected to a plurality of pixels 10 arranged in the row direction. One control line 19 commonly controls a plurality of pixels 10 arranged in one row. The row selection circuit 12 includes a shift register, a gate circuit, a buffer circuit, etc. The row selection circuit 12 outputs control signals to the pixel array 11 based on a vertical synchronization signal, a horizontal synchronization signal, a clock signal, etc., and drives the plurality of pixels 10 for each row.

[0020] Additionally, multiple vertical output lines 20 are arranged in each column of the pixel array 11, extending in the column direction. Each of the multiple vertical output lines 20 is electrically connected to a corresponding one of the multiple pixels 10 arranged in the column direction. The multiple pixels 10 arranged in each column are electrically connected to a signal processing circuit 13 via each of the multiple vertical output lines 20, and pixel signals output from the multiple pixels 10 are input to the signal processing circuit 13 row by row. The signal processing circuit 13 includes multiple analog-to-digital (AD) conversion circuits 21 corresponding to each pixel column in which the multiple pixels 10 are arranged. The AD conversion circuits 21 perform signal processing such as AD conversion on pixel signals read from the pixels 10 arranged in the corresponding column. In this embodiment, slope-type AD conversion is described as the AD conversion method, but other AD conversion methods such as successive approximation AD conversion and ΔΣ AD conversion may also be used. Note that the number of vertical output lines 20 arranged for the multiple pixels 10 arranged in one column is not limited to one and may be multiple. In this case, an AD conversion circuit 21 corresponding to each vertical output line 20 is required. When multiple vertical output lines 20 are provided for one column, multiple pixels 10 arranged in multiple rows can be read out at the same time, enabling high-speed pixel signal readout.

[0021] Furthermore, the reference signal output circuit 14 outputs a reference signal, which is a signal whose voltage changes over time. The AD conversion circuit 21 performs AD conversion on the pixel signals, which are analog signals, using the reference signal, and outputs the result as a digital signal. The reference signal may be generated by the reference signal output circuit 14, or by a circuit different from the reference signal output circuit 14. For example, the reference signal may be generated using various methods, such as a capacitive charging method, a DAC method, or a current steering method. In this embodiment, a reference signal having a constant slope (amount of voltage change per unit time) is used, but a reference signal whose slope changes along the way may also be used. A reference signal whose slope changes along the way may change in a stepwise manner, for example.

[0022] Furthermore, the counter circuit 15 outputs a count signal CNT used for AD conversion performed by the signal processing circuit 13. The count signal CNT is a signal that counts the clock pulse signal CLK supplied from a clock pulse supply circuit (not shown) in synchronization with the timing at which the reference signal of the reference signal output circuit 14 starts to change depending on time. Note that although the counter circuit 15 shown in FIG. 1 is provided in common to the plurality of AD conversion circuits 21, it may also be provided corresponding to each of the plurality of AD conversion circuits 21.

[0023] The column selection circuit 16 also includes logic circuits such as a shift register and an address decoder. The column selection circuit 16 selects a column in which the pixels 10 are arranged. The AD-converted pixel signals corresponding to the column selected by the column selection circuit 16 are sequentially output to the outside of the photoelectric conversion device via a horizontal output line 22 and an output circuit 17.

[0024] The output circuit 17 includes a buffer amplifier, a differential amplifier, etc., and performs predetermined signal processing on pixel signals output from the pixels 10 in the column selected by the column selection circuit 16, and outputs the processed pixel signals. Examples of signal processing performed by the output circuit 17 include correction processing using correlated double sampling (CDS) and amplification processing. The output circuit 17 also includes an LVDS (Low Voltage Differential Signal) serial output circuit, and outputs the processed digital signals to the outside of the photoelectric conversion device at high speed and with low power consumption. The output method is not limited to LVDS, and other methods may be used.

[0025] The control circuit 18 supplies control signals to the row selection circuit 12 , the signal processing circuit 13 , the reference signal output circuit 14 , the counter circuit 15 , and the column selection circuit 16 .

[0026] 1 shows an example in which one circuit block for reading out pixel signals is provided, including the signal processing circuit 13, the column selection circuit 16, and the output circuit 17. However, multiple circuit blocks for reading out pixel signals may be provided across the pixel array 11. In this case, for example, pixel signals of the pixels 10 arranged in even-numbered columns are input to one circuit block, and pixel signals of the pixels 10 arranged in odd-numbered columns are input to the other circuit block, thereby enabling high-speed readout of pixel signals.

[0027] 2 is an example of a circuit diagram of a pixel 10 included in the photoelectric conversion device 1 according to this embodiment. Note that the present disclosure can be applied to both front-illuminated and back-illuminated sensors.

[0028] As shown in FIG. 2, the pixel 10 has a photoelectric conversion element 200, a transfer transistor 201, and a floating diffusion 202. Hereinafter, in this specification, the floating diffusion 202 may be referred to as FD202 (FD is an abbreviation for Floating Diffusion). The FD202 may also be referred to as a floating diffusion region 202. The pixel 10 also has a reset transistor 205 for resetting the FD202, an amplifier transistor 203 for amplifying a signal, and a selection transistor 204. The photoelectric conversion element 200 is electrically connected to a ground voltage node GND and is supplied with a ground voltage. The reset transistor 205 and the amplifier transistor 203 are electrically connected to a power supply voltage node VDD and are supplied with a power supply voltage.

[0029] Note that the transfer transistor 201, the reset transistor 205, the amplification transistor 203, and the selection transistor 204 may each be an N-type MOS transistor or a P-type MOS transistor. In this embodiment, a case will be described in which, of the electron-hole pairs generated in the photoelectric conversion element 200 by incident light, electrons are used as signal charges. When electrons are used as signal charges, each transistor included in the pixel 10 may be configured as an N-type MOS transistor. However, the signal charges are not limited to electrons, and holes may also be used as signal charges. When holes are used as signal charges, each transistor included in the pixel 10 may be configured as a P-type MOS transistor different from that described in this embodiment.

[0030] The photoelectric conversion element 200 is, for example, a photodiode. The photoelectric conversion element 200 is not limited to a photodiode and may be, for example, a photoelectric conversion film. The photoelectric conversion element 200 receives light incident on the pixel 10, generates charges corresponding to the incident light, and accumulates the charges. The reset transistor 205 is driven by a control signal PRES. When the reset transistor 205 is turned on (conductive), the FD 202 is reset to a voltage based on the power supply voltage. When the reset transistor 205 is turned off (non-conductive), the FD 202 is released from the reset state. The transfer transistor 201 is driven by a control signal PTX. When the transfer transistor 201 is turned on, the charges generated in the photoelectric conversion element 200 are transferred to the FD 202. The FD 202 temporarily holds the charges input from the photoelectric conversion element 200 and functions as a charge-voltage converter that converts the held charges into a voltage signal. The amplification transistor 203 amplifies the pixel signal (voltage signal) converted by the FD 202. The selection transistor 204 is driven by a control signal PSEL to connect the amplification transistor 203 to the vertical output line 20 and output the pixel signal amplified by the amplification transistor 203 to the vertical output line 20. The pixel signal may include a reset level signal (noise signal) of the FD 202 and a signal (photoelectric conversion signal) output from the photoelectric conversion element 200. The noise signal is a signal that mainly includes noise components possessed by the pixel 10.

[0031] 2 is an example, and the pixel 10 may further include a transistor. For example, a transistor that changes the capacitance value of the FD 202 or a transistor that discharges charge from the photoelectric conversion element 200 may be further provided. Alternatively, the pixel 10 may be configured not to include the selection transistor 204, and the selected / non-selected state of the pixel 10 may be changed depending on the voltage input from the reset transistor 205 to the FD 202.

[0032] FIG. 3 is an example of a circuit diagram of the AD conversion circuit 21 included in the photoelectric conversion device 1 according to this embodiment.

[0033] As shown in FIG. 3 , the AD conversion circuit 21 includes a current source 301, a first buffer circuit 302, a comparator 303, and a memory circuit 304. The AD conversion circuit 21 also includes a first capacitance element C1, a second capacitance element C2, a first switch SW1, a second switch SW2, and a third switch SW3. In this specification, the voltage of the vertical output line 20 may be referred to as VOUT. The voltage VOUT may fluctuate when pixel signals are input from the pixels 10 to the vertical output line 20. In this specification, the reference signal may be referred to as RAMP, and the voltage of the reference signal may be referred to as VRAMP.

[0034] The comparator 303 is configured by, for example, a differential amplifier circuit. The comparator 303 has a first input node INP which is a non-inverting input terminal of the differential stage, a second input node INN which is an inverting input terminal, a first output node FBN which is an inverting output terminal, and a second output node FBP which is a non-inverting output terminal. The comparator 303 also has a third output node OUT which is an output terminal of the amplifier stage. The comparator 303 may perform an offset clamp operation based on the voltage of the pixel signal and the voltage of the reference signal.

[0035] The second switch SW2 is electrically connected to the first input node INP and the first output node FBN and is disposed between the first input node INP and the first output node FBN. The third switch SW3 is electrically connected to the second input node INN and the second output node FBP and is disposed between the second input node INN and the second output node FBP. The second switch SW2 and the third switch SW3 are switches controlled by a control signal PFB supplied from the control circuit 18 via a feedback signal line 306. The second switch SW2 and the third switch SW3 are switches for resetting the threshold voltage of the comparator 303.

[0036] The first buffer circuit 302 has an input node and an output node. A reference signal is supplied to the input node of the first buffer circuit 302 from the reference signal output circuit 14 via a reference signal line 305. The output node of the first buffer circuit 302 is electrically connected to the first input node INP via a first capacitance element C1. That is, the reference signal output from the reference signal output circuit 14 is input to the first input node INP via the reference signal line 305, the first buffer circuit 302, and the first capacitance element C1.

[0037] The vertical output line 20 is electrically connected to a second input node INN via a second capacitance element C2. A pixel signal output from the pixel 10 is input to a second input node INN of the comparator 303 via the vertical output line 20 and the second capacitance element C2. The vertical output line 20 is also electrically connected to a current source 301. The current source 301 serves as a load current source for the amplification transistor 203 of the pixel 10. The first switch SW1 has a first node electrically connected to a first voltage node 309 and a second node electrically connected to the vertical output line 20. That is, the vertical output line 20 is electrically connectable to the first voltage node 309 via the first switch SW1. The first switch SW1 is controlled by a control signal PVLRES supplied from the control circuit 18 via a first switch control line 308. When the control signal PVLRES goes high, the vertical output line 20 is electrically connected to the first voltage node 309. It is sufficient that a voltage (first voltage) equal to or greater than a predetermined value is supplied to first voltage node 309, and for example, the power supply voltage supplied to power supply voltage node VDD may be supplied.

[0038] The comparator 303 outputs a comparison result signal COUT indicating the result of comparing the pixel signal input via the vertical output line 20 with the reference signal to the memory circuit 304. For example, the comparator 303 outputs a low level when the voltage of the reference signal is higher than the voltage of the pixel signal (when the signal amplitude of the reference signal is smaller than that of the pixel signal). The comparator 303 outputs a high level when the voltage of the reference signal is lower than the voltage of the pixel signal (when the signal amplitude of the reference signal is larger than that of the pixel signal). Note that this relationship between the high level and the low level is just an example, and the opposite relationship may also be true. The memory circuit 304 holds a count signal CNT input via a count signal line 307 from the counter circuit 15 shown in FIG. 1 based on a change in the value of the comparison result signal COUT output from the comparator 303. As a result, the memory circuit 304 holds the count signal CNT having a signal value corresponding to the value of the pixel signal as a digital signal corresponding to the pixel signal, and the pixel signal output from the pixel 10 is AD converted. The digital signals held in the memory circuit 304 are transferred to the output circuit 17 via the horizontal output line 22 in sequence for each column in response to a control signal supplied from the column selection circuit 16 .

[0039] In this embodiment, all of the above-mentioned circuit blocks may be arranged on one substrate, or a stacked configuration may be used in which multiple substrates are stacked, with these multiple circuit blocks being arranged separately on each substrate.

[0040] FIG. 4 is an example of a circuit diagram of the comparator 303 included in the AD conversion circuit 21 according to this embodiment.

[0041] 4, the comparator 303 has a differential stage and an amplification stage. The differential stage includes a first input transistor 400, a second input transistor 401, a first current source 402, a first current mirror transistor 403, and a second current mirror transistor 404. The first input transistor 400 is arranged corresponding to a first input node INP, and the second input transistor 401 is arranged corresponding to a second input node INN. The amplification stage includes a third input transistor 405 and a second current source 406.

[0042] FIG. 5 is an example of a drive timing chart for the photoelectric conversion device 1 according to the reference example. In FIG. 5, the horizontal axis represents time and the vertical axis represents voltage. FIG. 5 also schematically shows the voltages of each control signal (timing of each drive pulse), the voltage VOUT, the voltage VRAMP, the voltage VINP at the first input node INP, and the voltage VINN at the second input node INN. The voltage VINP is indicated by a solid line, while the voltage VINN is indicated by a dashed line. The control signals shown in FIG. 5 correspond to the control signals shown in FIGS. 2 and 3. When a control signal is at a high level, the corresponding transistors and switches are turned on, and when the control signal is at a low level, the corresponding transistors and switches are turned off.

[0043] 5 shows the timing for reading pixel signals from pixels 10 arranged in any two consecutive rows (hereinafter referred to as the first row and the second row). Note that period T1 indicates the readout period for pixel signals output from pixels 10 arranged in the first row (first pixel 10-1), and period T2 indicates the readout period for pixel signals output from pixels 10 arranged in the second row (second pixel 10-2). Control signals PTX1, PRES1, and PSEL1 are control signals output to the first pixel 10-1, and control signals PTX2, PRES2, and PSEL2 are control signals output to the second pixel 10-2. Here, for example, it is assumed that the amount of light incident on the first pixel 10-1 is greater than the amount of light incident on the second pixel 10-2.

[0044] At time t100, the control signal PSEL1 changes from low to high, turning on the selection transistor 204 of the first pixel 10-1, and the first row is selected as the row from which the pixel signal is output.

[0045] During the period from time t101 to time t104, the control signal PRES1 goes high, turning on the reset transistor 205 of the first pixel 10-1, and the first pixel 10-1 outputs a noise signal as a pixel signal to the vertical output line 20 arranged in the corresponding column.

[0046] During the period from time t102 to time t105, the control signal PFB goes high, turning on the second switch SW2 and the third switch SW3. The first input node INP and the second input node INN of the comparator 303 are reset to the reset-level voltage. At time t103, the voltage VRAMP becomes the reference voltage, and the offset removal operation is performed.

[0047] That is, at time t105, the node of the second capacitance element C2 on the first pixel 10-1 side is at the reset level voltage of FD202, and the node of the second capacitance element C2 on the comparator 303 side is at the reset level voltage of the comparator 303. Furthermore, the node of the first capacitance element C1 on the reference signal output circuit 14 side is at the reference voltage of the reference signal, and the node of the first capacitance element C1 on the comparator 303 side is at the reset level voltage of the comparator 303. Therefore, the threshold voltage of the comparator 303 is reset to a voltage corresponding to the difference between the reset level voltage of FD202 (the voltage of the noise signal) and the reference voltage of the reference signal. The threshold voltage of the comparator 303 is a voltage corresponding to the difference between the voltage VOUT and the voltage VRAMP when the value of the comparison result signal COUT output from the comparator 303 changes. That is, the value of the comparison result signal COUT output from the comparator 303 changes around the timing when the difference between the voltage VOUT and the voltage VRAMP corresponds to the reset voltage. Therefore, the comparator 303 outputs a comparison result signal COUT that indicates a different value when the difference between the voltage VOUT and the voltage VRAMP is smaller than the threshold voltage and when it is larger than the threshold voltage.

[0048] At time t106, the voltage VRAMP increases from the reference voltage to a predetermined start voltage. Next, during the period from time t107 to time t109, the voltage VRAMP decreases from the start voltage depending on time. At time t107, as the voltage VRAMP changes, the counter circuit 15 starts counting clock pulse signals and supplies a count signal CNT indicating the count value to the memory circuit 304 of each column via the count signal line 307. The comparator 303 compares the voltage VOUT input to the first input node INP with the voltage VRAMP input to the second input node INN. When the magnitude relationship between the voltage VOUT and the voltage VRAMP changes (for example, at time t108 in FIG. 5), the value of the comparison result signal COUT output from the comparator 303 changes. The memory circuit 304 holds the count value indicated by the count signal CNT supplied from the counter circuit 15 at the time the value of the comparison result signal COUT changes. At this time, the value of the count signal CNT held by the memory circuit 304 is a digital value obtained by AD converting the noise signal. In this way, the noise signal, which is one of the pixel signals, is AD converted based on the comparison result of the comparator 303. Thereafter, the AD conversion circuits 21 are sequentially operated in response to a control signal from the column selection circuit 16, whereby the digital signal held in the memory circuit 304 is transferred to the output circuit 17.

[0049] At time t109, the time-dependent change of the voltage VRAMP is stopped, and the voltage VRAMP is reset to the starting voltage. The counter circuit 15 stops counting the clock pulse signal, and returns the count signal CNT to its initial value.

[0050] At time t110, the control signal PTX1 changes from low to high, turning on the transfer transistor 201 of the first pixel 10-1. Then, the charge accumulated in the photoelectric conversion element 200 during a predetermined exposure period is transferred to the FD 202, and the first pixel 10-1 outputs a photoelectric conversion signal as a pixel signal to the vertical output line 20 arranged in the corresponding column. At this time, the voltage of the FD 202 decreases in accordance with the amount of charge transferred from the photoelectric conversion element 200, and the voltage VOUT also decreases.

[0051] During the period from time t111 to time t113, the voltage VRAMP decreases from the start voltage over time. At time t111, as the voltage VRAMP changes, the counter circuit 15 starts counting clock pulse signals and supplies a count signal CNT indicating the count value to the memory circuit 304 of each column via the count signal line 307. The comparator 303 compares the voltage VOUT input to the first input node INP with the voltage VRAMP input to the second input node INN. At the timing when the magnitude relationship between the voltage VOUT and the voltage VRAMP changes (for example, at time t112 in FIG. 5), the value of the comparison result signal COUT output from the comparator 303 changes. The memory circuit 304 holds the count value indicated by the count signal CNT supplied from the counter circuit 15 at the timing when the value of the comparison result signal COUT changes. At this time, the value of the count signal CNT held by the memory circuit 304 is a digital value obtained by AD-converting the photoelectric conversion signal. In this way, the photoelectric conversion signal, which is one of the pixel signals, is AD converted based on the comparison result of the comparator 303. Thereafter, the AD conversion circuits 21 are sequentially operated in response to a control signal from the column selection circuit 16, whereby the digital signal held in the memory circuit 304 is transferred to the output circuit 17.

[0052] The digital pixel signals thus obtained are subjected to correction processing using correlated double sampling in the output circuit 17. In the correction processing using correlated double sampling, the digitized noise signal is subtracted from the digitized photoelectric conversion signal to remove the noise component superimposed on the photoelectric conversion signal. In other words, the light component signal is calculated as the difference between the photoelectric conversion signal corresponding to the count value from time t111 to time t112 and the noise signal corresponding to the count value from time t107 to time t108.

[0053] During a period T2 from time t150 to time t250, the amount of change in the voltage VOUT at the timing when the control signal PTX goes high is different from that during a period T1 from time t0 to time t150. Specifically, at time t210, the control signal PTX2 goes from low to high, turning on the transfer transistor 201 of the second pixel 10-2. Then, the charge accumulated in the photoelectric conversion element 200 during a predetermined exposure period is transferred to the FD 202, and the second pixel 10-2 outputs a photoelectric conversion signal as a pixel signal to the vertical output line 20 arranged in the corresponding column. At this time, the voltage of the FD 202 decreases in accordance with the amount of charge transferred from the photoelectric conversion element 200, and the voltage VOUT also decreases. Here, because the amount of light incident on the second pixel 10-2 is less than the amount of light incident on the first pixel 10-1, the amount of decrease in the voltage VOUT of the vertical output line 20 is less than that of the first pixel 10-1. Therefore, the amount of voltage change in the vertical output line 20 is smaller for the second pixel 10-2 than for the first pixel 10-1. During period T2, the count value from time t207 to time t208 is treated as a noise signal, and the count value from time t211 to time t212 is treated as a photoelectric conversion signal. Then, as in period T1, a light component signal, which is the difference between the photoelectric conversion signal and the noise signal, is calculated. Of the driving operations in period T2, those not described are the same as those described for period T1. Through the above driving, the pixel signals, which are analog signals output from the first pixel 10-1 and the second pixel 10-2, which has a different amount of incident light from the first pixel 10-1, are converted into digital signals.

[0054] However, as shown in Fig. 5, when pixel signals output from a plurality of pixels 10 with different amounts of incident light are continuously read out, the AD conversion operation in period T1 may affect the AD conversion operation in period T2. This case will be described with reference to Fig. 6.

[0055] FIG. 6 is an example of a drive timing chart for the photoelectric conversion device 1 according to the reference example. In FIG. 6, the horizontal axis represents time and the vertical axis represents voltage. FIG. 6 also schematically shows the voltages of each control signal (timing of each drive pulse), the voltage VOUT, the voltage VRAMP, the voltage VINP at the first input node INP, and the voltage VINN at the second input node INN. Note that the voltage VINP is indicated by a solid line, while the voltage VINN is indicated by a dashed line. Note that each control signal shown in FIG. 6 corresponds to each control signal shown in FIGS. 2 and 3. Note that when a control signal is at a high level, the corresponding transistors and switches are turned on, and when the control signal is at a low level, the corresponding transistors and switches are turned off.

[0056] 6 shows the timing for reading pixel signals from the pixels 10 arranged in the first and second rows that are successively read out. Note that period T1 indicates the readout period for the pixel signal output from the first pixel 10-1, and period T2 indicates the readout period for the pixel signal output from the second pixel 10-2. Control signals PTX1, PRES1, and PSEL1 are control signals output to the first pixel 10-1, and control signals PTX2, PRES2, and PSEL2 are control signals output to the second pixel 10-2. Here, for example, it is assumed that the amount of light incident on the first pixel 10-1 is greater than the amount of light incident on the second pixel 10-2.

[0057] The timing of each driving pulse shown in FIG. 6 is the same as that shown in FIG. 5. Using FIG. 6, we will explain how the readout operation of the photoelectric conversion signal during period T1 affects the readout operation of the photoelectric conversion signal during period T2. In FIG. 6, the difference between voltage VINN and voltage VINP is larger during the periods from time t113 to time t114 and from time t213 to time t214 than during other periods. Furthermore, because the amount of light incident on the first pixel 10-1 is larger than the amount of light incident on the second pixel 10-2, the change in voltage VOUT during period T1 is larger than during period T2. Therefore, during the period from time t113 to time t114, the difference between voltage VOUT and voltage VRAMP is larger than during the period from time t213 to time t214. That is, during the period from time t113 to time t114, the difference between voltage VINN and voltage VINP is larger than during the period from time t213 to time t214. Therefore, the greater the amount of incident light, the greater the difference between the voltages VINN and VINP, and the longer the period during which the difference between the voltages VINN and VINP is greater than a predetermined amount.

[0058] In this reference example, the period during which the potential difference between the source and gate of the first input transistor 400 is large is longer than that of the second input transistor 401. In this case, a high voltage is applied to the first input transistor 400, causing a fluctuation in the threshold voltage of the first input transistor 400 due to hot carrier injection. Specifically, this hot carrier injection traps carriers, increasing the threshold voltage of the first input transistor 400. Operation when the threshold voltage increases is shown in the period from time t202 to time t213 in FIG. 6 . Here, the amount of change in the threshold voltage of the first input transistor 400 is denoted as ΔV. During the reset period of the comparator 303 from time t202 to time t205, the voltage VINP increases by ΔV, and the current values ​​flowing through the first input transistor 400 and the second input transistor 401 become equal. In other words, the threshold voltage of the comparator 303 is reset to a voltage corresponding to the difference ΔV between the reset level voltage of the voltage VOUT and the reference voltage of the reference signal. 6 shows the adjustment voltage when the current values ​​flowing through the first input transistor 400 and the second input transistor 401 are adjusted to be equal. Note that this adjustment voltage is adjusted such that the trapped carriers are released after time t206, and the threshold voltage of the first input transistor 400 changes to a normal value, and ΔV, which is the amount of change in the threshold voltage, approaches 0. In this reference example, ΔV, which is the amount of change in the threshold voltage, approaches 0 from time t210 to time t211. Note that the change in voltage VINP during the period from time t202 to time t250 shown in FIG. 5 is indicated by a dotted line in FIG. 6.

[0059] During the period from time t207 to time t209 in FIG. 6, the voltage VRAMP decreases over time from a voltage that is ΔV higher than the predetermined start voltage shown in FIG. 5. Then, at time t208, the value of the comparison result signal COUT output from the comparator 303 changes. The memory circuit 304 holds the count value indicated by the count signal CNT supplied from the counter circuit 15 at the timing when the value of the comparison result signal COUT changed. At this time, the value of the count signal CNT held by the memory circuit 304 is a digital value obtained by AD converting the noise signal. Note that, due to the influence of a change in the threshold voltage of the first input transistor 400, the output of the comparator 303 is inverted at the timing when the voltage VINP is higher than the voltage VINN by ΔV.

[0060] During the period from time t211 to time t213 in FIG. 6, the voltage VRAMP decreases over time from a voltage ΔV higher than the predetermined start voltage shown in FIG. 5. Then, at time t212′, the value of the comparison result signal COUT output from the comparator 303 changes. The memory circuit 304 holds the count value indicated by the count signal CNT supplied from the counter circuit 15 at the timing when the value of the comparison result signal COUT changed. At this time, the value of the count signal CNT held by the memory circuit 304 is a digital value obtained by AD converting the photoelectric conversion signal. Note that, due to the influence of a change in the threshold voltage of the first input transistor 400, the output of the comparator 303 inverts when the voltage VINP is higher than the voltage VINN by ΔV. Note that during this period, the threshold voltage of the first input transistor 400 returns to its normal value, so the value of the comparison result signal COUT output from the comparator 303 changes at time t212′ when the magnitude relationship between the voltage VINP and the voltage VINN changes.

[0061] Here, we compare the light component signal read out from the second pixel 10-2 when the threshold voltage change shown in Figure 5 does not occur with the light component signal read out from the second pixel 10-2 when the threshold voltage change shown in Figure 6 occurs.

[0062] 5, the light component signal read out from the second pixel 10-2 is calculated using a count value corresponding to the noise signal from time t207 to time t208 and a count value corresponding to the photoelectric conversion signal from time t211 to time t212. That is, the light component signal is calculated using equation (1). Here, the count value corresponding to the noise signal from time t207 to time t208 is set to NOUT, and the count value corresponding to the photoelectric conversion signal from time t211 to time t212 is set to SOUT. (Light component signal) = SOUT-NOUT (1)

[0063] 6, the light component signal read out from the second pixel 10-2 is calculated using a count value corresponding to the noise signal during the period from time t207 to time t208 and a count value corresponding to the photoelectric conversion signal during the period from time t211 to time t212'. That is, the light component signal is calculated using equation (2). Here, the count value corresponding to the photoelectric conversion signal during the period (Δt) from time t212 to time t212' is defined as ΔOUT. (Light component signal)=SOUT+ΔOUT-NOUT...(2)

[0064] Comparing equations (1) and (2), when the threshold voltage change shown in FIG. 6 occurs, the light component signal read from the second pixel 10-2 is read out as being larger than the actual value by ΔOUT. In other words, the accuracy of AD conversion is reduced. Furthermore, consider a case where the amount of light incident on the first pixel 10-1 is greater than the amount of light incident on the second pixel 10-2. In this case, the artificial increase in the light component signal read from the second pixel 10-2 results in an image that is brighter than the image that would actually be obtained corresponding to the second pixel 10-2, resulting in reduced image quality.

[0065] The driving method of this embodiment for solving the above problem will be described with reference to FIG.

[0066] FIG. 7 is an example of a drive timing chart for the photoelectric conversion device 1 according to this embodiment. In FIG. 7, the horizontal axis represents time and the vertical axis represents voltage. FIG. 7 also schematically shows the voltages of each control signal (timing of each drive pulse), the voltage VOUT, the voltage VRAMP, the voltage VINP at the first input node INP, and the voltage VINN at the second input node INN. The voltage VINP is indicated by a solid line, while the voltage VINN is indicated by a dashed line. The control signals shown in FIG. 7 correspond to the control signals shown in FIGS. 2 and 3. When a control signal is at a high level, the corresponding transistors and switches are turned on, and when the control signal is at a low level, the corresponding transistors and switches are turned off.

[0067] FIG. 7 shows the timing for reading pixel signals from the pixels 10 arranged in the first and second rows, which are successively read out. Note that period T1 indicates the readout period for the pixel signal output from the first pixel 10-1, and period T2 indicates the readout period for the pixel signal output from the second pixel 10-2. Control signals PTX1, PRES1, and PSEL1 are control signals output to the first pixel 10-1, and control signals PTX2, PRES2, and PSEL2 are control signals output to the second pixel 10-2. Here, for example, it is assumed that the amount of light incident on the first pixel 10-1 is greater than the amount of light incident on the second pixel 10-2. Note that the difference between the driving method shown in FIG. 7 and the driving methods shown in FIGS. 5 and 6 lies in the driving methods of the control signals PFB and PVLRES. This difference will be explained using the readout operation of the pixel signal output from the second pixel 10-2 during period T2.

[0068] At time t113, the voltage VRAMP changes to the start voltage at time t111, completing AD conversion of the pixel signal output from the first pixel 10-1. At time t114, the control signal PSEL1 changes from high to low, electrically disconnecting the first pixel 10-1 and the vertical output line 20. At time t115, the control signal PFB changes from low to high, starting the reset operation of the comparator 303. Note that the period from time t115 to time t205, during which the control signal PFB is at high, is the reset period of the comparator 303. During the reset period, from time t117 to time t119, the control signal PVLRES goes high. This turns on the first switch SW1, electrically connecting the vertical output line 20 to the first voltage node 309. As the control signal PVLRES goes high, the voltage VINN increases at time t117. When the voltage VINN increases, the comparator 303 is in a reset state. To reset the comparator 303 to a predetermined voltage, a current is biased toward the second input transistor 401 in response to the increase in the voltage VINN. This causes a fluctuation in the threshold voltage of the second input transistor 401 due to hot carrier injection. Specifically, this hot carrier injection traps carriers, increasing the threshold voltage of the second input transistor 401. As a result, the threshold voltage changes that occur in the first input transistor 400 and the second input transistor 401 are approximately equal, and the first input transistor 400 and the second input transistor 401 can be considered to be approximately the same transistor. Therefore, the photoelectric conversion signal output from the second pixel 10-2 can be AD converted in the same way as if no threshold voltage fluctuation occurs.

[0069] In this embodiment, the AD conversion accuracy can be improved by the driving method shown in FIG. 7. In the driving method shown in FIG. 7, the direction in which the voltage of the vertical output line 20 changes when a pixel signal is input to the second input node INN is different from the direction in which the voltage of the vertical output line 20 changes when a first voltage is input to the second input node INN. Furthermore, consider a case in which the amount of light incident on the first pixel 10-1 is greater than the amount of light incident on the second pixel 10-2. In this case, the spurious increase in the light component signal read out from the second pixel 10-2 is suppressed, and an image substantially equivalent to the image originally obtained corresponding to the second pixel 10-2 is obtained, thereby improving the image quality of the obtained image.

[0070] Second Embodiment A photoelectric conversion device 1 according to a second embodiment of the present invention will be described with reference to Figures 8 and 9. Note that components similar to those in the first embodiment are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0071] This embodiment differs from the first embodiment in the configuration of the AD conversion circuit 21. Fig. 8 is an example of a circuit diagram of the AD conversion circuit 21 included in the photoelectric conversion device 1 according to this embodiment.

[0072] As shown in FIG. 8 , the AD conversion circuit 21 includes a fourth switch SW4. The fourth switch SW4 is electrically connected to a second input node INN and a connection node between the vertical output line 20 and the first switch SW1. The fourth switch SW4 is also disposed between the second input node INN and the connection node between the vertical output line 20 and the first switch SW1. The fourth switch SW4 is controlled by a control signal PVLON supplied from the control circuit 18 via a fourth switch control line 310. When the control signal PVLON goes high, the fourth switch SW4 is turned on, electrically connecting the connection node between the vertical output line 20 and the first switch SW1 to a node of the second capacitance element C2 on the pixel 10 side. On the other hand, when the control signal PVLON goes low, the fourth switch SW4 is turned off, electrically isolating the connection node between the vertical output line 20 and the first switch SW1 from the node of the second capacitance element C2 on the pixel 10 side.

[0073] FIG. 9 is an example of a drive timing chart for the photoelectric conversion device 1 according to this embodiment. In FIG. 9, the horizontal axis represents time and the vertical axis represents voltage. FIG. 9 also schematically shows the voltages of each control signal (timing of each drive pulse), the voltage VOUT, the voltage VRAMP, the voltage VINP at the first input node INP, and the voltage VINN at the second input node INN. Note that the voltage VINP is indicated by a solid line, while the voltage VINN is indicated by a dashed line. Note that each control signal shown in FIG. 9 corresponds to each control signal shown in FIGS. 2 and 8. Note that when a control signal is at a high level, the corresponding transistors and switches are turned on, and when the control signal is at a low level, the corresponding transistors and switches are turned off.

[0074] FIG. 9 shows the timing for reading pixel signals from the pixels 10 arranged in the first and second rows that are successively read out. Note that period T1 indicates the readout period for the pixel signal output from the first pixel 10-1, and period T2 indicates the readout period for the pixel signal output from the second pixel 10-2. Control signals PTX1, PRES1, and PSEL1 are control signals output to the first pixel 10-1, and control signals PTX2, PRES2, and PSEL2 are control signals output to the second pixel 10-2. Here, for example, it is assumed that the amount of light incident on the first pixel 10-1 is greater than the amount of light incident on the second pixel 10-2. Note that this embodiment differs from the first embodiment in that the control signal PVLON is changed from high to low at times t116 and t216, and from low to high at times t118 and t218.

[0075] At time t117, when the control signal PVLON is at a low level, the control signal PVLRES goes to a high level, as in the first embodiment, and the voltage VOUT increases. Then, at time t118, the control signal PVLON goes from a low level to a high level, and the voltage VINN also increases. The effect obtained by this series of operations to increase the voltage VINN is the same as in the first embodiment. This suppresses the effect of the change in threshold voltage occurring in the first input transistor 400, and improves the AD conversion accuracy of the pixel signal output from the second pixel 10-2 during the period T2.

[0076] In the first embodiment, if the parasitic capacitance of the vertical output line 20 is large, the time constant of the voltage fluctuation of the vertical output line 20 increases when the first switch SW1 is turned on and the vertical output line 20 is connected to the first voltage node 309. If the time constant of the voltage fluctuation of the vertical output line 20 is large, the comparator 303 remains in a reset state while the first switch SW1 is on. This prevents the voltage VINN from tracking the change in the voltage VOUT and from increasing to the desired voltage. In this embodiment, the fourth switch SW4 is appropriately controlled to sufficiently change the voltage VOUT before electrically connecting the vertical output line 20 to the node of the second capacitance element C2 on the pixel 10 side. Therefore, after turning on the fourth switch SW4, it is only necessary to drive the second capacitance element C2, which allows the voltage VINN to change sharply and increase to the desired voltage.

[0077] Third Embodiment A photoelectric conversion device 1 according to a third embodiment of the present invention will be described with reference to Figures 10 and 11. Note that components similar to those in the first and second embodiments are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0078] This embodiment differs from the first and second embodiments in the configuration of the AD conversion circuit 21. Fig. 10 is an example of a circuit diagram of the AD conversion circuit 21 included in the photoelectric conversion device 1 according to this embodiment.

[0079] As shown in FIG. 10 , the AD conversion circuit 21 includes a fourth switch SW4. The fourth switch SW4 is electrically connected to the pixel 10 and the connection node between the vertical output line 20 and the first switch SW1. The fourth switch SW4 is also arranged between the pixel 10 and the connection node between the vertical output line 20 and the first switch SW1. The fourth switch SW4 is controlled by a control signal PVLON supplied from the control circuit 18 via a fourth switch control line 310. When the control signal PVLON goes high, the fourth switch SW4 is turned on, electrically connecting the pixel 10 to the connection node between the vertical output line 20 and the first switch SW1. On the other hand, when the control signal PVLON goes low, the fourth switch SW4 is turned off, electrically disconnecting the pixel 10 from the connection node between the vertical output line 20 and the first switch SW1. The connection node between the vertical output line 20 and the first switch SW1 is also arranged between the fourth switch SW4 and the second capacitance element C2.

[0080] FIG. 11 is an example of a drive timing chart for the photoelectric conversion device 1 according to this embodiment. In FIG. 11, the horizontal axis represents time and the vertical axis represents voltage. FIG. 11 also schematically illustrates the voltages of each control signal (the timing of each drive pulse), the voltage VOUT, the voltage VRAMP, the voltage VINP at the first input node INP, and the voltage VINN at the second input node INN. The voltage VINP is indicated by a solid line, while the voltage VINN is indicated by a dashed line. The control signals shown in FIG. 11 correspond to the control signals shown in FIGS. 2 and 10. When a control signal is at a high level, the corresponding transistors and switches are turned on, and when the control signal is at a low level, the corresponding transistors and switches are turned off.

[0081] FIG. 11 shows the timing for reading pixel signals from the pixels 10 arranged in the first and second rows, which are successively read out. Note that period T1 indicates the readout period for the pixel signal output from the first pixel 10-1, and period T2 indicates the readout period for the pixel signal output from the second pixel 10-2. Control signals PTX1, PRES1, and PSEL1 are control signals output to the first pixel 10-1, and control signals PTX2, PRES2, and PSEL2 are control signals output to the second pixel 10-2. Here, for example, the amount of light incident on the first pixel 10-1 is assumed to be greater than the amount of light incident on the second pixel 10-2. Note that the driving during the periods from time t116 to time t119 and from time t216 to time t219 differs from that of the first and second embodiments.

[0082] At time t116, the control signal PVLON changes from high to low, and the node of the second capacitance element C2 on the pixel 10 side becomes floating. From time t117 to time t118, the control signal PVLRES changes to high, and the node of the second capacitance element C2 on the pixel 10 side is electrically connected to the first voltage node 309. Then, by increasing the voltage VINN, it is possible to improve the AD conversion accuracy of the pixel signal output from the second pixel 10-2 during the period T2. Note that the driving after the control signal PVLON changes from low to high at time t119 is the same as in the second embodiment.

[0083] In this embodiment, as in the second embodiment, the voltage VINN can be changed sharply and increased to a desired voltage. In the second embodiment, in order to sufficiently increase the voltage VINN, time was required to charge a portion of the vertical output line 20 arranged between the connection node between the vertical output line 20 and the first switch SW1 and the fourth switch SW4. In contrast, in this embodiment, the connection node between the vertical output line 20 and the first switch SW1 is arranged between the fourth switch SW4 and the second capacitance element C2. Therefore, the distance of the vertical output line 20 that needs to be charged is shorter than in the second embodiment. Therefore, in this embodiment, the voltage VINN can be changed more sharply and increased to a desired voltage in a short period of time.

[0084] Fourth Embodiment A photoelectric conversion device 1 according to a fourth embodiment of the present invention will be described with reference to Fig. 12. Note that components similar to those in the first, second, and third embodiments are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0085] This embodiment differs from the first, second, and third embodiments in the configuration of the AD conversion circuit 21. Fig. 12 is an example of a circuit diagram of the AD conversion circuit 21 included in the photoelectric conversion device 1 according to this embodiment.

[0086] As shown in FIG. 12 , the AD conversion circuit 21 includes a fourth switch SW4 and a fifth switch SW5. The fourth switch SW4 is electrically connected to the pixel 10 and a node of the second capacitance element C2 on the pixel 10 side. The fourth switch SW4 is also arranged between the pixel 10 and a node of the second capacitance element C2 on the pixel 10 side. The fourth switch SW4 is a switch controlled by a control signal PVLON supplied from the control circuit 18 via a fourth switch control line 310. When the control signal PVLON goes high, the fourth switch SW4 is turned on, electrically connecting the pixel 10 and the node of the second capacitance element C2 on the pixel 10 side. On the other hand, when the control signal PVLON goes low, the fourth switch SW4 is turned off, electrically isolating the pixel 10 and the node of the second capacitance element C2 on the pixel 10 side. The connection node between the vertical output line 20 and the first switch SW1 is arranged between the second capacitance element C2 and the comparator 303.

[0087] The fifth switch SW5 is electrically connected to the second voltage node 311 and the first input node INP. The fifth switch SW5 is also disposed between the second voltage node 311 and the first input node INP. The fifth switch SW5 is a switch controlled by a control signal PVLON_2 supplied from the control circuit 18 via a fifth switch control line 312. When the control signal PVLON_2 becomes high level, the fifth switch SW5 is turned on, electrically connecting the second voltage node 311 and the first input node INP. On the other hand, when the control signal PVLON becomes low level, the fifth switch SW5 is turned off, electrically separating the second voltage node 311 and the first input node INP. The fifth switch SW5 may be controlled to be turned on or off at the same timing as the first switch SW1, or may be controlled to be always off. A voltage substantially equal to the voltage supplied to the first voltage node 309 is supplied to the second voltage node 311.

[0088] Although the reference signal is input to the first input node INP, which is the non-inverting input terminal of the comparator 303, and the pixel signal is input to the second input node INN, which is the inverting input terminal, the configuration may be reversed. That is, the pixel signal may be input to the first input node INP, and the reference signal may be input to the second input node INN.

[0089] In the present embodiment, similarly to the first embodiment, the voltage VINN increases, thereby improving the AD conversion accuracy of the pixel signal output from the second pixel 10-2 in the period T2.

[0090] Furthermore, in this embodiment, as in the third embodiment, the voltage VINN can be changed sharply and increased to a desired voltage. In this embodiment, the distance of the vertical output line 20 that needs to be charged is shorter than in the third embodiment. Therefore, in this embodiment, the voltage VINN can be changed more sharply and increased to a desired voltage in a short period of time.

[0091] Furthermore, in this embodiment, by having a fifth switch SW5 in addition to the first switch SW1, the parasitic capacitances can be made approximately equal between the first input node INP and the second input node INN, thereby improving the accuracy of AD conversion.

[0092] Fifth Embodiment A photoelectric conversion device 1 according to a fifth embodiment of the present invention will be described with reference to Figures 13 to 15. Note that components similar to those in the first, second, third, and fourth embodiments are denoted by the same reference numerals, and descriptions of these components may be omitted or simplified.

[0093] This embodiment differs from the first, second, third, and fourth embodiments in the configuration of the AD conversion circuit 21. Fig. 13 is an example of a circuit diagram of the AD conversion circuit 21 included in the photoelectric conversion device 1 according to this embodiment.

[0094] 13, the AD conversion circuit 21 includes an amplifier 313, a second buffer circuit 314, a third capacitance element C3, a fourth capacitance element C4, a fifth capacitance element C5, a sixth switch SW6, a seventh switch SW7, and an eighth switch SW8. Between the pixel 10 and the comparator 303, the fourth switch SW4, the third capacitance element C3, the amplifier 313, the seventh switch SW7, the second buffer circuit 314, and the second capacitance element C2 are arranged in this order and electrically connected to each other.

[0095] The amplifier 313 has a third input node A which is a non-inverting input terminal, a fourth input node B which is an inverting input terminal, and an output node CAOUT. The vertical output line 20 is electrically connected to the fourth input node B via the third capacitance element C3. A pixel signal output from the pixel 10 is input to the fourth input node B via the vertical output line 20 and the third capacitance element C3. A voltage VC0R output from the control circuit 18 is input to the third input node A. The fourth capacitance element C4 is electrically connected to the output node CAOUT and the fourth input node B and is disposed between the output node CAOUT and the fourth input node B. The amplifier 313 applies a gain of (C3 / C4) to the input pixel signal (amplifies the signal by (C3 / C4)), and outputs the pixel signal. Note that in this specification, the voltage at the output node CAOUT of the amplifier 313 may be referred to as VCAOUT.

[0096] The sixth switch SW6 is electrically connected to the output node CAOUT and the fourth input node B, and is disposed between the output node CAOUT and the fourth input node B. The sixth switch SW6 is a switch controlled by a control signal PC0R supplied from the control circuit 18 via a sixth switch control line 316. When the control signal PC0R goes high, the amplifier 313 is reset.

[0097] The second buffer circuit 314 has an input node and an output node. The input node of the second buffer circuit 314 is supplied with a pixel signal from the pixel 10 via the amplifier 313. The output node of the second buffer circuit 314 is electrically connected to the second input node INN via the second capacitance element C2. That is, the pixel signal output from the pixel 10 is input to the second input node INN via the amplifier 313, the second buffer circuit 314, and the second capacitance element C2.

[0098] The seventh switch SW7 is electrically connected to the output node CAOUT and the input node of the second buffer circuit 314, and is disposed between the output node CAOUT and the input node of the second buffer circuit 314. The seventh switch SW7 is a switch controlled by a control signal PSH supplied from the control circuit 18 via a seventh switch control line 317.

[0099] The eighth switch SW8 is electrically connected to the input node of the second buffer circuit 314 and the ground voltage node GND, and is disposed between the input node of the second buffer circuit 314 and the ground voltage node GND. The eighth switch SW8 is a switch controlled by a control signal PCAORES supplied from the control circuit 18 via an eighth switch control line 318. When the control signal PCAORES goes high, the input node of the second buffer circuit 314 is electrically connected to the ground voltage node GND.

[0100] The fifth capacitance element C5 is electrically connected to the input node of the second buffer circuit 314 and the ground voltage node GND, and is disposed between the input node of the second buffer circuit 314 and the ground voltage node GND.

[0101] FIG. 14 is an example of a circuit diagram of the comparator 303 included in the AD conversion circuit 21 according to this embodiment.

[0102] 14, the comparator 303 has a differential stage and an amplification stage. The differential stage includes a fourth input transistor 500, a fifth input transistor 501, a third current source 502, a third current mirror transistor 503, and a fourth current mirror transistor 504. The fourth input transistor 500 is arranged corresponding to a third input node A, and the fifth input transistor 501 is arranged corresponding to a fourth input node B. The amplification stage includes a sixth input transistor 505 and a fourth current source 506.

[0103] The comparator 303 shown in FIG. 4 has a first input transistor 400, a second input transistor 401, and a third input transistor 405, which are configured with N-type MOS transistors. The comparator 303 shown in FIG. 4 also has a first current mirror transistor 403 and a second current mirror transistor 404, which are configured with P-type MOS transistors. On the other hand, the comparator 303 of this embodiment shown in FIG. 14 has a fourth input transistor 500, a fifth input transistor 501, and a sixth input transistor 505, which are configured with P-type MOS transistors. The comparator 303 of this embodiment shown in FIG. 14 also has a third current mirror transistor 503 and a fourth current mirror transistor 504, which are configured with N-type MOS transistors.

[0104] FIG. 15 is an example of a drive timing chart for the photoelectric conversion device 1 according to this embodiment. In FIG. 15, the horizontal axis represents time and the vertical axis represents voltage. FIG. 15 also schematically illustrates the voltages of each control signal (the timing of each drive pulse), the voltage VCAOUT, the voltage VRAMP, the voltage VINP at the first input node INP, and the voltage VINN at the second input node INN. The voltage VINP is indicated by a solid line, while the voltage VINN is indicated by a dashed line. The control signals shown in FIG. 15 correspond to the control signals shown in FIGS. 2 and 13. When a control signal is at a high level, the corresponding transistors and switches are turned on, and when the control signal is at a low level, the corresponding transistors and switches are turned off. In FIG. 15, the control signal PVLRES is always at a low level, and the control signal PVLON is always at a high level.

[0105] 15 shows the timing for reading pixel signals from the pixels 10 arranged in the first and second rows that are successively read out. Note that period T1 indicates the readout period for the pixel signal output from the first pixel 10-1, and period T2 indicates the readout period for the pixel signal output from the second pixel 10-2. Control signals PTX1, PRES1, and PSEL1 are control signals output to the first pixel 10-1, and control signals PTX2, PRES2, and PSEL2 are control signals output to the second pixel 10-2. Here, for example, it is assumed that the amount of light incident on the first pixel 10-1 is greater than the amount of light incident on the second pixel 10-2.

[0106] At time t100, the control signal PSEL1 changes from low to high, turning on the selection transistor 204 of the first pixel 10-1, and the first row is selected as the row from which the pixel signal is output.

[0107] During the period from time t101 to time t103, the control signal PRES1 goes high, turning on the reset transistor 205 of the first pixel 10-1, and the first pixel 10-1 outputs a noise signal as a pixel signal to the vertical output line 20 arranged in the corresponding column.

[0108] During the period from time t102 to time t104, the control signal PC0R goes high, turning on the fourth switch SW4, and the amplifier 313 enters a reset state, and the fourth input node B, which is the inverting input terminal, is reset to the voltage VC0R.

[0109] During the period from time t105 to time t111, the control signal PFB goes high, turning on the second switch SW2 and the third switch SW3. The first input node INP and the second input node INN of the comparator 303 are reset to the reset-level voltage. At time t110, the voltage VRAMP becomes the reference voltage, and the offset removal operation is performed.

[0110] At time t112, the voltage VRAMP decreases from the reference voltage to a predetermined start voltage. Next, during the period from time t113 to time t115, the voltage VRAMP increases from the start voltage in a time-dependent manner. Note that in this embodiment, the amplifier 313 is an inverting amplifier, and therefore the polarity of the output amplitude of the pixel signal input to the comparator 303 via the amplifier 313 differs from that of the first to fourth embodiments. Therefore, as shown in FIG. 15 , the voltage VRAMP is controlled to increase from the start voltage in a time-dependent manner, which differs from the first to fourth embodiments.

[0111] In addition to the difference in the polarity of the output amplitude as described above, the following describes how this embodiment differs from the above-described embodiments. This embodiment differs from the above-described embodiments in the driving during the period from time t106 to time t109 and the driving during the period from time t206 to time t209. Here, the driving during the period from time t206 to time t209 will be described as a representative example.

[0112] 15, the difference between voltages VINN and VINP is larger during the period from time t119 to time t120 and the period from time t219 to time t220 than during other periods. Furthermore, because the amount of light incident on the first pixel 10-1 is greater than the amount of light incident on the second pixel 10-2, the amount of change in voltage VOUT during period T1 is larger than during period T2. Therefore, the difference between voltages VOUT and VRAMP during the period from time t119 to time t120 is larger than during the period from time t219 to time t220. In other words, the difference between voltages VINN and VINP during the period from time t119 to time t120 is larger than during the period from time t219 to time t220. Therefore, the greater the amount of incident light, the larger the difference between voltages VINN and VINP, and the longer the period during which the difference between voltages VINN and VINP is greater than a predetermined amount.

[0113] In this embodiment, the period during which the potential difference between the source and gate of the fourth input transistor 500 is large is longer than that of the fifth input transistor 501. In such a case, a high voltage is applied to the fourth input transistor 500, causing a fluctuation in the threshold voltage of the fourth input transistor 500 due to hot carrier injection. Specifically, this hot carrier injection traps carriers, increasing the threshold voltage of the fourth input transistor 500. Then, as described in the first embodiment, the threshold of the fourth input transistor 500 included in the comparator 303 changes, resulting in a decrease in AD conversion accuracy.

[0114] In this embodiment, at time t205, the control signal PFB changes from low to high, starting the reset operation of the comparator 303. The period from time t205 to time t211, during which the control signal PFB is high, is the reset period of the comparator 303. From time t206 to time t209, the control signal PSH changes to low, rendering the amplifier 313 and the comparator 303 non-conductive. From time t207 to time t208, the control signal PCAORES changes to high. This turns on the eighth switch SW8, electrically connecting the second input node INN to the ground voltage node GND via the second capacitance element C2 and the second buffer circuit 314. As the control signal PCAORES changes to high, the voltage VINN decreases at time t207. When the voltage VINN decreases, the comparator 303 is in a reset state and is reset to a predetermined voltage, so that current is biased toward the fifth input transistor 501 in response to the decrease in the voltage VINN. This causes a fluctuation in the threshold voltage of the fifth input transistor 501 due to hot carrier injection. Specifically, this hot carrier injection traps carriers, increasing the threshold voltage of the fifth input transistor 501. As a result, the threshold voltage changes that occur in the fourth input transistor 500 and the fifth input transistor 501 are approximately equal, and the fourth input transistor 500 and the fifth input transistor 501 can be considered to be approximately the same transistor. Therefore, the photoelectric conversion signal output from the second pixel 10-2 can be AD converted in the same way as if there were no fluctuation in the threshold voltage.

[0115] In this embodiment, the AD conversion accuracy can be improved by the driving shown in Fig. 15. Furthermore, consider a case where the amount of light incident on the first pixel 10-1 is greater than the amount of light incident on the second pixel 10-2. In this case, a spurious increase in the light component signal read out from the second pixel 10-2 is suppressed, and an image substantially equivalent to the image originally obtained corresponding to the second pixel 10-2 is obtained, improving the image quality of the obtained image.

[0116] Sixth Embodiment The sixth embodiment can be applied to any of the first to fifth embodiments. FIG. 16(a) is a schematic diagram illustrating an apparatus 9191 including a semiconductor device 930 according to this embodiment. The photoelectric conversion device according to any of the above-described embodiments can be used for the semiconductor device 930. The apparatus 9191 including the semiconductor device 930 will be described in detail. The semiconductor device 930 can include a semiconductor device 910. The semiconductor device 930 can include, in addition to the semiconductor device 910, a package 920 that houses the semiconductor device 910. The package 920 can include a base to which the semiconductor device 910 is fixed and a lid such as glass that faces the semiconductor device 910. The package 920 can further include bonding members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910.

[0117] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and includes an optical system that guides light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0118] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0119] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0120] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0121] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft (drone, aircraft). The mechanical device 990 in the transportation equipment can be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0122] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0123] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0124] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS. 16(b) and 16(c).

[0125] FIG. 16(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 includes a photoelectric conversion device 1. The photoelectric conversion device 1 is the photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 8 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 1, and a parallax acquisition unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 8. Here, the photoelectric conversion system 8 may include an optical system (not shown) that guides light to the photoelectric conversion device 1, such as a lens, shutter, or mirror. Furthermore, multiple photoelectric conversion units that are approximately conjugate with the pupil of the optical system may be arranged in pixels of the photoelectric conversion device 1. For example, the multiple photoelectric conversion units that are approximately conjugate with the pupil are arranged corresponding to one microlens. The multiple photoelectric conversion units receive light beams that have passed through different positions on the pupil of the optical system, and the photoelectric conversion device 1 outputs image data corresponding to the light beams that have passed through the different positions. The parallax acquisition unit 802 may then calculate the parallax using the output image data. The photoelectric conversion system 8 also includes a distance acquisition unit 803 that calculates the distance to the object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information about the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may determine the possibility of a collision using any of this distance information. The distance information may be acquired using ToF (Time of Flight). The distance information acquisition means may be realized by dedicated hardware or a software module. It may also be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or the like, or a combination thereof.

[0126] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0127] In this embodiment, the photoelectric conversion system 8 captures an image of the surroundings of the vehicle, for example, the front or rear. Fig. 16(c) shows the photoelectric conversion system 8 when capturing an image of the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 1. This configuration can further improve the accuracy of distance measurement.

[0128] While the above describes an example of control to prevent collisions with other vehicles, the present invention can also be applied to other applications, such as autonomous driving control to follow other vehicles and autonomous driving control to prevent vehicles from drifting out of their lanes. Furthermore, the photoelectric conversion system 8 can be applied not only to automobiles and other vehicles, but also to moving bodies (mobile devices) such as ships, aircraft, and industrial robots. The moving body includes one or both of a driving force generator that generates a driving force primarily used to move the moving body and a rotating body primarily used to move the moving body. The driving force generator can be an engine, a motor, or the like. The rotating body can be a tire, a wheel, a ship's screw, an aircraft's propeller, or the like. In addition to moving bodies, the present invention can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0129] As used herein, expressions such as "A or B," "at least one of A and B," "at least one of A or / and B," "one or more of A or / and B," and the like, include all possible combinations of the listed items unless expressly defined otherwise. That is, the above expressions are understood to disclose all cases, including cases containing at least one A, cases containing at least one B, and cases containing both at least one A and at least one B. This applies equally to combinations of three or more elements.

[0130] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration.

[0131] The disclosure of this embodiment includes the following configurations.

[0132] (Method 1) A method for driving a photoelectric conversion device comprising: a pixel that generates a pixel signal by photoelectric conversion; an output line electrically connectable to the pixel; and a comparator having a first input node to which a reference signal is input and a second input node to which the pixel signal is input via the output line, wherein during a reset period of the comparator, a first voltage is input to the second input node, and the direction in which the voltage of the output line changes when the pixel signal is input to the second input node is different from the direction in which the voltage of the output line changes when the first voltage is input to the second input node.

[0133] (Method 2) The method for driving a photoelectric conversion device described in Method 1, characterized in that the pixels are arranged in multiple rows, the pixels include a first pixel arranged in a first row and a second pixel arranged in a second row, and the comparator is reset between the timing when a pixel signal is output from the first pixel and the timing when a pixel signal is output from the second pixel.

[0134] (Method 3) The method for driving a photoelectric conversion device described in Method 1 or 2, characterized in that the comparator has a first input transistor corresponding to the first input node and a second input transistor corresponding to the second input node, and the threshold voltage of the second input transistor changes when the first voltage is input to the second input node during a reset period of the comparator.

[0135] (Method 4) 4. A method for driving a photoelectric conversion device according to any one of Methods 1 to 3, characterized in that the threshold voltage of the first input transistor changes when the pixel signal is input to the second input node, and the amount of change in the threshold voltage of the first input transistor and the amount of change in the threshold voltage of the second input transistor are approximately equal.

[0136] (Method 5) A method for driving a photoelectric conversion device described in any one of Methods 1 to 4, characterized in that the photoelectric conversion device includes a capacitive element electrically connected between the output line and the second input node, and the first voltage is input to the second input node via the capacitive element during a reset period of the comparator.

[0137] (Method 6) A method for driving a photoelectric conversion device described in any one of methods 1 to 5, characterized in that the photoelectric conversion device comprises a first voltage node electrically connectable to the output line and supplied with the first voltage, and a first switch arranged between the first voltage node and the output line, and the first switch is controlled from off to on during a reset period of the comparator.

[0138] (Method 7) The photoelectric conversion device is characterized in that the first switch has a first node connected to the first voltage node and a second node connected to the output line, and a fourth switch is arranged between the second node and the comparator, and the first switch is controlled from off to on during a period when the fourth switch is off.

[0139] (Method 8) A method for driving a photoelectric conversion device described in any one of methods 1 to 7, characterized in that the photoelectric conversion device includes a fourth switch arranged between the second node and the pixel, the first switch having a first node connected to the first voltage node and a second node connected to the output line, and the first switch being controlled from off to on during a period when the fourth switch is off.

[0140] (Method 9) A method for driving a photoelectric conversion device described in any one of Methods 1 to 8, characterized in that the photoelectric conversion device comprises a second voltage node electrically connectable to the first input node, and a fifth switch arranged between the second voltage node and the first input node, and the fifth switch is controlled to change from off to on at approximately the same timing as the first switch.

[0141] (Method 10) 10. A method for driving a photoelectric conversion device according to any one of methods 1 to 9, wherein the photoelectric conversion device comprises an amplifier arranged between the pixel and the comparator, and the amplifier amplifies the pixel signal.

[0142] (Method 11) A method for driving a photoelectric conversion device described in any one of methods 1 to 10, characterized in that the comparator has a second switch and a third switch for resetting the threshold voltage of the comparator, and the comparator is reset when the second switch and the third switch are turned on.

[0143] (Method 12) 12. The method for driving a photoelectric conversion device according to any one of Methods 1 to 11, wherein the first voltage is a power supply voltage.

[0144] (Method 13) 13. A method for driving a photoelectric conversion device according to any one of methods 1 to 12, wherein the comparator performs analog-to-digital (AD) conversion of the pixel signal by comparing the pixel signal with the reference signal.

[0145] (Configuration 1) A photoelectric conversion device comprising: a pixel that generates a pixel signal by photoelectric conversion; an output line electrically connectable to the pixel; a comparator having a first input node to which a reference signal is input and a second input node to which the pixel signal is input via the output line; a first switch arranged between a first voltage node and the output line; and a control circuit that controls the first switch, wherein the control circuit controls the first switch from off to on during a reset period of the comparator.

[0146] (Configuration 2) The photoelectric conversion device described in configuration 1, characterized in that the comparator has a first input transistor corresponding to the first input node and a second input transistor corresponding to the second input node, and during a reset period of the comparator, the first voltage is input from the first voltage node to the second input node, thereby changing the threshold voltage of the second input transistor.

[0147] (Configuration 3) The photoelectric conversion device according to configuration 1 or 2, characterized in that when the pixel signal is input to the second input node, the threshold voltage of the first input transistor changes, and the amount of change in the threshold voltage of the first input transistor and the amount of change in the threshold voltage of the second input transistor are approximately equal.

[0148] (Configuration 4) An apparatus comprising the photoelectric conversion device according to any one of configurations 1 to 3, further comprising at least one of an optical device that guides light to the photoelectric conversion device, a control device that controls the photoelectric conversion device, a processing device that processes signals output from the photoelectric conversion device, a display device that displays information obtained by the photoelectric conversion device, a storage device that stores information obtained by the photoelectric conversion device, and a mechanical device that operates based on the information obtained by the photoelectric conversion device. [Explanation of symbols]

[0149] 10 pixels 20 vertical output lines 303 Comparator 309 First Voltage Node INP First input node INN Second input node

Claims

1. a pixel that generates a pixel signal by photoelectric conversion; an output line electrically connectable to the pixel; a comparator having a first input node to which a reference signal is input and a second input node to which the pixel signal is input via the output line; A method for driving a photoelectric conversion device comprising: a first voltage is input to the second input node during a reset period of the comparator; A direction in which the voltage of the output line changes when the pixel signal is input to the second input node is different from a direction in which the voltage of the output line changes when the first voltage is input to the second input node. A method for driving a photoelectric conversion device.

2. 2. The method for driving a photoelectric conversion device according to claim 1, wherein the pixels are arranged in a plurality of rows, the pixels include a first pixel arranged in a first row and a second pixel arranged in a second row, and the comparator is reset between the timing at which a pixel signal is output from the first pixel and the timing at which a pixel signal is output from the second pixel.

3. 2. The method for driving a photoelectric conversion device according to claim 1, wherein the comparator has a first input transistor corresponding to the first input node and a second input transistor corresponding to the second input node, and the threshold voltage of the second input transistor changes when the first voltage is input to the second input node during a reset period of the comparator.

4. 4. The method for driving a photoelectric conversion device according to claim 3, wherein the threshold voltage of the first input transistor changes when the pixel signal is input to the second input node, and the amount of change in the threshold voltage of the first input transistor and the amount of change in the threshold voltage of the second input transistor are approximately equal.

5. the photoelectric conversion device includes a capacitance element electrically connected between the output line and the second input node, 2. The method for driving a photoelectric conversion device according to claim 1, wherein the first voltage is input to the second input node via the capacitive element during a reset period of the comparator.

6. the photoelectric conversion device includes: a first voltage node electrically connectable to the output line and supplied with the first voltage; and a first switch disposed between the first voltage node and the output line; 2. The method for driving a photoelectric conversion device according to claim 1, wherein the first switch is controlled to change from off to on during a reset period of the comparator.

7. the photoelectric conversion device includes a fourth switch, the first switch having a first node connected to the first voltage node and a second node connected to the output line, and the fourth switch being disposed between the second node and the comparator; 7. The method for driving a photoelectric conversion device according to claim 6, wherein the first switch is controlled to change from OFF to ON during a period in which the fourth switch is OFF.

8. the photoelectric conversion device includes a fourth switch, the first switch having a first node connected to the first voltage node and a second node connected to the output line, and the fourth switch being disposed between the second node and the pixel; 7. The method for driving a photoelectric conversion device according to claim 6, wherein the first switch is controlled to change from OFF to ON during a period in which the fourth switch is OFF.

9. the photoelectric conversion device includes a second voltage node electrically connectable to the first input node, and a fifth switch disposed between the second voltage node and the first input node; 7. The method for driving a photoelectric conversion device according to claim 6, wherein the fifth switch is controlled to be turned on from off at substantially the same timing as the first switch.

10. 2. The method for driving a photoelectric conversion device according to claim 1, wherein the photoelectric conversion device includes an amplifier disposed between the pixel and the comparator, and the amplifier amplifies the pixel signal.

11. 2. The method for driving a photoelectric conversion device according to claim 1, wherein the comparator has a second switch and a third switch for resetting the threshold voltage of the comparator, and the comparator is reset when the second switch and the third switch are turned on.

12. 2. The method for driving a photoelectric conversion device according to claim 1, wherein the first voltage is a power supply voltage.

13. 2. The method for driving a photoelectric conversion device according to claim 1, wherein the comparator performs analog-to-digital (AD) conversion of the pixel signal by comparing the pixel signal with the reference signal.

14. a pixel that generates a pixel signal by photoelectric conversion; an output line electrically connectable to the pixel; a comparator having a first input node to which a reference signal is input and a second input node to which the pixel signal is input via the output line; a first switch disposed between a first voltage node and the output line; a control circuit for controlling the first switch; A photoelectric conversion device comprising: The control circuit controls the first switch from OFF to ON during a reset period of the comparator. A photoelectric conversion device characterized by:

15. 15. The photoelectric conversion device of claim 14, wherein the comparator has a first input transistor corresponding to the first input node and a second input transistor corresponding to the second input node, and the threshold voltage of the second input transistor changes when the first voltage is input from the first voltage node to the second input node during a reset period of the comparator.

16. 16. The photoelectric conversion device according to claim 15, wherein the threshold voltage of the first input transistor changes when the pixel signal is input to the second input node, and the amount of change in the threshold voltage of the first input transistor and the amount of change in the threshold voltage of the second input transistor are approximately equal.

17. An apparatus comprising the photoelectric conversion device according to claim 14, an optical device that guides light to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

Images