Semiconductor device

Abstract

To provide a semiconductor device with a novel structure.SOLUTION: A calculation block 21_O includes a storage circuit part 30 that holds a plurality of pieces of first weight data, a calculation circuit 45, a first switch circuit (switch circuit 42), and a second switch circuit (switch circuit 44). The first switch circuit applies any of the pieces of first weight data to a first wire WOL. The second switch circuit applies any of the applied first weight data or second weight data applied to a second wire WEL to a first calculation circuit (calculation circuit 45). A calculation block 21_E includes a storage circuit part 30 that holds a plurality of pieces of second weight data, a second calculation circuit (calculation circuit 45), a third switch circuit (switch circuit 42), and a fourth switch circuit (switch circuit 44). The third switch circuit applies any of the pieces of second weight data to the second wire WEL. The fourth switch circuit applies any of the applied first weight data or the second weight data applied to the second wire to the second calculation circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention is a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, etc. , storage devices, display systems, electronic devices, lighting devices, input devices, input / output devices, and their driving The method, or the method for producing the same, can be mentioned as an example. [Background technology]

[0003] A semiconductor device including a CPU (Central Processing Unit) Electronic devices that process large amounts of data at high speed are becoming widespread. Therefore, there is active development of technologies to improve the performance of semiconductor devices. For example, applications such as GPUs (Graphics Processing Units) SoC (System on Chip) is a system that tightly couples the accelerator and CPU. With the development of SoCs, semiconductor devices have become more powerful, but they also generate more heat and consume more power. It becomes a problem.

[0004] In AI (Artificial Intelligence) technology, the number of parameters is The increase in the amount of calculations leads to an increase in heat generation and power consumption. Therefore, architectures to reduce the amount of calculations have been actively proposed. As an architecture, Binary Neural Network (BNN) and and Ternary Neural Network (TNN), which reduce the circuit scale, This is particularly effective for reducing power consumption (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 078924 Summary of the Invention [Problem to be solved by the invention]

[0006] AI technology requires faster calculation processing. To speed up calculation processing, circuit integration is required. The weight data (also called weight parameters, filters, etc.) and the input data are By integrating the calculation circuit that performs the calculation with the memory circuit that stores the weight data, AI technology In this case, the operation can be realized by an integrated circuit through wiring such as bit lines. The necessary data such as weight data is read from the memory circuit to the arithmetic circuit. In the path electrically connecting the circuit and the arithmetic circuit, the frequency of reading data such as weight data is high. Therefore, the charge and discharge energy of the bit line increases, and there is a risk that power consumption will increase. do.

[0007] In particular, in neural networks that perform convolutional operations, the same weight data is used by multiple operation circuits. In this case, the memory circuit and the arithmetic circuit may be configured to perform arithmetic processing using a memory. As the number of electrical connection paths increases, it is necessary to read weight data and other data at high speed. In this case, it may be difficult to charge and discharge the wiring at high speed. It may become difficult to improve the

[0008] In order to reduce the charge and discharge energy of the bit line, it is effective to shorten the bit line. However, since the arithmetic circuits and memory circuits are arranged alternately, the peripheral circuits There is a risk that the road area will increase significantly.

[0009] An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another embodiment of the present invention is to provide a semiconductor device with improved arithmetic processing speed. Another object of one embodiment of the present invention is to provide a miniaturized semiconductor device. Another object of the present invention is to provide a semiconductor device with a novel structure.

[0010] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but It is sufficient if the invention can solve at least one of the problems. Other issues than these are not covered by the description, claims, drawings, etc. It becomes clear from the description, claims, drawings, etc. It is possible to extract other issues besides these. [Means for solving the problem]

[0011] One aspect of the present invention is a first processing block including a first memory circuit unit and a first processing circuit unit. a second calculation block having a second memory circuit unit and a second calculation circuit unit; a first wiring; and a second wiring, and the first memory circuit unit includes a first memory circuit for storing a plurality of first weight data. the second memory circuit unit has a second memory circuit for storing a plurality of second weight data; The arithmetic circuit unit has a first arithmetic circuit, a first switching circuit, and a third switching circuit, and a second arithmetic circuit The path unit includes a second arithmetic circuit, a second switching circuit, and a fourth switching circuit, and the first switching circuit includes: The second switching circuit has a function of providing one of the plurality of first weight data to the first wiring, The third switching circuit has a function of providing one of the second weight data of the first number to the second wiring, Either the first weight data given to the wiring or the second weight data given to the second wiring The fourth switching circuit has a function of supplying one of the first signals to the first arithmetic circuit, and the fourth switching circuit has a function of supplying one of the first signals to the first wiring. Either the weight data or the second weight data given to the second wiring is sent to the second calculation circuit. The semiconductor device has a function of providing the above.

[0012] One aspect of the present invention is a first processing block including a first memory circuit unit and a first processing circuit unit. a second calculation block having a second memory circuit unit and a second calculation circuit unit; a first wiring; and a second wiring, and the first memory circuit unit includes a first memory circuit for storing a plurality of first weight data. the second memory circuit unit has a second memory circuit for storing a plurality of second weight data; The arithmetic circuit unit has a first arithmetic circuit, a first switching circuit, and a third switching circuit, and a second arithmetic circuit The path unit includes a second arithmetic circuit, a second switching circuit, and a fourth switching circuit, and the first switching circuit includes: The second switching circuit has a function of providing one of the plurality of first weight data to the first wiring, a function of providing any one of a number of second weight data to the second wiring, and a number of first weight data The operation of providing any one of the plurality of second weight data to the first wiring is performed by providing any one of the plurality of second weight data to the second wiring. The third switching circuit is configured to switch the first weight data provided to the first wiring during a period different from the period when the first weight data is provided to the first wiring. and providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the first arithmetic circuit. The fourth switching circuit has a function of switching the first weight data given to the first wiring or the second wiring and the second weight data given to the first distribution circuit, The operation of providing the first weight data given to the line to the first arithmetic circuit is This is a semiconductor device in which the operation of providing the two weighted data to the second arithmetic circuit is performed in a different period from the operation of providing the two weighted data to the second arithmetic circuit.

[0013] In one embodiment of the present invention, the first memory circuit unit is stacked on a layer having the first arithmetic circuit unit. The second memory circuit section is provided in a layer stacked on the layer having the second arithmetic circuit section. The semiconductor device is preferably a semiconductor device that can

[0014] In one aspect of the present invention, the first arithmetic circuit and the second arithmetic circuit each independently perform a multiply-accumulate operation. A semiconductor device that performs arithmetic processing is preferred.

[0015] In one embodiment of the present invention, the first memory circuit unit and the second memory circuit unit each include a first transistor. the first transistor has a semiconductor layer having a metal oxide in a channel formation region; A semiconductor device having the above structure is preferred.

[0016] In one embodiment of the present invention, the metal oxide is a semiconductor device containing In, Ga, and Zn. Positioning is preferred.

[0017] In one aspect of the present invention, the first arithmetic circuit unit and the second arithmetic circuit unit each include a second transistor. the second transistor has a semiconductor layer having silicon in a channel formation region; The semiconductor device preferably has the following characteristics.

[0018] Other aspects of the present invention will be described in the following embodiments and and as described in the drawings. [Effects of the Invention]

[0019] One embodiment of the present invention can provide a semiconductor device with low power consumption. One embodiment of the present invention can provide a semiconductor device with improved processing speed. Alternatively, one embodiment of the present invention can provide a miniaturized semiconductor device. A semiconductor device with a novel configuration can be provided.

[0020] The description of a plurality of effects does not preclude the existence of other effects. It is not necessary to have all of the effects exemplified above. Problems, effects, and novel features other than those described above can be easily understood from the description and drawings of this specification. It will become clear as time goes by. [Brief explanation of the drawings]

[0021] [Figure 1] 1A, 1B, and 1C are diagrams illustrating configuration examples of a semiconductor device. [Figure 2] 2A, 2B, 2C, and 2D are diagrams illustrating configuration examples of a semiconductor device. [Figure 3] 3A, 3B, and 3C are diagrams illustrating configuration examples of semiconductor devices. [Figure 4] 4A and 4B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 5] 5A and 5B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 6] FIG. 6 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 7] 7A and 7B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 8] FIG. 8 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 9] FIG. 9 is a diagram illustrating a configuration example of a semiconductor device. [Figure 10] 10A and 10B are diagrams illustrating a configuration example of a semiconductor device. [Figure 11] 11A and 11B are diagrams illustrating a configuration example of a semiconductor device. [Figure 12] FIG. 12 is a diagram illustrating a configuration example of a semiconductor device. [Figure 13] FIG. 13 is a timing chart illustrating an example of the operation of the semiconductor device. [Figure 14] FIG. 14 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 15] FIG. 15 is a diagram illustrating a configuration example of a semiconductor device. [Figure 16] 16A and 16B are diagrams illustrating a configuration example of a semiconductor device. [Figure 17] FIG. 17 is a diagram illustrating an example of the configuration of a processing system. [Figure 18] FIG. 18 is a diagram illustrating an example of the configuration of a CPU. [Figure 19] 19A and 19B are diagrams illustrating an example of the configuration of a CPU. [Figure 20] FIG. 20 is a timing chart showing an example of the operation of the CPU. [Figure 21] FIG. 21 is a diagram illustrating an example of the configuration of a transistor. [Figure 22] 22A and 22B are diagrams showing examples of the configuration of a transistor. [Figure 23] 23A and 23B are diagrams illustrating an example of the configuration of an integrated circuit. [Figure 24] 24A and 24B are diagrams illustrating an application example of an integrated circuit. [Figure 25] 25A and 25B are diagrams illustrating an application example of an integrated circuit. [Figure 26] 26A, 26B, and 26C are diagrams illustrating an application example of an integrated circuit. [Figure 27] FIG. 27 is a diagram illustrating an application example of an integrated circuit. DETAILED DESCRIPTION OF THE INVENTION

[0022] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description. The present invention is not limited to the above, and various modifications and variations in form and detail may be made without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified as follows. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0023] In this specification, the ordinal numbers "first," "second," and "third" refer to the constituent elements. The numbers are added to avoid confusion and do not limit the number of components. The order of the components is not limited. The element referred to as "first" in one embodiment may be used in other embodiments or in the claims. In addition, for example, the second component may be the component referred to as "second" in this specification. A component referred to as "first" in one embodiment may be used in other embodiments, or It may be omitted in the claims.

[0024] In the drawings, elements that are the same or have similar functions, elements that are made of the same material, or In some cases, elements formed at the same time may be given the same reference numerals, and repeated explanations thereof will be omitted. This may occur.

[0025] In this specification, for example, the power supply potential VDD is abbreviated as potential VDD, VDD, etc. This may be due to the presence of other components (e.g., signals, voltages, circuits, elements, electrodes, wiring, etc.). The same applies to (etc.).

[0026] Also, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, The code is followed by an identifying code such as "_1", "_2", "[n]", or "[m,n]". For example, the second wiring GL is written as wiring GL[2].

[0027] (Embodiment 1) The structure, operation, and the like of a semiconductor device according to one embodiment of the present invention will be described.

[0028] In this specification and the like, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. device, lighting device, electro-optical device, power storage device, memory device, semiconductor circuit, imaging device, electronic device etc. may be said to have a semiconductor device.

[0029] FIG. 1A is a diagram illustrating a semiconductor device 10 according to an embodiment of the present invention. 1B and 1C are diagrams for explaining configuration examples of the processing blocks included in the semiconductor device 10. .

[0030] The semiconductor device 10 executes a program (kernel or It also functions as an accelerator, executing programs called kernel programs. The semiconductor device 10 is suitable for, for example, parallel processing of matrix operations in graphic processing, neural networks, and the like. Parallel processing of multiply-and-accumulate operations in neural networks, parallel processing of floating-point operations in scientific and technological computing etc. can be done.

[0031] As shown in FIG. 1A, the semiconductor device 10 includes a plurality of operation blocks 21. The block 21 includes a memory circuit section 30 (also called a memory cell array) and an arithmetic circuit section 40. As shown in FIG. 1A, the memory circuit section 30 and the arithmetic circuit section 40 have: xy The layers are arranged in different directions (z direction in FIG. 1A) approximately perpendicular to the plane. The memory circuit section 30 and the arithmetic circuit section 40 are stacked.

[0032] "Approximately vertical" refers to an arrangement at an angle between 85 degrees and 95 degrees. In this specification, the X direction, Y direction, and Z direction shown in FIG. 1A etc. are mutually exclusive. The X and Y directions are either perpendicular or intersecting with each other. The Z direction is perpendicular or approximately perpendicular to the substrate surface.

[0033] The multiple processing blocks shown in FIG. 1A are two or more blocks with different operations and connection relationships. In this specification, a plurality of processing blocks are divided into odd-numbered processing blocks. Although the description will be given assuming that the lock unit 20_O and the even-numbered operation block unit 20_E are used, if three or more blocks are used, The operation blocks in the operation block section 20_O may be divided into operation blocks. The operation block in the operation block section 20_E is sometimes called an operation block 21_O. It may be called Lock 21_E.

[0034] The operation block 21_O and the operation block 21_E are shown in FIGS. 1B and 1C. As shown, each block has a memory circuit section 30 and an arithmetic circuit section 40. In the configurations shown in the block 21_0 and the block 21_E, the common parts are explained in the same way. The explanation can be used as appropriate.

[0035] The memory circuit unit 30 has a plurality of memory circuits 31. The memory circuit unit 30 is a memory cell array The memory circuit 31 may be called a memory cell. The drive circuit 12 and the drive circuit 13 control the readout. 13 is also called a data control circuit.

[0036] The memory circuit 31 included in the memory circuit portion 30 is a transistor having an oxide semiconductor in a channel formation region. The data stored (held) in the memory circuit 31 is Data corresponding to the weight parameters used in the product-sum operation of the neural network ( The weight data is digital data, which makes it resistant to noise and fast. The weight data can be analog data. good.

[0037] The weight data is calculated using 1-bit data (i.e., data of '1' or '0'). It may be configured to perform processing, or may be configured to perform arithmetic processing using multi-bit data. For multi-bit (for example, n-bit) data, use the number of wires corresponding to the number of bits. The weight data may be supplied in this manner.

[0038] The memory circuit 31 included in the memory circuit unit 30 can have a NOSRAM circuit configuration. "NOSRAM (registered trademark)" means "Nonvolatile Oxide Semiconductor NOSRAM is an abbreviation for "semiconductor RAM." NOSRAM is a memory cell with two transistors. It is a 2T or 3T gain cell, and the access transistor This refers to memory in which the transistors are OS transistors.

[0039] In the off state, an OS transistor has a leakage current, which is a current that flows between the source and drain. NOSRAM responds to data with extremely low leakage current characteristics. By storing the charge in the memory circuit, it can be used as a nonvolatile memory. NOSRAM is capable of reading data without destroying it (non-destructive read). Since it is possible to read data repeatedly, neural networks This is suitable for parallel processing of multiply-and-accumulate operations.

[0040] The memory circuit 31 has an OS transistor such as NOSRAM or DOSRAM. A memory that functions as an oxide semiconductor (hereinafter also referred to as an OS memory) is suitable. Since the band gap of metal oxides is 2.5 eV or more, OS transistors have a very small off-state potential. As an example, when the voltage between the source and drain is 3.5V and the temperature is 25°C, The off-current per 1 μm of channel width is 1×10 -20 Less than A, 1 x 10 -22 A Full, or 1 x 10 -24 A. Therefore, the OS memory can be The amount of charge leaking from the storage node through the transistor is extremely small. Since the memory can function as a nonvolatile storage circuit, the power gating of the semiconductor device 10 This becomes possible.

[0041] Semiconductor devices with highly integrated transistors may generate heat due to circuit operation. This heat generation can cause the temperature of the transistor to rise, which can affect the characteristics of the transistor. This can cause changes in the field-effect mobility and a decrease in operating frequency. Since the transistor has higher heat resistance than the Si transistor, the field effect transfer caused by temperature changes is The change in the operating frequency is also unlikely to occur. The drain current of a transistor is an exponential function of the gate-source voltage, even at high temperatures. Therefore, by using OS transistors, high This allows stable operation in a wide temperature environment.

[0042] Metal oxides used in OS transistors include Zn oxide, Zn-Sn oxide, and Ga- Sn oxide, In-Ga oxide, In-Zn oxide, In-M-Zn oxide (M is Ti , Ga, Y, Zr, La, Ce, Nd, Sn or Hf). When metal oxides using ZnO are used in OS transistors, the ratio of elements can be adjusted to This is preferable because it allows a transistor to have excellent electrical characteristics such as field effect mobility. In addition, oxides containing indium and zinc are mixed with aluminum, gallium, yttrium, copper, , vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, Zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, The alloy may contain one or more elements selected from the group consisting of tungsten, magnesium, and the like.

[0043] Metal oxides applied to the semiconductor layer to improve the reliability and electrical properties of OS transistors are metal oxides with crystalline parts such as CAAC-OS, CAC-OS, and nc-OS. CAAC-OS is a c-axis-aligned crystal CAC-OS is an abbreviation for line oxide semiconductor. Cloud-Aligned Composite oxide semiconductor nc-OS is an abbreviation of nanocrystalline oxide. It is an abbreviation for semiconductor.

[0044] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted by the connection of multiple nanocrystals. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. Indicates the point where the direction is changing.

[0045] CAC-OS has the function of flowing electrons (or holes) that act as carriers, and the function of discharging the electrons that act as carriers. The function of allowing electrons to flow and the function of not allowing electrons to flow are separated. In other words, CAC-OS can be used as an OS transition. By using it in the channel formation region of a semiconductor, it is possible to achieve both a high on-current and an extremely low off-current. This can be achieved.

[0046] Metal oxides have a large band gap, which makes it difficult for electrons to be excited, and the effective quality of holes is Due to the large amount of silicon, OS transistors are less costly than conventional Si transistors. Therefore, for example, avalanche breakdown may not occur easily. By suppressing hot carrier degradation, high drive The OS transistor can be driven by the drain voltage.

[0047] OS transistors are accumulation-type transistors that use electrons as majority carriers. , it is shorter than an inversion transistor (typically a Si transistor) having a pn junction. One of the channel effects is the drain-induced barrier loss (DIBL). In other words, OS transistors have a lower power dissipation than Si transistors. Also, it has high resistance to short channel effects.

[0048] OS transistors have high resistance to short channel effects, By using OS transistors, the channel length can be reduced without degrading reliability. The degree of circuit integration can be increased. As the channel length becomes smaller, the drain electric field becomes stronger. However, as mentioned above, OS transistors have a higher avalanche breakdown rate than Si transistors. is less likely to occur.

[0049] In addition, OS transistors have high resistance to short channel effects, making them superior to Si transistors. For example, the channel length and the channel Even for miniaturized transistors with widths of 50 nm or less, a gate insulating film as thick as 10 nm is required. It may be possible to reduce the parasitic capacitance by making the gate insulating film thicker. This allows for faster operation of the circuit. This reduces the leakage current through the gate insulating film, which leads to a reduction in static current consumption.

[0050] As described above, the semiconductor device 10 has the storage circuit 31 which is an OS memory, and therefore the power supply voltage Therefore, the power gating of the semiconductor device 10 is This makes it possible to significantly reduce power consumption.

[0051] The memory circuit unit 30 of the operation block 21_0 may be referred to as a first memory circuit unit. The memory circuit unit 30 of the operation block 21_E may be referred to as a second memory circuit unit. The memory circuit 31 of the memory circuit unit 30 of the clock 21_0 may be referred to as a first memory circuit. The memory circuit 31 of the memory circuit unit 30 of the operation block 21_E may be referred to as a second memory circuit. The weight data stored in the memory circuit 31 of the memory circuit unit 30 of the calculation block 21_0 is The weight data may be referred to as the first weight data. The weight data stored in the path 31 may be referred to as second weight data. This weight data is different from the second weight data.

[0052] The layer having the arithmetic circuit section 40 includes a latch circuit 41, a switching circuit 42, a buffer circuit 43_0, and a (43_E), a switching circuit 44, and an arithmetic circuit 45. The control and processing of input and output are controlled by a control circuit 14 and a processing circuit 15. The circuit 14 and the processing circuit 15 are also called an arithmetic control circuit, an arithmetic processing circuit, or an arithmetic circuit.

[0053] Latch circuit 41, switching circuit 42, buffer circuit 43_O (43_E), switching circuit 44, Each circuit of the arithmetic circuit 45 is a transistor having silicon in the channel forming region (Si transistor). This configuration allows for high-speed switching of the connection state. Alternatively, the configuration may be such that calculation processing is performed.

[0054] Also, the latch circuit 41, the switching circuit 42, the buffer circuit 43_O (43_E), the switching circuit 4 4. Each circuit of the arithmetic circuit 45 is made of Si transistor, so that it can be stacked with OS transistor. That is, the memory circuit portion 30 formed of OS transistors can be provided as It can be stacked with the arithmetic circuit section 40 which can be configured with i-transistors. Therefore, the area in which the memory circuit section 30 can be arranged can be increased without increasing the circuit area. The area where the memory circuit section 30 is provided is on the substrate where the arithmetic circuit section 40 is provided. As a result, compared to when the memory circuit section 30 and the arithmetic circuit section 40 are arranged on the same layer, In this case, the memory capacity required for the arithmetic processing in the semiconductor device 10 functioning as an accelerator is increased. The increased memory capacity allows for faster transfer of calculations from external storage devices to semiconductor devices. This reduces the number of data transfers required for processing, which leads to lower power consumption. Cut.

[0055] The latch circuit 41 is connected to the wiring (local bit The ability to hold multiple weighted data that are read out via the data lines (also called read bit lines) The latch circuit 41 can be omitted if necessary.

[0056] The wiring connected to the memory circuit 31 of the memory circuit unit 30 is connected from the memory circuit unit 30 to the latch circuit It is preferable to make the length short in order to read out the weight data to the memory circuit section 41 at high speed. The wiring connected to the memory circuit 31 of 30 is It is preferable to shorten the time period. The physical distance between the memory circuit unit 30 and the memory circuit unit 30 is reduced, for example, by stacking the memory circuit unit 30 and the memory circuit unit 30. By shortening the distance, the parasitic capacitance generated in the signal line can be reduced, which enables lower power consumption. is.

[0057] The switching circuit 42 selects one of the weight data held in the latch circuit 41. The switching circuit 42 outputs the signal to the buffer circuit 43_O (43_E). The switching circuit 42 has a function of selecting one of a plurality of input signals. The control signal lsel that controls the switching circuit 42 is , control signal lsel_O, and in the arithmetic circuit unit 40 of the arithmetic block 21_E, the control signal lse 1_E, and they can be controlled separately. The switching circuit 42 of the operation block 21_E may be referred to as a first switching circuit. The switching circuit 42 of the circuit section 40 may be referred to as a third switching circuit.

[0058] The buffer circuit 43_O is a switching circuit in the arithmetic circuit unit 40 of the arithmetic block 21_O. The weight data selected by 42 is transmitted to the wiring WOL. In the calculation circuit section 40 of the block 21_E, the weight data selected by the switching circuit 42 is transmitted to the wiring W The buffer circuits 43_O and 43_E function as tri-state buffer circuits. The buffer circuits 43_O and 43_E are configured to receive the control signals gsel_O and gsel_E. Therefore, each is controlled.

[0059] The wiring WOL is connected to the memory circuit unit 3 in the operation block 21_O of the operation block unit 20_O. The weight data (W O ) and the wiring WEL has the function of transmitting the Weight data stored in the memory circuit section 30 in the calculation block 21_E of the block section 20_E (W E ) is transmitted via the wiring WOL and the wiring WEL. The data is stored in the arithmetic circuits of the arithmetic blocks 21_O and 21_E. 45 via the switching circuit 44. The wiring WOL may be referred to as the first wiring. The wiring WEL may also be called the second wiring. Wiring is arranged according to the number of blocks in the locking section, and there may be three or more wires. obtain.

[0060] The switching circuit 44 selects either the weight data transmitted to the wiring WOL or the weight data transmitted to the wiring WEL. The switching circuit 44 selects one of the signals and outputs it to the arithmetic circuit 45. The switching circuit 44 has a multiplexer function. The control signal wsel that controls the switching circuit 44 is transmitted to the arithmetic circuit unit 40 of the arithmetic block 21_O, The same control can be performed by the arithmetic circuit unit 40 of the arithmetic block 21_E. The switching circuit 44 of the arithmetic circuit unit 40 of the clock 21_0 may be referred to as a second switching circuit. The switching circuit 44 of the arithmetic circuit unit 40 of the arithmetic block 21_E may be referred to as a fourth switching circuit. .

[0061] The arithmetic circuit 45 has a function of executing arithmetic processing such as a product-sum operation. , the input data input from the control circuit 14 and the weight data given from the switching circuit 44 The input data and weight data are preferably digital data. Digital data is less susceptible to noise, so the calculation circuit 45 performs highly accurate calculations. The calculation circuit of the calculation block 21_0 is suitable for performing calculation processing for which a result is required. The arithmetic circuit 45 of the calculation block 40 may be referred to as a first arithmetic circuit. The arithmetic circuit 45 of the arithmetic circuit unit 40 may be referred to as a second arithmetic circuit. In addition to calculations such as summation, activation function calculations, quantization calculations, pooling calculations, etc. The following configuration may also be used.

[0062] Next, an example of the operation of the semiconductor device 10 shown in FIGS. 1A to 1C will be described. In the configuration of the operation block 21 applicable to the operation blocks 21_O and 21_E, The weight data (weight data W) read from the circuit 31 O or W E , W in the figure O / W E and Figure The buffer circuit 43, which is applicable to the buffer circuit 43_O or 43_E, and the wiring WO The dashed arrows show the state in which the signal is given to the arithmetic circuit 45 via the L, WEL, and switching circuit 44. The calculation circuit 45 calculates the weight data W O / W E and, the product-sum operation The output data MAC is output by the calculation process. O (O stands for odd number) , W O1 The weight data represented by W corresponds to the first weight data described above. E ( E is an even number), W E1 The weight data represented as above corresponds to the second weight data described above.

[0063] The arithmetic circuit section 40 in the arithmetic block 21_O of the arithmetic block section 20_O is shown in FIG. If we express it in a simplified form following the state of the weight data shown in the figure, it can be expressed as shown in FIG. 2B. In FIG. 2B, weight data read out from the memory circuit unit 30 (not shown) W O 4 is applied to the wiring WOL via the buffer circuit 43_O. In 2B, the weight data W given to the wiring WOL O and the weight data given to the wiring WEL TaW E and either of the weight data (W in the figure) O / WE ) is selected by the switching circuit 44, The diagram shows how the signal is provided to the arithmetic circuit 45 (not shown).

[0064] 2B, the calculation block 21_E of the calculation block section 20_E performs calculations. The arithmetic circuit unit 40 can be represented in a simplified form as shown in FIG. The weight data W read out from the circuit section 30 (not shown) E passes through the buffer circuit 43_E 2C shows the state of the wiring WEL. Weight data W O and the weight data W given to the wiring WEL E and either one of the weight data Data (W in the figure O / W E ) is selected by a switching circuit 44 and is given to an arithmetic circuit 45 (not shown). The figure shows how this is done.

[0065] In FIG. 2D, the arithmetic circuit unit 40 of the arithmetic block unit 20_O illustrated in FIGS. 2B and 2C 2D is a schematic diagram illustrating a combination of the arithmetic circuit unit 40 of the arithmetic block unit 20_E and the arithmetic circuit unit 40 of the arithmetic block unit 20_E. In the arithmetic circuit section 40 of each arithmetic block section 20_0, The weight data W read from O1 or W ON (N is a natural number) In addition, in the arithmetic circuit unit 40 of each arithmetic block unit 20_E, the memory circuit unit 30 Weight data W read from (not shown) E1 or W EN The calculation block is shown. The memory circuits corresponding to the arithmetic circuit unit 40 included in the block unit 20_O and the arithmetic block unit 20_E are The path section 30 (not shown) holds different weight data and selects the weight data (W in the figure). O / W E ) to the arithmetic circuit 45 (not shown).

[0066] 2B and 2C, the weight data W O / W E Switch and output Although the configuration in which the input signal is input is shown, other configurations are also possible. For example, the input signal shown in Figs. 3A and 3B As shown in the figure, the calculation circuit unit 40 (calculation block 21_O, calculation block 21_E) The weight data is sent to the switching circuit 44 without going through the buffer circuit 43_E (buffer circuit 43_O). TaW FC 3A and 3B, the switching circuit 4 4 is the selected weight data (W in the figure) O / W E / W FC ) to the calculation circuit 45 (not shown). The configuration may be such that the signal is output.

[0067] Weight data W FC is a fully connected operation in a neural network that performs convolutional operations. In the fully connected operation, different weight data is used for each operation circuit. The calculation is performed using different weight data W FC The weight data W FC_1 Weight data W FC_ N (N is a natural number of 2 or more), as shown in FIG. 3C, Weight data W FC_1 Weight data W FC_N is selected by the switching circuit 44 and the calculation circuit 4 5 (not shown).

[0068] 3A to 3C, the weight data W O / W E of The weight data W may be shared by a plurality of arithmetic circuits or may be different for each arithmetic circuit unit 40. FC Using Therefore, it is possible to switch between performing the convolution operation in the arithmetic circuit and performing the operation in the arithmetic circuit. Weight data required for convolutional operations and full-connection operations in neural networks can be read out near the arithmetic circuit that requires it.

[0069] Next, the operations of the operation blocks 21_O and 21_E illustrated in FIG. 2D will be described with reference to FIG. 4A, 4B, 5A, and 5B.

[0070] The operation of Fig. 4A will be described. Fig. 4A shows the operation of the odd-numbered operation block unit 20_O. The weight data W is output from the memory circuit section corresponding to the arithmetic circuit section 40_O1. O1 Select and read Wiring WOL is weight data W O1 The dashed arrows show the charging and discharging of the potential according to the 4A corresponds to the initial operation before the start of the calculation, and at this point, the wiring WO The connection between the wiring WOL L and the arithmetic circuit 45 is cut off by the switching circuit 44. The charge and discharge operation of the switching circuit 44 does not determine the operation rate of the calculation in the calculation circuit 45. The output is connected to the wiring WEL and the arithmetic circuit 45, or to another fixed potential (H potential, or It is preferable to supply a potential (or L potential) to prevent the transistor from going into an unstable state.

[0071] The operation of FIG. 4B will be described. FIG. 4B shows the odd-numbered operation block units 20_O and the even-numbered operation block units 20_O. In the switching circuit 44 in the arithmetic circuit unit 40 of the arithmetic block unit 20_E, the wiring WO By making the connection between L and the calculation circuit 45 conductive, the calculation circuit 45 receives the weight data W O1 The buffer circuit 43_O of the arithmetic circuit unit 40_O1 supplies the wiring Since the charging of the WOL has been completed, even if the charge supply capacity of the buffer circuit 43_O is small, , it does not become a rate-limiting factor for the calculations in the calculation circuit 45.

[0072] In the operation of FIG. 4B, the arithmetic circuit unit 40_E belonging to the even-numbered arithmetic block unit 20_E Weight data W from the memory circuit section corresponding to 1 E1 Select and read the wiring WEL and set the weight data. Data W E1 At this point, the connection between the wiring WEL and the arithmetic circuit 45 is cut off by the switching circuit 44, and the wiring WOL and the arithmetic circuit 45 are By driving in this way, the charge and discharge operation of the wiring WEL is This does not limit the operation rate of the calculation circuit 45.

[0073] The operation of FIG. 5A will be described. FIG. 5A shows the odd-numbered operation block units 20_O and the even-numbered operation block units 20_O. In the switching circuit 44 in the arithmetic circuit unit 40 of the certain arithmetic block unit 20_E, the wiring WE By making the connection between L and the calculation circuit 45 conductive, the calculation circuit 45 receives the weight data W E1 The buffer circuit 43_E of the arithmetic circuit unit 40_E1 supplies the wiring Since charging of the WEL is completed, even if the charge supply capacity of the buffer circuit 43_E is small, , it does not become a rate-limiting factor for the calculation of the calculation circuit 45.

[0074] In the operation of FIG. 5A, the arithmetic circuit unit 40_O belonging to the odd-numbered arithmetic block unit 20_O Weight data W from the memory circuit corresponding to 2 O2 Select and read the wiring WOL and set the weight data. Data W O2At this point, the connection between the wiring WOL and the arithmetic circuit 45 is cut off by the switching circuit 44, and the wiring WEL and the arithmetic circuit 45 are connected by the switching circuit 44. By driving in this way, the charge and discharge operation of the wiring WOL is This does not limit the operation rate of the calculation circuit 45.

[0075] The operation of FIG. 5B will be described. FIG. 5B shows the odd-numbered operation block units 20_O and the even-numbered operation block units 20_O. In the switching circuit 44 in the arithmetic circuit unit 40 of the arithmetic block unit 20_E, the wiring WO By making the connection between L and the calculation circuit 45 conductive, the calculation circuit 45 receives the weight data W O2 The buffer circuit 43_O of the arithmetic circuit unit 40_O2 supplies the wiring Since the charging of the WOL has been completed, even if the charge supply capacity of the buffer circuit 43_O is small, , it does not become a rate-limiting factor for the calculation of the calculation circuit 45.

[0076] In the operation of FIG. 5B, the arithmetic circuit unit 40_E belonging to the even-numbered arithmetic block unit 20_E Weight data W from the memory circuit corresponding to 2 E2 Select and read the wiring WEL and set the weight data. Data W E2 At this point, the connection between the wiring WEL and the arithmetic circuit 45 is cut off by the switching circuit 44, and the wiring WOL and the arithmetic circuit 45 are By driving in this way, the charge and discharge operation of the wiring WEL is This does not limit the operation rate of the calculation circuit 45.

[0077] 4A, 4B, 5A, and 5B, the odd-numbered operation block units 2 0_O and the even-numbered operation block unit 20_E, and charge and discharge the wiring WOL or WEL, The weight data charged and discharged to the wiring WOL or WEL is supplied to the calculation circuit 45 alternately. As described above, in the configuration of one embodiment of the present invention, the charging and discharging operations of the wirings WOL and WEL are performed by the calculation circuit. This does not limit the operation speed of the calculation of the circuit 45, and the operation speed of the calculation can be improved.

[0078] In the configuration of the semiconductor device 10 according to the embodiment of the present invention described above, the buffer circuit is not limited. In cases where the charge supply capacity of the buffer circuit is limited, such as when designing with a limited area, Even if the wiring is not connected to the power supply, it is possible to achieve a configuration in which the wiring can be charged at high speed. In this way, the buffer circuit 43 of the arithmetic circuit unit 40 does not need to be switched over to operate, and the signal is transmitted via the wiring WL. When weight data W is supplied to the arithmetic circuit 45, the weight data W is supplied to the wiring WL. It takes time for the potential to change, and the calculation speed may not be sufficient. In one embodiment of the present invention, the charging speed in the WEL is increased, and the calculation processing speed is improved. The semiconductor device can be formed by the above method.

[0079] 7A shows the operation block 21_0 shown in FIG. 1B, which is connected to the memory circuit unit 30 and the operation block 21_0. 1 shows a schematic diagram of a case where the memory circuit section 30 and the arithmetic circuit section 40 are stacked. The configuration of FIG. 7A allows the memory to be connected without increasing the circuit area. As a result, a huge amount of weight data can be stored in the memory circuit section. This reduces the number of times weight data needs to be transferred from external memory, resulting in low power consumption. This allows for reduced power consumption and also allows for miniaturization of the semiconductor device.

[0080] FIG. 7B shows the operation block 21_0 shown in FIG. 7A, in which the memory circuit unit 30, the operation circuit 10 is a diagram for explaining transistors suitable for the path section 40. It is also applicable to

[0081] The memory circuit portion 30 includes a memory circuit 31. The memory circuit 31 includes a transistor 51. The semiconductor layer 52 of the transistor 51 is made of an oxide semiconductor (metal oxide). Thus, the memory circuit 31 can be formed using the above-described OS transistor.

[0082] The arithmetic circuit unit 40 includes a latch circuit 41, a switching circuit 42, a buffer circuit 43_O, a switching circuit The arithmetic circuit unit 40 includes a transistor 53 and an arithmetic circuit 45. The semiconductor layer 54 of the transistor 53 is made of silicon, which is The circuits may be circuits included in the arithmetic circuit section 40 that is made up of transistors.

[0083] By locating the memory circuit unit 30 on the substrate where the arithmetic circuit unit 40 is located, Compared to when the memory circuit section 30 and the arithmetic circuit section 40 are arranged on the same layer, The memory capacity required for the arithmetic processing in the semiconductor device 10 functioning as a memory, that is, the memory circuit The increase in memory capacity allows for the transfer of data from external storage devices to semiconductor devices. This reduces the number of data transfers required for processing, leading to lower power consumption. It is possible.

[0084] When the memory circuit unit 30 and the arithmetic circuit unit 40 are separate chips, the bus width is determined according to the number of pins on the chip. On the other hand, as in the configuration of one embodiment of the present invention, the memory circuit unit 30 and the arithmetic circuit unit 40 In the stacked structure, the number of parallel data required for the calculation process is determined according to the opening where the wiring LBL is provided. Therefore, it is possible to perform efficient calculation processing.

[0085] If there are multiple operation blocks, connect them along the wiring WOL and WEL as shown in Figure 8. , and the operation blocks 21_O and 21_E are provided. Since the distance between OL and WEL and the operation blocks 21_O and 21_E can be shortened, This allows for a more compact device with lower power consumption.

[0086] Next, in FIG. 9, a processing system including a semiconductor device 10 that functions as an AI accelerator is shown. A block diagram showing the entire system 100 will now be described.

[0087] 9, in addition to the accelerator section 130 having a plurality of semiconductor devices 10 described in FIG. 1A, 1, the CPU 110 and the bus 120 are shown. The CPU 110 includes a CPU core 200 and a and a backup circuit 222. The accelerator unit 130 includes a plurality of semiconductor devices 1 0, the semiconductor device 10 includes a control unit 131 for controlling input and output of data between the semiconductor device 10.

[0088] The CPU 110 runs the operating system, controls data, and performs various calculations and programs. The CPU 110 has a function to perform general-purpose processing such as executing a program. The CPU core 200 corresponds to one or more CPU cores. 0 is a backup that can retain data in the CPU core 200 even if the supply of power voltage is stopped. The power supply voltage is supplied from the power domain. It can be controlled by electrically disconnecting it using a switch or the like. The backup circuit 222 may be, for example, an OS transistor. An OS memory having:

[0089] The backup circuit 222, which is made up of OS transistors, is made up of Si transistors. The backup circuit 22 can be stacked with the CPU core 200. Since the area of ​​2 is smaller than the area of ​​CPU core 200, C A backup circuit 222 may be placed on the PU core 200. The back register 222 has a function of holding data in the registers of the CPU core 200. The backup circuit 222 is also called a data retention circuit. The details of the configuration of the CPU core 200 including the backup circuit 222 will also be described in the third embodiment. Reveal.

[0090] The control unit 131 has a memory circuit such as an SRAM inside. The output data MAC obtained by the device 10 is stored in a memory circuit. The output data MAC is output to a plurality of semiconductor devices. It is possible to perform parallel calculations with an increased degree of parallelism using a large number of semiconductor devices.

[0091] The bus 120 electrically connects the CPU 110 and the accelerator unit 130. The CPU 110 and the semiconductor device 10 can transmit data via a bus 120. .

[0092] FIG. 10A shows a circuit configuration applicable to the memory circuit section 30 in the semiconductor device 10 of the present invention. 10A is a diagram illustrating an example of a matrix having M rows and N columns (M and N are natural numbers equal to or greater than 2). The write word lines WWL_1 to WWL_M and the read word line RW are arranged in the direction L_1 to RWL_M, write bit lines WBL_1 to WBL_N, and wiring LBL_1 1 to LBL_N. Also, the memory circuits 3 connected to each word line and bit line are shown. 1 is shown.

[0093] FIG. 10B is a diagram illustrating an example of a circuit configuration applicable to the memory circuit 31. The circuit 31 includes a transistor 61, a transistor 62, a transistor 63, and a capacitance element 64 (capacitor element 64). It has a saccharin (also called capashita).

[0094] One of the source and drain of the transistor 61 is connected to the write bit line WBL. The gate of the transistor 61 is connected to the write word line WWL. The other of the source and drain of the transistor 62 is connected to one electrode of the capacitor 64 and the other of the drain of the transistor 62. The gate of the transistor 62 is connected to the source or drain of the capacitor element 63. The other electrode of 64 is connected to a wiring that provides a fixed potential, for example, a ground potential. The other of the source or drain of the transistor 62 is connected to the source or drain of the transistor 63. The gate of the transistor 63 is connected to one of the read word lines RWL. The other of the source and the drain of the transistor 63 is connected to the wiring LBL. The LBL is approximately perpendicular to the substrate surface on which the Si transistors of the arithmetic circuit section 40 are provided. The latch circuit 41 (not shown) of the arithmetic circuit unit 40 is connected to the latch circuit 41 via wiring extending in the direction of the arrow. (without

[0095] The circuit configuration of the memory circuit 31 shown in FIG. 10B is a three-transistor (3T) gain cell with N The transistors 61 to 63 correspond to OSRAM. In the off state, an OS transistor allows current to flow between the source and drain, i.e., leakage current. NOSRAM has extremely low leakage current characteristics, allowing data to be By storing a charge corresponding to the amount of charge in the memory circuit, it can be used as a non-volatile memory. .

[0096] The circuit configuration applicable to the memory circuit 31 of FIG. 10A is a 3T type NOSRAM of FIG. 10B. For example, a circuit equivalent to the 2T type NOSRAM shown in FIG. In FIG. 11A, a transistor 61B, a transistor 62B, and a capacitor 64B are included. The memory circuit 31A is shown. The transistors 61B and 62B are The transistors 61B and 62B are semiconductor layers in different layers. The OS transistor may have a semiconductor layer disposed therein, or a semiconductor layer disposed therein. The memory circuit 31A functions as a write bit line WBL and a read bit line. The write word line WWL, the read word line RWL, the source line SL, and An example in which the transistor is connected to the back gate line BGL is shown.

[0097] The circuit configuration applicable to the memory circuit 31 of FIG. 10A is a 3T type NOS shown in FIG. In FIG. 11B, a memory that can hold data with different logics is used. The figure shows a memory circuit 31B having a memory circuit 31_P and a memory circuit 31_N. 1B, transistor 61_P, transistor 62_P, transistor 63_P, and A memory circuit 31_P having a capacitor element 64_P, a transistor 61_N, a transistor 6 a memory circuit 31_N having a transistor 63_N and a capacitor 64_N; Each transistor included in the memory circuit 31_P and the memory circuit 31_N is The transistors included in the memory circuit 31_P and the memory circuit 31_N are S transistors. The transistor may be an OS transistor with semiconductor layers disposed in different layers, or may be an OS transistor with semiconductor layers disposed in the same layer. The memory circuit 31B may be an OS transistor in which the write bit line WBL_P , wiring LBL_P, write bit line WBL_N, wiring LBL_N, write word line WWL 1, an example in which the memory circuit 31B is connected to a read word line RWL is shown. The data to be read is stored, and data with different logic is read out to the wiring LBL_P and wiring LBL_N. It is possible.

[0098] FIG. 12 shows the switching circuit 42, the buffer circuit 43 (43_O, 43_E), and the switching circuit 44. 12 is a diagram illustrating the operation of the semiconductor device. In FIG. 12, the four calculation blocks are configured as follows: The memory circuit units 30_1 to 30_4 and the arithmetic circuit units 40_1 to 40_4 are illustrated. The combination of the memory circuit unit 30_1 and the arithmetic circuit unit 40_1, and the combination of the memory circuit unit 30_3 and the arithmetic circuit unit 40_2 The combination of the arithmetic circuit unit 40_1 and the arithmetic circuit unit 40_2 corresponds to the configuration of the odd-numbered arithmetic block unit. The combination of the memory circuit unit 30_2 and the arithmetic circuit unit 40_2, and the combination of the memory circuit unit 30_4 and the arithmetic circuit unit 40_2 The combination of the arithmetic circuit unit 40_1 and the arithmetic circuit unit 40_4 corresponds to the configuration of the even-numbered arithmetic block unit.

[0099] The memory circuit portion 30_1 includes a memory circuit 31 connected to the wirings LBL_11 to LBL_1N. The memory circuit unit 30_1 stores the weight data W11 or W 1N The memory circuit section holds The memory circuit 30_2 includes a memory circuit 31 connected to the wirings LBL_21 to LBL_2N. The memory circuit unit 30_2 stores the weight data W 21 or W 2N The memory circuit unit 30_3 holds: The memory circuit 31 is connected to the wirings LBL_31 to LBL_3N. _3 is the weight data W 31 or W 3N The memory circuit unit 30_4 stores the wiring LBL_ The memory circuit 30_4 has a memory circuit 31 connected to the weights LBL_41 to LBL_4N. Data W 41 or W 4N Hold.

[0100] In FIG. 12, wirings LBL_11 to LBL_1N, wirings LBL_21 to LBL_2N, The wirings LBL_31 to LBL_3N and the wirings LBL_41 to LBL_4N are shown in the figure. Wiring LBL P is a vertical line connecting the memory circuit section on the upper layer and the arithmetic circuit section on the lower layer. Corresponds to the extending wiring. Wiring LBL P is shorter than the horizontally extending wires. , Wiring LBL_11 to LBL_1N, Wiring LBL_21 to LBL_2N, Wiring LBL _31 to LBL_3N and the parasitic capacitance of the wirings LBL_41 to LBL_4N is reduced. This reduces the charge required for charging and discharging wiring, leading to lower power consumption and improved computing efficiency. In addition, the weight data can be read from the memory circuit 31 to the latch circuit at high speed. Cut.

[0101] The arithmetic circuit unit 40_1 includes a latch circuit 41_1, a switching circuit 42_1, a buffer circuit 43_ The latch circuit 41_1 has a wiring LBL _11 to LBL_1N from the memory circuit 31 included in the memory circuit portion 30_1. The weight data W 11 or W 1N The switching circuit 42_1 holds the control signal lsel_O The buffer circuit 43_1 is controlled by a control signal gsel_O1. The circuit 44_1 is controlled by a control signal wsel. The weight data selected by the switching circuit 44_1 is used for the multiplication and accumulation operation, and the output data is Outputs data MAC1.

[0102] The arithmetic circuit unit 40_2 includes a latch circuit 41_2, a switching circuit 42_2, a buffer circuit 43_ 2, a switching circuit 44_2, and an arithmetic circuit 45_2. The latch circuit 41_2 is connected to the wiring LBL _21 to LBL_2N from the memory circuit 31 included in the memory circuit portion 30_2. The weight data W 21 or W 2N The switching circuit 42_2 holds the control signal lsel_E The buffer circuit 43_2 is controlled by a control signal gsel_E1. The circuit 44_2 is controlled by a control signal wsel. The weight data selected by the switching circuit 44_2 is used for the multiplication and accumulation operation, and the output data is Output data MAC2.

[0103] The arithmetic circuit unit 40_3 includes a latch circuit 41_3, a switching circuit 42_3, a buffer circuit 43_ The latch circuit 41_3 has a line LBL _31 to LBL_3N from the memory circuit 31 included in the memory circuit portion 30_3. The weight data W31 or W 3N The switching circuit 42_3 holds the control signal lsel_O The buffer circuit 43_3 is controlled by a control signal gsel_O2. The circuit 44_3 is controlled by a control signal wsel. The weight data selected by the switching circuit 44_3 is used for the multiplication and accumulation operation, and the output data is Output data MAC3.

[0104] The arithmetic circuit unit 40_4 includes a latch circuit 41_4, a switching circuit 42_4, a buffer circuit 43_ The latch circuit 41_4 has a wiring LBL _41 to LBL_4N from the memory circuit 31 included in the memory circuit portion 30_4. The weight data W 41 or W 4N The switching circuit 42_4 holds the control signal lsel_E The buffer circuit 43_4 is controlled by the control signal gsel_E2. The circuit 44_4 is controlled by a control signal wsel. The weight data selected by the switching circuit 44_4 is used for the multiplication and accumulation operation, and the output data is Output data MAC4.

[0105] FIG. 13 shows a timing chart for explaining the operation of each component explained in FIG. The arithmetic circuit 45 responds to the toggle operation of the clock signal CLK (for example, at times T0 to T6). Weight data is given according to the clock signal, and calculation processing is performed with the input data A1 to A4. By increasing the frequency of CLK, it is possible to speed up the calculation process.

[0106] Input data A INWhen switching the weight data at high speed according to the clock signal CLK, It is necessary to switch the data of the given wiring WOL and WEL at high speed.

[0107] Wiring LBL_11 to LBL_1N, wiring LBL_21 to LBL_2N, wiring LBL Weight data W1 1 to W 1N , weight data W 21 or W 2N , weight data W 31 or W 3N , weight data W 41 or W 4N are held in the latch circuits 41_1 to 41_4. Weight data W 11 or W 1N , weight data W 21 or W 2N , weight data W 31 ~W3 N , weight data W 41 or W 4N The readout may be performed simultaneously in each memory circuit unit. Or you can go in order.

[0108] At time T1, the control signal lsel_O outputs weight data from the latch circuits 41_1 and 41_3. W 11 , weight data W 31 The control signal gsel_O1 is set to H level, and the The weight data W selected by the circuit 42_1 11 The potential corresponding to this is charged to the wiring WOL. As described above, charging via the wired WOL can be performed at high speed.

[0109] At time T2, the control signal lsel_E outputs weight data from the latch circuits 41_2 and 41_4. W 21 , weight data W 41The control signal gsel_E1 is set to H level, and the The weight data W selected by the circuit 42_2 21 The potential corresponding to this is charged to the wiring WEL. As described above, the charging of the wiring WEL can be performed at high speed. The weight data W of the wiring WOL charged at the previous time T1 11 A potential switching circuit 44 The control signal wsel is given to the arithmetic circuits 45_1 to 45_4. In the calculation circuits 45_1 to 45_4, the same weight data W 11 Multiply and add operations according to Processing is performed to calculate output data MAC1 to MAC4.

[0110] At time T3, the control signal gsel_O2 is set to H level, and the switching circuit 42_3 selects The weight data W 31 The potential corresponding to this is charged to the wiring WOL. As described above, this can be done at high speed. Also, at time T3, the charge at the previous time T2 is The weight data W of the wiring WEL 21 to the switching circuits 44_1 to 44_4. The control signal wsel is used to switch between the two signals and provide them to the arithmetic circuits 45_1 to 45_4. 5_1 to 45_4 have the same weight data W 21 The product-sum operation is performed according to the Calculates MAC1 to MAC4.

[0111] At time T4, the control signal gsel_E2 is set to H level, and the switching circuit 42_4 selects The weight data W 41 The potential corresponding to the value is charged to the wiring WEL. As described above, this can be done at high speed. Also, at time T4, the battery that was charged at time T3 is The weight data W of the wiring WOL31 to the switching circuits 44_1 to 44_4. The control signal wsel is used to switch between the two signals and provide them to the arithmetic circuits 45_1 to 45_4. 5_1 to 45_4 have the same weight data W 31 The product-sum operation is performed according to the Calculates MAC1 to MAC4.

[0112] At time T5, the weight data is output from the latch circuits 41_1 and 41_3 in response to the control signal lsel_O. W 12 , weight data W 32 The control signal gsel_O1 is set to H level, and the The weight data W selected by the circuit 42_1 12 The potential corresponding to this is charged to the wiring WOL. As described above, the charging of the wiring WOL can be performed at high speed. The weight data W of the wiring WEL charged at the previous time T4 41 A potential switching circuit 44 The control signal wsel is given to the arithmetic circuits 45_1 to 45_4. In the calculation circuits 45_1 to 45_4, the same weight data W 41 Multiply and add operations according to Processing is performed to calculate output data MAC1 to MAC4.

[0113] At time T6, the weight data is output from the latch circuits 41_2 and 41_4 in response to the control signal lsel_E. W 22 , weight data W 42 The control signal gsel_E1 is set to H level, and the The weight data W selected by the circuit 42_2 22 The potential corresponding to this is charged to the wiring WEL. As described above, the charging of the wiring WEL can be performed at high speed. The weight data W of the wiring WOL charged at the previous time T5 12A potential switching circuit 44 The control signal wsel is given to the arithmetic circuits 45_1 to 45_4. In the calculation circuits 45_1 to 45_4, the same weight data W 12 Multiply and add operations according to Processing is performed to calculate output data MAC1 to MAC4.

[0114] At subsequent times, the weight data can be switched at high speed by switching each control signal. The arithmetic circuits 45_1 to 45_4 perform product-sum operations, and the output data MAC1 to MAC 4 can be calculated.

[0115] 14 shows a specific example of the configuration of the arithmetic circuit 45. In FIG. 14, weight data W (as described above) Did W O , W E ) and an arithmetic circuit 4 capable of performing a multiply-and-accumulate operation on input data A. 14 shows an example of the configuration of the multiplication circuit 71, the addition circuit 72 and the register 73. The data multiplied by the multiplication circuit 71 is input to an addition circuit 72. The output of the adder circuit 72 is held in a register 73, and the data multiplied by the multiplier circuit 71 is added. The sum of products is calculated by adding them together in the circuit 72. The register 73 is connected to the clock signal It is controlled by the signal CLK and the reset signal reset_B. The output data MAC corresponding to the sum-of-products operation of the weight data W and the input data A can be obtained. do.

[0116] 15, the memory circuit section 3 is stacked on the arithmetic circuit section 40 as described in FIG. 1A. 15 shows an example of the configuration of the driving circuit. 12, drive circuit 13, control circuit 14, processing circuit 15, memory circuit 31, switching circuit 42, switching The circuit 44 and the calculation circuit 45 are shown.

[0117] Although not shown in FIG. 15, each circuit in FIG. 15 has a control circuit for controlling each circuit. Control signals, input data, and output data are input to and output from external circuits.

[0118] FIG. 16A shows a block for controlling the memory circuit unit 30 in each configuration shown in FIG. 16A shows the memory circuit 31 in the memory circuit section 30 as well as the drive circuit. The circuit 12 and the drive circuit 13 are shown in isolation.

[0119] The drive circuit 12 and the drive circuit 13 process the input signal from the outside and store it in the memory circuit 31. A signal for writing weight data and a signal for reading weight data from the memory circuit 31 A signal is generated, and the generated signal is provided to the memory circuit via a wiring.

[0120] FIG. 16B shows a block for controlling the arithmetic circuit unit 40 in each configuration shown in FIG. 16B is a diagram of the switching circuit 42 and the switching circuit 4 4 and the arithmetic circuit 45, the control circuit 14, the processing circuit 15, and the wiring WOL and WEL are also shown. In FIG. 16B, the latch circuit 41, the buffer circuit 43, etc. are omitted. do.

[0121] The control circuit 14 generates input data A and outputs it to the arithmetic circuit 45. The switching circuit 42 The weight data read from the memory circuit 31 is selected and sent via a buffer circuit (not shown). The switching circuit 44 selects the wiring WOL or WEL, Weight data W (as mentioned above) O , W EThe calculation circuit 45 outputs the result (corresponding to , a multiplication and accumulation operation is performed on the weight data W and the input data A, and the output data MAC is sent to the processing circuit 15. The processing circuit 15 performs post-processing on the output data MAC and outputs it to the control circuit 14. The control circuit 14 re-inputs the input data A to the arithmetic circuit unit 40.

[0122] In the semiconductor device 10, the control circuit 14 sends the processed data back to the arithmetic circuit unit 40. Therefore, the data in the middle of the calculation can be stored outside the semiconductor device 10. The semiconductor device 1 can perform arithmetic processing without reading the data into a main memory or the like. In the example shown in FIG. 0, an opening is provided in an insulating film or the like to provide electrical connection between the memory circuit section and the arithmetic circuit section. This can be done through wiring, so the number of parallel connections can be increased by increasing the number of wiring. Therefore, in the semiconductor device 10, parallel calculation of the number of bits equal to or greater than the data bus width of the CPU is possible. In addition, since the arithmetic circuit section is stacked with the memory circuit section, As a result, a huge number of weight data can be stored in the memory circuit section. This reduces the number of times weight data needs to be transferred from external memory. This allows for lower power consumption.

[0123] As described above, one embodiment of the present invention is a miniaturized semiconductor device that functions as an accelerator. Alternatively, one embodiment of the present invention can provide a semiconductor device that can reduce power consumption. It is possible to provide a semiconductor device that functions as an accelerator. It is possible to provide a semiconductor device with a novel configuration that functions as an accelerator.

[0124] (Embodiment 2) In this embodiment, the program executed by the CPU 110 described in the above embodiment is An example of an operation when a part of the calculation is executed by the accelerator described as the semiconductor device 10. Explain.

[0125] Figure 17 shows the case where part of the calculations of a program executed by the CPU is executed by the accelerator. 10 is a diagram illustrating an example of the operation of FIG.

[0126] The host program is executed by the CPU (host program execution; step S1). .

[0127] The CPU uses the accelerator to store the data required for calculations. When the instruction to reserve the data is confirmed in the circuit section (memory reservation instruction; step S2), A memory area is reserved in the memory circuit unit (memory reservation; step S3).

[0128] Next, the CPU transfers input data from the main memory or external storage device to the memory circuit unit. The weight data is transmitted (data transmission; step S4). The weight data is received and stored in the area secured in step S2 (data reception ;Step S5).

[0129] When the CPU confirms the instruction to start the kernel program ( Step S6), the accelerator starts executing the kernel program ( Start of calculation (step S7).

[0130] Immediately after the accelerator starts executing the kernel program, the CPU is put into a state where it can perform calculations. It may be switched from the power gating state to the PG (power gating) state (PG state transition; step In this case, just before the accelerator finishes executing the kernel program, U is switched from the PG state to a state in which calculations are performed (PG state stop; step S9). During the period from step S8 to step S9, the CPU is put into the PG state, and the calculation processing system The entire system can reduce power consumption and heat generation.

[0131] When the accelerator finishes executing the kernel program, the output data is sent to the accelerator. The calculation result is stored in the storage unit that holds the calculation result in the data (calculation end; step S10).

[0132] After the execution of the kernel program is completed, the CPU reads the output data stored in the memory. When a command to send data to main memory or external storage device is confirmed (data transmission request Step S11), the output data is sent to the main memory or an external storage device. The data is transmitted and stored in the main memory or an external storage device (data transmission; step S12 ).

[0133] By repeating the above steps S1 to S14, the CPU and The accelerator reduces power consumption and heat generation while transferring part of the calculations performed by the CPU to the accelerator. The semiconductor device according to one embodiment of the present invention can be implemented by a non-von Neumann accelerator. It has a von Neumann architecture, which increases power consumption as processing speed increases. Compared to conventional architectures, it can perform calculations with significantly less power consumption.

[0134] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0135] (Embodiment 3) In this embodiment, an example of a CPU having a CPU core capable of power gating will be described. and explain.

[0136] FIG. 18 shows an example of the configuration of the CPU 110. The CPU 110 includes a CPU core (CPU Co re) 200, L1 (Level 1) cache memory device (L1 Cache) 202, L 2 cache memory device (L2 Cache) 203, bus interface unit (Bus I / F 205, power switches 210 to 212, and a level shifter (LS) 214. The CPU core 200 includes a flip-flop 220.

[0137] The bus interface unit 205 connects the CPU core 200 and the L1 cache memory device A L2 cache memory device 202 and an L2 cache memory device 203 are connected to each other.

[0138] Interrupts input from the outside, In response to signals such as the signal SLEEP1, the PMU 193 outputs the clock signal GCLK1 and various P Generation of G (power gating) control signals The clock signal GCLK1 and the PG control signal are input to the CPU 110. The signal controls power switches 210 to 212 and flip-flop 220.

[0139] The power switches 210 and 211 are connected to a virtual power line V_VDD (hereinafter referred to as the V_VDD line). The power switch 212 controls the supply of voltages VDDD and VDD1 to the It controls the supply of voltage VDDH to the bell shifter (LS) 214. The voltage VSSS is input to U193 without going through a power switch. , the voltage VDDD is input without passing through the power switch.

[0140] Voltages VDDD and VDD1 are drive voltages for the CMOS circuit. Voltage VDD1 is voltage VD It is lower than DD and is the drive voltage in sleep mode. The voltage VDDH is for the OS transistor. This is the drive voltage, which is higher than the voltage VDDD.

[0141] L1 cache memory device 202, L2 cache memory device 203, bus interface Each of the interface sections 205 has at least one power domain that can be power gated. A power-gating capable power domain has one or more power switches. These power switches are controlled by a PG control signal.

[0142] The flip-flop 220 is used as a register. A backup circuit is provided. The flip-flop 220 will now be described.

[0143] FIG. 19 shows an example of the circuit configuration of the flip-flop 220. Flip-flop 220 is a scan flip-flop 221 , and a backup circuit 222.

[0144] The scan flip-flop 221 is connected to nodes D1, Q1, SD, SE, RT, CK, and It has a lock buffer circuit 221A.

[0145] Node D1 is the data input node, and node Q1 is the data output node. The node SD is an input node for scan test data. The node SE is a signal SC The node CK is the input node of the clock signal GCLK1. The clock signal GCLK1 is input to the clock buffer circuit 221A. The analog switch of the drop 221 is connected to the nodes CK1 and C of the clock buffer circuit 221A. Node RT is connected to the input node of the reset signal. It is a code.

[0146] The signal SCE is a scan enable signal and is generated by the PMU 193. 93 generates signals BK and RC. A level shifter 214 level-shifts the signals BK and RC. The signal BK is the backup signal, and the signal RC is the recovery signal. It's a signal.

[0147] The circuit configuration of the scan flip-flop 221 is not limited to that shown in FIG. Flip-flops available in the library can be applied.

[0148] The backup circuit 222 includes nodes SD_IN, SN11, and transistors M11 to M1 3, and has a capacitance element C11.

[0149] The node SD_IN is the input node for scan test data and is connected to the scan flip-flop. The node SN11 is connected to the node Q1 of the backup circuit 222. The capacitor C11 is a storage capacitor for holding the voltage of the node SN11. be.

[0150] The transistor M11 controls the conduction state between the node Q1 and the node SN11. Transistor M12 controls the conduction state between node SN11 and node SD. controls the conduction state between the node SD_IN and the node SD. The on / off of transistor M12 is controlled by signal RCH. will be done.

[0151] The transistors M11 to M13 correspond to the transistors 61 to 64 of the memory circuit 31. The transistors M11 to M13 are OS transistors, similar to the transistor 63. The back gates of the transistors M11 to M13 are connected to a voltage VBG1 It is connected to the power supply line that supplies

[0152] At least the transistors M11 and M12 are preferably OS transistors. The voltage at node SN11 is reduced by the extremely low leakage current of the OS transistor. It can suppress deterioration of data and consumes almost no power to retain data, The backup circuit 222 has nonvolatile characteristics. The data is stored by charging and discharging the capacitance element C11. In principle, the backup circuit 222 has no restrictions on the number of times it can be rewritten, and low energy Data can be written and read using a single memory card.

[0153] It is very important that all transistors in the backup circuit 222 are OS transistors. As shown in Figure 19B, a scan flip circuit constructed with silicon CMOS circuitry is preferred. A backup circuit 222 can be stacked on the flop 221 .

[0154] The backup circuit 222 has a much larger number of elements than the scan flip-flop 221. Since the number of scan flip-flops 22 is small, the number of scan flip-flops 22 is small. 1. In other words, the backup circuit 222 does not require any modification of the circuit configuration and layout. This is a highly versatile backup circuit. Since the backup circuit 222 can be provided in the formed area, the backup Even if the flip-flop circuit 222 is incorporated, the area overhead of the flip-flop 220 is zero. Therefore, the backup circuit 222 is provided in the flip-flop 220. This enables power gating of CPU core 200. Because it requires less energy, the CPU core 200 can be power-gated efficiently. It is possible to do this.

[0155] By providing the backup circuit 222, the parasitic capacitance of the transistor M11 is The parasitic capacitance due to the logic circuit connected to node Q1 is added to node Q1. Since this is small compared to the above, it does not affect the operation of the scan flip-flop 221. The backup circuit 222 does not substantially degrade the performance of the flip-flop 220. stomach.

[0156] The low power consumption state of the CPU core 200 may be, for example, a clock gating state, a power The PMU193 can be set to the gating state, hibernation state, and interrupt signal. Based on the signal SLEEP1, etc., the low power consumption mode of the CPU core 200 is selected. For example, when transitioning from normal operation to clock gating, the PMU193 The generation of clock signal GCLK1 is stopped.

[0157] For example, when going from normal operation to hibernation, the PMU193 monitors the voltage and Or frequency scaling. For example, if you want to perform voltage scaling, use PMU193 turns off the power switch 210 to input the voltage VDD1 to the CPU core 200. , turns on the power switch 211. The voltage VDD1 is applied to the scan flip-flop 22 This is the voltage that does not cause data loss. When frequency scaling is performed, the PMU193 The frequency of the clock signal GCLK1 is reduced.

[0158] When the CPU core 200 is shifted from the normal operation state to the power gating state, The data of the flip-flop 221 is backed up to the backup circuit 222. The CPU core 200 is returned from the power gating state to the normal operating state. In this case, the data in the backup circuit 222 is recovered to the scan flip-flop 221. The operation is performed.

[0159] FIG. 20 shows an example of a power gating sequence for the CPU core 200. In 20, t1 to t7 represent time. This is a control signal for the switches 210 to 212 and is generated by the PMU 193. When the signals PSE1 and PSE2 are low, the power switch 210 is on / off. The same is true for .

[0160] Before time t1, the power supply is in normal operation. The switch 210 is on, and the voltage VDDD is input to the CPU core 200. The flip-flop 221 operates normally. At this time, the level shifter 214 is not in operation. Since there is no need to turn on the power, the power switch 212 is off and the signals SCE, BK, and RC are Since the node SE is at "L", the scan flip-flop 221 In the example of FIG. 20, at time t1, the backup circuit The node SN11 of 222 is at "L".

[0161] The operation during backup is explained below. At operation time t1, PMU193 Stop the clock signal GCLK1 and set the signals PSE2 and BK to "H". Level shifter 2 14 becomes active and outputs a signal BKH of “H” to the backup circuit 222.

[0162] The transistor M11 of the backup circuit 222 turns on, and the scan flip-flop The data at node Q1 of the backup circuit 221 is written to node SN11 of the backup circuit 222. If the node Q1 of the scan flip-flop 221 is at "L", the node SN11 If it remains at "L" and node Q1 is at "H", node SN11 goes to "H".

[0163] The PMU193 sets the signals PSE2 and BK to "L" at time t2, and the PSE 0 is set to "L." At time t3, the state of CPU core 200 transitions to the power gating state. The signal PSE0 may fall at the same timing as the signal BK falls.

[0164] The operation during power gating will be described. Signal PSE0 When this signal goes to "L", the voltage on the V_VDD line drops, causing the data on node Q1 to be lost. The node SN11 continues to hold the data of the node Q1 at time t3.

[0165] The operation during recovery is explained below. At time t4, PMU193 outputs a signal By setting PSE0 to "H", the state transitions from the power gating state to the recovery state. Charging of the V_VDD line begins, and the voltage of the V_VDD line reaches VDDD (time t5 ), the PMU193 sets the signals PSE2, RC, and SCE to "H."

[0166] The transistor M12 is turned on, and the charge on the capacitor C11 is transferred to the nodes SN11 and S If node SN11 is at "H", the voltage at node SD rises. Since the signal SE is at "H", the input latch circuit of the scan flip-flop 221 receives a signal. At time t6, the clock signal GCLK1 is input to node CK. When the data is input, the data in the input latch circuit is written to node Q1. The data of N11 has been written to node Q1.

[0167] At time t7, the PMU193 sets the signals PSE2, SCE, and RC to "L" to start the recovery operation. ends.

[0168] The backup circuit 222 using OS transistors has both dynamic and static low power consumption. It is very suitable for normally-off computing because of its small size. CPU 110 including CPU core 200 with backup circuit 222 using a transistor can be called NoffCPU (registered trademark). NoffCPU is a nonvolatile It has memory and can be powered off when no operation is required. Even with the 220 cores installed, there is almost no performance degradation or increase in dynamic power compared to the 200 cores. It can prevent this from happening.

[0169] Note that the CPU core 200 may have multiple power domains that can be power gated. The multiple power domains may have one or more power switches to control the voltage input. The CPU core 200 is provided with one or more power gating switches. For example, there may be a power domain in which power gating is not performed. The flip-flop 220 and the power switches 210 to 212 are controlled in the power domain. A power gating control circuit may be provided to perform this.

[0170] The application of the flip-flop 220 is not limited to the CPU 110. In the present invention, a flip-flop is provided in a register provided in a power domain capable of power gating. ROP 220 can be applied.

[0171] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0172] (Fourth embodiment) In this embodiment, the CPU 110 and the semiconductor device 10 described in the above embodiment are An example of the structure of a transistor applicable to the accelerator described above will be described. As an example, a structure in which transistors having different electrical characteristics are stacked will be described. This configuration allows for increased freedom in designing the semiconductor device. By stacking transistors having electrical characteristics that are suitable for the semiconductor device, the degree of integration can be increased. It is possible.

[0173] A part of the cross-sectional structure of the semiconductor device is shown in FIG. 21. The semiconductor device shown in FIG. 22A shows a circuit diagram of a transistor 500, a capacitor 550, a transistor 500, and a capacitor 600. 22A is a cross-sectional view of the transistor 500 in the channel length direction, and FIG. 22B is a cross-sectional view of the transistor 500 in the channel length direction. For example, the transistor 500 is the same as the memory cell shown in the above embodiment. The OS transistor included in the circuit 31, that is, the transistor having an oxide semiconductor in a channel formation region, The transistor 550 corresponds to the arithmetic circuit unit shown in the above embodiment. 40 has a Si transistor, that is, a transistor having silicon in the channel forming region The capacitor 600 corresponds to the capacitor included in the memory circuit 31.

[0174] The transistor 500 is an OS transistor. Therefore, the data voltage written to the storage node via the transistor 500 is In other words, the refresh operation of the storage node The frequency of refresh operations is reduced, or refresh operations are not required, so the power consumption of the semiconductor device is reduced. can be reduced.

[0175] In FIG. 21, the transistor 500 is provided above the transistor 550, and the capacitance element 6 00 is provided above transistor 550 and transistor 500.

[0176] The transistor 550 is provided on a substrate 311. The substrate 311 is, for example, a p-type silicon The substrate 311 may be an n-type silicon substrate. The oxide layer 314 is The insulating layer (BO) formed by buried oxide on 311 The transistor 550 is preferably made of a silicon oxide layer, for example. A single crystal silicon, so-called SOI (Silicon on Insulator), is provided on the substrate 311 via an oxide layer 314. It is mounted on an Insulator-On-Insulator (Ion-Insulator) substrate.

[0177] The substrate 311 in the SOI substrate is provided with an insulator 313 that functions as an element isolation layer. The substrate 311 also has a well region 312. The well region 312 is a region for forming a transistor. This region is given n-type or p-type conductivity depending on the conductivity type of 550. The single crystal silicon in the semiconductor region 315 may function as a source or drain region. The well region 312 is provided with a low resistance region 316a and a low resistance region 316b. has a low resistance region 316c.

[0178] The transistor 550 is formed in a well region 312 to which an impurity element that provides conductivity is added. The well region 312 can be independently provided with a potential via the low resistance region 316c. By changing the gate electrode of the transistor 550, Therefore, the threshold voltage of the transistor 550 can be controlled. If the transistor 550 is an n-channel transistor, a negative potential is applied to the well region 312. By applying the voltage, the threshold voltage of the transistor 550 is increased and the off-state current is reduced. Therefore, by applying a negative potential to the well region 312, Reduce the drain current when the potential applied to the gate electrode of a Si transistor is 0V As a result, the through current in the arithmetic circuit section 40 having the transistor 550 This can reduce power consumption due to the above and improve the efficiency of calculations.

[0179] The transistor 550 has an insulator 317 on the top surface of the semiconductor layer and on the side surface in the channel width direction. It is preferable that the transistor is a so-called fin type, which is covered with a conductor 318 through a gap. By making the transistor 550 a fin type, the effective channel width is increased, The on-state characteristics of the transistor 550 can be improved. Since the potential can be increased, the off-state characteristics of the transistor 550 can be improved.

[0180] The transistor 550 may be a p-channel transistor or an n-channel transistor. The transistor may be either one of the two.

[0181] Conductor 318 may function as a first gate (also called top gate) electrode. The well region 312 also functions as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the well region 312 is applied via the low resistance region 316c. can be controlled by

[0182] The region where the channel of the semiconductor region 315 is formed, the region in the vicinity thereof, the source region, or The low resistance region 316a and the low resistance region 316b, which will be the drain region, and the well region 312 In the low resistance region 316c connected to the electrode for controlling the potential of the silicon-based semiconductor It is preferable that the semiconductor material contains a semiconductor such as silicon dioxide, and it is preferable that the semiconductor material contains single crystal silicon. e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), It may be formed of a material having a crystal structure such as GaAlAs (gallium aluminum arsenide). A silicon structure in which the effective mass is controlled by applying stress to the molecules and changing the lattice spacing. Alternatively, the transistor 550 may be formed by using GaAs and GaAlAs. HEMT (High Electron Mobility Transistor) and You may do so.

[0183] Well region 312, low resistance region 316a, low resistance region 316b, and low resistance region 31 6c is a semiconductor material applied to the semiconductor region 315, and n-type conductive materials such as arsenic and phosphorus are also used. It contains an element that imparts p-type conductivity, or an element that imparts p-type conductivity, such as boron.

[0184] The conductor 318, which functions as a gate electrode, is made of arsenic, phosphorus, or the like, which provides n-type conductivity. Semiconductor materials such as silicon that contain elements or elements that give them p-type conductivity, such as boron Conductive materials such as aluminum, metal, alloy, or metal oxide materials can be used. The conductor 318 may also be made of a silicide such as nickel silicide.

[0185] Since the work function is determined by the material of the conductor, it is necessary to select the material of the conductor. Specifically, the conductor is made of nitride silicon, and the threshold voltage of the transistor can be adjusted. It is preferable to use materials such as tantalum or tantalum nitride. To achieve this, metal materials such as tungsten and aluminum are used as layers for the conductor. It is preferable to use tungsten, in particular, in terms of heat resistance.

[0186] The low resistance region 316a, the low resistance region 316b, and the low resistance region 316c are formed of different conductive materials. Alternatively, a structure may be adopted in which silicide such as nickel silicide is stacked. By forming the electrode in this manner, the conductivity of the region that functions as an electrode can be increased. , the side of the conductor 318 which functions as a gate electrode, and the insulating layer which functions as a gate insulating layer. The sides of the edge are covered with an insulator that acts as a sidewall spacer (also called a sidewall insulating layer). By adopting such a configuration, the conductor 318 and the low resistance region 316 This can prevent the low-resistance region 316a and the low-resistance region 316b from being electrically connected to each other.

[0187] Over the transistor 550, the insulator 320, the insulator 322, the insulator 324, and the insulator The edge members 326 are stacked in order.

[0188] The insulators 320, 322, 324, and 326 may be, for example, an acid. silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, Aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used.

[0189] In this specification, silicon oxynitride refers to a material having a higher content of oxygen than nitrogen in its composition. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen. In this specification, aluminum oxynitride refers to a material with a high content. Aluminum oxide nitride is a material that has a higher oxygen content than nitrogen. It refers to a material that contains more nitrogen than oxygen as a constituent.

[0190] The insulator 322 serves to eliminate a step caused by the transistor 550 and the like provided below. For example, the top surface of the insulator 322 may have a function as a planarizing film. To improve flatness, the surface is flattened by a planarization process using chemical mechanical polishing (CMP) or other methods. It may be possible.

[0191] The insulator 324 is also provided with a substrate 311 or a transistor 550 or the like. A film having a barrier property to prevent diffusion of hydrogen and impurities is formed in the area where the star 500 is provided. It is preferable to use

[0192] An example of a film having a barrier property against hydrogen is silicon nitride formed by CVD. Here, a semiconductor having an oxide semiconductor such as the transistor 500 can be used. The diffusion of hydrogen into semiconductor elements can cause a deterioration in the characteristics of the semiconductor elements. Therefore, a film that suppresses hydrogen diffusion is provided between the transistor 500 and the transistor 550. Specifically, the film that suppresses the diffusion of hydrogen is a film that reduces the amount of hydrogen desorption. The membrane is thin.

[0193] The amount of hydrogen desorption can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorption from the insulator 324 can be determined by TDS analysis as follows: In the range of 50°C to 500°C, the amount of desorption converted to hydrogen atoms is Converted to a hit, it's 10 x 10 15 atoms / cm 2 Less than or equal to 5 x 10 15 a toms / cm 2 The following is fine.

[0194] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, The dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the insulator 326 is preferably 0.7 times or less than the relative dielectric constant of the insulator 324, and more preferably 0.6 times or less. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. can be reduced.

[0195] In addition, the insulators 320, 322, 324, and 326 are provided with capacitive elements. The conductor 328 and the conductor 330 are buried in the conductive layer 600 or the transistor 500. The conductors 328 and 330 are plugs or wires. In addition, the conductor having the function of a plug or wiring has a plurality of configurations. In addition, in this specification and the like, the wiring and the wiring The conductor and the plug to be connected may be an integral part. In some cases, a part of the conductor functions as a plug.

[0196] The materials for each plug and wiring (conductor 328, conductor 330, etc.) include metal materials, Conductive materials such as alloy materials, metal nitride materials, or metal oxide materials can be used in single or multilayer configurations. High-temperature materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, can be used. It is preferable to use a material with a melting point, and it is preferable to use tungsten. It is preferable to form the wiring board from a low-resistance conductive material such as aluminum or copper. This can reduce the wiring resistance.

[0197] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring that connects to the transistor 550. The conductor 356 is made of the same material as the conductors 328 and 330. It can be established as follows.

[0198] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 350 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 550 and the transistor 500 may be separated by a barrier layer. This can suppress the diffusion of hydrogen from the transistor 550 to the transistor 500.

[0199] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from transistor 550 can be suppressed while maintaining the overall conductivity. In this case, the tantalum nitride layer having a barrier property against hydrogen is It is preferable that the insulating material 350 has a structure in which the insulating material 350 is in contact with the insulating material 350.

[0200] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. An insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed on the insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductors 328 and 330 can be formed using the same materials.

[0201] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 360 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 550 and the transistor 500 may be separated by a barrier layer. This can suppress the diffusion of hydrogen from the transistor 550 to the transistor 500.

[0202] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. An insulator 370, an insulator 372, and an insulator 374 are stacked in this order. In addition, a conductor 376 is formed on the insulators 370, 372, and 374. The conductor 376 functions as a plug or wiring. The conductors 328 and 330 can be formed using the same materials.

[0203] For example, the insulator 370 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. In particular, an insulator 370 having a barrier property against hydrogen is useful. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 550 and the transistor 500 may be separated by a barrier layer. This can suppress the diffusion of hydrogen from the transistor 550 to the transistor 500.

[0204] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. An insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed on the insulators 380, 382, ​​and 384. The conductor 386 functions as a plug or wiring. The conductors 328 and 330 can be formed using the same materials.

[0205] For example, the insulator 380 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulator 380 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 550 and the transistor 500 may be separated by a barrier layer. This can suppress the diffusion of hydrogen from the transistor 550 to the transistor 500.

[0206] In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the conductor 376 The wiring layer including the conductor 386 has been described. The semiconductor device is not limited to this. The number of layers may be three or less, or five or more wiring layers similar to the wiring layer including the conductor 356. That's fine.

[0207] On the insulator 384 are an insulator 510, an insulator 512, an insulator 514, and an insulator 516. are stacked in this order. It is preferable that the insulator 516 is made of a material that has a barrier property against oxygen and hydrogen. It's nice.

[0208] For example, the insulator 510 and the insulator 514 may include, for example, the substrate 311 or the transformer. Hydrogen and impurities are introduced from the region where the resistor 550 is provided to the region where the transistor 500 is provided. Therefore, it is preferable to use a film having a barrier property against the insulator 324. The following materials can be used.

[0209] As an example of a film with barrier properties against hydrogen, silicon nitride formed by CVD is used. Here, a semiconductor element including an oxide semiconductor, such as the transistor 500, However, the diffusion of hydrogen may deteriorate the characteristics of the semiconductor element. A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 550. It is preferable that:

[0210] In addition, as a film having a barrier property against hydrogen, for example, an insulator 510 and an insulator 514 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable that

[0211] In particular, aluminum oxide is highly resistant to oxygen and water, which can cause fluctuations in the electrical characteristics of transistors. It has a high blocking effect that prevents impurities such as oxygen and moisture from penetrating the membrane. Aluminum oxide is a material that can withstand hydrogen, moisture, and other chemicals during and after the transistor manufacturing process. This can prevent impurities from entering the transistor 500. This can suppress the release of oxygen from the oxide that makes up the transistor. It is suitable for use as a protective film for the substrate 500.

[0212] For example, the insulators 512 and 516 may be made of the same material as the insulator 320. In addition, materials with relatively low dielectric constants can be used as insulators. For example, the insulator 512 and the insulator 513 can reduce the parasitic capacitance between the wirings. The edge 516 may be a silicon oxide film, a silicon oxynitride film, or the like.

[0213] In addition, the insulators 510, 512, 514, and 516 are made of conductive materials. 518, and the conductors (for example, conductor 503) that constitute the transistor 500 are filled in. Note that the conductor 518 is connected to the capacitor 600 or the transistor 550. The conductor 518 functions as a plug or wiring for connecting the conductor 328 and the The conductive material 330 can be used to form the conductive layer 330 .

[0214] In particular, the insulator 510 and the conductor 518 in the region in contact with the insulator 514 are oxidized to oxygen, hydrogen, and It is preferable that the conductive material has a barrier property against water. The transistor 550 and the transistor 500 have barrier properties against oxygen, hydrogen, and water. The layer having the hydrogen atoms can be separated from the transistor 550 to the transistor 500. The diffusion of can be suppressed.

[0215] Above the insulator 516 is the transistor 500 .

[0216] As shown in FIGS. 22A and 22B, transistor 500 includes an insulator 514 and an insulator 516. A conductor 503 disposed so as to be embedded in an insulator 516, an insulator 516 and a conductor An insulator 522 disposed on the insulator 503, and an insulator 524 disposed on the insulator 522. , an oxide 530a disposed on the insulator 524, and an oxide 530b disposed on the oxide 530a. The oxide 530b is provided with a conductor 542a and a conductor 542b spaced apart from each other on the oxide 530b. and a conductive material 542b, which is disposed on the conductive material 542a and the conductive material 542b. The insulator 580 has an opening formed therein overlapping the conductive member 542b, and the bottom and side surfaces of the opening are and a conductor 560 disposed on the surface of the insulator 545. do.

[0217] 22A and 22B, the oxide 530a, the oxide 530b, the conductive The insulator 544 is disposed between the conductor 542a and the conductor 542b and the insulator 580. As shown in FIGS. 22A and 22B, the conductor 560 is preferably made of an insulator 560. 45, and a conductor 560a provided inside the conductor 560a. 22A and 22B. As shown in FIG. 1, an insulator 574 is disposed on top of an insulator 580, a conductor 560, and an insulator 545. It is preferable to place

[0218] In this specification and the like, the oxide 530a and the oxide 530b are collectively referred to as oxides. This is sometimes called item 530.

[0219] In the transistor 500, an oxide is formed in the region where the channel is formed and in the vicinity thereof. 5 shows a structure in which two layers of a carbide 530a and an oxide 530b are stacked. For example, a single layer of oxide 530b or a stack of three or more layers may be used. A layer structure may be provided.

[0220] Although the transistor 500 shows the conductor 560 as having a two-layer structure, The present invention is not limited to this. For example, the conductor 560 may have a single layer structure. Alternatively, it may have a laminated structure of three or more layers. The transistor 500 shown is an example, and the circuit configuration, driving method, etc. are not limited to this configuration. An appropriate transistor may be used depending on the application.

[0221] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and and the conductor 542b function as a source electrode and a drain electrode, respectively. Thus, conductor 560 is inserted through the opening in insulator 580 and through conductors 542a and 542b. The conductor 560, the conductor 542a, and the conductor 542b are formed so as to be embedded in the region sandwiched between them. The placement of the conductor 542b is selected to be self-aligned with the opening of the insulator 580. In the transistor 500, the gate electrode is disposed between the source electrode and the drain electrode. Therefore, the conductor 560 can be arranged in a self-aligned manner without providing a margin for alignment. Since the transistor 500 can be formed without any problem, the area occupied by the transistor 500 can be reduced. This allows for miniaturization and high integration of semiconductor devices.

[0222] Furthermore, the conductor 560 is self-aligned in the region between the conductors 542a and 542b. Since the conductor 560 is formed, the area where the conductor 560 overlaps with the conductor 542a or the conductor 542b is As a result, the conductor 560 does not have a gap between the conductor 542a and the conductor 542b. The parasitic capacitance formed can be reduced. This improves the scanning speed and provides high frequency characteristics.

[0223] Conductor 560 may function as a first gate (also called top gate) electrode. In addition, the conductor 503 may function as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor 503 is connected to the potential applied to the conductor 560. By independently varying the threshold voltage of the transistor 500, the threshold voltage of the transistor 500 can be controlled. In particular, applying a negative potential to the conductor 503 can turn on the transistor 500. Therefore, it is possible to increase the threshold voltage and reduce the off-state current. Applying a negative potential to the conductor 503 is more effective than applying a negative potential to the conductor 560. This can reduce the drain current when the applied potential is 0V.

[0224] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. When a potential is applied to the conductor 560 and the conductor 503, The electric field generated by the conductor 503 is connected to the electric field generated by the conductor 503, and the choke formed in the oxide 530 is generated. The channel forming area can be covered.

[0225] In this specification, a pair of gate electrodes (a first gate electrode and a second gate electrode) The structure of a transistor in which the channel formation region is electrically surrounded by the electric field of This is called a rounded channel (S-channel) configuration. The S-channel configuration disclosed in is different from the fin type and planar type configurations. By adopting the S-channel structure, the resistance to the short channel effect is increased. This makes it possible to provide a transistor in which the short channel effect is less likely to occur.

[0226] The conductor 503 has the same structure as the conductor 518, and the insulator 514 and the insulator Conductor 503a is formed in contact with the inner wall of the opening of 516, and conductor 503b is formed further inside. In the transistor 500, the conductor 503a and the conductor 503b However, the present invention is not limited to this. For example, The conductor 503 may be provided as a single layer or a stacked structure of three or more layers.

[0227] Here, the conductor 503a is a diffusion layer for impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has the function of suppressing the impurities (i.e., the impurities are less likely to permeate). Alternatively, the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) can be suppressed. It is preferable to use a conductive material that has the function of preventing oxygen from permeating through the conductive material. In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of the above impurities or oxygen. has the function of suppressing the diffusion of any one or all of the above oxygen.

[0228] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503 This can prevent b from being oxidized and the electrical conductivity from decreasing.

[0229] When the conductor 503 also functions as a wiring, the conductor 503b is made of tungsten, copper, or the like. It is preferable to use a conductive material having high conductivity, such as aluminum or aluminum-based. In this embodiment, the conductor 503 is illustrated as a stack of conductors 503a and 503b. However, the conductor 503 may have a single layer structure.

[0230] The insulator 522 and the insulator 524 function as a second gate insulating film.

[0231] Here, the insulator 524 in contact with the oxide 530 has more oxygen than the stoichiometric composition. It is preferable to use an insulator containing a large amount of oxygen. The oxygen is released from the film by heating. In this specification and elsewhere, the oxygen released by heating is sometimes referred to as "excess oxygen." That is, the insulator 524 has a region containing excess oxygen (also called an "excess oxygen region"). It is preferable that the insulator containing such excess oxygen is formed in contact with the oxide 530. By providing the oxide 530, oxygen vacancies (V O :oxygen vacancy This can reduce the oxide film thickness (also referred to as oxide film thickness) and improve the reliability of the transistor 500. When hydrogen enters the oxygen vacancy in the oxide 530, the defect (hereinafter referred to as V O It may be called H ) can act as a donor, generating electrons as carriers. Some of them may combine with oxygen, which bonds with metal atoms, to generate electrons, which act as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is a normally-on transistor. In addition, hydrogen in oxide semiconductors tends to move due to stresses such as heat and electric fields. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor will decrease. In one embodiment of the present invention, V in the oxide 530 O Reduce H as much as possible, It is preferable to make it highly pure or substantially highly pure. O H is enough To obtain an oxide semiconductor with reduced impurities, it is necessary to remove impurities such as moisture and hydrogen from the oxide semiconductor. (also called "dehydration" or "dehydrogenation treatment") and supplying oxygen to the oxide semiconductor. It is important to compensate for the oxygen deficiency by adding oxygen (also called "oxygenation treatment"). O H, etc. To use an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor This allows stable electrical properties to be imparted.

[0232] As an insulator having an excess oxygen region, specifically, an oxide in which a part of oxygen is released by heating is used. It is preferable to use oxide materials. Oxides that release oxygen when heated are called TDS (Th Thermal Desorption Spectroscopy (DSS) analysis revealed that the oxygen atoms The converted amount of oxygen desorption is 1.0 x 10 18 atoms / cm 3 Above 1.0, preferably 1.0 x10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / c m 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is 100°C or higher and 700°C or lower, or The temperature is preferably in the range of 00°C or higher and 400°C or lower.

[0233] In addition, the insulator having the excess oxygen region and the oxide 530 are brought into contact with each other and subjected to heat treatment. One or more of microwave treatment and RF treatment may be performed. By performing this, water or hydrogen in the oxide 530 can be removed. At 530, a reaction occurs in which the VoH bond is broken, in other words, "V O H→Vo+ The reaction "H" occurs, and some of the hydrogen generated at this time is It combines with oxygen to form H2O, which is then removed from the oxide 530 or the insulators adjacent to the oxide 530. In addition, some of the hydrogen may be gettered to the conductor 542. .

[0234] The microwave treatment may be carried out using, for example, an apparatus having a power source that generates high-density plasma. Alternatively, it is preferable to use a device having a power source that applies RF to the substrate side. By using a gas containing oxygen and high density plasma, high density oxygen radicals are generated. By applying RF to the substrate side, the high density plasma generated Oxygen radicals are efficiently introduced into the oxide 530 or into the insulator near the oxide 530. The microwave treatment can be carried out at a pressure of 133 Pa or more, preferably 200 The pressure may be 400 Pa or more, more preferably 400 Pa or more. The gases introduced into the device are, for example, oxygen and argon, with an oxygen flow rate ratio (O / (O2+Ar)) is set to 50% or less, preferably 10% or more and 30% or less.

[0235] In addition, during the manufacturing process of the transistor 500, the surface of the oxide 530 is exposed. The heat treatment is preferably carried out at a temperature of, for example, 100° C. or higher and 450° C. or lower. The heat treatment is preferably performed at a temperature of 350° C. or higher and 400° C. or lower. Or in an inert gas atmosphere, or oxidizing gas is 10 ppm or more, 1% or more, or For example, it is preferable to carry out the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 530, and oxygen vacancies (V O) can be reduced. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out under nitrogen gas or nitrogen gas. After heat treatment in an active gas atmosphere, oxidizing gas was added at 10p to compensate for the oxygen that was released. The treatment may be carried out in an atmosphere containing at least pm, at least 1%, or at least 10% of an oxidizing gas. After heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more, Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0236] In addition, by performing an oxygen addition treatment on the oxide 530, oxygen vacancies in the oxide 530 are filled with oxygen. In other words, it promotes the reaction "Vo + O → null" Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530. This allows the hydrogen to be removed as H2O (dehydration). The hydrogen remaining in the substance 530 recombines with the oxygen vacancy to form V. O inhibits the formation of H It is possible.

[0237] Also, if the insulator 524 has an excess oxygen region, the insulator 522 may be oxygen-rich (e.g., It has the function of suppressing the diffusion of oxygen atoms, oxygen molecules, etc. (the oxygen is less likely to permeate) It is preferable that:

[0238] The insulator 522 has a function of suppressing the diffusion of oxygen and impurities, and the oxide 530 The oxygen contained in the conductive material 503 is preferably not diffused to the conductive material 503 side. This can prevent the insulator 524 and the oxide 530 from reacting with oxygen.

[0239] The insulator 522 may be, for example, aluminum oxide, hafnium oxide, aluminum and hafnium oxide. Oxides containing hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, Lead zirconate titanate (PZT), strontium titanate (SrTiO3), or ( Insulators containing so-called high-k materials such as Ba,Sr)TiO3 (BST) are deposited in a single layer or As transistors become smaller and more highly integrated, Thinning the gate insulating film can cause problems such as leakage current. By using a high-k material as an insulator that functions as a transistor, the physical thickness can be maintained. This makes it possible to reduce the gate potential during transistor operation.

[0240] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the oxygen is less likely to permeate). a) Insulators containing oxides of one or both of aluminum and hafnium, which are insulating materials It is recommended to use an insulator containing oxides of either or both aluminum and hafnium. Aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium ( It is preferable to use materials such as hafnium aluminate. When the insulator 522 is formed, the insulator 522 prevents oxygen from being released from the oxide 530 and prevents the transistor from being damaged. This layer functions as a layer that suppresses the intrusion of impurities such as hydrogen from the periphery of the capacitor 500 into the oxide 530. do.

[0241] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, or the like may be added to these insulators. um, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Zirconium oxide may be added, or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the insulator. .

[0242] 22A and 22B, the transistor 500 has a two-layer structure. As the second gate insulating film, an insulator 522 and an insulator 524 are shown. The gate insulating film may have a single layer, three layers, or a laminated structure of four or more layers. In this case, the laminated structure is not limited to a laminated structure made of the same material, and may be a laminated structure made of different materials.

[0243] The transistor 500 includes an oxide 530 including a channel formation region, and an oxide semiconductor For example, In-M-Zn oxide (originally The element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, or boron. , titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium Choose from aluminum, neodymium, hafnium, tantalum, tungsten, or magnesium. It is preferable to use a metal oxide such as one or more metal oxides selected from the group consisting of fluorine and methyl methacrylate.

[0244] The metal oxide that functions as an oxide semiconductor may be formed by a sputtering method. Alternatively, the deposition may be performed by ALD (Atomic Layer Deposition).

[0245] In addition, the metal oxide that functions as a channel formation region in the oxide 530 is a band gap. It is preferable to use a material with a gap of 2 eV or more, preferably 2.5 eV or more. As shown in Fig. 1, by using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. can be reduced.

[0246] The oxide 530 has an oxide 530a under the oxide 530b, so that the oxide 530a The diffusion of impurities from the structure formed below the oxide 530b can be suppressed. can.

[0247] The oxide 530 has a laminated structure of a plurality of oxide layers with different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 530a, it is preferable to use The atomic ratio of element M in the metal oxide used for oxide 530b is It is preferable that the atomic ratio of the metal oxide used for the oxide 530a is larger than that of the element M. In the oxide 530b, the atomic ratio of element M to In is In the oxide 530b, the atomic ratio of the element M to In is preferably larger than that of the element M. In the metal oxide used for the oxide 530a, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In to the element M in the metal oxide is larger than that of In.

[0248] In addition, the energy of the conduction band minimum of the oxide 530a is greater than the energy of the conduction band minimum of the oxide 530b. In other words, the electron affinity of the oxide 530a is preferably higher than the electron affinity of the oxide 530a. is preferably smaller than the electron affinity of oxide 530b.

[0249] Here, at the junction between the oxide 530a and the oxide 530b, the energy of the bottom of the conduction band is In other words, the junction of oxide 530a and oxide 530b The energy level of the conduction band minimum at the junction changes continuously or is called a continuous junction. To achieve this, the oxide 530a and the oxide 530b are This is advantageous in that the defect level density of the mixed layer formed by this method is reduced.

[0250] Specifically, the oxide 530a and the oxide 530b have a common element other than oxygen (mainly By using the oxide as a component, it is possible to form a mixed layer with a low defect level density. When the material 530b is an In-Ga-Zn oxide, the oxide 530a is an In-Ga-Zn It is preferable to use oxide, Ga-Zn oxide, gallium oxide, etc.

[0251] At this time, the main path of the carriers is the oxide 530b. By forming the oxide 530a and the oxide 530b in this manner, the defect state density at the interface between the oxide 530a and the oxide 530b is reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and The transistor 500 can obtain a high on-state current.

[0252] On the oxide 530b, a conductor 542 is formed, which functions as a source electrode and a drain electrode. The conductors 542a and 542b are provided as follows: are aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum Niobium, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium Strontium, Beryllium, Indium, Ruthenium, Iridium, Strontium, Lanthanum or an alloy containing the above metal element as a component, or the above metal element It is preferable to use an alloy in which the above-mentioned materials are combined. For example, tantalum nitride, titanium nitride, tantalum tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum , ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum It is preferable to use oxides containing tantalum and nickel. titanium and aluminum nitrides, tantalum and aluminum nitrides, and titanium oxides Ruthenium, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel Oxides containing chlorine are conductive materials that are resistant to oxidation, or that maintain conductivity even when they absorb oxygen. Furthermore, metal nitride films such as tantalum nitride are preferred because they are materials that can withstand hydrogen or It is preferable because it has a barrier property against oxygen.

[0253] In addition, in FIG. 22A, the conductor 542a and the conductor 542b are shown as having a single layer configuration. However, a laminated structure of two or more layers may be used. For example, a tantalum nitride film and a tungsten film may be laminated. Alternatively, a titanium film and an aluminum film may be stacked. Two-layer structure with an aluminum film laminated on top, and copper on a copper-magnesium-aluminum alloy film Two-layer structure with a copper film laminated on a titanium film, two-layer structure with a copper film laminated on a tungsten film It may also be a two-layer structure in which these are laminated.

[0254] Also, a titanium film or titanium nitride film and an aluminum film overlaid on the titanium film or titanium nitride film are used. An aluminum film or a copper film is laminated, and a titanium film or a titanium nitride film is further formed thereon. A three-layer structure consisting of a molybdenum film or molybdenum nitride film and a molybdenum film or molybdenum nitride film. An aluminum or copper film is layered on top of the molybdenum film, and then a molybdenum or In addition, there are three-layer structures in which indium oxide, tin oxide or molybdenum nitride is formed. Alternatively, a transparent conductive material containing zinc oxide may be used.

[0255] As shown in FIG. 22A, the oxide 530 is formed of the conductor 542a (conductor 542b). At the interface and in the vicinity thereof, a region 543a and a region 543b are formed as low resistance regions. In this case, the region 543a may be used as either a source region or a drain region. The region 543b functions as the other of the source region and the drain region. A channel forming region is formed in the region sandwiched between the region 543a and the region 543b.

[0256] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, The oxygen concentration in the region 543a (region 543b) may decrease. The metal contained in the conductor 542a (conductor 542b) and the oxide 530 are In such a case, a metal compound layer containing the component may be formed in the region 543a (region The carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region. become.

[0257] The insulator 544 is provided to cover the conductor 542a and the conductor 542b. The insulator 544 prevents oxidation of the conductive material 542a and the conductive material 542b. It may be provided to cover the side of object 530 and to be in contact with insulator 524.

[0258] Insulator 544 includes hafnium, aluminum, gallium, yttrium, and zirconium. Smoke, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum Alternatively, a metal oxide containing one or more selected from magnesium, etc. may be used. The insulator 544 may be made of silicon oxynitride or silicon nitride. It can also be used.

[0259] In particular, the insulator 544 may be an oxide of aluminum or hafnium or both. Insulators containing aluminum oxide, hafnium oxide, aluminum, and hafnium It is preferable to use oxides containing hafnium (hafnium aluminate). Hafnium aluminate has higher heat resistance than hafnium oxide film. This is preferable because it is difficult to crystallize during heat treatment at room temperature. The body 542b is made of a material that is resistant to oxidation or that does not lose conductivity even when it absorbs oxygen. In this case, the insulator 544 is not an essential component. It should be designed appropriately.

[0260] By including the insulator 544, impurities such as water and hydrogen contained in the insulator 580 can be removed. The diffusion of the insulator 580 into the oxide 530b can be suppressed. The excess oxygen can prevent the conductor 542 from being oxidized.

[0261] The insulator 545 functions as a first gate insulating film. Similar to the body 524, an insulator containing excess oxygen and releasing oxygen when heated is used. It is preferable to form

[0262] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, Silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon, and Silicon oxide doped with nitrogen and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferred because they are stable to heat.

[0263] By providing an insulator containing excess oxygen as the insulator 545, oxygen can be removed from the insulator 545. Oxygen can be effectively supplied to the channel forming region of the oxide 530b. As with 524, the concentration of impurities such as water or hydrogen in the insulator 545 is reduced. The thickness of the insulator 545 is preferably 1 nm or more and 20 nm or less. The above-described microwave treatment may be performed before and / or after the formation of the insulator 545. good.

[0264] In addition, in order to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530, A metal oxide may be provided between the insulating layer 545 and the conductor 560. It is preferable to suppress the diffusion of oxygen from the body 545 to the conductor 560. By providing a metal oxide, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. In other words, it is possible to suppress the decrease in the amount of excess oxygen supplied to the oxide 530. In addition, oxidation of the conductor 560 due to excess oxygen can be suppressed. Any material that can be used for the insulator 544 may be used.

[0265] Note that the insulator 545 may have a stacked structure similar to the second gate insulating film. As transistors become smaller and more highly integrated, the gate insulating film becomes thinner, which reduces leakage current and other problems. Therefore, the insulator that functions as the gate insulating film should be high-k By using a laminated structure of a material that is thermally stable, the thickness of the material can be maintained while maintaining the thickness of the material. This allows the gate potential to be reduced during transistor operation. A simple laminated structure can be achieved.

[0266] The conductor 560 that functions as the first gate electrode has a two-layer structure in FIGS. 22A and 22B. However, it may have a single layer structure or a laminated structure of three or more layers.

[0267] The conductor 560a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule. (N2O, NO, NO2, etc.), conductive material with the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material containing a small amount of oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of suppressing the diffusion of at least one of the conductors. Since 60a has the function of suppressing the diffusion of oxygen, the oxygen contained in the insulator 545 This can prevent the conductor 560b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing scattering include tantalum, tantalum nitride, and tantalum fluoride. It is preferable to use ruthenium oxide or ruthenium oxide as the conductor 560a. Therefore, an oxide semiconductor that can be used for the oxide 530 can be used. By forming the conductive material 60b by sputtering, the electrical resistance value of the conductive material 560a is reduced. It can be made into a conductor. This is called an OC (Oxide Conductor) electrode. It is possible.

[0268] The conductor 560b is a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 560b also functions as a wiring, It is preferable to use a conductor with high conductivity, such as tungsten, copper, or aluminum. The conductor 560b can be made of a conductive material containing aluminum as a main component. For example, a laminated structure of titanium or titanium nitride and the above conductive material may be used. good.

[0269] The insulator 580 is disposed on the conductor 542a and the conductor 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. 80 includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and fluorine. Nitrogen-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide It is preferable that the material be silicon oxide, silicon oxide having pores, or resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and silicon oxide with vacancies easily form excess oxygen regions in later processes. This is preferable because it can

[0270] The insulator 580 preferably has an excess oxygen region. Oxygen is released upon heating. By providing the insulator 580, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. It should be noted that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced. It is preferable that

[0271] The opening in the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b. As a result, the conductor 560 is connected to the opening of the insulator 580 and the conductor 542a. It is formed so as to be embedded in the region sandwiched between the bodies 542b.

[0272] In miniaturizing semiconductor devices, it is required to shorten the gate length. It is necessary to prevent the conductivity of the conductor 60 from decreasing. In this embodiment, the conductor 560 may have a shape with a high aspect ratio. The conductor 560 is provided so as to be embedded in the opening of the insulator 580. Even a shape with a high ratio can be formed without causing the conductor 560 to collapse during the process. Cut.

[0273] The insulator 574 is disposed on the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. The insulator 574 is preferably provided in contact with the surface. Thus, an excess oxygen region can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied into the oxide 530 from the excess oxygen region.

[0274] For example, the insulator 574 may be hafnium, aluminum, gallium, yttrium, Zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium It is possible to use a metal oxide containing one or more metals selected from the group consisting of cadmium, cadmium, and sulphur. Cut.

[0275] In particular, aluminum oxide has a high barrier property and is a thin film of 0.5 nm to 3.0 nm. Therefore, the diffusion of hydrogen and nitrogen can be suppressed even if sputtering is performed. The aluminum oxide film formed by this method is a source of oxygen and also a barrier for impurities such as hydrogen. It can also function as a film.

[0276] In addition, it is preferable to provide an insulator 581 that functions as an interlayer film over the insulator 574. The insulator 581, like the insulator 524, has a low impurity concentration such as water or hydrogen in the film. is preferably reduced.

[0277] Also, the insulating material 581, the insulating material 574, the insulating material 580, and the insulating material 544 are formed. The conductor 540a and the conductor 540b are disposed in the opening. The conductor 540a and the conductor 540b are provided opposite each other with the conductor 560 in between. 0b has the same configuration as conductor 546 and conductor 548, which will be described later.

[0278] An insulator 582 is provided on the insulator 581. The insulator 582 is resistant to oxygen and hydrogen. Therefore, the insulator 582 is preferably made of an insulating material. The insulator 582 may be made of the same material as the insulator 514. For example, aluminum oxide may be used. It is preferable to use metal oxides such as tungsten oxide, hafnium oxide, and tantalum oxide.

[0279] In particular, aluminum oxide is highly resistant to oxygen and water, which can cause fluctuations in the electrical characteristics of transistors. It has a high blocking effect that prevents impurities such as oxygen and moisture from penetrating the membrane. Aluminum oxide is a material that can withstand hydrogen, moisture, and other chemicals during and after the transistor manufacturing process. This can prevent impurities from entering the transistor 500. This can suppress the release of oxygen from the oxide that makes up the transistor. It is suitable for use as a protective film for the substrate 500.

[0280] An insulator 586 is provided on the insulator 582. The insulator 586 is The same materials as those of 320 can be used. In addition, these insulators have a relatively low dielectric constant. By using a material with high insulating properties, the parasitic capacitance between wiring can be reduced. The edge 586 can be a silicon oxide film, a silicon oxynitride film, or the like.

[0281] Also, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator 574, the insulator The edge 581, the insulator 582, and the insulator 586 are connected to the conductor 546 and the conductor 54 8th magnitude is embedded.

[0282] The conductor 546 and the conductor 548 are connected to the capacitor 600, the transistor 500, or The conductor 546 functions as a plug or wiring connected to the transistor 550. The conductor 548 is made of the same material as the conductor 328 and the conductor 330. It is possible.

[0283] After the transistor 500 is formed, an opening is formed to surround the transistor 500. An insulator having high barrier properties against hydrogen or water may be formed so as to cover the opening. By encasing the transistor 500 in the insulator with high barrier properties, moisture, In addition, it is possible to prevent hydrogen from penetrating the transistors 500. The whole may be wrapped in an insulator that has high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, the insulator 522 or the insulator An opening is formed that reaches the insulator 514, and the above-mentioned barrier is placed in contact with the insulator 522 or the insulator 514. If a highly flexible insulator is formed, the manufacturing process of the transistor 500 can be performed simultaneously. In addition, examples of insulators with high barrier properties against hydrogen or water include A material similar to that of the insulator 522 or the insulator 514 may be used.

[0284] Next, a capacitor 600 is provided above the transistor 500. 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0285] Furthermore, a conductor 612 may be provided over the conductor 546 and the conductor 548. 612 has a function as a plug or wiring that connects to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. The conductive material 610 and the conductive material 610 can be formed simultaneously.

[0286] Conductor 612 and conductor 610 may be made of molybdenum, titanium, tantalum, tungsten, or the like. Metal film containing elements selected from the group consisting of silicon, aluminum, copper, chromium, neodymium, and scandium or a metal nitride film containing the above-mentioned elements (tantalum nitride film, titanium nitride film, nitride Molybdenum film, tungsten nitride film, etc. can be used. oxides containing tungsten oxide, indium zinc oxides containing tungsten oxide Lead oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide, Conductive materials such as indium zinc oxide and indium tin oxide doped with silicon oxide are used. It can also be used.

[0287] In this embodiment, the conductor 612 and the conductor 610 are shown as having a single-layer structure. For example, a conductive material having a barrier property and a conductive material having a barrier property may be used. Conductors with barrier properties and highly conductive conductors A highly adhesive conductor may be formed.

[0288] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. The conductor 620 is made of a conductive material such as a metal material, an alloy material, or a metal oxide material. High-melting-point materials such as tungsten and molybdenum, which are both heat-resistant and conductive, are used. It is preferable to use tungsten, and it is particularly preferable to use tungsten. When forming the insulating film simultaneously with other components, low-resistance metal materials such as Cu (copper) and Al (aluminum) are used. You can use a .um.

[0289] An insulator 640 is provided on the conductor 620 and the insulator 630. The insulator 40 can be made of the same material as the insulator 320. , and may function as a planarizing film that covers the underlying unevenness.

[0290] By using this structure, a semiconductor device including a transistor having an oxide semiconductor This allows for miniaturization or high integration.

[0291] The configurations, structures, methods, and the like shown in this embodiment may be used in conjunction with other embodiments and examples. The configuration, structure, method, etc. can be used in appropriate combination.

[0292] (Embodiment 5) In this embodiment, the components of the data processing system 100 described in the above embodiment are The configuration of an integrated circuit including the above will be described with reference to FIGS. 23A and 23B.

[0293] FIG. 23A is a diagram illustrating an integrated circuit including each component of the processing system 100. 23A is an example of a schematic diagram. The integrated circuit 390 shown in FIG. The accelerator described as the device 10 includes a part of its circuitry made of OS transistors. By doing so, each circuit can be integrated into a single integrated circuit.

[0294] As shown in FIG. 23A, in the CPU 110, the O The backup circuit 222 may be provided in a layer having an S transistor. As shown in FIG. 23A, in the accelerator described as the semiconductor device 10, The layer above the layer having the Si transistors that constitute the arithmetic circuit section 40 is an OS transistor. The memory circuit portion 30 can be provided in a layer having an OS transistor. The layer having the data may be configured to include an OS memory 300N. As for 00N, in addition to the NOSRAM described in the above embodiment, DOSRAM is also applied. In addition, in the OS memory 300N, a layer having a Si transistor is provided. By stacking a layer containing OS transistors on the driver circuit, memory density can be improved. This can be done.

[0295] As shown in FIG. 23A, the CPU 110, the accelerator described as the semiconductor device 10, In the case of an SoC in which each circuit such as the processor and OS memory are tightly coupled, there is a problem of heat generation. However, the fluctuation of electrical characteristics due to heat in OS transistors is smaller than that in Si transistors. In addition, as shown in FIG. 23A, circuits can be integrated in three dimensions. By doing so, through silicon vias (TSV) The parasitic capacitance can be reduced compared to stacked structures using This reduces the power consumption required for discharging, thereby improving the efficiency of calculation processing. This can be done.

[0296] FIG. 23B shows an example of a semiconductor chip incorporating an integrated circuit 390. The semiconductor chip 391 has leads 392 and an integrated circuit 390. The integrated circuit 390 includes: As explained in FIG. 23A, the various circuits shown in the above embodiments are provided on one die. The integrated circuit 390 has a stacked structure, and a layer having a Si transistor (Si transistor a wiring layer 394; a layer having an OS transistor (an OS transistor layer 395); The OS transistor layer 395 is stacked on the Si transistor layer 393. Since the semiconductor chip 391 can be provided, it is easy to reduce the size of the semiconductor chip 391.

[0297] In FIG. 23B, the package of the semiconductor chip 391 is a QFP (Quad Flat Pack). Although the packaging is applied, the packaging form is not limited to this. Examples include DIP (Dual In-line Package), which is an insertion type, PGA (Pin Grid Array), surface mount SOP (Small Outlet Package) tline Package), SSOP(Shrink Small Outline Package), TSOP (Thin-Small Outline Packag) e), LCC (Leaded Chip Carrier), QFN (Quad Fla tNon-leaded package), BGA(Ball Grid Arra y), FBGA (Fine pitch Ball Grid Array), contact mounting DTP (Dual Tape carrier Package), QTP (Q Structures such as a tape-carrier package can be used as appropriate. do.

[0298] An arithmetic circuit and a switching circuit having Si transistors, and a memory having OS transistors The circuit is entirely made up of a Si transistor layer 393, a wiring layer 394 and an OS transistor layer 39 That is, the elements constituting the semiconductor device can be formed in the same manufacturing process. Therefore, the IC shown in FIG. 23B can be formed by the following process. Even if the number of semiconductor devices increases, there is no need to increase the manufacturing process, and the semiconductor device can be incorporated at low cost. can.

[0299] According to the above-described embodiment of the present invention, a novel semiconductor device and an electronic device can be provided. According to one embodiment of the present invention, a semiconductor device and an electronic device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device and a semiconductor device capable of suppressing heat generation can be provided. and electronic equipment.

[0300] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0301] (Embodiment 6) In this embodiment, the integrated circuit 390 described in the above embodiment can be applied. The electronic device, the mobile object, and the computing system will be described with reference to FIGS.

[0302] FIG. 24A shows an external view of an automobile as an example of a moving object. A simplified diagram of data exchange within a car 590. A car 590 is equipped with multiple cameras 591, etc. The automobile 590 also has an infrared radar, a millimeter wave radar, a laser radar, It is equipped with various sensors (not shown), such as:

[0303] In the automobile 590, the integrated circuit 390 (or the integrated circuit The semiconductor chip 391 incorporating the camera 390 can be used. The image sensor 591 captures a plurality of images taken in a plurality of imaging directions 592 in the same manner as in the embodiment above. The processing is performed by the circuit 390, and a host controller 594 or the like outputs a plurality of images via a bus 593 or the like. By analyzing all the images at once, it is possible to determine the surrounding traffic conditions, such as the presence of guardrails or pedestrians. It can also be used in systems that provide road guidance and risk prediction. It is possible.

[0304] The integrated circuit 390 processes the obtained image data using a neural network or other arithmetic processing. By doing this, for example, it is possible to increase the resolution of images, reduce image noise, perform face recognition (for crime prevention purposes, etc.), Object recognition (for the purpose of autonomous driving, etc.), image compression, image correction (wide dynamic range), Processing of image restoration, positioning, character recognition, reflection reduction, etc. for lensless image sensors This can be done.

[0305] In the above description, an automobile is used as an example of a moving body. For example, the moving object may be a train, a monorail, a ship, an aircraft (helicopter, These include vehicles such as drones, airplanes, and rockets. Applying a computer according to one aspect of the present invention to a moving object gives it a system that utilizes artificial intelligence. It is possible.

[0306] 25A is an external view showing an example of a portable electronic device. The portable electronic device 595 is a simplified diagram of data exchange within the device. It has a substrate 596, a speaker 597, a camera 598, a microphone 599, etc.

[0307] In a portable electronic device 595, the integrated circuit 390 is provided on a printed wiring board 596. The portable electronic device 595 includes a speaker 597, a camera 598, a microphone The integrated circuit 390 described in the above embodiment is used to obtain a plurality of data obtained from the phone 599, etc. By processing and analyzing the data, it is possible to improve user convenience. It can be used in systems that perform image searches, etc.

[0308] The integrated circuit 390 processes the obtained image data using a neural network or other arithmetic processing. By doing this, for example, it is possible to increase the resolution of images, reduce image noise, perform face recognition (for crime prevention purposes, etc.), Object recognition (for the purpose of autonomous driving, etc.), image compression, image correction (wide dynamic range), Processing of image restoration, positioning, character recognition, reflection reduction, etc. for lensless image sensors This can be done.

[0309] The portable game machine 1100 shown in FIG. 26A includes a housing 1101, a housing 1102, and a housing 1103. 3, a display unit 1104, a connection unit 1105, operation keys 1107, etc. The body 1102 and the housing 1103 can be removed. By attaching the connector 1105 to the housing 1108, the image is output to the display unit 1104. The video can be output to another video device. By attaching the housing 1109 to the housing 1102, the housing 1103 is integrated, and the operation The chips provided on the substrates of the housings 1102 and 1103 function as a part. The integrated circuit 390 shown in the previous embodiment can be incorporated into any of these.

[0310] FIG. 26B shows a stick-type electronic device 1120 that can be connected via USB. 20 includes a housing 1121, a cap 1122, a USB connector 1123, and a circuit board 1124. The substrate 1124 is housed in the housing 1121. For example, the substrate 1124 has , memory chip 1125, and controller chip 1126 are mounted on the board 11. The integrated circuit 390 shown in the previous embodiment is incorporated into the controller chip 1126 of 24. It can be done.

[0311] Figure 26C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106, and a control circuit 2110. For example, the control circuit 2110 includes the The integrated circuit 390 shown in the form of

[0312] The integrated circuit 390 described in the above embodiment is not built into the electronic device, but is installed in the electronic device. In this case, the electronic device and the server can be used to communicate with each other. 27 shows an example of the configuration of the system 3000.

[0313] The system 3000 is configured by an electronic device 3001 and a server 3002. Communication between the slave device 3001 and the server 3002 is performed via the Internet line 3003. It is possible to do so.

[0314] The server 3002 has multiple racks 3004. The multiple racks each have multiple bases. A substrate 3005 is provided, and the integrated circuit 390 described in the above embodiment is provided on the substrate 3005. This allows the server 3002 to be equipped with a neural network. The server 3002 then receives the data from the electronic device 3001 via the internet line 30 Using the data input via 03, neural network calculations can be performed. The results of the calculations by the server 3002 can be transmitted via the internet line 3003 as needed. This allows the electronic device 3001 to receive the data. This can reduce the computational burden.

[0315] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0316] (Notes regarding the present specification) The following additional notes will be given regarding the above-described embodiments and the respective configurations in the embodiments. .

[0317] The configurations shown in each embodiment may be appropriately combined with the configurations shown in other embodiments or examples. In addition, one embodiment may include a plurality of configurations. When examples are shown, the configuration examples can be combined as appropriate.

[0318] It should be noted that the contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the form, and / or one or more other The contents (or a part of the contents) described in the embodiment of the present invention may be applied, combined, or You can make substitutions etc.

[0319] The contents described in the embodiments are explained using various drawings in each embodiment. This refers to the content stated in the specification or the content stated using the text in the specification.

[0320] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. Another figure (or a part thereof) described in the embodiment, and / or one or more The figures (or a part thereof) described in a plurality of different embodiments may be combined. allows for the construction of even more diagrams.

[0321] In addition, in the block diagrams in this specification, components are classified by function and are independent of each other. However, in actual circuits, the components are divided into functional blocks. It is difficult to separate the functions into separate parts, and there are cases where multiple functions are involved in one circuit, or where a circuit is involved in multiple circuits. Therefore, the blocks in the block diagram may be The present invention is not limited to the components described above, and may be rephrased appropriately depending on the situation.

[0322] In addition, in the drawings, the size, layer thickness, and area are arbitrarily scaled for convenience of explanation. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely schematic illustrations for the sake of convenience, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or timing deviations. This may include variations in signal, voltage, or current due to the

[0323] In addition, the positional relationships of the components shown in the drawings are relative. When describing components by reference, the terms "above" and "below" that indicate positional relationships are used for convenience. The positional relationship of the components is not limited to the contents described in this specification, and may vary depending on the situation. It can be rephrased appropriately depending on the situation.

[0324] In this specification and the like, when describing the connection relationship of a transistor, the term "source or drain" is used. "one of the two" (or first electrode, or first terminal), "the other of the two The term "second electrode" is used to refer to the source and drain of a transistor. This is because the drain varies depending on the structure or operating conditions of the transistor. The names of the source and drain of a transistor are the source (drain) terminal and the source (drain) terminal. In) electrodes, etc., can be rephrased appropriately depending on the situation.

[0325] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. This is not a limitation. For example, an "electrode" may be used as part of a "wiring." , and vice versa. Furthermore, the terms "electrode" and "wiring" may be used interchangeably with "electrodes" and "wiring." This also includes cases where the wiring is formed integrally.

[0326] In this specification and the like, the terms voltage and potential can be interchanged as appropriate. The potential difference from the reference potential. For example, the reference potential is the ground voltage (earth If we use the term "voltage", we can translate voltage into potential. Ground potential is not necessarily 0V. It does not necessarily mean that the potential is relative, and depending on the reference potential, The potential applied to wiring etc. may be changed.

[0327] In this specification, a node may be a terminal, a wiring, or the like depending on a circuit configuration, a device structure, or the like. The term "electrode," "conductive layer," "conductor," "impurity region," etc. may also be used. Lines and the like can be referred to as nodes.

[0328] In this specification, "A and B are connected" means that A and B are electrically connected. Here, A and B are electrically connected to each other. Objects (switches, transistor elements, diodes, etc.), or the elements and A connection that allows transmission of electrical signals between A and B when there is a circuit (including wiring, etc.) If A and B are electrically connected, it is considered that A and B are directly connected. Here, A and B being directly connected means that they are connected via the above object. Instead, electrical signals can be transmitted between A and B via wiring (or electrodes) etc. In other words, a direct connection is a connection that can be seen as the same circuit diagram when expressed as an equivalent circuit. This refers to the connection that can be made.

[0329] In this specification, a switch refers to a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It refers to a device that has the function of controlling whether or not current flows by entering a state where it is in a non-operating state. A switch is a device that has the function of selecting and switching a path through which a current flows.

[0330] In this specification and the like, the channel length is, for example, the length of a semiconductor the body (or the part of the semiconductor through which current flows when the transistor is on) and the gate The distance between the source and drain in the region where they overlap or where the channel is formed. It means separation.

[0331] In this specification, the channel width is, for example, the width of a semiconductor (or a transistor) when it is in an on state. The area where the gate electrode overlaps with the gate electrode (the area where current flows in the semiconductor when the gate electrode is in the non-transistor state), or the channel The length of the portion where the source and drain face each other in the region where the capacitor is formed. .

[0332] In this specification, the terms "film" and "layer" are used in some cases or in other situations. For example, the term "conductive layer" can be used interchangeably with " It may be possible to change the term to "conductive film." In some cases, the term "insulating layer" can be changed to the term "insulating layer." [Explanation of symbols]

[0333] WEL: wiring, WOL: wiring, 10: semiconductor device, 12: driving circuit, 13: driving circuit, 1 4: control circuit, 15: processing circuit, 20_E: calculation block section, 20_O: calculation block section ,21_E: Calculation block, 21_O: Calculation block, 21: Calculation block, 30: Memory Circuit section, 31: memory circuit, 40: arithmetic circuit section, 41: latch circuit, 42: switching circuit, 43 _E: Buffer circuit, 43_O: Buffer circuit, 44: Switching circuit, 45: Arithmetic circuit

Claims

[Claim 1] a first processing block having a first memory circuit unit and a first processing circuit unit; a second calculation block having a second memory circuit unit and a second calculation circuit unit; The semiconductor device includes a first wiring and a second wiring, the first storage circuit unit has a first storage circuit that holds a plurality of first weight data; the second storage circuit unit has a second storage circuit that holds a plurality of second weight data; the first arithmetic circuit unit includes a first arithmetic circuit, a first switching circuit, and a third switching circuit; the second arithmetic circuit unit includes a second arithmetic circuit, a second switching circuit, and a fourth switching circuit; the first switching circuit has a function of providing any one of the plurality of first weight data to the first wiring, the second switching circuit has a function of providing any one of the plurality of second weight data to the second wiring, the third switching circuit has a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the first arithmetic circuit; the fourth switching circuit has a function of providing either the first weight data provided to the first wiring or the second weight data provided to the second wiring to the second arithmetic circuit.

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