Semiconductor device

Abstract

To provide a semiconductor device capable of product-sum operation with low consumption power.SOLUTION: In a semiconductor device, a calculation circuit MAC1 includes a circuit WCS, a circuit XCS, a circuit WSD, a circuit SWS1, a circuit SWS2, a cell array CA, and a conversion circuit ITRZ[1] to a conversion circuit ITRZ[n] (n is an integer of 1 or more). The cell array CA includes a cell IM[1, 1] to a cell IM[m, n] (m is an integer of 1 or more) and a cell IMref[1] to a cell IMref[m]. Each of the cells IM[1, 1] to IM[m, n] keeps the potentials corresponding to the amount of current according to first data. The cell IM[1] to the cell IM[m] supply the kept potentials and potentials according to second data required to perform the product-sum operation to a wire XCL[1] to a wire XCL[m]. Each cell IM includes transistors F1 and F2 and a capacitor C5. Each cell IMref includes transistors F1m and F2m and a capacitor C5m.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an object, a driving method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. Therefore, one embodiment of the present invention disclosed in this specification more specifically relates to The technical fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, and imaging devices. Devices, storage devices, signal processing devices, sensors, processors, electronic devices, systems, and their driving Examples include methods, methods for producing them, or methods for inspecting them. [Background technology]

[0003] Currently, the development of integrated circuits that mimic the mechanisms of the human brain is progressing vigorously. The brain's mechanisms are incorporated as electronic circuits, and the brain's "neurons" and "systems" are connected. Therefore, such an integrated circuit is called a "neuromorph." It is sometimes called "brain-morphic," "brain-inspired," etc. The integrated circuit has a non-von Neumann architecture, and power consumption decreases as processing speed increases. Compared to the von Neumann architecture, which has a high power consumption, parallel processing is possible with extremely low power consumption. It is expected that this will be possible.

[0004] An information processing model that mimics a neural network with "neurons" and "synapses" is called an artificial Artificial neural networks (ANNs) are used to This makes it possible to make inferences with accuracy comparable to or even exceeding that of humans. In this network, the main operation is the sum of weighted neuron outputs, i.e., the sum of products operation. do.

[0005] Non-Patent Document 1 proposes a product-sum operation circuit using non-volatile memory elements. In the sum-of-products operation circuit, each memory element has a transistor having silicon in the channel forming region. The multiplier stored in each memory element is calculated using the subthreshold operation of the The current corresponding to the multiplication of the data corresponding to the multiplicand and the input data corresponding to the multiplicand is output. The sum of the currents output by the memory elements in each column is used to obtain data corresponding to the sum-of-products operation. The sum-of-products operation circuit has an internal memory element, so it does not require external memory for multiplication and addition. Therefore, reading and writing data from the memory can be prevented. This reduces the number of data transfers due to writing and other processes, thereby reducing power consumption. It is expected that this will reduce [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] X. Guo et al., “Fast, Energy-Efficient, Robust, and Reproducible Mixed-Signal Neuromorphic Classifier Based on Embedded NOR Flash Memory Technology” IEDM2017, pp.151-154. Summary of the Invention [Problem to be solved by the invention]

[0007] A transistor that has silicon in the channel formation region changes its state due to temperature changes. In particular, when a product-sum operation circuit is used as an integrated circuit, the capacitance characteristics, field-effect mobility, etc. are easily affected. When the integrated circuit is formed, the temperature of the integrated circuit rises due to heat generated when it is operated, and the There is a risk that the characteristics of the transistors used will change and correct calculations will not be possible.

[0008] In addition, when a multiply-and-accumulate operation is performed by a digital circuit, the digital data that becomes the multiplier (multiplier data The digital multiplication circuit multiplies the digital data (multiplicand data) that is the multiplicand. Then, the digital data (product data) obtained by the multiplication is added to the digital addition circuit. The multiplication and accumulation operation is executed in the path, and digital data (multiplication and accumulation data) is obtained as a result of the multiplication and accumulation operation. The digital multiplication circuit and digital addition circuit must be capable of handling multi-bit operations. However, in this case, the digital multiplication circuit and the digital addition circuit are Since it is necessary to increase the scale of each circuit, the circuit area increases and power consumption also increases. There is a risk that

[0009] In addition, by combining the calculation circuit that performs the neural network calculations with the sensor, This may enable electronic devices to recognize various information. By combining a light sensor (e.g., a photodiode) with the arithmetic circuit, Pattern recognition such as face recognition and image recognition can be performed from the image data obtained by the sensor. This can be done.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device capable of performing a product-sum operation. An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. An object of one embodiment of the present invention is to provide a semiconductor device with a reduced circuit area. Another embodiment of the present invention is to provide a semiconductor device in which deterioration in operating capability due to heat is suppressed. This is one of the challenges.

[0011] Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like. An object of one embodiment of the present invention is to provide an electronic device including the semiconductor device. do.

[0012] Note that the problems of one embodiment of the present invention are not limited to the above-listed problems. This does not preclude the existence of other problems. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by understanding the specification or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the above-listed objects and other objects. One aspect of the present invention is to solve the above-listed problems and other problems. You don't need to solve all of them. [Means for solving the problem]

[0013] (1) One aspect of the present invention is a battery comprising a first circuit, a second circuit, a third circuit, a first cell, a second cell, The semiconductor device has a first wiring and a second wiring. The first cell includes a first transistor. the second cell has a second transistor; and the third circuit has a sensor and a third transistor. The first cell is electrically connected to the first circuit via a first wiring. is electrically connected to the second wiring, the second cell is electrically connected to the second wiring, and the sensor is , electrically connected to the first terminal of the third transistor, and the second terminal of the third transistor is The first circuit is electrically connected to the first wiring. The first circuit has a function of passing a first current through the first wiring, and the second circuit has a function of passing a second current through the second wiring. Furthermore, the sensor performs sensing and generates a third current according to the sensing result. The third circuit has a function of outputting a first signal when the third transistor is in an on state. The first cell has a function of passing a third current through the second wiring. The first cell also has a function of passing a potential according to the first current through the first wiring. By holding it at the gate of the transistor, the voltage between the first terminal and the second terminal of the first transistor The second cell has a function of setting the amount of current flowing through the second wiring to the amount of the first current, and the second cell has a function of setting the amount of current flowing through the second wiring to the amount of the first current. By holding a potential corresponding to the current at the gate of the second transistor, the first transistor of the second transistor It has the function of setting the amount of current flowing between the terminal and the second terminal to the amount of current flowing through the second wiring. do.

[0014] (2) In the configuration (1), when the third transistor is in an off state, the second circuit A second current is passed from the second circuit to the second cell via the second wiring, and a second current is passed from the second circuit to the second wiring. A first potential corresponding to the amount of the second current is applied to each of the first cell and the second cell via the wire. The third circuit may have a function of turning on the third transistor. By passing a third current from the first cell to the second wiring, the voltages given to the first cell and the second cell are respectively The first cell may have a function of changing the first potential to the second potential. When the first transistor switches from the off state to the on state, the first terminal of the first transistor and the The amount of the first current flowing between the two terminals is determined by the amount of the fourth current that corresponds to the difference between the first potential and the second potential. The amount of the first current and the amount of the fourth current may be changed by the first current. The range of current that flows when the transistor operates in the subthreshold region, The amount of the current, the amount of the third current, and the sum of the amount of the second current and the amount of the third current are This is the range of current that flows when operating in the subthreshold region.

[0015] (3) In the configuration (1) or (2), the first transistor and the second transistor Each of the channel formation regions may contain a metal oxide.

[0016] (4) One aspect of the present invention is a battery comprising a first circuit, a second circuit, a third circuit, a first cell, a second cell, The semiconductor device has a first wiring and a second wiring. The first cell has a first transistor and , a fourth transistor, and a first capacitance, and the second cell has a second transistor and a fifth transistor. the third circuit has a sensor and a third transistor; The first circuit is electrically connected to the first wiring, and the second circuit is electrically connected to the second wiring. The third circuit is electrically connected to the second wiring. a first terminal of the fourth transistor and a first wiring electrically connected to the gate of the first transistor; the port is electrically connected to the second terminal of the fourth transistor and the first terminal of the first capacitor; The second terminal of the first capacitor is electrically connected to the second wiring. The second transistor is electrically connected to the first terminal of the fifth transistor and the second wiring. The gate of the fifth transistor is electrically connected to the second terminal of the fifth transistor and the first terminal of the second capacitor. The second terminal of the second capacitor is electrically connected to the second wiring. The second terminal of the third transistor is electrically connected to the first wiring. The first circuit is electrically connected to the first cell through the first wiring. The first circuit has a function of passing a first current through the first wiring, and the second circuit has a function of passing a second current through the second wiring. The function of sensing is to output a third current according to the sensing result. and a third circuit configured to supply a third current to the second transistor when the third transistor is in an on state. The first cell has the function of supplying a potential corresponding to the first current to the gate of the first transistor. By keeping the voltage at the first terminal, the amount of current flowing between the first terminal and the second terminal of the first transistor is The second cell has a function of setting the amount of current flowing through the second wiring to the first potential. By holding the voltage at the gate of the second transistor, the voltage between the first terminal and the second terminal of the second transistor The amount of current flowing between the first and second wirings is set to the amount of current flowing through the second wiring.

[0017] (5) In the configuration of (4) above, when the third transistor is in an off state, the second circuit A second current flows from the second circuit to the first terminal of the second transistor via the second wiring; and The second terminal of the first capacitor and the second terminal of the second capacitor are connected from the second circuit via a second wiring. The third circuit may have a function of applying a first potential to the third By turning on the transistor and passing a third current from the third circuit to the second wiring, the first capacitor The first potential applied to the second terminal of the first capacitance and the second terminal of the second capacitance is converted to a second potential. The first cell may have a function of changing the third transistor from an off state to an on state. When the first transistor is switched to the on state, the second current that flows between the first terminal and the second terminal of the first transistor is The amount of the first current is changed to the amount of the fourth current according to the difference between the first potential and the second potential. The amount of the first current and the amount of the fourth current may be determined based on the amount of the first transistor in the subthreshold region. The range of current that flows when operating in the short range, including the amount of the second current and the amount of the third current. , and the sum of the second current amount and the third current amount is This is the range of current that flows when the device is operating at

[0018] (6) In the configuration of (4) or (5), the first transistor and the second transistor The channel forming regions of the first transistor, the fourth transistor, and the fifth transistor are each made of gold. Metal oxides may also be included.

[0019] (7) In addition, in any one of the configurations (1) to (6) above, the first circuit includes a sixth transistor In particular, the seventh transistor may have a first gate and a second gate, and a first terminal of the sixth transistor is electrically connected to the first wiring. The second terminal of the sixth transistor is connected to the first terminal of the seventh transistor. and the second gate of the seventh transistor are preferably electrically connected to the first gate of the seventh transistor. I wish.

[0020] (8) In the configuration (7), the sixth transistor and the seventh transistor are Each channel forming region may contain a metal oxide.

[0021] (9) In addition, in any one of the above configurations (1) to (8), the sensor is a photodiode. It may have a code.

[0022] (10) One aspect of the present invention is a semiconductor device having any one of the semiconductor devices (1) to (9) above and a housing. The electronic device can perform a product-sum operation using the semiconductor device.

[0023] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics. Circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.) It also refers to any device that can function by utilizing the properties of semiconductors. For example, Integrated circuits, chips with integrated circuits, and electronic components that house chips in packages are all semiconductors. In addition, a storage device, a display device, a light-emitting device, a lighting device, an electronic device, etc. , may themselves be semiconductor devices or may contain semiconductor devices.

[0024] In addition, in this specification, when it is stated that X and Y are connected, it means that X and Y are connected. When X and Y are electrically connected, when X and Y are functionally connected, and when X and The case where Y is directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text, but may be applied to connections shown in drawings or text. Connections other than those shown in the figure or text are also considered to be disclosed. The object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) .

[0025] An example of the case where X and Y are electrically connected is The elements that function as One or more devices (diode, display device, light-emitting device, load, etc.) are connected between X and Y. The switch has a function to control on / off. This means that the switch is either in a conducting state (ON state) or a non-conducting state (OFF state), and the current It has the function of controlling whether or not to let water flow.

[0026] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (digital-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.) ), potential level conversion circuits (power supply circuits (booster circuits, step-down circuits, etc.), voltage sources, current sources, switching circuits, amplifier circuits (such as level shifter circuits that can Circuits that can increase the amount of current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc. There are one or more circuits between X and Y (e.g., a power supply circuit, a signal generating circuit, a memory circuit, a control circuit, etc.) It is possible to connect X and Y. For example, if another circuit is inserted between X and Y, However, if the signal output from X is transmitted to Y, then X and Y are functionally connected. It shall be.

[0027] When it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically connected. When X and Y are electrically connected (i.e., when another element or circuit is inserted between X and Y) X and Y are directly connected (i.e., there is no other This includes cases where the device is connected without any element or other circuit in between.

[0028] Also, for example, "X and Y and the source (or first terminal, etc.) and drain ( or the second terminal, etc.) are electrically connected to each other, and X is the source of the transistor (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y in that order. It can be expressed as "electrically connected to the source ( or the first terminal) is electrically connected to X, and the drain (or second terminal, etc.) is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor. , the drain (or second terminal, etc.) of the transistor, Y, are electrically connected in this order. Alternatively, "X is the source (or first terminal) of the transistor." The transistor is electrically connected to Y through the drain (or second terminal, etc.) and the transistor is electrically connected to X. The source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor (e.g., Y is provided in this connection order). By using a similar expression method to specify the order of connections in a circuit configuration, The source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are connected to each other. The technical scope can be determined by distinguishing between the two. Note that these methods of expression are merely examples. , and is not limited to these representation methods. Here, X and Y represent objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0029] Note that the circuit diagram shows independent components as if they are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both the electrode and the electrode. Electrical connection means that one conductive film has the functions of multiple components. This case will also be included in that category.

[0030] In this specification, the term "resistance element" refers to a resistor having a resistance value higher than 0 Ω. Therefore, in this specification and the like, the term "resistance element" can be used as a circuit element, wiring, etc. " refers to wiring with resistance, transistors with current flowing between the source and drain, and diodes. Therefore, the term "resistive element" is used to refer to "resistor," "Load" or "area with a resistance value" and conversely, "resistance" or The terms "load" and "area having a resistive value" can be replaced with terms such as "resistive element." The resistance value is preferably, for example, 1 mΩ or more and 10 Ω or less, and more preferably The resistance can be set to 5 mΩ or more and 5 Ω or less, and more preferably 10 mΩ or more and 1 Ω or less. , for example, 1 Ω or more, 1×10 9 It may be set to Ω or less.

[0031] In this specification, the term "capacitance element" refers to a capacitance element having a capacitance value higher than 0 F. a circuit element having a capacitance value, a wiring area having a capacitance value, a parasitic capacitance, a gate of a transistor Therefore, in this specification, a "capacitive element" refers to a pair of Not only circuit elements including electrodes and dielectrics included between the electrodes, but also wiring and wiring The parasitic capacitance that appears between the gate and the source or drain of the transistor. Also, the term "capacitance element," "parasitic capacitance," and "gate capacitance" are included. Terms such as "amount" can be replaced with terms such as "capacity" and vice versa. The term "capacitance element," "parasitic capacitance," "gate capacitance," etc. In addition, the term "pair of electrodes" in "capacitance" can be used to refer to "pair of conductors" or "pair of conductors." The capacitance value can be expressed as follows: For example, it can be set to 0.05 fF or more and 10 pF or less. It may be 10 μF or less.

[0032] In this specification, a transistor is referred to as a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source and drain are the input and output terminals of the transistor. The two input / output terminals are used to select the transistor conductivity type (n-channel, p-channel) and the Depending on the potential applied to the three terminals of the transistor, one becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain are interchangeable. In addition, in this specification and the like, the connection relationship of the transistors is explained. When this is done, "one of the source and drain" (or the first electrode, or the first terminal), The other side of the drain is called the "second electrode" or the "second terminal." Depending on the structure of the transistor, it may have a back gate in addition to the three terminals mentioned above. In this case, in this specification and the like, one of the gate and the back gate of the transistor is referred to as a first The other of the gate and back gate of the transistor is called the second gate. Furthermore, the terms "gate" and "backgate" can be used interchangeably for the same transistor. In some cases, they can be interchanged. Also, transistors with three or more gates In this case, in this specification, the respective gates are referred to as the first gate, the second gate, the third gate, It is sometimes called a gate.

[0033] In this specification, a node may be a terminal, a wiring, or the like depending on a circuit configuration, a device structure, or the like. It can be called a line, an electrode, a conductive layer, a conductor, an impurity region, etc. Wiring and the like can be called nodes in other words.

[0034] In addition, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, If we consider the earth potential (ground potential), then "voltage" can be rephrased as "potential." Round potential does not necessarily mean 0V. Also, potential is relative. By changing the reference potential, the potential applied to the wiring, the potential applied to the circuit, etc. The potential, the potential output from the circuit, etc. also changes.

[0035] In addition, in this specification, the terms "high level potential" and "low level potential" are used to refer to For example, if two wires are both at a high level potential, When it says "acts as a wire supplying the The high level potentials do not have to be equal to each other. If both are described as "functioning as wiring that supplies low-level potential," The low level potentials provided by the respective switches may not be equal to each other.

[0036] "Current" refers to the phenomenon of the movement of electric charges (electrical conduction). For example, "the electric current of a positively charged body" The statement "electrical conduction is occurring in the opposite direction" means "electrical conduction is occurring in the negatively charged body." Therefore, in this specification and the like, unless otherwise specified, the term "current" is used. In this case, the term "electrical conduction" refers to the phenomenon of charge transfer accompanying the movement of carriers. Carriers include electrons, holes, anions, cations, complex ions, etc., and are the carriers through which current flows. The carriers differ depending on the system (e.g., semiconductor, metal, electrolyte, vacuum, etc.). The "direction of current" in a wire, etc. is the direction in which positive carriers move, and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of the current, and the negative Therefore, in this specification, the positive and negative currents (or the direction of the current) Unless otherwise specified, statements such as "current flows from element A to element B" should be interpreted as "current flows from element B to element This can be rephrased as "current flows through element A" or "current flows through element A." A statement such as "current is input" can be rephrased as "current is output from element A" Let's say.

[0037] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to indicate constituent elements. Therefore, it does not limit the number of components. In addition, the order of the components is not limited. The element referred to as "first" in the above may be used in other embodiments or in the claims. In addition, for example, in the present specification, A component referred to as "first" in one embodiment may be used in other embodiments or in particular It may be omitted within the scope of the claims.

[0038] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship may be used for convenience in explaining the configuration with reference to the drawings. The positional relationship between them changes depending on the direction in which each component is depicted. The terms are not limited to those explained in the detailed instructions, but can be rephrased appropriately depending on the situation. For example, the expression "insulator on top of conductor" means that the orientation of the drawing shown is rotated 180 degrees. By turning it around, it can be rephrased as "an insulator located on the underside of a conductor."

[0039] The terms "above" and "below" mean that the positional relationship of the components is directly above or directly below, and For example, the expression "electrode B on insulating layer A" does not necessarily mean that the electrodes are in contact with each other. In this case, electrode B does not need to be formed directly on insulating layer A. This does not exclude the inclusion of other components between the two.

[0040] In addition, in this specification and the like, the terms "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." In some cases, or depending on the circumstances, it may be possible to change the term to " For example, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Alternatively, for example, the terms "insulating layer" and "insulating film" may be changed to "insulator." It may be possible to change the term to

[0041] In addition, in this specification, terms such as "electrode," "wiring," and "terminal" refer to these components. It does not limit the function of the element. For example, "electrode" is used as part of "wiring." Furthermore, terms such as "electrode" and "wiring" may be used interchangeably, and vice versa. This also includes cases where multiple "electrodes" or "wiring" are integrally formed. "Terminal" is sometimes used as part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" refers to a plurality of "electrodes," "wiring," "terminals," etc. Therefore, for example, "electrode" can be used to refer to "wiring" or " For example, a "terminal" can be a part of a "wiring" or an "electrode." In addition, terms such as "electrode," "wiring," and "terminal" may be used interchangeably. , and may be replaced with terms such as "area."

[0042] In addition, in this specification, terms such as "wiring," "signal line," and "power line" may be used interchangeably. Depending on the situation, they can be interchanged. For example, "wiring" It may be possible to change the term to "signal line". In some cases, it may be possible to change the term "wiring" to a term such as "power line." And vice versa, terms such as "signal line" and "power line" have been changed to "wiring." It may be possible to change terms such as "power line" to terms such as "signal line". In some cases, it is possible to use "signal line" instead of "power line." In addition, the term "potential" applied to the wiring can be changed to "voltage". In some cases or depending on the situation, the term "signal" may be changed to "signal" or similar. And vice versa, terms such as "signal" may be used in conjunction with "potential." It may be possible to change the term to something like this.

[0043] In this specification, impurities in a semiconductor are, for example, substances other than the main components constituting a semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are considered impurities. This leads to, for example, an increase in the density of defect states in the semiconductor, a decrease in carrier mobility, When the semiconductor is an oxide semiconductor, the crystallinity may be reduced. Impurities that change the properties of a conductor include, for example, elements of Group 1, Group 2, and Group 13. Elements of Group 14, Group 15, and transition metals other than the main component are included. element (including water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, when the semiconductor is a silicon layer, there are impurities that change the properties of the semiconductor. Examples of the elements include Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements, and the like, excluding hydrogen. Oxygen and the like.

[0044] In this specification, a switch is a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It is a device that has the function of controlling whether or not current flows by entering a state where it is in a switched state. A switch is a device that has the function of selecting and switching the path through which current flows. , electrical switches, mechanical switches, etc. can be used. The device is not limited to a specific one as long as it can control the current.

[0045] An example of an electrical switch is a transistor (e.g., a bipolar transistor, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die MIS (Metal Insulator Semiconductor) die diode-connected transistors, etc.), or logic circuits that combine these When using a transistor as a switch, the "conduction state" of the transistor This means that the source and drain electrodes of the transistor are considered to be electrically short-circuited. The "non-conducting state" of a transistor refers to the state in which the source electrode and drain electrode of the transistor are in a non-conducting state. This refers to a state in which the input electrode can be considered to be electrically disconnected. When operating as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0046] An example of a mechanical switch is a MEMS (microelectromechanical system). There are switches that use stem technology. These switches are electrically operated switches that can be mechanically operated. It has poles, and the movement of these electrodes controls conduction and non-conduction.

[0047] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" or "approximately parallel" means that two straight lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. "Almost perpendicular" or "roughly perpendicular" means that two straight lines are arranged at an angle of 60° or more and 120° or less. This refers to a state in which something is happening. [Effects of the Invention]

[0048] According to one embodiment of the present invention, a semiconductor device capable of performing a product-sum operation can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with a reduced circuit area can be provided. According to one embodiment of the present invention, a semiconductor device in which deterioration of operation capability due to heat is suppressed is provided. This can be done.

[0049] According to one embodiment of the present invention, a novel semiconductor device or the like can be provided. According to one embodiment of the present invention, an electronic device including the semiconductor device can be provided.

[0050] The effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to a person skilled in the art from the description or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may have the above-listed effects. In some cases, the [Brief explanation of the drawings]

[0051] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 2] 2A to 2C are block diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 3] 3A to 3D are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 4] 4A to 4C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 5] FIG. 5 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 6] FIG. 6 is a timing chart showing an example of the operation of the semiconductor device. [Figure 7] FIG. 7 is a block diagram showing a configuration example of a semiconductor device. [Figure 8] 8A to 8C are block diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 9] FIG. 9 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 10] FIG. 10A is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device, and FIG. 10B is a block diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 11] 11A and 11B are block diagrams showing examples of the configuration of a circuit included in a semiconductor device, and FIGS. 11C and 11D are circuit diagrams showing examples of the configuration of a circuit included in a semiconductor device. [Figure 12] FIG. 12 is a block diagram showing a configuration example of a semiconductor device. [Figure 13] 13A and 13B are block diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 14] FIG. 14 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 15] FIG. 15 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 16] FIG. 16 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 17] FIG. 17 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 18] FIG. 18 is a block diagram showing a configuration example of a semiconductor device. [Figure 19] 19A and 19B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 20] 20A and 20B are block diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 21] 21A and 21B are timing charts showing an example of the operation of the semiconductor device. [Figure 22] 22A and 22B are diagrams illustrating a hierarchical neural network. [Figure 23] FIG. 23 is a block diagram showing a configuration example of a semiconductor device. [Figure 24] FIG. 24 is a block diagram showing a configuration example of a semiconductor device. [Figure 25] FIG. 25 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 26] FIG. 26 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 27] 27A to 27C are cross-sectional views showing examples of the structure of a transistor. [Figure 28] 28A and 28B are cross-sectional views showing examples of the structure of a transistor. [Figure 29] FIG. 29 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 30] 30A and 30B are cross-sectional views showing examples of the structure of a transistor. [Figure 31] FIG. 31 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 32] FIG. 32A is a top view showing an example of the configuration of a capacitive element, and FIGS. 32B and 32C are cross-sectional perspective views showing the example of the configuration of a capacitive element. [Figure 33] 33A is a top view showing an example of the configuration of a capacitive element, FIG. 33B is a cross-sectional view showing an example of the configuration of a capacitor, and FIG. 33C is a cross-sectional perspective view showing an example of the configuration of a capacitive element. [Figure 34] FIG. 34 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 35] FIG. 35A is a diagram illustrating the classification of IGZO crystal structures, FIG. 35B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 35C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 36] FIG. 36A is a perspective view showing an example of a semiconductor wafer, FIG. 36B is a perspective view showing an example of a chip, and FIGS. 36C and 36D are perspective views showing an example of an electronic component. [Figure 37] 37A to 37F are perspective views of a package and a module that house an imaging device. [Figure 38] FIG. 38 is a perspective view showing an example of an electronic device. [Figure 39] 39A to 39C are perspective views showing examples of electronic devices. [Figure 40] 40A to 40C are schematic diagrams showing examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0052] In artificial neural networks (hereafter referred to as neural networks), The strength of synapses can be changed by providing existing information to the neural network. In this way, existing information can be fed into the neural network to create connections. The process of determining the strength is sometimes called "learning."

[0053] In addition, no action is taken against the neural network that has undergone "learning" (the connection weights have been determined). By providing some information, new information can be output based on the connection strength. In this way, neural networks make decisions based on the given information and connection strengths. The process of generating new information from the input is sometimes called "inference" or "cognition."

[0054] Neural network models include, for example, Hopfield and hierarchical types. In particular, neural networks with multi-layer structures are called "deep neural networks." They call machine learning using deep neural networks "DNNs" and call machine learning using deep neural networks " It is sometimes called "deep learning."

[0055] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductors (also called oxide semiconductors or simply OS), For example, when a metal oxide is used in the active layer of a transistor, the metal oxide In other words, metal oxides have amplifying, rectifying, and and forming a channel forming region of a transistor having at least one of a switching function and a If possible, the metal oxide is referred to as a metal oxide semiconductor. In addition, when written as an OS transistor, In other words, the transistor may be a transistor having a metal oxide or an oxide semiconductor. .

[0056] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides (metal ox). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0057] In addition, in this specification and the like, the configurations shown in each embodiment may be interchangeable with the configurations shown in other embodiments. The above-described embodiments can be combined appropriately to form one aspect of the present invention. When multiple configuration examples are shown, the configuration examples can be combined with each other as appropriate.

[0058] It should be noted that the contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the embodiment and one or more other embodiments The content described (or a part of the content) is applied to, combined with, or at least one of the contents. or replacement, etc.

[0059] The contents described in the embodiments refer to the following in each embodiment (or example): The content described using various figures or the text in the specification be.

[0060] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. In the embodiment, another figure (or a part thereof) and one or more other embodiments may be used. At least one of the drawings (or a part thereof) described in the embodiment is combined with By adding more, more figures can be constructed.

[0061] The embodiments described in this specification will be described with reference to the drawings. The present invention may be embodied in many different forms without departing from the spirit and scope thereof. It will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiment. In the configuration of the invention of the embodiment, the same parts or parts having similar functions are designated by the same reference numerals. The same elements are used in different drawings, and repeated explanations may be omitted. In some cases, in order to ensure clarity of the drawings, some components may be omitted. be.

[0062] In this specification and the like, when the same reference numeral is used for a plurality of elements, it is not necessary to distinguish them. When necessary, a distinguishing code such as "_1", "[n]", or "[m,n]" is added to the code. It may be stated in writing.

[0063] Also, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely conceptual examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or timing errors This can include variations in signal, voltage, or current.

[0064] (Embodiment 1) In this embodiment, an example of a circuit capable of product-sum operation, which is a semiconductor device of one embodiment of the present invention, will be described. This article explains:

[0065] <Configuration example 1 of an arithmetic circuit> FIG. 1 shows a multiplication and accumulation operation of a first data item that is positive or "0" and a second data item that is positive or "0". The calculation circuit MAC1 shown in FIG. A multiplication and accumulation operation is performed on the first data corresponding to the potential thus obtained and the second data inputted, and the multiplication and accumulation operation is performed on the first data corresponding to the potential thus obtained. This is a circuit that calculates an activation function using the result of the sum operation. The data may be, for example, analog data or multi-valued data (discrete data). It is possible.

[0066] The arithmetic circuit MAC1 includes a circuit WCS, a circuit XCS, a circuit WSD, a circuit SWS1, The circuit SWS2, the cell array CA, and the conversion circuits ITRZ[1] to ITRZ[n ] (where n is an integer equal to or greater than 1).

[0067] The cell array CA includes cells IM[1,1] to IM[m,n] (where m is 1 or more). ) and cells IMref[1] to IMref[m]. Each of cells IM[1,1] to IM[m,n] corresponds to the amount of current according to the first data. The cells IMref[1] to IMref[m] have the function of holding the potential. The potential corresponding to the second data required to perform the multiplication and accumulation operation is wired to XCL[1 ] to wiring XCL[m].

[0068] The cell array CA in FIG. 1 has cells arranged in a matrix of m rows and n+1 columns. However, the cell array CA has a structure in which cells are arranged in a matrix with one or more rows and two or more columns. It is fine as long as it is complete.

[0069] Each of the cells IM[1,1] to IM[m,n] is, for example, a transistor F1, a transistor F2, and a capacitor C5, and cells IMref[1] to IM For example, each of ref[m] is a transistor F1m, a transistor F2m, and , and has a capacity C5m.

[0070] In particular, the transistors included in each of the cells IM[1,1] to IM[m,n] The size of the transistor F1 (e.g., channel length, channel width, transistor configuration, etc.) and each of the cells IM[1,1] to IM[m,n] is preferably equal to The sizes of the transistors F2 included in the cell I are preferably equal to each other. The transistor F1m included in each of the cells Mref[1] to IMref[m] The sizes of the cells IMref[1] to IMref[m ] are preferably equal in size to each other. Moreover, it is preferable that the sizes of the transistors F1 and F1m are equal to each other. , the sizes of the transistors F2 and F2m are preferably equal to each other.

[0071] By making the transistors the same size, the voltage of each transistor Therefore, the electric characteristics of the cells IM[1,1] to IM[m The size of the transistor F1 included in each of the cells IM[1, The size of the transistor F2 included in each of the cells IM[m, n] to IM[m, n] is equalized. By this, each of the cells IM[1,1] to IM[m,n] is Under the same conditions, the same operation can be performed. For example, the potentials of the source, drain, gate, etc. of the transistor F1, the transistor The potentials of the source, drain, gate, etc. of F2, cells IM[1,1] to IM[m,n Similarly, the voltage input to each of the cells IMref[1] and IMref[2] is The size of the transistor F1m included in each of the cells IMref[m] is set to be equal. The transistors included in each of the cells IMref[1] to IMref[m] are By making the size of cell F2m equal, for example, cell IMref[1] to cell IMref[m] will perform almost the same operation under the same conditions. The same conditions here are, for example, the source, drain, and gate of the transistor F1m. the potential of the source, drain, gate, etc. of transistor F2m, the potential of cell IM This refers to the voltages input to each of cells ref[1] through IMref[m].

[0072] Unless otherwise specified, the transistors F1 and F1m are in the on state. The above cases include the case where the circuit finally operates in the linear region. The gate, source, and drain voltages of each transistor operate in the linear region. However, this includes cases where the voltage is appropriately biased in the range For example, the transistors F1 and F1m are in an on state. In the case of the linear mode, it may operate in the saturation region. It is acceptable to mix these cases.

[0073] In addition, unless otherwise specified, the transistors F2 and F2m are sub-threads. When operating in the threshold region (i.e., when transistor F2 or transistor F2m In this case, if the gate-source voltage is lower than the threshold voltage, it is more preferable that the drain This includes the case where the current increases exponentially with the gate-source voltage. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors is properly biased to a voltage within the subthreshold operating range. Therefore, the transistor F2 and the transistor F2m are This includes cases where an off-state current flows between the in-state and the out-state.

[0074] In addition, the transistor F1 and / or the transistor F1m may be, for example, an OS transistor. In addition, the transistor F1 and / or the transistor F1 The channel forming region of m is an oxide containing at least one of indium, gallium, and zinc. It is more preferable to use indium or element M (element M) instead of the oxide. Examples of M include aluminum, gallium, yttrium, copper, vanadium, and beryllium. Smoke, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum Titanium, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium and oxides containing at least one of zinc. The transistor F1 and / or the transistor F1m may be used in particular in the embodiment. More preferably, the transistor has the structure described in 5.

[0075] An OS transistor is used as the transistor F1 and / or the transistor F1m. This reduces the leakage current of the transistor F1 and / or the transistor F1m. This allows the power consumption of the arithmetic circuit to be reduced. When the transistor F1 and / or the transistor F1m are in a non-conducting state, The leakage current from the storage node to the write word line can be made very small. The number of potential refresh operations can be reduced. By doing so, the power consumption of the arithmetic circuit can be reduced. By making the leakage current to the line WCL or the wiring XCL very small, the cell is retained. Since the potential of the node can be maintained for a long time, the accuracy of the calculation of the calculation circuit can be improved.

[0076] Also, the transistor F2 and / or the transistor F2m are also OS transistors. By using a capacitor, it is possible to operate in a wide current range in the subthreshold region. Therefore, the current consumption can be reduced. By using an OS transistor for transistor F2m, Since it can be fabricated at the same time as the resistor F1m, the fabrication process of the arithmetic circuit can be shortened. In addition, the transistor F2 and / or the transistor F2m may be In addition to transistors, there are transistors that contain silicon in the channel formation region (hereinafter referred to as Si The silicon can be, for example, amorphous silicon. silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon Silicon, single crystal silicon, etc. can be used.

[0077] Incidentally, when semiconductor devices are highly integrated into chips, the chips contain a large number of circuits. Heat may be generated by driving the device. This heat may cause the temperature of the transistor to rise. This changes the characteristics of the transistor, causing changes in field-effect mobility, a decrease in operating frequency, etc. OS transistors have higher heat resistance than Si transistors, The field-effect mobility is less likely to change due to temperature changes, and the operating frequency is also less likely to decrease. Furthermore, in OS transistors, the drain current is constant even when the temperature rises. Therefore, it is easy to maintain the exponential increase characteristic with respect to the inter-transistor voltage. By using a thermal imager, it is easy to perform calculations and processing even in high temperature environments. In order to configure a semiconductor device that is resistant to heat generated by driving, an OS transistor is used as a transistor. It is preferable to apply a resistor.

[0078] In each of the cells IM[1,1] to IM[m,n], the transistor F1 The first terminal is electrically connected to the gate of the transistor F2. The first terminal of the capacitor C5 is electrically connected to the wiring VE. It is electrically connected to the gate of F2.

[0079] In addition, in each of the cells IMref[1] to IMref[m], The first terminal of the transistor F1m is electrically connected to the gate of the transistor F2m. The first terminal of the capacitor C5m is electrically connected to the wiring VE. The terminal is electrically connected to the gate of transistor F2m.

[0080] In FIG. 1, a transistor F1, a transistor F2, a transistor F1m, and a transistor F2m are connected to the transistor F1. The back gate of the transistor F2m is shown in the figure, and the connection configuration of the back gate is as follows: Although not shown, the electrical connection destination of the back gate is determined at the design stage. For example, in a transistor having a back gate, To increase the current, the gate and back gate may be electrically connected. For example, the gate and back gate of the transistor F1 may be electrically connected. The gate and back gate of the transistor F1m may be electrically connected. In a transistor having a back gate, the threshold voltage of the transistor is changed. In order to increase the resistance of the transistor or to reduce the off-state current of the transistor, Wiring is provided to electrically connect the back gate to an external circuit or the like, A potential may be applied to the back gate of the transistor by using a transistor such as a gate electrode.

[0081] The transistors F1 and F2 shown in FIG. However, the semiconductor device of one embodiment of the present invention is not limited thereto. The illustrated transistors F1 and F2 do not have back gates. In other words, a transistor with a single gate structure may be used. Some transistors have a back gate, and some transistors have a back gate. The configuration may not have a port.

[0082] The transistors F1 and F2 shown in FIG. 1 are n-channel transistors. Although a transistor is used in the present invention, the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistors F1 and F2 may be partly or entirely p-channel transistors. It may be replaced with sta.

[0083] The above-mentioned examples of the changes in the structure and polarity of the transistors are as follows: transistor F1 and transistor F2. It is not limited to the transistor F2. For example, the transistor F1m, the transistor F2m , transistors F3[1] to F3[n], and transistor F4[1 ] to transistor F4[n], as well as transistors described elsewhere in the specification. The structure, polarity, etc. of the transistors shown in other drawings may also be changed in the same manner. That's fine.

[0084] The wiring VE is connected to the transistors F of the cells IM[1,1] to IM[m,n]. 2 is a wiring for passing a current between the first terminal and the second terminal, and as shown in FIG. The first transistor F2m of each of the cells IMref[1] to IMref[m] It functions as a wiring for passing current between the terminal and the second terminal. For example, the wiring VE is It functions as a wiring that supplies a constant voltage. The constant voltage may be, for example, a low-level potential, a connection It can be earth potential or the like.

[0085] In the cell IM[1,1], the second terminal of the transistor F1 is connected to the wiring WCL[1]. The gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of the transistor F2 is electrically connected to the wiring WCL[1], and the capacitor C5 The second terminal of the cell IM is electrically connected to the wiring XCL[1]. In [1,1], the first terminal of the transistor F1, the gate of the transistor F2, and the capacitor The connection point between the first terminal of the quantity C5 and the node NN[1,1].

[0086] In the cell IM[m,1], the second terminal of the transistor F1 is connected to the wiring WCL[1]. The gate of the transistor F1 is electrically connected to the wiring WSL[m]. The second terminal of the transistor F2 is electrically connected to the wiring WCL[1], and the capacitor C5 The second terminal of the cell IM is electrically connected to the wiring XCL[m]. In [m, 1], the first terminal of the transistor F1, the gate of the transistor F2, and the capacitor The connection point between the first terminal of the quantity C5 and the node NN[m,1].

[0087] In the cell IM[1,n], the second terminal of the transistor F1 is connected to the wiring WCL[n]. The gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of the transistor F2 is electrically connected to the wiring WCL[n] and the capacitor C5 The second terminal of the cell IM is electrically connected to the wiring XCL[1]. In [1,n], the first terminal of the transistor F1, the gate of the transistor F2, and the capacitor The connection point between the first terminal of the quantity C5 and the node NN[1,n].

[0088] In the cell IM[m,n], the second terminal of the transistor F1 is connected to the wiring WCL[n]. The gate of the transistor F1 is electrically connected to the wiring WSL[m]. The second terminal of the transistor F2 is electrically connected to the wiring WCL[n] and the capacitor C5 The second terminal of the cell IM is electrically connected to the wiring XCL[m]. In [m, n], the first terminal of the transistor F1, the gate of the transistor F2, and the capacitor The connection point between the first terminal of the quantity C5 and the node NN[m, n].

[0089] In the cell IMref[1], the second terminal of the transistor F1m is connected to the line XCL[1] The gate of the transistor F1m is electrically connected to the wiring WSL[1]. The second terminal of the transistor F2m is electrically connected to the wiring XCL[1]. The second terminal of the capacitor C5m is electrically connected to the wiring XCL[1]. In cell IMref[1], the first terminal of transistor F1m and the first terminal of transistor F2 The connection point between the gate of m and the first terminal of the capacitance C5m is called node NNref[1]. do.

[0090] In the cell IMref[m], the second terminal of the transistor F1m is connected to the wiring XCL[m] The gate of the transistor F1m is electrically connected to the wiring WSL[m]. The second terminal of the transistor F2m is electrically connected to the wiring XCL[m]. The second terminal of the capacitor C5m is electrically connected to the wiring XCL[m]. In the cell IMref[m], the first terminal of the transistor F1m and the first terminal of the transistor F2 The connection point between the gate of m and the first terminal of the capacitance C5m is called node NNref[m]. do.

[0091] Note that nodes NN[1,1] to NN[m,n] and node NNref[1] The node NNref[m] functions as a holding node for each cell.

[0092] In the cells IM[1,1] to IM[m,n], for example, the transistor F1 is turned on. When the transistor F2 is in the on state, the transistor F2 is in a diode-connected configuration. The constant voltage applied is the ground potential (GND), and the transistor F1 is in the on state and the wiring W When a current of I flows from CL to the second terminal of transistor F2, The potential of the gate (node ​​NN) is determined according to the amount of current I. Since transistor F1 is on, the potential of the two terminals is ideally The gate of transistor F1 (node ​​NN) is equal to the gate of transistor F2. As a result, the potential of the gate (node ​​NN) of the transistor F2 is maintained. , the transistor F2 is connected to the ground potential of the first terminal of the transistor F2 and the A current of a magnitude I corresponding to the potential of the gate (node ​​NN) flows between the source and drain of transistor F2. In this specification, such an operation is referred to as "transistor of cell IM." The amount of current flowing between the source and drain of the capacitor F2 is set to I (programmed). It is called "do".

[0093] The circuit SWS1 includes, for example, transistors F3[1] to F3[n]. The first terminal of the transistor F3[1] is electrically connected to the wiring WCL[1]. The second terminal of the transistor F3[1] is electrically connected to the circuit WCS, and the second terminal of the transistor F The gate of transistor F3[n] is electrically connected to wiring SWL1. The first terminal of the transistor F3[n] is electrically connected to the wiring WCL[n], and the second terminal of the transistor F3[n] is electrically connected to the wiring WCL[n]. The transistor F3[n] is electrically connected to the circuit WCS, and the gate of the transistor F3[n] is connected to the wiring SWL. 1 is electrically connected to

[0094] The transistors F3[1] to F3[n] are, for example, The transistors applicable to the transistor F1 and / or the transistor F2 can be used. In particular, the transistors F3[1] to F3[n] are each Preferably, an OS transistor is used.

[0095] The circuit SWS1 is connected to the circuit WCS and each of the wirings WCL[1] to WCL[n]. , functions as a circuit that puts the gap between the two terminals into a conductive state or a non-conductive state.

[0096] The circuit SWS2 includes, for example, transistors F4[1] to F4[n]. A first terminal of the transistor F4[1] is electrically connected to the wiring WCL[1], The second terminal of the transistor F4[1] is electrically connected to the input terminal of the conversion circuit ITRZ[1]. The gate of the transistor F4[1] is electrically connected to the wiring SWL2. The first terminal of the transistor F4[n] is electrically connected to the wiring WCL[n]. The second terminal of the F4[n] is electrically connected to the input terminal of the conversion circuit ITRZ[n]. The gate of the transistor F4[n] is electrically connected to the wiring SWL2.

[0097] Each of the transistors F4[1] to F4[n] may be, for example, The transistors applicable to the transistor F1 and / or the transistor F2 can be used. In particular, the transistors F4[1] to F4[n] are each Preferably, an OS transistor is used.

[0098] The circuit SWS2 is connected between the wiring WCL[1] and the conversion circuit ITRZ[1], and between the wiring WCL It has the function of making the connection between the ITRZ[n] and the conversion circuit ITRZ[n] conductive or non-conductive. Although not shown in FIG. 1, the same applies to any one of the second to n-1 columns. Similarly, the wiring WCL and the conversion circuit ITRZ are connected to each other in a conductive or non-conductive state. do.

[0099] The circuit WCS supplies data to be stored in each cell of the cell array CA. It has the function of

[0100] The circuit XCS is electrically connected to the wirings XCL[1] to XCL[m]. The path XCS is a path of the cells IMref[1] to IMref[m] of the cell array CA. For each, the amount of current according to the reference data or the amount of current according to the second data, which will be described later, is It has the function of flowing water.

[0101] The circuit WSD is electrically connected to the wirings WSL[1] to WSL[m]. When writing the first data to the cells IM[1,1] to IM[m,n], the path WSD By supplying predetermined signals to the wirings WSL[1] to WSL[m], the first data The wiring WSL has the function of selecting the row of the cell array CA to which the data is written. The wirings [1] to WSL[m] function as write word lines.

[0102] In addition, the circuit WSD is electrically connected to the wiring SWL1 and the wiring SWL2, for example. The circuit WSD supplies a predetermined signal to the wiring SWL1. A function to make the connection between CS and the cell array CA conductive or non-conductive, and a ... By supplying a certain signal, the conversion circuits ITRZ[1] to ITRZ[n] and the cell array CA.

[0103] Each of the conversion circuits ITRZ[1] to ITRZ[n] is, for example, For example, the output terminal of the conversion circuit ITRZ[1] is connected to the wiring O L[1], and the output terminal of the conversion circuit ITRZ[n] is connected to the wiring OL[n]. are electrically connected.

[0104] Each of the conversion circuits ITRZ[1] to ITRZ[n] receives an input signal at its input terminal. It converts the current into a voltage depending on the amount of current received and outputs the voltage from the output terminal. The voltage may be, for example, an analog voltage or a digital voltage. Each of the conversion circuits ITRZ[1] to ITRZ[n] can be expressed by the function In this case, for example, the converted voltage is used to calculate the voltage. The function is calculated by the path, and the result of the calculation is output to wiring OL[1] through wiring OL[n]. You may do so.

[0105] In particular, when performing calculations on a hierarchical neural network, the above-mentioned functions are, for example, For example, sigmoid function, tanh function, softmax function, ReLU function, threshold function Numbers, etc. can be used.

[0106] <<Circuit WCS, Circuit XCS>> Here, specific examples of the circuit WCS and the circuit XCS will be described.

[0107] First, the circuit WCS will be described. Figure 2A shows a block diagram of an example of the circuit WCS. 2A is a diagram showing the electrical connection between the circuit WCS and the peripheral circuits. The circuit SWS1, the transistor F3, the wiring SWL1, and the wiring WCL are also shown.

[0108] The circuit WCS has, for example, as many circuits WCSa as the number of wirings WCL. S has n circuits WCSa.

[0109] The circuit SWS1 also has transistors F3 in the same number as the number of wirings WCL. Therefore, the circuit SWS1 has n transistors F3.

[0110] Therefore, the transistor F3 shown in FIG. 2A is included in the arithmetic circuit MAC1 in FIG. It can be any one of transistors F3[1] to F3[n]. Similarly, the wiring WCL is the wiring WCL[1] included in the arithmetic circuit MAC1 in FIG. to WCL[n].

[0111] Therefore, each of the wirings WCL[1] to WCL[n] has a separate transistor. The separate circuits WCSa are electrically connected via the first power supply F3.

[0112] The circuit WCSa shown in FIG. 2A includes, as an example, a switch SWW. The first terminal of the switch SWW is electrically connected to the second terminal of the transistor F3. The terminal is electrically connected to the wiring VINIL1. This serves as a wiring that provides an initialization potential to the D), low level potential, high level potential, etc. It is turned on only when an initialization potential is applied to the wiring WCL, and is turned off at other times. This will be the state.

[0113] The switch SWW can be an electrical switch such as an analog switch or a transistor. As the switch SWW, for example, a transistor When a transistor is applied, the transistor is the same as the transistor F1 and the transistor F2. In addition to electrical switches, mechanical switches can also be used. A switch may be applied.

[0114] Moreover, the circuit WCSa in FIG. 2A includes, as an example, a plurality of current sources CS. , the circuit WCSa is K bits (2 K value) (K is an integer of 1 or more) as the amount of current In this case, the circuit WCSa has a function of outputting K -It has one current source CS. The circuit WCSa has a current source CS that outputs the information corresponding to the value of the first bit as a current. and two current sources CS that output information corresponding to the value of the second bit as a current. The current source CS outputs the information corresponding to the value of the Kth bit as a current. K-1 have .

[0115] In FIG. 2A, each current source CS has a terminal T1 and a terminal T2. The terminal T1 of each current source CS supplies a current to the second terminal of the transistor F3 of the circuit SWS1. In addition, terminal T2 of one current source CS is electrically connected to wiring DW[1]. The terminals T2 of the two current sources CS are electrically connected to the wiring DW[2]. , 2 K-1 Each of the terminals T2 of the current sources CS is electrically connected to the wiring DW[K]. There are.

[0116] The multiple current sources CS in the circuit WCSa each supply the same constant current I Wut Terminal T1 In reality, in the manufacturing stage of the arithmetic circuit MAC1, Errors occur due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the constant voltages output from the terminals T1 of the multiple current sources CS are Flow I Wut The error should preferably be within 10%, more preferably within 5%, and less than 1%. In this embodiment, the multiple circuits included in the circuit WCSa are preferably The constant current I is output from terminal T1 of the current source CS. Wut This explanation is based on the assumption that there is no error. do.

[0117] The wirings DW[1] to DW[K] receive a constant current from a current source CS electrically connected thereto. I Wut Specifically, for example, When a high-level potential is applied to the wiring DW[1], The current source CS is a constant current I Wut to the second terminal of transistor F3, Also, when a low-level potential is applied to the wiring DW[1], The connected current source CS is I Wut Also, for example, if the wiring DW[2] When a high-level potential is applied, the two potentials electrically connected to the wiring DW[2] The source CS is 2I in total. Wut A constant current of is passed through the second terminal of the transistor F3, and When a low-level potential is applied to DW[2], the The current sources CS used are a total of 2I WutFor example, the wiring DW[K ] is given a high-level potential, K -1 The current sources CS are K-1 I Wut A constant current of When a low-level potential is applied to the wiring DW[K], a current is applied to the wiring DW[K]. The electrically connected current source CS is K-1 I Wut It does not output a constant current.

[0118] The current flowing from one current source CS electrically connected to the wiring DW[1] is 1 bit. The currents flowing from the two current sources CS electrically connected to the wiring DW[2] correspond to the values ​​of the first and second values. The quantity corresponds to the value of the second bit, and is the K current sources electrically connected to the wiring DW[K]. The amount of current flowing through CS corresponds to the value of the Kth bit. Here, the circuit WC when K is 2 is For example, when the value of the first bit is "1" and the value of the second bit is "0", the wiring D A high level potential is applied to the wiring W[1], and a low level potential is applied to the wiring DW[2]. At this time, a constant current flows from the circuit WCSa to the second terminal of the transistor F3 in the circuit SWS1. TE I Wut For example, if the value of the first bit is "0" and the value of the second bit is "1", When this happens, a low level potential is applied to the wiring DW[1] and a high level potential is applied to the wiring DW[2]. At this time, the second terminal of the transistor F3 of the circuit SWS1 is connected to the circuit WCSa. A constant current of 2I is applied to the Wut For example, if the value of the first bit is "1" and the value of the second bit is "2", When the value of the first bit is "1", a high level potential is applied to the wiring DW[1] and wiring DW[2]. At this time, a constant voltage is applied from the circuit WCSa to the second terminal of the transistor F3 of the circuit SWS1. Flow 3I Wut For example, if the value of the first bit is "0" and the value of the second bit is "0", When the value is "0", a low level potential is applied to the wiring DW[1] and the wiring DW[2]. At this time, a constant current flows from the circuit WCSa to the second terminal of the transistor F3 in the circuit SWS1. do not have.

[0119] Although FIG. 2A illustrates the circuit WCSa when K is an integer equal to or greater than 3, If the value is 1, the circuit WCSa in FIG. 2A is electrically connected to the wiring DW[2] to the wiring DW[K]. In addition, if K is 2, then The circuit WCSa in FIG. 2A is electrically connected to the wiring DW[3] to the wiring DW[K]. A configuration without the current source CS may be used.

[0120] Next, a specific example of the configuration of the current source CS will be described.

[0121] The current source CS1 shown in FIG. 3A can be applied to the current source CS included in the circuit WCSa of FIG. 2A. The current source CS1 has a transistor Tr1 and a transistor Tr2. do.

[0122] The first terminal of the transistor Tr1 is electrically connected to the wiring VDDL, and the second terminal of the transistor T The second terminal of r1 is connected to the gate of transistor Tr1 and the back gate of transistor Tr1. and the first terminal of the transistor Tr2. The second terminal of the transistor Tr2 is electrically connected to the terminal T1, and the gate of the transistor Tr2 is electrically connected to the terminal T2. The terminal T2 is electrically connected to the wiring DW.

[0123] The wiring DW is any one of the wirings DW[1] to DW[n] in FIG. 2A.

[0124] The line VDDL functions as a line that applies a constant voltage. The constant voltage may be, for example, It can be a high level potential.

[0125] When the constant voltage applied by the line VDDL is set to a high level potential, the first terminal of the transistor Tr1 A high-level potential is input to the second terminal of the transistor Tr1. At this time, the first terminal of the transistor Tr1 is at a potential lower than the high-level potential. The second terminal of the transistor Tr1 functions as a source. The gate of the transistor Tr1 and the second terminal of the transistor Tr1 are electrically connected. Therefore, the gate-source voltage of the transistor Tr1 is 0V. If the threshold voltage of transistor Tr1 is within the appropriate range, the first terminal of transistor Tr1 A current (drain current) in the current range of the subthreshold region flows between the second terminals. When the transistor Tr1 is an OS transistor, the amount of the current is, for example, 1 .0×10 -8 A or less, and 1.0 × 10 -12 A or below More preferably, 1.0 × 10 -15 It is more preferable that it is A or less. For example, the current is in a range that increases exponentially with the gate-source voltage. That is, the transistor Tr1 operates in the subthreshold region. It functions as a current source for supplying a current in the current range when Wut , or I, as described below. Xut is equivalent to

[0126] The transistor Tr2 functions as a switching element. When the potential at the first terminal of r2 is higher than the potential at the second terminal of transistor Tr2, The first terminal of transistor Tr2 acts as the drain, and the second terminal of transistor Tr2 acts as the source. The back gate of the transistor Tr2 and the first gate of the transistor Tr2 function as a Since the two terminals are electrically connected, the back gate-source voltage is 0V. Therefore, if the threshold voltage of the transistor Tr2 is within an appropriate range, the transistor When a high-level potential is input to the gate of transistor Tr2, transistor Tr2 is turned on. When a low-level potential is input to the gate of transistor Tr2, Specifically, when transistor Tr2 is in the ON state, When the current in the subthreshold region is When the transistor Tr2 is in the off state, the current flows from the terminal T1 to the terminal T2. No current flows from the second terminal of transistor Tr1 to terminal T1.

[0127] The circuit that can be applied to the current source CS included in the circuit WCSa in FIG. 2A is the current For example, the current source CS1 is not limited to the back gate of the transistor Tr2. and the second terminal of the transistor Tr2 are electrically connected. The back gate of the transistor Tr2 may be electrically connected to another wiring. An example of such a configuration is shown in FIG. 3B. The current source CS2 shown in FIG. The back gate is electrically connected to the wiring VTHL. When the wiring VTHL is electrically connected to an external circuit, etc., the A predetermined potential is applied to the wiring VTHL, and the back gate of the transistor Tr2 is supplied with the predetermined potential. This allows the threshold voltage of the transistor Tr2 to be varied. In particular, by increasing the threshold voltage of the transistor Tr2, The off-current of the transistor Tr2 can be reduced.

[0128] For example, the current source CS1 is connected between the back gate of the transistor Tr1 and the back gate of the transistor T The second terminal of transistor Tr2 is electrically connected to the second terminal of transistor Tr1. A voltage may be maintained between the back gate and the second terminal by a capacitor. Such a configuration example is shown in FIG. 3C. The current source CS3 shown in FIG. 3C includes a transistor Tr1 and a transistor Tr2. In addition to the transistor Tr2, the circuit also includes a transistor Tr3 and a capacitor C6. 3 is a capacitance C6 between the second terminal of the transistor Tr1 and the back gate of the transistor Tr1. The back gate of transistor Tr1 is electrically connected to the back gate of transistor Tr2 via the It differs from the current source CS1 in that it is electrically connected to the first terminal of the current source Tr3. The power supply CS3 is connected to the second terminal of the transistor Tr3 electrically connected to the line VTL. The gate of the transistor Tr3 is electrically connected to the wiring VWL. S3 applies a high level potential to the wiring VWL to turn on the transistor Tr3. By this, the wiring VTL and the back gate of the transistor Tr1 are brought into a conductive state. At this time, a predetermined potential is applied from the wiring VTL to the back gate of the transistor Tr1. Then, a low-level potential is applied to the wiring VWL, and the transistor Tr By turning off the transistor Tr3, the capacitor C6 connects the second terminal of the transistor Tr1 to the The voltage between the back gate of the transistor Tr1 and the wiring V By determining the voltage applied to the back gate of transistor Tr1, TL The threshold voltage of transistor Tr1 can be varied, and transistor Tr3 and capacitor C6 This makes it possible to fix the threshold voltage of the transistor Tr1.

[0129] For example, the following circuit can be applied to the current source CS included in the circuit WCSa of FIG. 2A: 3D. The current source CS4 is the current source CS3 in FIG. 3C. The back gate of the transistor Tr2 is connected to the wiring instead of the second terminal of the transistor Tr2. In other words, the current source CS4 is electrically connected to the current As with the source CS2, the potential applied by the line VTHL determines the threshold voltage of the transistor Tr2. The voltage can be varied.

[0130] In the current source CS4, a large current flows between the first and second terminals of the transistor Tr1. When the current is supplied from the terminal T1 to the outside of the current source CS4, a transistor Tr In this case, the current source CS4 must be connected to the line VTHL at a high level. By applying a bell potential, the threshold voltage of the transistor Tr2 is lowered, and the transistor Tr2 By increasing the on-current of the transistor Tr1, A large current can be caused to flow from the terminal T1 to the outside of the current source CS4.

[0131] As the current source CS included in the circuit WCSa of FIG. 2A, the current sources shown in FIGS. 3A to 3D By applying current sources CS1 to CS4, the circuit WCSa generates the first data of K bits. The amount of current can be determined by, for example, the amount of the transistor. F1 flows between the first and second terminals within the range in which it operates in the subthreshold region. It can be the amount of current.

[0132] Moreover, the circuit WCSa shown in FIG. 2B may be applied as the circuit WCSa in FIG. 2A. The circuit WCSa in FIG. 2B is configured such that the wirings DW[1] to DW[K] are connected to the respective wirings DW[1] to DW[K]. The current source CS is connected to the transistor Tr1[1]. The channel width of transistor Tr1 is w[1], the channel width of transistor Tr2 is w[2], When the channel width of Tr1[K] is w[K], the ratio of each channel width is w[1 ]:w[2]:w[K]=1:2:2 K-1 It operates in the subthreshold region. The current flowing between the source and drain of a transistor is proportional to the channel width, so The circuit WCSa shown in FIG. 2B, like the circuit WCSa shown in FIG. 2A, performs the following operations on the first data of K bits: It is possible to output a current according to the voltage.

[0133] Note that transistor Tr1 (transistor Tr1[1] to transistor Tr2[K] ), transistor Tr2 (transistor Tr2[1] to transistor Tr2[K ]), and the transistor Tr3 may be, for example, a transistor F1, and / or a transistor The transistors applicable to the transistor F2 can be used. In particular, the transistor Tr1 (including transistors Tr1[1] to Tr2[K]), transistor Tr 2 (including transistors Tr2[1] to Tr2[K]), and It is preferable to use an OS transistor as the transistor Tr3.

[0134] Next, a specific example of the circuit XCS will be described.

[0135] FIG. 2C is a block diagram showing an example of the circuit XCS. To show the electrical connection of S with the peripheral circuits, wiring XCL is also shown.

[0136] The circuit XCS has, for example, as many circuits XCSa as there are wirings XCL. S has m circuits XCSa.

[0137] Therefore, the wiring XCL shown in FIG. 2C is the wiring X included in the arithmetic circuit MAC1 in FIG. Therefore, the wiring X Each of the wirings CL[1] to XCL[m] is electrically connected to a separate circuit XCSa. It is being done.

[0138] The circuit XCSa shown in FIG. 2C includes, as an example, a switch SWX. The first terminal of the switch SWX is electrically connected to the wire XCL, and the second terminal of the switch SWX is electrically connected to the wire VI The wiring VINIL2 is electrically connected to the wiring XCL. The potential for initialization is the ground potential (GND), low-level potential (LVP), and The potential for initialization given by the wiring VINIL2 can be set to a low level, a high level potential, etc. The potential may be equal to the potential provided by the wiring VINIL1. It is turned on only when an initialization potential is applied to the wiring XCL, and is turned off at other times. This will be the state.

[0139] The switch SWX can be a switch that can be applied to the switch SWW, for example. can.

[0140] The circuit configuration of the circuit XCSa in FIG. 2C is almost the same as that of the circuit WCSa in FIG. 3A. Specifically, the circuit XCSa has a function of outputting the reference data as a current amount. No, L bit (2 L A function to output the second data of the current value (L is an integer of 1 or more) as a current amount. In this case, the circuit XCSa has two L -One current source CS. The circuit XCSa has one current source CS that outputs the information corresponding to the value of the first bit as a current. It has two current sources CS that output information corresponding to the value of the second bit as a current, and The current source CS outputs the information corresponding to the second value as a current. L-1 There are individual ones.

[0141] Incidentally, the reference data output by the circuit XCSa as a current is, for example, 1 bit The first bit can be "1" and the second bit and subsequent bits can be "0".

[0142] In FIG. 2C, the terminal T2 of one current source CS is electrically connected to the wiring DX[1], Each of the terminals T2 of the two current sources CS is electrically connected to the wire DX[2]. L-1 Each of the terminals T2 of the current sources CS is electrically connected to the wiring DX[L].

[0143] The multiple current sources CS in the circuit XCSa are each set to the same constant current I Xut The end The wiring DX[1] to the wiring DX[L] have the function of outputting from the slave T1. Current source CS connected to I Xut The wiring is used to transmit the control signal for outputting That is, the circuit XCSa functions by receiving the signals from the wiring DX[1] to the wiring DX[L]. It has the function of passing a current amount corresponding to the L-bit information through the wiring XCL.

[0144] Specifically, consider the circuit XCSa when L is set to 2. For example, the first bit When the value of the first bit is "1" and the value of the second bit is "0", a high-level potential is applied to the wire DX[1]. At this time, a low level potential is applied to the wiring DX[2]. XCL is applied as a constant current I Xut For example, if the value of the first bit is "0" and the value of the second bit is "0", When the value of the 1st bit is "1", a low level potential is applied to the wire DX[1] and a low level potential is applied to the wire DX[2]. At this time, a constant current and 2I Xut For example, if the value of the first bit is "1" and the value of the second bit is " When the voltage is 1", a high-level potential is applied to the wiring DX[1] and the wiring DX[2]. Then, a constant current of 3I is supplied from the circuit XCSa to the wiring XCL. Xut Also, for example, When the value of the first bit is "0" and the value of the second bit is "0", the wiring DX[1] and wiring DX [2] is given a low level potential. At this time, a constant voltage is applied from the circuit XCSa to the wiring XCL. At this time, in this specification and the like, no current flows from the circuit XCSa to the wiring XCL. In other words, a current of 0 flows. Also, the current output by the circuit XCSa is 0, I Xut , 2I Xut , 3I Xut are the second data output by the circuit XCSa. In particular, the amount of current I output by the circuit XCSa Xut is the output of the circuit XCSa. This can be used as reference data.

[0145] The current of the transistor included in each current source CS of the circuit XCSa is If an error occurs due to variations in electrical characteristics, the The constant current I Xut The error should be within 10%, preferably within 5%. It is more preferable that the difference is within 1%. The constant current I is output from terminal T1 of multiple current sources CS included in Sa. Xut The error is It will be explained as if it does not exist.

[0146] The current source CS of the circuit XCSa is the same as the current source CS of the circuit WCSa, as shown in Figure 3. Any of the current sources CS1 to CS4 in FIGS. 3A to 3D can be applied. In this case, the wiring DW shown in FIGS. 3A to 3D can be replaced with the wiring DX. Therefore, the circuit XCSa uses the subthreshold data as the reference data or the second data of L bits. A current within the current range of the gate region can be passed through the wiring XCL.

[0147] The circuit XCSa in FIG. 2C has the same circuit configuration as the circuit WCSa shown in FIG. 2B. In this case, the circuit WCSa shown in FIG. 2B is replaced with the circuit XCSa. , replace wiring DW[1] with wiring DX[1], and replace wiring DW[2] with wiring DX[2]. Replace the wiring DW[K] with the wiring DX[L], and replace the switch SWW with the switch SWX. This can be achieved by replacing the wiring VINIL1 with the wiring VINIL2.

[0148] <<Conversion circuit ITRZ[1] to conversion circuit ITRZ[n]>> Here, the conversion circuits ITRZ[1] to ITRZ[2] included in the arithmetic circuit MAC1 in FIG. A specific example of a circuit that can be applied to TRZ[n] will be explained.

[0149] The conversion circuit ITRZ1 shown in FIG. 4A is the same as the conversion circuits ITRZ[1] to IT 4A shows an example of a circuit that can be applied to the conversion circuit ITRZ1. To show the electrical connection with the circuit of the side, we use the circuit SWS2, the wiring WCL, the wiring SWL2, and the trace The wiring WCL is included in the arithmetic circuit MAC1 in FIG. The transistor F4 is any one of the wirings WCL[1] to WCL[n]. The transistors F4[1] to F4[2] included in the arithmetic circuit MAC1 in FIG. n].

[0150] The conversion circuit ITRZ1 in FIG. 4A is electrically connected to the wiring WCL via the transistor F4. The conversion circuit ITRZ1 is electrically connected to the wiring OL. The circuit ITRZ1 is a current flowing from the conversion circuit ITRZ1 to the wiring WCL, or from the wiring WCL to the The amount of current flowing from the converter ITRZ1 to the analog voltage is converted into an analog voltage and the analog voltage is output to the wiring OL. In other words, the conversion circuit ITRZ1 has a function of outputting a current-to-voltage conversion circuit. do.

[0151] The conversion circuit ITRZ1 of FIG. 4A includes, for example, a resistor R5 and an operational amplifier OP1. do.

[0152] The inverting input terminal of the operational amplifier OP1 is connected to the first terminal of the resistor R5 and the second terminal of the transistor F4. The non-inverting input terminal of the operational amplifier OP1 is electrically connected to the wiring VRL The output terminal of the operational amplifier OP1 is electrically connected to the second terminal of the resistor R5 and the It is electrically connected to the line OL.

[0153] The wiring VRL functions as a wiring that applies a constant voltage. It can be earth potential (GND), low level potential, etc.

[0154] By configuring the conversion circuit ITRZ1 as shown in FIG. 4A, the wiring WCL The amount of current flowing into the converter circuit ITRZ1 via the converter F4 or from the converter circuit ITRZ1 The amount of current flowing through the wiring WCL is converted into an analog voltage via the transistor F4. The signal can be output to line OL.

[0155] In particular, by using the constant voltage provided by the wiring VRL as the ground potential (GND), The inverting input terminal of amplifier OP1 is a virtual ground, so the analog voltage output to wiring OL is It can be a voltage referenced to earth potential (GND).

[0156] Furthermore, the conversion circuit ITRZ1 in FIG. 4A is configured to output an analog voltage. The circuit configuration that can be applied to the conversion circuits ITRZ[1] to ITRZ[n] in FIG. For example, the conversion circuit ITRZ1 may be an analog-to-digital converter, as shown in FIG. Specifically, the conversion circuit ITRZ in FIG. 2 is the input terminal of the analog-to-digital conversion circuit ADC, and the output terminal of the operational amplifier OP1. The second terminal of resistor R5 is electrically connected to the output terminal of the analog-to-digital conversion circuit ADC. is electrically connected to the wiring OL. Therefore, the conversion circuit ITRZ2 of FIG. 4B can output a digital signal to the wiring OL. .

[0157] In addition, in the conversion circuit ITRZ2, the digital signal output to the wiring OL is converted into 1 bit ( In this case, the conversion circuit ITRZ2 is replaced with the conversion circuit ITRZ3 shown in FIG. 4C. The conversion circuit ITRZ3 of FIG. 4C may be implemented by adding a comparator to the conversion circuit ITRZ1 of FIG. Specifically, the conversion circuit ITRZ3 is configured with a comparator CMP1. The first input terminal of CMP1 is connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5. The second input terminal of the comparator CMP1 is electrically connected to the wiring VRL2. The output terminal of the comparator CMP1 is electrically connected to the wiring OL. The wiring VRL2 supplies a potential to be compared with the potential of the first terminal of the comparator CMP1. By using this configuration, the conversion circuit IT RZ3 is the current flowing between the source and drain of transistor F4 by the current-voltage conversion circuit. Depending on the magnitude of the voltage converted from the flow rate and the voltage given by wiring VRL2, It is possible to output a low-level potential or a high-level potential (binary digital signal).

[0158] In addition, the conversion circuits ITRZ[1] to IT RZ[n] is not limited to the conversion circuits ITRZ1 to ITRZ3. When the calculation circuit MAC1 is used as the calculation of the layered neural network, the conversion circuit It is preferable that the conversion circuits ITRZ1 to ITRZ3 have a function-based arithmetic circuit. In addition, the function system calculation circuits include sigmoid function, tanh function, softmax function, It can be an arithmetic circuit such as a ReLU function or a threshold function.

[0159] Note that one embodiment of the present invention is not limited to the circuit configuration of the arithmetic circuit MAC1 described in this embodiment. The arithmetic circuit MAC1 can change its circuit configuration depending on the situation. For example, , the arithmetic circuit MAC1 does not include the circuit SWS1, as shown in FIG. 5. In the case of the arithmetic circuit MAC1, the circuit SWS1 The current flowing through the wirings WCL[1] to WCL[n] can be stopped from In the case of the circuit MAC1A, the circuit WCS is connected to the wiring WCL[1] to the wiring WCL[2]. The current flowing through WCL[n] can be stopped. The circuit WCSa in Figure 2A is used as the circuit WCSa included in the circuit WCS, and the current source CS When the current source CS1 of FIG. 3A is applied as A low level potential is input to each of them, and the switch SWW is turned off. By operating the circuit WCS in this way, the wiring WCL[1] to the wiring WCL[n ] can stop the current flowing from the circuit WCS to the wiring WCL[1] By stopping the current flowing through the wiring WCL[n], instead of the arithmetic circuit MAC1, The calculation can be performed using the calculation circuit MAC1A.

[0160] <Operation example 1 of the arithmetic circuit> Next, an example of the operation of the arithmetic circuit MAC1 will be described.

[0161] FIG. 6 shows a timing chart of an example of the operation of the arithmetic circuit MAC1. The port is connected to the wiring SWL1 between the time T11 and the time T23 and in the vicinity thereof. , wiring SWL2, wiring WSL[i] (i is an integer between 1 and m-1), wiring WSL [i+1], wiring XCL[i], wiring XCL[i+1], node NN[i,j] (j is 1 (an integer greater than or equal to n-1), node NN[i+1,j], node NNref[i], The voltage fluctuation of the node NNref[i+1] is shown. The cell IM[i,j] includes a transistor F2. The cell IM[i,j] includes a transistor F2. The transistor F2 has a first terminal and a second terminal. Amount of current flowing I F2 [i,j] and the transistor F contained in the cell IMref[i] The current I flows between the first and second terminals of 2 m F2m [i] and cell IM[i+1,j] The amount of current I flowing between the first and second terminals of the transistor F2 included in F2 [i+1 , j] and the first terminal-th terminal of transistor F2m included in cell IMref[i+1] Amount of current flowing between the two terminals I F2m The respective fluctuations of [i+1] and .

[0162] The circuit WCS of FIG. 2A is applied to the circuit WCS of the arithmetic circuit MAC1. The circuit XCS of the circuit MAC1 is the circuit XCS of FIG. 2C.

[0163] In this operation example, the potential of the wiring VE is set to the ground potential GND. Before this, the initial setting is Node NN[i,j], Node NN[i+1,j], The potentials of the node NNref[i] and the node NNref[i+1] are set to the ground potential G Specifically, for example, the initialization of the wiring VINIL1 in FIG. The potential of the switch SWW, the transistor F3, and the cell IM[i, j], and each transistor F1 included in the cell IM[i+1,j] is turned on. By doing so, the potentials of the nodes NN[i,j] and NN[i+1,j] are set to the ground potential. GND. Also, for example, the potential for initialization of the wiring VINIL2 in FIG. 2C can be is set to the ground potential GND, and the switch SWX, cell IMref[i,j], cell IMre By turning on each transistor F1m included in f[i+1,j], Therefore, the potential of the node NNref[i,j] and the node NNref[i+1,j] is set to the ground potential. It can be connected to GND.

[0164] <<From time T11 to time T12>> Between time T11 and time T12, a high-level potential ( High) is applied to the wiring SWL2, and a low-level potential (Low in Figure 6) is applied to the wiring SWL3. This causes transistors F3[1] to F4[2] to A high level potential is applied to the gate of each of the transistors F3[n], to F3[n] are turned on, and transistors F4[1] to A low level potential is applied to the gate of each of the transistors F4[n]. Each of the transistors F4[1] to F4[n] is turned off.

[0165] In addition, between time T11 and time T12, the wiring WSL[i], wiring WSL[i+ 1] is applied with a low level potential. This causes the cell I The gate of the transistor F1 included in the cells M[i,1] to IM[i,n], and the cell A low-level potential is applied to the gate of the transistor F1m included in IMref[i]. As a result, the transistors F1 and F1m are turned off. The cells IM[i+1,1] to IM[i+1,n] in the i+1th row of the cell array CA The gate of the transistor F1 contained in the cell IMref[i+1] is A low level potential is applied to the gate of each transistor F1m. and transistor F1m are turned off.

[0166] In addition, between time T11 and time T12, the wiring XCL[i] and the wiring XCL[ i+1] is applied with a ground potential GND. When the line XCL is the wiring XCL[i] and the wiring XCL[i+1], The potential for initialization of the line VINIL2 is set to the ground potential GND, and the switch SWX is turned on. By doing so, the potential of the wiring XCL[i] and the wiring XCL[i+1] is set to the ground potential GND. It is possible.

[0167] Also, between time T11 and time T12, the transistor F3 The wirings WCL[1] to WCL[n] are electrically connected to the respective circuits of FIG. In the circuit WCSa, the first data is input to the wiring DW[1] to the wiring DW[K]. In this case, in the circuit WCSa of FIG. 2A, the wirings DW[1] to DW[K] A low level potential is input to each of them. 2 are electrically connected to the wirings XCL[1] to XCL[m]. In each of the circuits XCSa in FIG. 2C, the wirings DX[1] to DX[L] are connected to the second data lines. In this case, in the circuit XCSa of Figure 2C, the wiring DX[1] It is assumed that a low level potential is input to each of the wirings DX[L].

[0168] Also, between time T11 and time T12, the wiring WCL[j] and the wiring XCL[i] , no current flows through the wire XCL[i+1]. F2 [i,j], I F2m [ i], I F2 [i+1,j], I F2m [i+1] becomes 0.

[0169] <<From time T12 to time T13>> Between time T12 and time T13, a high-level potential is applied to the wiring WSL[i]. As a result, the cells IM[i,1] to IM[i, The gate of transistor F1 contained in cell IMref[i] is A high level potential is applied to the gate of the transistor F1m, and F1 and transistor F1m are turned on. Between them, the wirings WSL[1] to WSL[m] except for the wiring WSL[i] have low level A cell potential is applied to the cells IM[1,1] to I other than the i-th row of the cell array CA. The transistor F1 included in M[m,n] and the cell IMref[1] other than the i-th row The transistor F1m included in the cell IMref[m] is in the off state. Let's say.

[0170] Furthermore, the wiring XCL[1] to the wiring XCL[m] have been connected to the ground voltage continuously since before time T12. A GND voltage is applied.

[0171] <<From time T13 to time T14>> Between time T13 and time T14, the transistor F3[j A current of a current amount I0[i,j] flows through the cell array CA as the first data through the transistors . Specifically, when the wiring WCL shown in FIG. 2A is the wiring WCL[j], the wiring DW By inputting a signal corresponding to the first data to each of the wirings DW[1] to DW[K], Then, a current I0[i,j] flows from the circuit WCSa to the second terminal of the transistor F3[j]. That is, the value of the K-bit signal input as the first data is expressed as α[i,j](α[i,j ] 0 to 2 K -1 or less), then I0[i,j]=α[i,j]×I Wut This becomes:

[0172] Note that when α[i,j] is 0, I0[i,j]=0, so strictly speaking, the circuit WC No current flows from Sa to the cell array CA via the transistor F3[j]. In books, it may be written as "A current of I0[i,j] = 0 flows."

[0173] Between time T13 and time T14, the cell IM[i , j] and the wiring WCL[j] are in a conductive state. and the cells IM[1,j] to IM[m , j] and the first terminal of the transistor F1 included in the wiring WCL[j] are in a non-conductive state. Since the current is in the state of 0, the current I0[i,j] flows from the wiring WCL[j] to the cell IM[i,j]. A current of flows.

[0174] By the way, when the transistor F1 included in the cell IM[i,j] is turned on, Therefore, the transistor F2 included in the cell IM[i,j] is configured as a diode. Therefore, when current flows from the wiring WCL[j] to the cell IM[i,j], The potentials of the gate of transistor F2 and the second terminal of transistor F2 are approximately equal. The potential is determined by the amount of current flowing from the wiring WCL[j] to the cell IM[i,j] and the In this example, the potential of the first terminal of the resistor F2 is determined by the potential of the first terminal of the resistor F3 (GND in this example). , a current of I0[i,j] flows from the wiring WCL[j] to the cell IM[i,j]. Therefore, the potential of the gate of transistor F2 (node ​​NN[i,j]) is V g [i,j ]. In other words, in transistor F2, the gate-source voltage is V g [i,j]-GND, and the current flowing between the first and second terminals of transistor F2 is The current amount I0[i,j] is set accordingly.

[0175] Here, the threshold voltage of transistor F2 is V th When [i,j], the transistor When the transistor F2 operates in the subthreshold region, the current I0[i,j] is calculated as follows: It can be described as:

[0176]

number

[0177] In addition, I a is V g [i,j] is V th The drain current when [i,j] is J is a correction coefficient determined by temperature, device structure, etc.

[0178] In addition, between time T13 and time T14, the wiring XCL[i ], and current amount I ref0 Specifically, the current shown in FIG. When the wiring XCL is the wiring XCL[i], the wiring DX[1] is at a high level potential, A low-level potential is input to each of the lines DX[2] to DX[K], and the circuit XCSa Current I flows from the wire XCL[i] ref0 In other words, I ref0 =I Xut becomes .

[0179] Between time T13 and time T14, the transaction included in cell IMref[i] Since there is conduction between the first terminal of the transistor F1m and the wiring XCL[i], A current I flows from the line XCL[i] to the cell IMref[i]. ref0 A current of flows.

[0180] Similarly to cell IM[i,j], transistor F1 contained in cell IMref[i] When m is turned on, the transistor F included in the cell IMref[i] 2m is configured as a diode connection. Therefore, the wiring XCL[i] to the cell IMref[ When a current flows through the transistor F2m, the gate of the transistor F2m and the second terminal of the transistor F2m The potentials of the cells IM and IM are almost equal. The amount of current flowing through ref[i] and the potential of the first terminal of transistor F2m (here, GND) In this example, the line XCL[i] is connected to the cell IMref[i]. Current amount I ref0 The current flows through the gate of transistor F2 (node ​​NN ref[i]) is V gm [i], and the current of the wiring XCL[i] at this time is Rank V gm [i]. That is, in the transistor F2m, the gate-source voltage V gm [i]-GND, and the current flowing between the first and second terminals of transistor F2m As a current, the amount of current I ref0 is set.

[0181] Here, the threshold voltage of transistor F2m is V thm When [i] is set, the transistor The amount of current I when the transistor F2m operates in the subthreshold region ref0 is expressed as follows: The correction coefficient J is the sum of the values ​​of the transistor F2 included in the cell IM[i,j]. For example, the device structure and size (channel length, channel width) of a transistor ) are the same. Also, due to manufacturing variations, the correction coefficient J of each transistor varies. However, it is assumed that the variation is suppressed to the extent that the discussion below can be carried out with sufficient accuracy for practical purposes. do.

[0182]

number

[0183] Here, the weighting coefficient w[i,j], which is the first data, is defined as follows:

[0184]

number

[0185] Therefore, equation (1.1) can be rewritten as follows:

[0186]

number

[0187] The current I output by the current source CS of the circuit WCSa in Figure 2A Wut and the circuit X in Figure 2C The current I output by the current source CS of CSa Xut If and are equal, then w[i,j]=α[i, j]. That is, I Wut And, I Xut If and are equal, α[i,j] is the first data Since it corresponds to the value of the data, Wut And, I Xut Preferably, and are equal to each other.

[0188] <<From time T14 to time T15>> Between time T14 and time T15, a low-level potential is applied to the wiring WSL[i]. As a result, the cells IM[i,1] to IM[i, The gate of transistor F1 contained in cell IMref[i] is A low level potential is applied to the gate of the transistor F1m, and F1 and transistor F1m are turned off.

[0189] When the transistor F1 included in the cell IM[i,j] is turned off, The capacitor C5 is connected to the potential of the gate of the transistor F2 (node ​​NN[i,j]) and the potential of the wiring XC The difference between the potential of L[i] and V g [i,j]-V gm [i] is held. Also, cell When the transistor F1 included in IMref[i] is turned off, the capacitance C5m is connected to the potential of the gate (node ​​NNref[i]) of transistor F2m and the potential of the wiring X The difference between the potential of CL[i] and 0 is maintained. The voltage maintained by the capacitance C5m is In the operation from time T13 to time T14, the transistors F1m and F2m When the voltage is not 0 (for example, Δ) depending on the transistor characteristics, etc. In this case, the potential of the node NNref[i] is calculated by adding Δ to the potential of the wiring XCL[i]. This can be thought of as a potential obtained by

[0190] <<From time T15 to time T16>> Between time T15 and time T16, GND is applied to the line XCL[i]. Specifically, for example, when the wiring XCL shown in FIG. 2C is the wiring XCL[i], Then, the potential for initialization of the wiring VINIL2 is set to the ground potential GND, and the switch SWX is turned on. By setting the line XCL[i] to this state, the potential of the line XCL[i] can be set to the ground potential GND.

[0191] Therefore, the cells IM[i,1] to IM[i,n] in the i-th row are The capacitance C5 in the node NN[i,1] to the node NN[i,n] is coupled by the capacitance C5. The potential changes, and the capacitance C5m included in cell IMref[i] causes The potential of the node NNref[i] changes.

[0192] The amount of change in the potential of the nodes NN[i,1] to NN[i,n] is The amount of change in the potential of each cell IM[i,1] to The potential is multiplied by the capacitive coupling coefficient determined by the configuration of the filter IM[i,n]. The number is calculated based on the capacitance of capacitor C5, the gate capacitance of transistor F2, parasitic capacitance, etc. In each of the cells IM[i,1] to IM[i,n], the capacitance C5 When the coupling coefficient is p, the potential of the node NN[i,j] of the cell IM[i,j] is From the potential at the time between T14 and T15, p(V gm [i]-GND) drop do.

[0193] Similarly, when the potential of the wire XCL[i] changes, the voltage contained in the cell IMref[i] The potential of node NNref[i] also changes due to the capacitive coupling caused by the capacitor C5m included in the When the capacitance coupling coefficient of the capacitance C5m is p, the same as the capacitance C5, the cell IMref The potential of the node NNref[i] of [i] is From the potential at gm [i]-GND) decreases.

[0194] This reduces the potential of node NN[i,j] of cell IM[i,j], The transistor F2 is turned off, and similarly, the node NNref[i] of the cell IMref[i] i] drops, the transistor F2m also turns off. Between time T5 and time T16, I F2 [i,j], I F2m Each of [i] is 0 In addition, between time T14 and time T15 in the timing chart of FIG. The potential of the node NN[i,j] is lower than the ground potential GND, but the potential of the transistor F If the node 2 is turned off, the potential may be equal to or higher than the ground potential GND. The potential of the node NNref[i] is the ground potential GND (i.e., p=1). If the transistor F2m is turned off, the It may be a potential lower than the potential or the ground potential GND.

[0195] <<From time T16 to time T17>> Between time T16 and time T17, a high-level potential is applied to the wiring WSL[i+1]. As a result, the cells IM[i+1,1] to IM[i+1,1] in the i+1th row of the cell array CA are The gate of transistor F1 in cell IM[i+1,n] and the gate of cell IMref[i +1], and a high level potential is applied to the gate of the transistor F1m. The transistors F1 and F1m are turned on. Between time T17 and time T18, the wirings WSL[1] to WSL[i+1] are A low level potential is applied to the line WSL[m], and all the cells except the i+1th row of the cell array CA are connected. The transistors F1 and i+1 included in the cells IM[1,1] to IM[m,n] Transistors included in cells IMref[1] to IMref[m] other than the row F1m is assumed to be in the off state.

[0196] Furthermore, the wiring XCL[1] to the wiring XCL[m] have been connected to the ground voltage continuously since before time T16. A GND voltage is applied.

[0197] <<From time T17 to time T18>> Between time T17 and time T18, the transistor F3[j ], a current of the amount of current I0[i+1,j] flows to the cell array CA as the first data. Specifically, when the wiring WCL shown in FIG. 2A is wiring WCL[j+1], A signal corresponding to the first data is input to each of the wirings DW[1] to DW[K]. As a result, a current I0[i+1, j] flows. That is, the value of the K-bit signal input as the first data is α[i+1, j] (α[i+1,j] is 0 to 2 K -1 or less), then I0[i,j ]=α[i+1,j]×I Wut This becomes:

[0198] Furthermore, when α[i+1,j] is 0, I0[i+1,j]=0, so strictly speaking, No current flows from the circuit WCSa to the cell array CA via the transistor F3[j]. In this specification and the like, the same as in the case of I0[i,j]=0, "I0[i+1,j]=0" is used. It may be written as "current flows."

[0199] At this time, the transaction included in the cell IM[i+1,j] in the i+1th row of the cell array CA The first terminal of the transistor F1 is in a conductive state with the wiring WCL[j], and the cell Included in cells IM[1,j] to IM[m,j] other than the i+1th row of Ray CA Since there is no conduction between the first terminal of the transistor F1 and the line WCL[j], A current of I0[i+1,j] flows from the wiring WCL[j] to the cell IM[i+1,j]. do.

[0200] By the way, the transistor F1 included in the cell IM[i+1,j] is turned on. As a result, the transistor F2 included in the cell IM[i+1,j] is in diode connection. Therefore, current flows from the wiring WCL[j] to the cell IM[i+1,j]. When the transistor F2 is turned on, the voltages at the gate of the transistor F2 and the second terminal of the transistor F2 are The potential flows from the wiring WCL[j] to the cell IM[i+1,j]. The amount of current flowing through the transistor F2 and the potential of the first terminal of the transistor F2 (GND in this case) are also determined. In this operation example, the amount of current I0[i+1 , j], the gate of transistor F2 (node ​​NN[i+1, j]) is V g [i+1,j]. That is, in transistor F2, When the gate-source voltage is V g [i+1,j]-GND, and transistor F2 The current amount I0[i+1,j] is set as the current flowing between the first terminal and the second terminal.

[0201] Here, the threshold voltage of transistor F2 is V th When [i+1,j] is used, When the transistor F2 operates in the subthreshold region, the current I0[i+1,j] is as follows: The correction coefficient is calculated by the following formula: The transistor F2 is set to J, which is the same as the transistor F2m included in the cell IMref[i]. do.

[0202]

number

[0203] In addition, between time T17 and time T18, the wiring XCL[i +1] as reference data for the current I ref0 Specifically, from time T13 onwards, Similarly to the period from time T10 to time T14, the wiring XCL shown in FIG. 2C is the wiring XCL[i+1]. In this case, the wiring DX[1] is at a high level potential, and the wirings DX[2] to DX[K] are at a low level potential. A low-level potential is input to each, and a current I flows from the circuit XCSa to the wire XCL[i+1]. ref0 =I Xut is playing.

[0204] Between time T17 and time T18, the value contained in cell IMref[i+1] Since the first terminal of the transistor F1m and the wiring XCL[i+1] are in a conductive state, The current amount I from the wiring XCL[i+1] to the cell IMref[i+1] ref0 A current of .

[0205] The transistor contained in cell IMref[i+1] is the same as that contained in cell IM[i+1,j]. When the F1m signal is turned on, the signal contained in the cell IMref[i+1,j] The transistor F2m connected to the wiring XCL[i+1] is a diode-connected transistor. When current flows from the cell IMref[i+1] to the gate of the transistor F2m, The potentials of the second terminal of the transistor F2m and the second terminal of the transistor F2m are approximately equal. The amount of current flowing from XCL[i+1] to cell IMref[i+1] and the amount of current flowing from transistor F2m In this operation example, the potential of the wiring XCL [i+1] to cell IMref[i+1] with current I ref0 The current flowing The gate of transistor F2 (node ​​NNref[i+1]) is V gm [i+1] At this time, the potential of the wiring XCL[i+1] is also V gm Let [i+1]. That is, in transistor F2m, the gate-source voltage is V gm [i+1]-GN D, and the current flowing between the first and second terminals of the transistor F2m is I r ef0 is set.

[0206] Here, the threshold voltage of transistor F2m is V thm When [i+1,j] is used, The current I when transistor F2m operates in the subthreshold region ref0 is expressed as The correction coefficient J is the sum of the total number of traces included in the cell IM[i+1,j]. It is the same as transistor F2.

[0207]

number

[0208] Here, the weighting coefficient w[i+1,j], which is the first data, is defined as follows:

[0209]

number

[0210] Therefore, equation (1.5) can be rewritten as follows:

[0211]

number

[0212] The current I output by the current source CS of the circuit WCSa in Figure 2AWut and the circuit X in Figure 2C The current I output by the current source CS of CSa Xut If and are equal, then w[i+1,j]=α[ i+1,j]. That is, I Wut And, I Xut If and are equal, then α[i+1,j ] corresponds to the value of the first data, so I Wut And, I Xut and are equal to each other. preferable.

[0213] <<From time T18 to time T19>> Between time T18 and time T19, a low-level potential is applied to the wiring WSL[i+1]. As a result, the cells IM[i+1,1] to IM[i+1,1] in the i+1th row of the cell array CA are The gate of transistor F1 in cell IM[i+1,n] and the gate of cell IMref[i +1], and a low level potential is applied to the gate of the transistor F1m. The transistors F1 and F1m are turned off.

[0214] When the transistor F1 included in the cell IM[i+1,j] is turned off, The capacitor C5 receives the potential of the gate of the transistor F2 (node ​​NN[i+1,j]) and The difference between the potential of the wiring XCL[i+1] and V g [i+1,j]-V gm [i+1] is saved Also, the transistor F1 included in the cell IMref[i+1] is in the off state. As a result, the capacitance C5m is connected to the gate of the transistor F2m (node ​​NNref The difference between the potential of the line XCL[i+1] and the potential of the line XCL[i+1] is kept at 0. The voltage held by the capacitor C5m is the voltage held by the transistor during the operation from time T18 to time T19. Depending on the transistor characteristics of transistors F1m and F2m, a voltage that is not 0 (here In this case, the power of node NNref[i+1] is The potential can be considered as a potential obtained by adding Δ to the potential of the wiring XCL[i+1].

[0215] <<From time T19 to time T20>> Between time T19 and time T20, the line XCL[i+1] is connected to the ground potential GND. Specifically, for example, the wiring XCL shown in FIG. 2C is applied to the wiring XCL[i+1] In this case, the potential for initialization of the wiring VINIL2 is set to the ground potential GND, and the switch By turning on the switch SWX, the potential of the wiring XCL[i+1] is set to the ground potential GND. It is possible.

[0216] Therefore, each of the cells IM[i+1,1] to IM[i+1,n] in the i+1th row The capacitance C5 included in the node NN[i,1] is used for capacitive coupling to the node NN[i,1]. The potential of [i+1,n] changes, and the capacitance C5m contained in cell IMref[i+1] The potential of the node NNref[i+1] changes due to capacitive coupling caused by the

[0217] The amount of change in the potential of the nodes NN[i+1,1] to NN[i+1,n] is The change in the potential of L[i+1] is calculated by dividing the potential of each cell IM[i +1,1] to cell IM[i+1,n] multiplied by the capacitive coupling coefficient determined by the configuration of cell IM[i+1,n] The capacitance coupling coefficient is determined by the capacitance of the capacitor C5, the gate capacitance of the transistor F2, and the parasitic capacitance Each of the cells IM[i+1,1] to IM[i+1,n] is calculated as follows: In this case, the capacitive coupling coefficient of the capacitor C5 is calculated by dividing the capacitance of the cells IM[i,1] to IM[i,n ], the capacitance coupling coefficient due to the capacitance C5 in each of the cells IM[i The potential of node NN[i+1,j] of node NN[i+1,j] is between time T18 and time T19. From the potential at time point, p(V gm [i+1]-GND) decreases.

[0218] Similarly, when the potential of the wiring XCL[i+1] changes, the cell IMref[i+ 1], the capacitance C5m of node NNref[i+1] When the capacitance coupling coefficient of the capacitance C5m is p, the same as the capacitance C5, The potential of the node NNref[i+1] of the filter IMref[i+1] is From the potential at the time points up to 19, p(V gm [i+1]-GND) decreases.

[0219] This causes the potential of node NN[i+1,j] of cell IM[i+1,j] to drop. Therefore, transistor F2 is turned off, and similarly, the node of cell IMref[i+1] Since the potential of NNref[i+1] drops, the transistor F2m also turns off. Therefore, between time T19 and time T20, I F2 [i+1,j], I F2m Each of [i+1] is 0. Note that from time T19 in the timing chart of FIG. Until time T20, the potential of node NN[i+1,j] is lower than the ground potential GND. However, if transistor F2 is turned off, a voltage higher than the ground potential GND must be applied. The potential of the node NNref[i+1] may be the ground potential GND. (i.e., p=1), the transistor F2m is in the off state. If there is a potential difference, it may be higher or lower than the ground potential GND. stomach.

[0220] <<From time T20 to time T21>> Between time T20 and time T21, a low-level potential is applied to the line SWL1. As a result, each of the transistors F3[1] to F3[n] A low level potential is applied to the gates of the transistors F3[1] to F3[n ] are each turned off.

[0221] <<From time T21 to time T22>> Between time T21 and time T22, a high-level potential is applied to the wiring SWL2. As a result, each of the transistors F4[1] to F4[n] A high-level potential is applied to the gates of the transistors F4[1] to F4[n ] are each turned on.

[0222] <<From time T22 to time T23>> Between time T22 and time T23, the circuit XCS sends the first 2. Current amount I ref0 x[i] times x[i]I ref0 A current of Specifically, for example, when the wiring XCL shown in FIG. 2C is the wiring XCL[i], Then, a high level is applied to each of the wirings DX[1] to DX[K] according to the value of x[i]. A potential or low-level potential is input, and the amount of current flows from the circuit XCSa to the wiring XCL[i]. x[i]I ref0 =x[i]I XutIn this example, x[i] is the 2 data value. At this time, the potential of the wiring XCL[i] is gm [i]+ It is assumed that the change is ΔV[i].

[0223] The potential of the wiring XCL[i] changes, and the cell IM [i,1] to cell IM[i,n], due to the capacitive coupling by the capacitor C5 included in each of the cells Therefore, the potentials of the nodes NN[i,1] to NN[i,n] also change. The potential of node NN[i,j] of cell IM[i,j] is V g [i,j]+pΔV[i] become.

[0224] Similarly, when the potential of the wire XCL[i] changes, the voltage contained in the cell IMref[i] The potential of node NNref[i] also changes due to the capacitive coupling caused by the capacitor C5m included in the Therefore, the potential of the node NNref[i] of the cell IMref[i] is V gm [i] +pΔV[i].

[0225] As a result, between time T22 and time T23, the first The current I1[i,j] flowing between the terminal and the second terminal of the transistor F2m is Amount of current flowing between terminals I ref1 [i,j] can be written as follows:

[0226]

number

[0227]

number

[0228] From equations (1.9) and (1.10), x[i] can be expressed as follows:

[0229]

number

[0230] Therefore, equation (1.9) can be rewritten as follows:

[0231]

number

[0232] That is, between the first terminal and the second terminal of the transistor F2 included in the cell IM[i,j] The amount of current flowing through is proportional to the product of the first data w[i,j] and the second data x[i]. .

[0233] In addition, between time T22 and time T23, the wiring XCL[i +1] as the second data, the current amount I ref0 x[i+1] is x[i+1] times I re f0 Specifically, for example, the wiring XCL shown in FIG. 2C is a wiring XCL[i +1], then, for each of the wirings DX[1] to DX[K], Depending on the value of [1], high-level or low-level potential is input, and the wiring from the circuit XCSa XCL[i+1] is the current amount x[i+1]I ref0 =x[i+1]I Xut flows In this example, x[i+1] corresponds to the value of the second data. The potential of XCL[i+1] is from 0 to V gm [i+1]+ΔV[i+1] do.

[0234] By changing the potential of the wiring XCL[i+1], the i+1th row of the cell array CA Capacitance C5 included in each of cells IM[i+1,1] to IM[i+1,n] The voltages of the nodes NN[i+1,1] to NN[i+1,n] are Therefore, the potential of node NN[i+1,j] of cell IM[i+1,j] is , V g [i+1,j]+pΔV[i+1].

[0235] Similarly, when the potential of the wiring XCL[i+1] changes, the cell IMref[i+ 1], the capacitance C5m of node NNref[i+1] Therefore, the potential of node NNref[i+1] of cell IMref[i+1] also changes. The potential is V gm [i+1]+pΔV[i+1].

[0236] As a result, between time T22 and time T23, the first The amount of current I1[i+1,j] flowing between the terminal and the second terminal of the transistor F2m is Amount of current flowing between the second terminals I ref1 [i+1,j] can be written as follows:

[0237]

number

[0238]

number

[0239] From equations (1.13) and (1.14), x[i+1] can be expressed as follows:

[0240]

number

[0241] Therefore, equation (1.13) can be rewritten as follows:

[0242]

number

[0243] That is, the first terminal and the second terminal of the transistor F2 included in the cell IM[i+1,j] The amount of current flowing between the elements is the first data w[i+1,j] and the second data x[i +1] and is proportional to the product of.

[0244] Here, from the conversion circuit ITRZ[j], the transistor F4[j] and the wiring WCL[j] Consider the total amount of current flowing through cells IM[i,j] and IM[i+1,j]. The total amount of current is I S If [j], then I S [j] is the product of equation (1.12) and equation (1. 16), it can be expressed by the following formula:

[0245]

number

[0246] Therefore, the amount of current output from the conversion circuit ITRZ[j] is the weight The coefficients w[i,j] and w[i+1,j] and the second data, the neuron signal value x[ The current amount is proportional to the sum of the products of x[i] and x[i+1].

[0247] In the above example of operation, the signal flowing to the cell IM[i,j] and the cell IM[i+1,j] We have dealt with the sum of the current amounts, but as multiple cells, cells IM[1,j] to IM[ m,j] can also be treated as the sum of the currents flowing through each of them. In this case, equation (1. 17) can be rewritten as the following equation:

[0248]

number

[0249] Therefore, in the case of the arithmetic circuit MAC1 having a cell array CA of three or more rows and two or more columns, In this case, the arithmetic circuit MAC1 can perform multiply-accumulate operations as described above. One of the columns is used as the current amount I ref0 , and xI ref0 By using the cell that holds , the multiply-and-accumulate operations can be simultaneously performed for the remaining number of columns. By increasing the number of columns in the memory cell array, we have developed a semiconductor device that can perform high-speed multiply-and-accumulate operations. can be provided.

[0250] The above-described example of the operation of the arithmetic circuit MAC1 is a multiplication of the positive first data and the positive second data. This is suitable for calculating the sum. In addition, the product of positive or negative first data and positive second data is An example of an operation for calculating a sum, and a sum of products of positive or negative first data and positive or negative second data An example of the operation for calculating will be described in the second embodiment.

[0251] In this embodiment, the transistors included in the arithmetic circuit MAC1 are OS transistors. In the above, the case where a silicon transistor or a silicon transistor is used has been described. The transistors included in the arithmetic circuit MAC1 are not limited to those made of, for example, Ge. Transistors with active layers made of ZnSe, CdS, GaAs, InP, GaN, SiGe, etc. Which compound semiconductors are used as active layers? Which carbon nanotubes are used as active layers? A transistor having an active layer made of an organic semiconductor, or the like can be used.

[0252] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0253] (Embodiment 2) In the first embodiment, the sum of the products of the first data, which is positive or "0", and the second data, which is positive or "0", is In the present embodiment, the arithmetic circuit for performing the above-described operation and an example of its operation have been described. A multiplication and addition operation of the first data of "0" and the second data of positive or "0", and a positive, negative or A calculation circuit capable of multiplying and adding the first data of "0" and the second data of positive, negative, or "0" Explain about the road.

[0254] <Configuration example 1 of an arithmetic circuit> FIG. 7 shows a multiplication and addition operation between first data, which is positive, negative, or "0," and second data, which is positive or "0." The arithmetic circuit MAC2 shown in FIG. 7 is the same as the arithmetic circuit MAC1 shown in FIG. Therefore, in the explanation of the arithmetic circuit MAC2, The explanation overlapping with that of the arithmetic circuit MAC1 will be omitted.

[0255] The cell array CA shown in Fig. 7 is composed of m cells IMref arranged in one column and m × n In FIG. 7, the cell IMref [1], cell IMref[m], circuit CES[1,j], and circuit CES[m,j] , is shown. The circuit CES[1,j] is composed of the cell IM[1,j] and the cell IM r[1,j], and the circuit CES[m,j] has a cell IM[m,j] and a cell IMr In this specification, circuits CES[1,j] to CES[m,j] are used. [m,j], cell IM[1,j], cell IMr[1,j], cell IM[m,j], cell I When explaining Mr[m,j] etc., the [m,n] etc. attached to each symbol are omitted. This may occur.

[0256] The cell IM is a cell IM[1, The cell IM[m, n] may have the same configuration as the cells IM[m, n] to IM[m, n].

[0257] The cell IMr can have the same configuration as the cell IM. As an example, the same configuration as cell IM is shown. Cell I and I are distinguishable from each other by the transistors, capacitance, etc. contained in each cell. The symbols indicating the transistors and capacitances included in Mr are marked with "r".

[0258] Specifically, the cell IMr includes a transistor F1r, a transistor F2r, and a capacitor C5 The transistor F1r corresponds to the transistor F1 of the cell IM. The transistor F2r corresponds to the transistor F2 of the cell IM, and the capacitance C5r corresponds to the capacitance of the cell IM. Therefore, the transistor F1r, the transistor F2r, and the capacitance C5r The electrical connection configurations of the IM[1,1] to the cell Please refer to the explanation of IM[m,n].

[0259] In the cell IMr, the first terminal of the transistor F1r and the second terminal of the transistor F2r The connection point between the gate and the first terminal of the capacitor C5r is a node NNr.

[0260] In the circuit CES[1,j], the second terminal of the capacitor C5 is electrically connected to the wiring XCL[1]. The gate of the transistor F1 is electrically connected to the wiring WSL[1]. The second terminal of the transistor F1 and the second terminal of the transistor F2 are electrically connected to the wiring WCL[j]. The second terminal of the capacitor C5r is electrically connected to the wiring XCL[1]. The gate of the transistor F1r is electrically connected to the wiring WSL[1]. The second terminal of F1r and the second terminal of transistor F2r are electrically connected to the wiring WCLr[j]. is connected.

[0261] Similarly, in the circuit CES[m,j], the second terminal of the capacitor C5 is connected to the wiring XCL[m]. The gate of the transistor F1 is electrically connected to the wiring WSL[m]. The second terminal of the transistor F1 and the second terminal of the transistor F2 are connected to the wiring WCL[j]. The second terminal of the capacitor C5r is electrically connected to the wiring XCL[m]. The gate of the transistor F1r is electrically connected to the wiring WSL[m]. The second terminal of the transistor F1r and the second terminal of the transistor F2r are connected to the wiring WCLr[j]. are electrically connected.

[0262] Each of the wiring WCL[j] and the wiring WCLr[j] is the wiring described in the first embodiment. As with the wirings WCL[1] to WCL[n], for example, It functions as a wiring that passes current to the included cells IM and IMr. , current is supplied from the conversion circuit ITRZD[j] to the cells IM and IMr included in the circuit CES. It functions as a wiring that carries

[0263] In the arithmetic circuit MAC2 of FIG. 7, the circuit SWS1 includes a transistor F3[j] and , and a transistor F3r[j]. The first terminal of the transistor F3[j] is connected to the wiring The second terminal of transistor F3[j] is electrically connected to the circuit WCS. The gate of the transistor F3[j] is electrically connected to the wiring SWL1. The first terminal of the transistor F3r[j] is electrically connected to the wiring WCLr[j]. , and the second terminal of the transistor F3r[j] is electrically connected to the circuit WCS, The gate of the transistor F3r[j] is electrically connected to the wiring SWL1.

[0264] In the arithmetic circuit MAC2 of FIG. 7, the circuit SWS2 includes a transistor F4[j] and , and a transistor F4r[j]. The first terminal of the transistor F4[j] is connected to the wiring The second terminal of the transistor F4[j] is electrically connected to the converter circuit IT RZD[j], and the gate of transistor F4[j] is electrically connected to wiring SWL2. The first terminal of the transistor F4r[j] is electrically connected to the wiring WCLr [j], and the second terminal of the transistor F4r[j] is electrically connected to the converter circuit ITRZ The gate of the transistor F4r[j] is electrically connected to the wiring SWL2. are electrically connected.

[0265] The conversion circuit ITRZD[j] is a conversion circuit ITRZ[1] to A circuit equivalent to the conversion circuit ITRZ[n], for example, a circuit equivalent to the conversion circuit ITRZD[j] The amount of current flowing from the conversion circuit ITRZD[j] to the wiring WCL[j] and from the conversion circuit ITRZD[j] to the wiring WCLr[ The function is to generate a voltage according to the difference between the amount of current flowing through wiring OL[j] and Possess the ability.

[0266] A specific example of the configuration of the conversion circuit ITRZD[j] is shown in FIG. 8A. TRZD1 is an example of a circuit that can be applied to the conversion circuit ITRZD[j] in FIG. In FIG. 8A, the circuit SW S2, wiring WCL, wiring WCLr, wiring SWL2, transistor F4, transistor F4 The wiring WCL and the wiring WCLr are also shown. For example, the wiring WCL[j] and the wiring WCLr[ j], and the transistors F4 and F4r are, for example, the arithmetic circuit M The transistors F4[j] and F4r[j] are included in AC2. can be done.

[0267] The conversion circuit ITRZD1 in FIG. 8A is electrically connected to the wiring WCL via a transistor F4. The conversion circuit ITRZD1 is connected to the wiring WCL through the transistor F4r. The conversion circuit ITRZD1 is electrically connected to the wiring OL. The conversion circuit ITRZD1 is configured to detect the current flowing from the conversion circuit ITRZD1 to the wiring WCL. The flow rate or the amount of current flowing from the wiring WCL to the conversion circuit ITRZD1 is converted into a first voltage. The function and the amount of current flowing from the conversion circuit ITRZD1 to the wiring WCLr, or from the wiring WCLr A function of converting the amount of current flowing through the conversion circuit ITRZD1 into a second voltage, and a function of converting the first voltage into the second voltage. and a function of outputting an analog voltage corresponding to the difference between the voltage of the input terminal and the voltage of the output terminal to the wiring OL.

[0268] The conversion circuit ITRZD1 of FIG. 8A includes, for example, a resistor RP, a resistor RM, and an operational amplifier OPP, an operational amplifier OPM, and an operational amplifier OP2.

[0269] The inverting input terminal of the operational amplifier OPP is connected to the first terminal of the resistor RP and the second terminal of the transistor F4. The non-inverting input terminal of the operational amplifier OPP is electrically connected to the wiring VRP. The output terminal of the operational amplifier OPP is electrically connected to the second terminal of the resistor RP. It is electrically connected to the non-inverting input terminal of the operational amplifier OP2. The inverting input terminal of the resistor RM is electrically connected to the first terminal of the resistor RM and the second terminal of the transistor F4r. The non-inverting input terminal of the operational amplifier OPM is electrically connected to the wiring VRML. The output terminal of the operational amplifier OPM is connected to the second terminal of the resistor RM and the The output terminal of the operational amplifier OP2 is electrically connected to the inverting input terminal of the are electrically connected.

[0270] The wiring VRPL functions as a wiring that applies a constant voltage. The constant voltage may be, for example, It can be set to a ground potential (GND), a low level potential, etc. Also, the wiring VRML is It functions as a wiring that applies a voltage. The constant voltage can be, for example, ground potential (GND), The potentials of the wirings VRPL and VRML can be low. The constant voltages applied by the wiring V may be equal to or different from each other. By setting the constant voltages given by RPL and wiring VRML to the ground potential (GND), The inverting input terminal of the operational amplifier OPP and the inverting input terminal of the operational amplifier OPM are This can be made into a virtual ground.

[0271] By configuring the conversion circuit ITRZD1 as shown in FIG. 8A, The amount of current flowing through the converter ITRZD1 or the converter ITRZD 1, the amount of current flowing through the wiring WCL via the transistor F4 is converted into a first voltage. In addition, the wiring WCLr is connected to the conversion circuit IT The amount of current flowing through the RZD1 or from the conversion circuit ITRZD1 through the transistor F4r Thus, the amount of current flowing through the wiring WCLr can be converted into the second voltage. An analog voltage corresponding to the difference between the first voltage and the second voltage can be output to the line OL.

[0272] Furthermore, the conversion circuit ITRZD1 in FIG. 8A is configured to output an analog voltage. The circuit configuration that can be applied to the conversion circuit ITRZD[j] in FIG. 7 is not limited to this. For example, the conversion circuit ITRZD1 is an analog-to-digital converter as shown in FIG. 8B, similar to FIG. 4B. It may also be configured to include a conversion circuit ADC. Specifically, the conversion circuit ITRZD2 in FIG. The input terminal of the analog-to-digital conversion circuit ADC is electrically connected to the output terminal of the operational amplifier OP2. and the output terminal of the analog-to-digital conversion circuit ADC is electrically connected to the wiring OL. By adopting such a configuration, the conversion circuit ITR of FIG. ZD2 can output a digital signal to the wiring OL. The TRZD2 is configured to output multiple bits from wiring OL, but it outputs only one bit (2 values). It may also be configured to output the information.

[0273] In addition, in the conversion circuit ITRZD2, the digital signal output to the wiring OL is converted into 1-bit In the case of (2-value), the conversion circuit ITRZD2 is replaced with the conversion circuit ITRZD3 shown in FIG. 8C. The conversion circuit ITRZD3 of FIG. 8C may be replaced with the conversion circuit ITRZD3 of FIG. 8A, similarly to FIG. 4C. The ITRZD1 is configured with a comparator CMP2. Specifically, the conversion circuit ITRZD3 is a resistor that connects the first input terminal of comparator CMP2 to the output terminal of operational amplifier OP2. The second input terminal of the comparator CMP2 is electrically connected to the wiring VRL3. The output terminal of the comparator CMP2 is electrically connected to the wiring OL. The wiring VRL3 is a potential line for comparing with the potential of the first terminal of the comparator CMP2. By using this configuration, the conversion circuit I TRZD3 is the third current converted from the amount of current flowing between the source and drain of transistor F4. The second voltage is converted from the voltage of 1 and the amount of current flowing between the source and drain of transistor F4r. A low level is applied to the wiring OL depending on the difference between the voltage of It can output a potential or a high-level potential (binary digital signal).

[0274] <<Example of first data retention>> Next, in the arithmetic circuit MAC2 of FIG. 7, the first data of positive, negative or "0" and the second data of positive or negative The first data is held in the circuit CES for performing a multiplication and accumulation operation with the second data of "0". An example will be described.

[0275] Since the circuit CES has the cell IM and the cell IMr, the circuit CES has the first data To hold the data, two circuits, cell IM and cell IMr, can be used. The circuit CES sets two current amounts and generates potentials according to the respective current amounts to the cells IM and Therefore, the first data can be stored in the cell IMr. The current amount can be expressed as the current amount set in the cell IMr.

[0276] Here, the positive first data, the negative first data, or the first data of "0" held in the circuit CES 1 Data is defined as follows:

[0277] When the circuit CES[1,j] holds the first positive data, the cell IM[1,j] holds the first positive data. For example, a positive first delay is applied between the first and second terminals of transistor F2 of cell IM[1,j]. The amount of current flowing depends on the absolute value of the data. The gate of cell 2 (node ​​NN[1,j]) maintains a potential according to the amount of current. For example, the first transistor F2r of the cell IMr[1,j] is Set so that no current flows between the terminal and the second terminal. The gate (node ​​NNr[1,j]) is supplied with the potential of the wiring VE, and the circuit WCSa in Fig. 2A. It is only necessary that the potential for initialization given by the wiring VINIL1 is maintained.

[0278] Also, when the negative first data is held in the circuit CES[1,j], the cell IMr[1,j] For example, a negative first data value is applied to the transistor F2r of the cell IMr[1,j]. The current flow is set to the absolute value. The cell IM[ For example, the cell IM[1,j] is configured so that no current flows through the transistor F2 of the cell IM[1,j]. Specifically, the gate of the transistor F2 (node ​​NN[1,j]) is set to The potential provided by the line VE, and the initialization potential provided by the wiring VINIL1 of the circuit WCSa in Figure 2A. etc. should be maintained.

[0279] In addition, when the first data of “0” is held in the circuit CES[1,j], as an example, Transistor F2 of cell IM[1,j] and transistor F2r of cell IMr[1,j] Set each so that no current flows through it. Specifically, the gate of transistor F2 ( node NN[1,j]) and the gate of transistor F2r (node ​​NNr[1,j]) , the potential given by the wiring VE, the initialization potential given by the wiring VINIL1 of the circuit WCSa in FIG. 2A. It is sufficient that the potential or the like is maintained.

[0280] In addition, the other circuits CES also hold positive first data or negative first data. Similarly to the circuit CES[1,j] described above, the cell IM and the wiring WCL, and the wiring WCLr, a current amount according to the first data is set to flow on one side, No current flows between the cell IMr and the wiring WCLr, or between the cell IMr and the wiring WCLr. Also, when the first data of "0" is held in another circuit CES, , as with the above-mentioned circuit CES[1,j], between the cell IM and the wiring WCL, and between the cell IM It is sufficient to set it so that no current flows between r and the wiring WCLr.

[0281] For example, the first data may be "+3", "+2", "+1", "0", "-1", " When the circuit CES is held in each of the cases of "-2" and "-3", the wiring WCL Setting the amount of current flowing to cell IM and the amount of current flowing from wiring WCLr to cell IMr By following the above, the first data "+3", "+2", "+1", "0", "- For example, each of "-1", "-2", and "-3" can be defined as shown in the following table. .

[0282] [Table 1]

[0283] Here, in the arithmetic circuit MAC2 of FIG. 7, the circuits CES[1,j] to CES[m , j], and the first data is stored in each of the wirings XCL[1] to XCL[m]. In this case, a low level potential is applied to the wiring SWL1. is applied to turn off the transistor F3[j] and the transistor F3r[j]. When this occurs, a high-level potential is applied to the wiring SWL2 to turn on the transistor F4[j] and the transistor F4r[j] is turned on. This turns on the conversion circuit ITRZD[j] and the wiring WCL[ Since the connection between the conversion circuit ITRZD[j] and the wiring WCL[j] is in a conductive state, the current flows from the conversion circuit ITRZD[j] to the wiring WCL[j]. In addition, there may be a current between the conversion circuit ITRZD[j] and the wiring WCLr[j]. Since the circuit is conductive, current flows from the conversion circuit ITRZD[j] to the wiring WCLr[j]. The total current flowing from the conversion circuit ITRZD[j] to the wiring WCL[j] is I S [j], and the sum of the currents flowing from the conversion circuit ITRZD[j] to the wiring WCLr[j] ISr [j], taking into consideration the operation example of the arithmetic circuit MAC1 explained in the first embodiment, , I S [j] and I Sr [j] can be expressed by the following formula:

[0284]

number

[0285] Note that w[i,j] in equation (2.1) is the first data written to cell IM[i,j]. is the value of the data, and is expressed as w r [i,j] is written to cell IMr[i,j] The value of the first data included in w[i,j] or w r One of [i,j] is "0" If the value is not r The other of [i,j] must be set to "0". Therefore, the first data held in the circuit CES[i,j] is, for example, the definition shown in Table 1. You can follow etc.

[0286] The conversion circuit ITRZD[j] calculates, for example, the sum I S [j] The total current I that flows through the wiring WCLr is converted into the first voltage. Sr [j] to the second voltage Then, the conversion circuit ITRZD[j] converts the first voltage to the second voltage. A voltage can be output to the wiring OL.

[0287] Incidentally, the conversion circuits ITRZD1 to ITRZD2 shown in FIGS. 8A to 8C, respectively, The TRZD3 has a circuit configuration in which a voltage is output to the wiring OL. For example, the conversion circuit ITRZD[j ] may be configured as a circuit that outputs a current.

[0288] The conversion circuit ITRZD4 shown in FIG. 9 is a conversion circuit included in the arithmetic circuit MAC2 shown in FIG. This is a circuit that can be applied to ITRZD[j], and is used for multiplication and addition operations and activation function operations. The circuit is configured to output the result as a current amount.

[0289] In FIG. 9, the circuit is shown in order to show the electrical connection between the conversion circuit ITRZD4 and the peripheral circuits. Path SWS2, wiring WCL, wiring WCLr, wiring OL, transistor F4, transistor F 4r are also shown. In addition, as an example, each of the wiring WCL and the wiring WCLr is shown in FIG. The wiring WCL[j] and the wiring WCLr[j] are included in the arithmetic circuit MAC2 of 7. The transistor F4 and the transistor F4r are included in the arithmetic circuit MAC2 of FIG. The transistors F4[j] and F4r[j] may be connected to the same node.

[0290] The conversion circuit ITRZD4 in FIG. 9 is electrically connected to the wiring WCL via the transistor F4. The conversion circuit ITRZD4 is connected to the wiring WCLr via the transistor F4r. The conversion circuit ITRZD4 is electrically connected to the wiring OL. The conversion circuit ITRZD4 controls the current flowing from the conversion circuit ITRZD4 to the wiring WCL. The amount of current flowing from the wiring WCL to the conversion circuit ITRZD4 is one of the amounts of current flowing from the wiring WCL to the conversion circuit ITRZD4. The amount of current flowing from ZD4 to the wiring WCLr, or from the wiring WCLr to the conversion circuit ITRZD4 It has a function to acquire the differential current between one of the current flows and the other. It has the function of flowing current between the switching circuit ITRZD4 and the wiring OL.

[0291] The conversion circuit ITRZD4 of FIG. 9 includes, for example, a transistor F5, a current source CI, and a current It has a current source CIr and a current mirror circuit CM1.

[0292] The second terminal of the transistor F4 is connected to the first terminal of the current mirror circuit CM1 and the current source CI The output terminal of the transistor F4r is electrically connected to the output terminal of the current mirror a second terminal of the circuit CM1, an output terminal of the current source CIr, and a first terminal of the transistor F5; The input terminal of the current source CI is electrically connected to the wiring VHE. The input terminal of the current source CIr is electrically connected to the wiring VHE. The third terminal of the current mirror circuit CM1 is electrically connected to the wiring VSE. The fourth terminal of CM1 is electrically connected to the line VSE.

[0293] The second terminal of the transistor F5 is electrically connected to the wiring OL. The port is electrically connected to the wiring OEL.

[0294] As an example, the current mirror circuit CM1 is The current mirror circuit CM1 is connected between the first and third terminals of the current mirror circuit CM1 and the current The second terminal and the fourth terminal of the mirror circuit CM1 are connected to each other.

[0295] The wiring VHE functions as, for example, a wiring that applies a constant voltage. The constant voltage may be a high level potential or the like.

[0296] The wiring VSE functions as, for example, a wiring that applies a constant voltage. The constant voltage may be a low level potential, a ground potential, or the like.

[0297] The wiring OEL is used to switch the transistor F5 on or off, for example. Specifically, for example, the wiring OEL has a high A level potential or a low level potential may be input.

[0298] The current source CI has a function of causing a constant current to flow between the input terminal and the output terminal of the current source CI. In addition, the current source CIr has the function of flowing a constant current between the input terminal and output terminal of the current source CIr. In the conversion circuit ITRZD4 of FIG. 9, the magnitude of the current flowing from the current source CI is , and the magnitude of the current flowing from the current source CIr are preferably equal.

[0299] Here, an example of the operation of the conversion circuit ITRZD4 in FIG. 9 will be described.

[0300] First, the current flowing from the conversion circuit ITRZD4 to the wiring WCL via the transistor F4 is The amount of I S and the conversion circuit ITRZD4 is connected to the wiring WCLr via the transistor F4r. The amount of current flowing is I Sr In addition, the currents flowing from the current sources CI and CIr are Let the amount of flow be I0.

[0301] I S In the arithmetic circuit MAC2 of FIG. 7, for example, the cell IM[1, The sum of the currents flowing through cells IM[m,j] to IM[m,j] is also called I Sr is the operation in Figure 7. In the circuit MAC2, for example, the cells IMr[1,j] to IMr[1,j] located in the j-th column This is the sum of the currents flowing through [m,j].

[0302] When a high-level potential is input to the wiring SWL2, the transistors F4 and Therefore, the first terminal of the current mirror circuit CM1 is turned on. The amount of current flowing through the third terminal is I0-I S In addition, the current mirror circuit CM1 The current mirror circuit CM1 has a second terminal connected to the fourth terminal, and the output voltage I0-I S A current of flows.

[0303] Next, a high-level potential is input to the wiring OEL, turning on the transistor F5. At this time, the amount of current flowing through the wiring OL is I out Then, I out =I0-(I0-I S )-I Sr =I S -I Sr This becomes:

[0304] Here, in the arithmetic circuit MAC2 of FIG. 7, the first data is positive, negative, or "0" and the positive, Or, the first data is held in the circuit CES for performing a multiplication and accumulation operation with the second data of "0". In this regard, please refer to the example of first data retention above.

[0305] That is, when the circuit CES[i,j] holds the positive first data, the cell IM[i,j] In the example, a positive first data signal is applied between the first terminal and the second terminal of the transistor F2 of the cell IM[i,j]. The current flow is set to the absolute value of the value of cell I It is set so that no current flows between the first and second terminals of the transistor F2r of Mr[i,j]. In addition, when the negative first data is held in the circuit CES[i,j], the cell IM[i, In cell IM[i,j], current flows between the first and second terminals of transistor F2 of cell IM[i,j]. The cell IMr[i,j] is set to have the transistor F The amount of current that flows between the first and second terminals of 2r corresponds to the absolute value of the negative first data value. In addition, when the first data of “0” is held in the circuit CES[i,j], the cell I M[i,j] contains a voltage between the first terminal and the second terminal of the transistor F2 of the cell IM[i,j]. The current is set to not flow, and the cell IMr[i,j] contains the transaction of the cell IMr[i,j]. Set resistor F2r so that no current flows between the first and second terminals.

[0306] Here, each of the wirings XCL[1] to XCL[m] of the arithmetic circuit MAC2 in FIG. When the second data is input to the first terminal of the transistor F2 of the cell IM[i,j], The amount of current flowing between the two terminals, and the first terminal of the transistor F2r of the cell IMr[i,j] The amount of current flowing between the second terminals is proportional to the second data.

[0307] I S is the amount of current flowing through cells IM[1,j] to IM[m,j] located in the j-th column. Therefore, I S is one of the circuits CES[1,j] to CES[m,j] , the total amount of current flowing through the cells IM included in the circuit CES in which the positive first data is held. It can be expressed as the sum of, for example, equation (2.1). S is the first positive It corresponds to the result of multiplying and accumulating the absolute value of the first data and the second data. Sr is in the jth column It is the sum of the currents flowing through the cells IMr[1,j] to IMr[m,j]. Therefore, I Sr is the first negative data among the circuits CES[1,j] to CES[m,j]. This is the sum of the currents flowing through the cells IMr included in the circuit CES where the data is held, For example, it can be expressed in the same way as equation (2.2). That is, I Sr is the negative of the first data It corresponds to the result of a multiplication and accumulation operation between the absolute value and the second data.

[0308] Therefore, the current flowing through the wiring OL is I out =I S -I Sr is the absolute value of the first positive data the result of the multiplication and addition operation between the value of the first data and the second data, and the result of the multiplication and addition operation between the absolute value of the negative first data and the second data. It corresponds to the difference between the result of the calculation and out =I S -I Sr is the circuit CES[1,j ] to the circuit CES[m,j], and the first data of negative, "0", or positive, and the The multiplication and accumulation operation with the second data input to each of the lines XCL[1] to XCL[m] Respond to the results.

[0309] By the way, the sum of the currents flowing through cells IM[1,j] to IM[m,j] is When the sum of the currents flowing through cells IMr[1,j] to IMr[m,j] is larger than the sum of the currents flowing through cells IMr[1,j] to IMr[m,j], Nawachi I S I Sr When it is greater than out The current is greater than 0, and the conversion circuit On the other hand, the current flows from the cell IM[1,j] to the cell IM[m,j] ] is the sum of the currents flowing through cells IMr[1,j] to IMr[m,j]. When it is smaller than the sum of the flows, that is, I S I Sr When the voltage is smaller than the In other words, there may be a case where no current flows through the ITRZD4 switching circuit. S I Sr is smaller than Ki, I out can be set to approximately 0. For this reason, the conversion circuit ITRZD4 is configured as follows: , can be considered to act as a ReLU function.

[0310] The ReLU function can be used, for example, as an activation function for neural networks. In the operation of a neural network, the value of each signal of the previous layer neuron ( For example, the second data) and a corresponding weighting factor (for example, the first data and It is necessary to calculate the sum of the products of the two. Therefore, we define the activation function of the neural network as Re When the LU function is used, the calculation of the neural network includes the conversion circuit ITRZD4. This can be done by using an arithmetic circuit MAC2 including:

[0311] The hierarchical neural network will be described later in the fourth embodiment.

[0312] Next, an example of a specific circuit configuration of the conversion circuit ITRZD4 in FIG. 9 will be described.

[0313] The conversion circuit ITRZD4 shown in FIG. 10A is an example of the conversion circuit ITRZD4 of FIG. Specifically, in FIG. 10A, a current mirror circuit CM1, a current source CI, and a current source CIr 1 shows examples of each of the above configurations.

[0314] In the conversion circuit ITRZD4 of FIG. 10A, the current mirror circuit CM1 is, for example, , transistor F6, and transistor F6r. The current source CI is, for example, The current source CIr includes, for example, a transistor F7r. O, transistor F6, transistor F6r, transistor F7, and transistor F7 r is an n-channel transistor.

[0315] For example, the first terminal of the current mirror circuit CM1 is connected to the first terminal of the transistor F6. The gate of the transistor F6 is electrically connected to the gate of the transistor F6r. The third terminal of the input mirror circuit CM1 is electrically connected to the second terminal of the transistor F6. The second terminal of the current mirror circuit CM1 is connected to the first terminal of the transistor F6r. The fourth terminal of the current mirror circuit CM1 is electrically connected to the second terminal of the transistor F6r. It is electrically connected to the terminal.

[0316] For example, the output terminal of the current source CI is connected to the first terminal of the transistor F7 and the second terminal of the transistor F8. The input terminal of the current source CI is electrically connected to the gate of the transistor F7. It is electrically connected to the second terminal.

[0317] For example, the output terminal of the current source CIr is connected to the first terminal of the transistor F7r. The gate of transistor F7r is electrically connected to the input terminal of current source CIr. The second terminal of the capacitor F7r is electrically connected to the second terminal of the capacitor F7r.

[0318] The transistor F7 and the transistor F7r each have a gate electrically connected to a first terminal. The second terminal and the wiring VHE are electrically connected to each other. Therefore, the gate-source voltages of the transistors F7 and F7r are 0 V, and the threshold voltages of the transistors F7 and F7r are appropriately set. If the voltage is within the range, the first terminals of the transistors F7 and F7r A constant current flows between the second terminals of the transistor F7 and the transistor F7r. Each of these functions as a current source.

[0319] The configuration of the current source CI and the current source CIr included in the conversion circuit ITRZD4 in FIG. , the current source CI and the current source CIr are not limited to those shown in FIG. 10A. The configurations of the current source CI and the current source CIr included in 4 may be changed depending on the situation. You may go.

[0320] For example, the current source CI and the current source CIr included in the conversion circuit ITRZD4 in FIG. Each of them may be the current source CI (current source CIr) shown in FIG. 10B.

[0321] The current source CI (current source CIr) in FIG. 10B has, as an example, a plurality of current sources CSA. Each of the multiple current sources CSA includes a transistor F7, a transistor F7s, and , terminal U1, terminal U2, and terminal U3.

[0322] As an example, the current source CSA outputs a current I between terminals U2 and U1. CSA Flow The current source CI (current source CIr) has a function of, for example, P -1 piece (P is 1 or more When we assume that we have a current source CSA with a current source CI (current source CIr) is the amount of current at the output terminal, s×I CSA (s is 0 to 2 P -1 or less) It is possible.

[0323] In practice, in the manufacturing stage of the current source CI (current source CIr), Errors may occur due to variations in the electrical characteristics of the transistors included in the CSA. Therefore, the constant current I is output from each of the terminals U1 of the multiple current sources CSA. CSA The error should preferably be within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the current source CI (current source CIr) includes The constant current I is output from terminal U1 of the multiple current sources CSA. CSA Assuming there is no error in explain.

[0324] In one of the plurality of current sources CSA, the first terminal of transistor F7s is electrically connected to terminal U1. The gate of transistor F7s is electrically connected to terminal U3. The first terminal of the transistor F7 is connected to the gate of the transistor F7 and the second terminal of the transistor F7s. The second terminal of transistor F7 is electrically connected to terminal U2. is connected to.

[0325] Each terminal U1 of the multiple current sources CSA is the output terminal of the current source CI (current source CIr). In addition, the terminal U2 of each of the multiple current sources CSA is electrically connected to the current source It is electrically connected to the input terminal of CI (current source CIr). In other words, multiple current sources CS There is electrical continuity between each terminal U2 of A and the wiring VHE.

[0326] In addition, the terminal U3 of one current source CSA is electrically connected to the wiring CL[1]. Each of the terminals U3 of the current source CSA is electrically connected to the wire CL[2]. P-1 Individual electricity Each of the terminals U3 of the current source CS is electrically connected to a wire CL[P].

[0327] The lines CL[1] to CL[P] are supplied with constant voltages from the electrically connected current source CSA. Flow I CSA It functions as a wiring that transmits a control signal to output. For example, when a high-level potential is applied to the wiring CL[1], The connected current source CSA outputs a constant current I CSA is passed to terminal U1, and the wiring CL When a low-level potential is applied to [1], it is electrically connected to the wiring CL[1]. The current source CSA is I CSA For example, if a high-level potential is applied to the wiring CL[2], When the following is given, the two current sources CSA electrically connected to the wire CL[2] are , total 2I CSA is applied to terminal U1 as a constant current, and a low-level potential is applied to wire CL[2]. When the current source CSA electrically connected to the wire CL[2] is given, the total 2I CSA For example, if a high-level potential is applied to the wiring CL[P], When the P-1 The current sources CSA are , total 2 P-1 I CSA is applied to terminal U1 as a constant current, and a low level is applied to wiring CL[P]. When a potential is applied to the wire CL[P], the current source CSA electrically connected to the wire CL[P] is , total 2 P-1 I CSA It does not output a constant current.

[0328] Therefore, the current source CI (current source CIr) is selected from the wiring CL[1] to the wiring CL[P]. By applying a high level potential to one or more of the exposed wires, the current source CI (current source CIr ) output terminal. The amount of the current is controlled by inputting a high-level potential. The wiring is a combination of one or more wirings selected from the wirings CL[1] to CL[P]. For example, when a high-level potential is applied to the wiring CL[1] and the wiring CL[2], When a low-level potential is applied to the wirings CL[3] to CL[P], a current The current source CI (current source CIr) has a total of 3I at the output terminal of the current source CI (current source CIr). CSA of It is possible to pass an electric current through it.

[0329] As described above, by using the current source CI (current source CIr) in FIG. 10B, Accordingly, the amount of current that the current source CI (current source CIr) supplies to the output terminal can be changed.

[0330] 10A is applied as the conversion circuit ITRZD4 of FIG. 9. By doing so, all the transistors included in the conversion circuit ITRZD4 are OS transistors. Also, the cell array CA of the arithmetic circuit MAC2, the circuit WCS, the circuit Since XCS and other circuits can be configured using only OS transistors, the conversion circuit ITRZD 4 can be fabricated simultaneously with the cell array CA, the circuit WCS, the circuit XCS, etc. Therefore, it may be possible to shorten the manufacturing process of the arithmetic circuit MAC2. , the current source CI and the current source CIr of the conversion circuit ITRZD4 of FIG. 10A are connected to the current source C The same applies to the case where I (current source CIr) is applied.

[0331] For example, the current source CI and the current source CIr included in the conversion circuit ITRZD4 in FIG. Since the same current must flow through each of the current sources CI and CIr, This may be replaced with a current mirror circuit.

[0332] The conversion circuit ITRZD4 shown in FIG. 11A is a circuit diagram of the current The current source CI and the current source CIr are replaced with a current mirror circuit CM2. The current mirror circuit CM2 includes, for example, a transistor F8 and a transistor F8r. The transistor F8 and the transistor F8r are p-channel transistors. It is called Jista.

[0333] The first terminal of the transistor F8 is connected to the gate of the transistor F8 and the second terminal of the transistor F8r. the gate, the second terminal of the transistor F4, and the first terminal of the current mirror circuit CM1; The second terminal of the transistor F8 is electrically connected to the wiring VHE. The first terminal of the transistor F8r is connected to the second terminal of the transistor F4r and the current The second terminal of the transistor F8r is electrically connected to the second terminal of the mirror circuit CM1. The two terminals are electrically connected to the wiring VHE.

[0334] As shown in the conversion circuit ITRZD4 of FIG. 11A, the voltages included in the conversion circuit ITRZD4 of FIG. By replacing the current source CI and the current source CIr with a current mirror circuit CM2, The connection point between the second terminal of the transistor F4 and the first terminal of the current mirror circuit CM1, The second terminal of the current mirror circuit CM1 and the second terminal of the transistor F5 are connected to each other. Approximately equal amounts of current can flow through the connection points with the first terminal.

[0335] In FIG. 11A, the current mirror circuit CM2 is made up of a transistor F8 and a transistor F8r, but the circuit configuration of the current mirror circuit CM2 is For example, the current mirror circuit CM2 may be configured as follows, similarly to FIG. 11C described later: The transistors included in the current mirror circuit CM2 may be cascode-connected. In this way, the circuit configuration of the current mirror circuit CM2 in FIG. 11A can be changed depending on the situation. may be performed.

[0336] The conversion circuit ITRZD4 in FIG. 11A is configured as the conversion circuit ITRZD4 shown in FIG. 11B. As shown in the configuration, the current mirror circuit CM1 may not be provided. The switching circuit ITRZD4 connects the first terminal of the current mirror circuit CM2 to the third terminal of the transistor F4. The amount of current flowing through the two terminals and the current from the second terminal of the current mirror circuit CM2 to the transistor F4r and the current flowing through the connection point between the second terminal of the transistor F1 and the first terminal of the transistor F5 are approximately equal to each other. Therefore, I S I Sr If the value is larger than the value shown in FIG. The amount of current flowing through L is I out is the same as the conversion circuit ITRZD4 in Figure 9. S -I Sr Let's say It is possible.

[0337] The conversion circuit ITRZD4 of FIG. 11B does not include the current mirror circuit CM1. Therefore, the circuit area can be reduced compared to the conversion circuit ITRZD4 in FIG. 11A. In addition, there is no steady current flowing from the current mirror circuit CM2 to the current mirror circuit CM1. Therefore, the conversion circuit ITRZD4 of FIG. 11B is more efficient than the conversion circuit ITRZD4 of FIG. 11A. Power consumption can be reduced.

[0338] In FIG. 11B, the transistors F8 and F8r are not shown. The current mirror circuit CM2 is shown as a block diagram. The current mirror circuit CM2 can be configured as shown in FIG. 11A depending on the situation. can be decided.

[0339] For example, the current mirror circuit CM2 included in the conversion circuit ITRZD4 in FIG. 11B is Alternatively, the current mirror circuit CM2 shown in FIG. 11C may be used. The current mirror circuit CM2 is a current mirror circuit CM2 shown in FIG. 11B, which further includes a p-channel transistor. The transistors F8s and F8sr are provided as transistors F8 and Transistor F8s is connected in cascode, and transistor F8r and transistor F8sr As shown in Figure 11C, the current mirror circuit The transistors included in the current mirror are connected in cascode, can be made more stable.

[0340] The current mirror circuit CM1 included in the conversion circuit ITRZD4 of FIG. 9 is The current mirror circuit CM1 shown in FIG. The configuration of the included current mirror circuit CM1 may be changed depending on the situation.

[0341] For example, the current mirror circuit CM1 included in the conversion circuit ITRZD4 of FIG. The current mirror circuit CM1 shown in FIG. 11D may be used. M1 is an n-channel transistor in addition to the current mirror circuit CM1 shown in FIG. 10A. The transistors F6s and F6sr are provided to The transistors F6r and F6sr are connected in cascode. As shown in Figure 11D, the current mirror circuit By connecting the transistors in cascode, the operation of the current mirror circuit becomes more stable. It can be determined.

[0342] <Configuration example 2 of an arithmetic circuit> FIG. 12 shows a first data value that is positive, negative, or "0", a second data value that is positive, negative, or "0", The arithmetic circuit MAC3 shown in FIG. The arithmetic circuit MAC2 of 7 has been modified. Therefore, the explanation of the arithmetic circuit MAC3 In the above, the explanations of the arithmetic circuits MAC1 and MAC2 are omitted. do.

[0343] The cell array CA shown in FIG. 12 includes m circuits CESref arranged in one column and m× 12, the circuit CE Sref[i] and the circuit CES[i,j] are excerpted and illustrated.

[0344] The circuit CES[i,j] is composed of cells IM[i,j], IMr[i,j], and IM s[i,j] and cell IMsr[i,j]. ES[i,j], cell IM[i,j], cell IMr[i,j], cell IMs[i,j], When explaining cells such as IMsr[i,j], the [i,j] symbols are added to each cell. etc. may be omitted.

[0345] The cell IMs and the cell IMsr can have the same configuration as the cell IM. The cells IMs and IMsr are illustrated as having the same configuration as the cell IM, as an example. In addition, the transistors included in each of the cells IM, IMs, and IMsr In order to distinguish the transistors and capacitances included in the cells IMs, The symbols are marked with "s" and indicate the transistors and capacitors included in the cell IMsr. is prefixed with "sr".

[0346] Specifically, the cell IMs includes a transistor F1s, a transistor F2s, and a capacitor C5 The transistor F1s corresponds to the transistor F1 of the cell IM. The transistor F2s corresponds to the transistor F2 of the cell IM, and the capacitance C5s corresponds to the capacitance of the cell IM. Therefore, the transistor F1s, the transistor F2s, and the capacitance C5s The electrical connection configurations of the IM[1,1] to the cell Please refer to the explanation of IM[m,n].

[0347] The cell IMsr includes a transistor F1sr, a transistor F2sr, and a capacitor C5 sr. The transistor F1sr corresponds to the transistor F1 of the cell IM. , transistor F2sr corresponds to transistor F2 of cell IM, and capacitance C5sr corresponds to cell I This corresponds to the capacitance C5 of M. Therefore, the transistors F1sr and F2sr The electrical connection configuration of the capacitors C5sr and C5sr is the same as that of the cells IMs. Please refer to the description of cells IM[1,1] to IM[m,n] in the first embodiment.

[0348] In addition, in the cell IMs, the first terminal of the transistor F1s and the second terminal of the transistor F2s The connection point between the gate and the first terminal of the capacitance C5s is the node NNs, and in the cell IMsr, The first terminal of the transistor F1sr, the gate of the transistor F2sr, and the capacitor C5 The connection point between the first terminal of sr and is designated as node NNsr.

[0349] In the circuit CES[i,j], the second terminal of the capacitor C5 is electrically connected to the wiring XCL[i]. The gate of the transistor F1 is electrically connected to the wiring WSL[i]. The second terminal of the transistor F1 and the second terminal of the transistor F2 are electrically connected to the wiring WCL[j]. The second terminal of the capacitor C5r is electrically connected to the wiring XCL[i]. The gate of the transistor F1r is electrically connected to the wiring WSL[i]. The second terminal of F1r and the second terminal of transistor F2r are electrically connected to the wiring WCLr[j]. is connected.

[0350] The second terminal of the capacitor C5s is electrically connected to the wiring XCLs[i]. The gate of the transistor F1s is electrically connected to the wiring WSLs[i]. The second terminal of the transistor F2s is electrically connected to the wiring WCL[j]. The second terminal of the capacitor C5sr is electrically connected to the line XCLs[i]. The gate of the transistor F1sr is electrically connected to the wiring WSLs[i]. The second terminal of transistor F2sr is electrically connected to the wiring WCLr[j]. is connected.

[0351] The circuit CESref[i] shown in FIG. 12 is composed of cells IMref[i] and IMrefs [i]. In this specification, the circuit CESref[i], the cell IMref When explaining cell [i], cell IMrefs[i], etc., the notation [i ] may be omitted.

[0352] The cell IMrefs can have the same configuration as the cell IMref. IMrefs is illustrated as having the same configuration as cell IMref, as an example. The transistors, capacitances, etc. included in each of the cells IMref and IMrefs To distinguish between them, we use the following: The symbols are prefixed with "s."

[0353] Specifically, the cell IMrefs includes the transistors F1ms and F2ms. , and capacitance C5ms. The transistor F1ms is the transistor of the cell IMref. Transistor F2ms corresponds to transistor F2m of cell IMref. Therefore, the capacitance C5ms corresponds to the capacitance C5m of the cell IMref. Electrical connection configurations of F1ms, transistor F2ms, and capacitance C5ms For details, please refer to the description of IMref[1] to IMref[m] in the first embodiment. do.

[0354] In addition, in the cell IMrefs, the first terminal of the transistor F1ms and the The connection point between the gate of F2ms and the first terminal of the capacitor C5ms is called node NNrefs. are.

[0355] In the circuit CESref[i], the second terminal of the capacitance C5m is electrically connected to the wiring XCL[i]. The gate of the transistor F1m is electrically connected to the wiring WSL[i], The second terminal of the transistor F1m and the second terminal of the transistor F2m are connected to the wiring XCL[i] The second terminal of the capacitor C5ms is electrically connected to the wiring XCLs[i]. The gate of the transistor F1ms is electrically connected to the wiring WSLs[i]. The second terminal of the transistor F1ms and the second terminal of the transistor F2ms are connected to each other by a wiring X It is electrically connected to CLs[i].

[0356] Each of the wiring XCL[i] and the wiring XCLs[i] is the wiring described in the first embodiment. As with the wirings XCL[1] to XCL[n], for example, Wiring that passes current to the included cells IM, IMr, IMs, and IMsr, For example, the cell IMref[i] included in the circuit CESref from the circuit XCS and cell IMrefs[i].

[0357] Each of the wiring WSL[i] and the wiring WSLs[i] is the wiring described in the first embodiment. Similarly to the wirings WSL[1] to WSL[m], for example, For the included cell IM, cell IMr, cell IMs, and cell IMsr, the first data For example, the wiring from the circuit WSD to the circuit C For the cell IMref and cell IMrefs included in the ESref, reference data is It functions as a wiring for transmitting a selection signal for writing.

[0358] The conversion circuit ITRZD[j] included in the arithmetic circuit MAC3 of FIG. 12 is the arithmetic circuit of FIG. A circuit applicable to the conversion circuit ITRZD[j] included in the circuit MAC2 can be used. That is, the conversion circuit ITRZD[j] included in the arithmetic circuit MAC3 may be, for example, Applying the conversion circuits ITRZD1 to ITRZD3 shown in FIGS. 8A to 8C can be done.

[0359] Next, in the arithmetic circuit MAC3 of FIG. 12, the first data of positive, negative, or "0" and the positive, The first data is held in the circuit CES for performing a product-sum operation with the second data, which is negative or "0". An example of inputting the second data to the circuit CES will be described below.

[0360] The circuit CES has a cell IM, a cell IMr, a cell IMs, and a cell IMsr. Therefore, the circuit CES stores the cells IM, IMr, and IMs as the first data storage. In other words, the circuit CES can be made up of four circuits: By setting the current amount, the potential corresponding to each current amount is set to cell IM, cell IMr, and cell Therefore, the first data can be stored in the cell I The current amount set by M, the current amount set by cell IMr, and the current amount set by cell IMs It can be expressed as the flow rate and the amount of current set in cell IMsr.

[0361] Here, the positive first data, the negative first data, or the first data of "0" held in the circuit CES The data is defined as follows:

[0362] When the circuit CES[i,j] holds the positive first data, the cell IM[i,j] holds the positive first data. For example, the transistor F2 of the cell IM[i,j] is set to a value corresponding to the absolute value of the positive first data. The amount of current flowing is set to the value specified by the cell IMsr[i,j]. For example, the amount of current flowing is set to correspond to the absolute value of the positive first data value. Specifically, the gate of transistor F2 (node ​​NN[i,j]) and the gate of transistor F The gate of 2sr (node ​​NNsr[i,j]) holds a potential according to the amount of current. In addition, in the cell IMr[i,j], as an example, the transistor F2 r is set so that no current flows, and the cell IMs[i,j] is set as follows: Set the transistor F2s of IMs[i,j] so that no current flows through it. Specifically, The gate of transistor F2r (node ​​NNr[i,j]) and the gate of transistor F2s The potential given by the wiring VE is applied to the node (NNs[i,j]), for example, as shown in FIG. 2A and FIG. 2B. It is only necessary that the potential for initialization given by the wiring VINIL1 of the circuit WCSa is held.

[0363] Also, when the circuit CES[i,j] holds negative first data, the cell IMr[i,j] For example, a negative first data value is applied to the transistor F2r of the cell IMr[1,j]. The current flow is set to the absolute value, and the transistor of cell IMs[i,j] For example, the amount of current flowing through the F2s is determined based on the absolute value of the negative first data value. Specifically, the gate (node ​​NNr[i,j]) of transistor F2r and the The gate of transistor F2s (node ​​NNs[i,j]) maintains a potential according to the amount of current. In addition, in the cell IM[i,j], as an example, the transistor Set F2 so that no current flows, and for example, in cell IMsr[i,j], The transistor F2sr of the cell IMsr[i,j] is set so that no current flows. Specifically, the gate of transistor F2 (node ​​NN[i,j]) and the gate of transistor F2sr The gate (node ​​NNsr[i,j]) of the If the initialization potential provided by the wiring VINIL1 of the circuit WCSa in FIG. 2B is maintained, good.

[0364] In addition, when the first data “0” is held in the circuit CES[i,j], for example, Transistor F2 of cell IM[i,j], transistor F2r of cell IMr[i,j], cell Transistor F2s of cell IMs[i,j] and transistor F of cell IMsr[i,j] 2sr are set so that no current flows through them. Specifically, gate (node ​​NN[i,j]) of transistor F2r and the gate (node ​​NNr[i,j ]) and the gate of transistor F2s (node ​​NNs[i,j]) and transistor F2sr The gate (node ​​NNsr[i,j]) of the If the initialization potential provided by the wiring VINIL1 of the circuit WCSa in FIG. 2B is maintained, good.

[0365] In addition, the other circuits CES also hold positive first data or negative first data. Similarly to the circuit CES[i,j] described above, the connection between the cell IM and the wiring WCL and the cell IMs r and the wiring WCLr, or between the cell IMr and the wiring WCLr and the cell IMs and the wiring WC The current amount corresponding to the first data is set to flow between the first and second terminals, and the current amount corresponding to the second data is set to flow between the first and second terminals. In addition, the first data of "0" is stored in another circuit CES. When the circuit CES[i,j] is maintained, the cell IM and the wiring WCL are connected to the cell IM. Between cell IMr and wiring WCLr, between cell IMs and wiring WCL, and between cell IMsr and wiring WCL It is sufficient to set it so that no current flows between the line WCLsr and the line WCLsr.

[0366] For example, the first data may be "+3", "+2", "+1", "0", "-1", " In the cases of "-2" and "-3", when the circuit CES is held, Setting the amount of current flowing to cell IM, setting the amount of current flowing from wiring WCLr to cell IMr, Setting the amount of current flowing from the line WCL to the cell IMs, and the amount of current flowing from the line WCLr to the cell IMsr By following the above procedure, the first data "+3", "+2", "+1" ", "0", "-1", "-2", and "-3" are defined as follows: It is possible.

[0367] [Table 2]

[0368] On the other hand, the circuit CES has wiring XCL and wiring XCLs as wirings for inputting second data. Therefore, the circuit CES stores two signals as the second data. That is, the second data can be inputted to the signal inputted to the wiring XCL and the The signal input to the line XCLs can be expressed as , the positive second data, the negative second data, or the second data of "0" input to the circuit CES. is defined as follows:

[0369] When inputting positive second data to the circuit CES[i,j], the cell IMref[i] contains As an example, the absolute value of the positive second data value in the transistor F2m of the cell IMref[i] Specifically, the gate (node) of transistor F2m is set to The voltage corresponding to the current is held in the node NNref[i]. For example, in [i], current flows through transistor F2ms of cell IMrefs[i]. Specifically, the gate of the transistor F2ms (node ​​NNrefs [i]) is given a potential by the wiring VE, and the wiring VINIL2 of the circuit XCSa in Figure 2C is given It is only necessary that the potential for initialization or the like is maintained.

[0370] Also, when negative second data is input to the circuit CES[i,j], the cell IMrefs[i ], as an example, the negative second data is input to the transistor F2ms of the cell IMrefs[i]. Specifically, the amount of current flowing through the transistor F2m is set to correspond to the absolute value of the value of The gate of s (node ​​NNrefs[i]) is held at a potential corresponding to the amount of current. For example, in the cell IMref[i], the transistor F2m of the cell IMref[i] The gate of transistor F2m (node ​​NN ref[i]) is the potential given by the wiring VE, the wiring VINIL2 of the circuit XCSa in Figure 2C It is only necessary that the initialization potential given by the

[0371] In addition, when the second data of “0” is input to the circuit CES[i,j], as an example, Transistor F2m of cell IMref[i] and transistor F of cell IMrefs[1] The transistor F2m is set so that no current flows during each of the 2ms. The gate of transistor F2ms (node ​​NNre fs[i]) is the potential given by the wiring VE, and the wiring VINIL2 of the circuit XCSa in Figure 2C It is only necessary that the applied initialization potential or the like is maintained.

[0372] When the positive second data or the negative second data is input to the other circuit CES, , as in the above-mentioned circuit CESref[i], between the cell IMref and the wiring XCL, or A current amount according to the second data flows between the cell IMrefs and the wiring XCLs. Set it as follows, and between cell IMref and wiring XCL, or between cell IMrefs and wiring XCL s and the other side, so that no current flows. When the second data of “0” is input, the cell I Current flows between Mref and the wiring XCL, and between cell IMrefs and the wiring XCLs. You can set it so that this is not the case.

[0373] For example, the second data may be "+3", "+2", "+1", "0", "-1", " In the cases of "-2" and "-3", when the input to the circuit CES is The amount of current flowing from the wiring XCLs to the cell IMrefs is set. By following the above procedure, the second data "+3", "+2", "+1" , "0", "-1", "-2", and "-3" are defined as shown in the following table. It is possible.

[0374] [Table 3]

[0375] Here, the first data stored in the circuit CES are "+3", "+2", "+1", " The first input to the CES circuit is either "0", "-1", "-2" or "-3". When the two data are either "+1", "0", or "-1", the wiring WC The amount of current flowing from L to the cells IM and IMs of the circuit CES, and from the wiring WCLr to the circuit Consider the amount of current flowing through the cells IMr and IMsr of the CES.

[0376] For example, when the second data input to the circuit CES is set to "+1", the capacitance of the circuit CES is The second terminals of C5 and the capacitor C5r receive the second data “+1 A potential corresponding to the absolute value of " is input, and the capacitances C5s and C5sr of the circuit CES are The second terminal of this terminal receives a potential corresponding to the ground potential (GND) from the wiring XCLs. In addition, when the first data held in the circuit CES is set to "+3", the node N The potential corresponding to the absolute value of the first data "+3" is applied to each of N and node NNsr. The node NNr and the node NNs are held at the ground potential (GND). At this time, a current is applied between the first and second terminals of the transistor F2 of the circuit CES. is calculated from equation (1.12) or equation (1.16) as 3I ref0 The amount of current that flows is also the first terminals of the transistors F2r, F2s, and F2sr; - No current flows between the second terminals. That is, 3I flows from the wiring WCL to the cell IM. ref0 of The current flows, and no current flows from the wiring WCL to the cell IMs, and the current flows from the wiring WCLr to the cell IMr Therefore, no current flows from the wiring WCLr to the cell IMsr.

[0377] Also, for example, the second data input to the circuit CES is set to "+1" and stored in the circuit CES. Therefore, the first data stored in the node NNr and the node NNs is set to "-3". The potential corresponding to the absolute value of the first data "-3" is held at each of the nodes NN and It is assumed that each of the nodes NNsr is held at the ground potential (GND). Then, between the first terminal and the second terminal of the transistor F2r of the circuit CES, the following equation (1.12) or From equation (1.16), 3I ref0 In addition, the amount of current flowing through transistor F2 is The current flows between the first and second terminals of the transistors F2s and F2sr. In other words, 3I flows from the wiring WCLr to the cell IMr. ref0 The current flowing through the wiring W No current flows from CL to cell IM, and no current flows from wiring WCL to cell IMs, and wiring WC No current flows from Lr to cell IMsr.

[0378] Also, for example, when the second data input to the circuit CES is set to "-1", the circuit CES The second terminals of the capacitors C5s and C5sr are connected to the second data line XCLs. A potential corresponding to the absolute value of "-1" is input, and the capacitances C5 and C5r of the circuit CES are A potential corresponding to the ground potential (GND) is input to each of the second terminals from the wiring XCL. In addition, when the first data stored in the circuit CES is set to "+3", The node NN and the node NNsr each have a value corresponding to the absolute value of the first data, "+3". The potential is maintained at the node NNr and the node NNs, and the ground potential (GND) is maintained at each of the nodes NNr and NNs. At this time, the first terminal-th terminal of the transistor F2sr in the circuit CES Between the two terminals, 3I is calculated from equation (1.12) or equation (1.16). ref0 A current of flows. In addition, the respective first and second transistors F2, F2r, and F2s No current flows between terminal 1 and terminal 2. In other words, 3 I ref0 The current amount flows, and no current flows from the wiring WCL to the cell IM, and from the wiring WCLr No current flows through cell IMr, and no current flows from wiring WCL to cell IMs.

[0379] Also, for example, the second data input to the circuit CES is set to "-1" and stored in the circuit CES. Therefore, the first data stored in the node NNr and the node NNs is set to "-3". The potential corresponding to the absolute value of the first data "-3" is held at each of the nodes NN and It is assumed that each of the nodes NNsr is held at the ground potential (GND). Then, between the first terminal and the second terminal of the transistor F2s of the circuit CES, the following equation (1.12) or From equation (1.16), 3I ref0 In addition, the amount of current flowing through transistor F2 is The current flows between the first and second terminals of the transistors F2r and F2sr. In other words, 3I from the wiring WCL to the cell IMs ref0 The current flow is No current flows from L to cell IM, no current flows from wiring WCLr to cell IMr, and wiring WC No current flows from Lr to cell IMsr.

[0380] Also, for example, when the second data input to the circuit CES is set to "0", The second terminals of the capacitors C5 and C5r are connected to the ground potential (GND) from the wiring XCL. The second terminals of the capacitors C5s and C5sr of the circuit CES are connected to the wiring Assume that the ground potential (GND) is input from XCLs. At this time, the voltage held in the circuit CES Whatever the value of the first data stored in the transistor F2, the transistor F2r, Between the first terminal and the second terminal of each of the transistors F2s and F2sr, No current flows.

[0381] Also, for example, when the first data held in the circuit CES is set to "0", the node NN, The nodes NNr, NNs, and NNsr are each connected to a ground potential (GND). At this time, the second data input to the circuit CES is The values ​​of transistors F2, F2r, F2s, and No current flows between the first terminal and the second terminal of each of the capacitors F2sr.

[0382] The above shows the cases when the first data is "+3", "-3", "0" and when the second data is "+1", We have explained the cases of "-1" and "0", but if we consider other cases in the same way, the wiring The amount of current flowing through the WCL and the wiring WCLr can be summarized as shown in the following table.

[0383] [Table 4]

[0384] As described above, by using the arithmetic circuit MAC2, the first data of positive, negative or "0" can be obtained. The calculation circuit can perform a multiplication and accumulation operation between the first data and the second data, which is positive or "0". By using MAC3, the first data can be positive, negative, or "0" and the second data can be positive, negative, or "0" " and the second data of " can be subjected to a multiply-and-accumulate operation.

[0385] Note that one embodiment of the present invention is a circuit configuration in which the arithmetic circuit MAC2 and the arithmetic circuit MA The circuit configuration of the arithmetic circuit MAC2 and the arithmetic circuit MAC3 is not limited to the circuit configuration of C3. For example, the circuit configuration can be changed by changing the capacity of the arithmetic circuit MAC3. The capacitance C5, capacitance C5r, capacitance C5s, capacitance C5sr, capacitance C5m, and capacitance C5ms are The capacitance can be the gate capacitance of the register (not shown). Node NN, Node NNr, Node NNs, Node NNsr, Node NNref, and If the parasitic capacitance between the node NNrefs and the surrounding wiring is large, the capacitance C5 and the capacitance C5r , the capacitance C5s, the capacitance C5sr, the capacitance C5m, and the capacitance C5ms are not necessarily provided. .

[0386] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0387] (Embodiment 3) In this embodiment, the arithmetic circuit MAC1 and the arithmetic circuit MAC1A described in the above embodiment are , a combination of one of the arithmetic circuits MAC2 and MAC3 and a sensor. The configuration will be explained.

[0388] <Configuration example of an arithmetic circuit to which the current generated by the sensor is input> FIG. 13A shows a configuration in which an arithmetic circuit MAC1 and a circuit SCA having a sensor are combined. 13A shows an example in which the cell array CA of the arithmetic circuit MAC1 is excerpted. It shows.

[0389] The circuit SCA includes, for example, sensors SNC[1] to SNC[m]. In 13A, for example, the sensors SNC[1] to SNC[m] are arranged in a matrix. It is arranged so that

[0390] The sensors SNC[1] to SNC[m] convert the sensed information into the amount of current. The sensors SNC[1] to SNC[m] have the function of outputting the amount of current. Examples of such sensors include optical sensors using photodiodes, pressure sensors, gyro sensors, and pressure sensors. It can be a speed sensor, an audio sensor, a temperature sensor, a humidity sensor, etc. By applying optical sensors as sensors SNC[1] to SNC[m], the circuit SCA can be part of the image sensor.

[0391] The sensors SNC[1] to SNC[m] sense information about the outside world, for example. Therefore, it is preferable that the circuit SCA is provided in an area close to the outside world. As shown in FIG. 13A, the circuit SCA is preferably provided above the arithmetic circuit MAC1. More specifically, it is preferable that the capacitor C is provided above the cell array CA.

[0392] In addition, the sensor SNC[i] (where i is an integer between 1 and m) is connected to the wiring XCL In other words, the sensor SNC[1] is electrically connected to the wiring XCL[1]. The sensor SNC[m] is electrically connected to the wiring XCL[m]. .

[0393] Therefore, in each of the sensors SNC[1] to SNC[m], When sensing is performed, each of the sensors SNC[1] to SNC[m] is A current amount according to the information is passed through the lines XCL[1] to XCL[m].

[0394] The circuit SCA sequentially detects the sensors SNC[1] to SNC[m]. The current is sequentially supplied to each of the wirings XCL[1] to XCL[m]. In this case, for example, the circuit SCA is configured to be a sensor As a configuration in which signal lines are provided for selecting the sensors SNC[1] to SNC[m], Sequentially operate sensors SNC[1] to SNC[m] by sending signals to the line. You should do so.

[0395] Specifically, for example, as shown in FIG. 13B, in the circuit configuration of FIG. 13A, the wiring XCL A circuit VINI may be provided in the wirings [1] to XCL[m]. The switches SW[1] to SW[m] are ] are electrically connected to the wirings XCL[1] to XCL[m]. , the second terminals of the switches SW[1] to SW[m] are connected to the wiring VINIL The wiring VINIL3 is electrically connected to, for example, a low level potential, a ground potential, etc. In particular, the constant potential is given by the wiring VE. It is preferable that the potential is lower than the potential of the switches SW[1] to S. Switch SW[m] is turned off and the remaining switches SW[m] is turned on. Consider turning off the switches SW[1] to SW[m] in sequence. When each of the sensors SNC[m] senses simultaneously, the sensor SNC[1] The sensor SNC[m] applies a current to each of the wirings XCL[1] to XCL[m]. At this time, the switches SW[1] to SW[m] that are in the ON state The wiring XCL electrically connected to the switch SW is in a conductive state with the wiring VINIL3. Therefore, the current flows to the wiring VINIL3. The potential of the wiring XCL electrically connected to the switch SW is given by the wiring VINIL3. On the other hand, among the switches SW[1] to SW[m], The potential of the wiring XCL electrically connected to the switch SW in the OFF state is It is determined according to the amount of current.

[0396] For example, the sensors SNC[1] to SNC[m] may be photodiodes or the like. In the case where the optical sensor is configured by the sensors SNC[1] to SNC[m ], a filter is prepared so that light is irradiated only onto one of the sensors SNC. In this case, there are m sensors SNC, so there are also m types of filters. In addition, a filter in which light is not irradiated onto any of the sensors SNC[1] to SNC[m] If a filter is prepared, the number of types of filters will be m+1. When the filter is switched sequentially, the sensors SNC[1] to SNC[ m] can perform sensing sequentially.

[0397] For example, the sensors SNC[1] to SNC[m] may be photodiodes or the like. In the case of an optical sensor configured as above, an arithmetic circuit MAC1, an arithmetic circuit MAC1A, The arithmetic circuit MAC2 or the arithmetic circuit MAC3 is a circuit for calculating the sensor SNC[1] to the sensor SNC[m ] may be configured to be individually irradiated with light. By doing so, the sensors SNC[1] to SNC[m] are sequentially irradiated with light, The sensors SNC[1] to SNC[m] can perform sensing sequentially.

[0398] As an example, the circuit SCA and the circuit VINI shown in FIG. 13B are provided in the arithmetic circuit MAC1. An example of the operation of the arithmetic circuit in this case will be described.

[0399] As an example of this operation, please refer to the timing chart in FIG. Among the explanations of the operation example of the arithmetic circuit MAC1 provided with the circuit SCA and the circuit VINI of B, The contents that overlap with the description of the first example of operation of the arithmetic circuit of the first form will be omitted.

[0400] The constant potential applied by the wiring VINIL3 is set to the ground potential.

[0401] From time T13 to time T15 in the timing chart of FIG. 6, the sensor of the circuit SCA The current amount I is sent from the sensor SNC[i] to the wiring XCL[i]. ref0 is playing. ref0 is, for example, the amount of reference current output by the sensor SNC[i] in FIG. 13B after sensing. In addition, in the circuit VINI, when the switch SW[i] is in the OFF state, As a result, the potential of the wiring XCL[i] becomes, for example, V gm [i] shall be the case.

[0402] Also, from time T13 to time T15 in the timing chart of FIG. 6, the sensor S The sensors SNC[1] to SNC[m] other than NC[i] perform sensing. In addition, at this time, the switches SW[i] other than the switch SW[i] By turning on all of the switches SW[1] to SW[m], all of the wires other than the wire XCL[i] are connected. The potential of each of the wirings XCL[1] to XCL[m] is, for example, the ground potential. Let's say.

[0403] From time T17 to time T19 in the timing chart of FIG. 6, the sensor of the circuit SCA The current I flows from the capacitor SNC[i+1] to the wiring XCL[i+1]. ref0 is playing. r ef0 is, for example, the voltage output by the sensor SNC[i+1] in FIG. 13B after sensing. In the circuit VINI, the switch SW[i+1] is turned on. By turning off the power, the potential of the wiring XCL[i+1] becomes, for example, V gm [i+1] and It shall be as follows.

[0404] Also, from time T17 to time T19 in the timing chart of FIG. 6, the sensor S The sensors SNC[1] to SNC[m] other than NC[i+1] perform sensing. In addition, at this time, the switches other than the switch SW[i+1] By turning on the switches SW[1] to SW[m], the wiring XCL[i+1 The potentials of the wirings XCL[1] to XCL[m] other than the wirings XCL[1] to XCL[m] are, for example, ground potential. It shall be as follows.

[0405] From time T22 to time T23 in the timing chart of FIG. 6, Connect the sensor SNC[i] to the wiring XCL[i]. ref0 x[i] times x[i]I re f0 The amount of current that flows is x[i]I ref0 For example, the sensor SNC[ i] can be the current that is sensed and output. Therefore, by turning off the switch SW[i], the potential of the wiring XCL[i] is Ba, V gm [i]+ΔV[i].

[0406] Also, from time T22 to time T23 in the timing chart of FIG. 6, the circuit SC Connect the sensor SNC[i+1] of A to the wiring XCL[i+1]. ref0 x[i+1] times x[i+1]I ref0 The current x[i+1]I flows. ref0 For example, , the sensor SNC[i+1] in FIG. 13B performs sensing and outputs the current. In addition, in the circuit VINI, by turning off the switch SW[i+1], Therefore, the potential of the wiring XCL[i+1] is, for example, V gm Change to [i+1]+ΔV[i+1] This shall be done.

[0407] Then, as explained in the timing chart of Figure 6, the conversion circuit ITRZ[j] and the wiring W The amount of current flowing between the first terminal of transistor F2 of cell IM[i,j] and CL[j] is -The amount of current I1[i,j] flowing between the second terminals and the transistor of cell IM[i+1,j] The current I1[i+1,j] flowing between the first and second terminals of F2 and the sum of (equation (1.1 Therefore, the output from the conversion circuit ITRZ[j] to the wiring WCL[j] is The amount of current to be input is determined by the weighting coefficients w[i,j] and w[i+1,j], which are the first data, and the The sum of the product of the two neuron signal values ​​x[i] and x[i+1], that is, , the current amount is proportional to x[i]w[i,j]+x[i+1]w[i+1,j].

[0408] The arithmetic circuit MAC1 to which the circuit SCA is applied is, for example, a hierarchical neural network. It can perform calculations from the first layer (input layer) to the second layer (middle layer). The information (values) obtained by the sensors SNC[1] to SNC[m] are The neurons in the 1st layer correspond to the signals sent to the neurons in the 2nd layer. The weight coefficient between the neuron in the th layer and the neuron in the second layer is calculated from cells IM[1,j] to By storing the information (value) and the weight in the cell IM[m,j], the calculation circuit MAC1 The sum of products with the coefficients can be calculated.

[0409] The hierarchical neural network will be described in detail in the fourth embodiment.

[0410] In FIG. 14, the sensors SNC[1] to SNC[m] in FIG. 13A are, for example, The circuit SCA using the photodiodes PD[1] to PD[m] is shown. In other words, the circuit SCA in FIG. 14 is assumed to be an image sensor as an example. .

[0411] When using an optical sensor in this way, the intensity of the light irradiated onto the optical sensor is It is desirable to set the intensity to a range that is irradiated in the environment in which the device is used.

[0412] <Configuration example of an arithmetic circuit with a sensor> In the configuration of the semiconductor device shown in FIGS. 13A and 13B, the sensor SNC [1] to sensor SNC[m] converts the sensed information into a current like a photodiode. The circuit configuration includes a device that converts the current into a quantity and outputs the quantity of current, and the peripheral circuit of the device. Specifically, for example, the configuration of the semiconductor device in FIG. 13A may be changed as shown in FIG. 13A. The sensors SNC[1] to SNC[m] in FIG. 13A are connected to the circuits SPR[1] to SPR[m]. It may be replaced by SPR[m].

[0413] Each of the circuits SPR[1] to SPR[m] has a function of sensing certain information. and a sensor SNC having a function of converting the information into a current amount and outputting the current amount. In addition, each of the circuits SPR[1] to SPR[m] has only the sensor SNC. The other functions may include circuits, elements, etc. having other functions. For example, the switch 100 switches the sensor SNC and the wiring XCL between a conductive state and a non-conductive state. function to temporarily stop the sensor SNC, etc. Examples include:

[0414] In addition, the semiconductor device of FIG. 15 includes, as an example, wirings XCL[1] to XCL[m]. The circuit CIR electrically connected to each of the above is also shown. For example, wirings XCL[1] to XC[m] are separate from the circuits SPR[1] to SPR[m]. A circuit for supplying current to L[m], a circuit for supplying potential to the wirings XCL[1] to XCL[m] It can be a road, etc.

[0415] In the semiconductor device of FIG. 15, the cell array CA and the circuit CIR are included in the same layer. However, the structure of the semiconductor device of one embodiment of the present invention is not limited to this. For example, as shown in FIG. 16, the circuit CIR is set to be located below the cell array CA. For example, as shown in FIG. 17, the circuit CIR may be arranged in the same layer as the circuit SCA. That is, the circuit SCA and the circuit CIR may be formed on the same substrate. Although not shown, the circuit CIR may be formed above the cell array CA. It may be provided so as to be located above the circuit SNC and below the circuit SNC. The circuit CIR may be divided into a plurality of layers. The circuit SCA is provided on the same layer as the circuit SCA, and the remaining part of the circuit CIR is provided below the cell array CA. That's fine.

[0416] Here, as an example, each of the circuits SPR[1] to SPR[m] is a sensor S It has a switching function that switches between the conductive state and non-conductive state of NC and wiring XCL. The configuration of the arithmetic circuit in this case will be described.

[0417] The arithmetic circuit MAC4 shown in FIG. 18 has the same configuration as the arithmetic circuit MAC1 in FIG. 1 or the arithmetic circuit MAC4 in FIG. This is a configuration example in which the configuration of the circuit MAC2 is combined with the circuit SCA shown in FIG. By configuring the arithmetic circuit MAC4, This allows for greater freedom in the current input to the cell array CA. By doing so, for example, the reference data described in the first embodiment or the second data can be obtained. The current can be set accordingly.

[0418] The arithmetic circuit MAC4 shown in FIG. 18 includes, as an example, a circuit LGC and a circuit LS. Illustrated.

[0419] The circuit LGC is electrically connected to the circuit LS by the wirings LXS[1] to LXS[m]. The circuit LS is connected to the wiring DXS[1] to the wiring DXS[m]. It is electrically connected to the circuit XCS.

[0420] As described in the first embodiment, the circuit XCS includes the wirings XCL[1] to XCL[m ], the amount of current according to the reference data or the amount of current according to the second data is supplied to each of the The circuit XCS has a function of applying the configuration of the circuit XCS shown in FIG. 2C as an example. It is possible.

[0421] In particular, when the circuit XCS shown in FIG. 2C is applied as the circuit XCS, the wiring XCL[1 The amount of current flowing through one of the wirings XCL[m] is determined by the amount of current flowing through the circuit electrically connected to that wiring. Depending on the combination of potentials input to the wiring DX[1] to wiring DX[L] of XCSa, In FIG. 18, the wiring DXS[1] is electrically connected to the wiring XCL[1]. The wiring DX[1] to DX[L] of the circuit XCSa are connected in series, and the wiring DXS [m] is the wiring DX[1] of the circuit XCSa electrically connected to the wiring XCL[m]. That is, one of the wirings DXS[1] to DXS[m] is a digital The signal may be a bus line for transmitting a digital signal.

[0422] The circuit LS has a function of level-shifting the input potential to a desired potential, for example. Specifically, the circuit LS converts the potential input from the wiring LXS[1] to a desired potential. The level shift is performed and the level-shifted potential is output to the wiring DXS[1]. The number of wires in LXS[1] can be the same as the number of wires in DXS[1]. The circuit LS level-shifts the potential input from the wiring LXS[m] to the desired potential. The level-shifted potential is output to the line DXS[m]. The number of the wirings DXS[m] can be the same as the number of the wirings LXS[1] to LXS[m]. One of XS[m] can be a bus line that transmits a digital signal.

[0423] For example, the circuit LGC sequentially holds the data DT input to the circuit LGC and outputs the desired At the same time, or sequentially, in parallel to the wiring LXS[1] to wiring LXS[m] The data DT here is output from, for example, the wiring XCL [1] to XCL[m] can be used as reference data or second data. That is, the circuit LGC is connected to the wirings XCL[1] to XCL[m] of the arithmetic circuit MAC4. In order to pass a current amount according to the reference data or a current amount according to the second data to the circuit LGC and retaining the reference data or the second data received from outside the Alternatively, the second data is transmitted to the wirings LXS[1] to LXS[m] at a predetermined timing. A specific example of the circuit configuration of the circuit LGC will be described later.

[0424] If there is no need to level-shift the voltage output from the circuit LGC, In the arithmetic circuit MAC4 shown in FIG. 1, the circuit LS is not provided, and the wirings LXS[1] to LXS[ and each of the wirings DXS[1] to DXS[m]. Just continue.

[0425] Next, the configuration of the circuit SCA shown in Fig. 18 will be described. Each of the circuits SPR[1] to SPR[m] includes, for example, a transistor F9 and and a sensor SNC.

[0426] In the circuit SPR[1] electrically connected to the wiring XCL[1], the transistor The first terminal of the transistor F9 is electrically connected to the line XCL[1], and the second terminal of the transistor F9 is is electrically connected to the first terminal of the sensor SNC, and the gate of the transistor F9 is connected to the wiring V The back gate of the transistor F9 is electrically connected to the wiring VBGL. The second terminal of the sensor SNC is electrically connected to the wiring VANL. are.

[0427] In the circuit SPR[m] electrically connected to the wiring XCL[m], The first terminal of the transistor F9 is electrically connected to the wiring XCL[m], and the second terminal of the transistor F9 is is electrically connected to the first terminal of the sensor SNC, and the gate of the transistor F9 is connected to the wiring V The back gate of the transistor F9 is electrically connected to the wiring VBGL. The second terminal of the sensor SNC is electrically connected to the wiring VANL. are.

[0428] As mentioned above, the sensor SNC has the function of sensing information and converting that information into the amount of current. and a function of converting the amount of current and outputting the amount of current.

[0429] In the arithmetic circuit MAC4 shown in FIG. 18, the transistor F9 has a back gate. Although a transistor is illustrated, one embodiment of the present invention is not limited thereto. For example, The transistor F9 may be a transistor with a single gate structure. The transistors may be, for example, OS transistors, Si transistors, etc. By using an OS transistor as the transistor F9, the off-state current of the transistor F9 can be reduced. Therefore, turning off the transistor F9 This makes it possible to minimize the current generated by the sensor SNC that flows through the wiring XCL. Cut.

[0430] For example, the wiring VTXL is used to switch the on and off states of the transistor F9. Therefore, the wiring VTXL is connected to a high level potential or a low level potential. A bell potential is applied.

[0431] The wiring VANL is, for example, a wiring that supplies a power supply voltage to the sensor SNC. The power supply voltage depends on the configuration of the sensor SNC, but may be, for example, It can be a level potential, a low level potential, a ground potential, or the like.

[0432] The wiring VBGL functions as a wiring that applies a constant voltage, for example. can be, for example, a high-level potential, a low-level potential, or a ground potential.

[0433] By applying a desired voltage to the wiring VBGL, the circuits SPR[1] to SPR[ m], the threshold voltage of the transistor F9 included in each of the For example, by applying a high-level potential to the wiring VBGL, the threshold voltage of the transistor F9 is For example, a low-level potential can be applied to the wiring VBGL. This allows the threshold voltage of the transistor F9 to be increased.

[0434] The sensors SNC included in each of the circuits SPR[1] to SPR[m] are shown in FIG. 13A and 13B, similar to the sensors SNC[1] to SNC[m] in FIG. The sensor SN also has the function of converting the measured information into a current amount and outputting that current amount. As for C, for example, as mentioned above, an optical sensor using a photodiode, a pressure sensor, etc. , gyro sensor, acceleration sensor, auditory sensor, temperature sensor, humidity sensor, etc. can be done.

[0435] As an example, the sensor SNC here has a structure including an optical sensor using a photodiode. The circuit SPR[i] in FIG. 19A includes a photodiode PDm in the sensor SNC. The input terminal (sometimes called the anode) of the photodiode PDm is The output terminal (cathode) of the photodiode PDm is electrically connected to the wiring VANL. The second terminal of transistor F9 is electrically connected to the second terminal of transistor F9. At this time, the constant voltage given by the wiring VANL is a low level potential, a ground potential, a negative potential For this reason, when light is irradiated onto the photodiode PDm, A current flows from the output terminal of PDm to the wiring VANL via the input terminal.

[0436] The current input from the wiring XCL[i] to the cell array CA in the circuit SCA of FIG. 19A One of the modes is, for example, a mode in which transistor F9 is turned off. By turning off the transistor F9, the current generated in the photodiode PDm Therefore, the current flowing from the wiring XCL[i] to the cell array CA The current to be measured is determined based on the reference data generated by the circuit XCS or based on the second data. It is possible.

[0437] Also, for example, from the wiring XCL[i] in the circuit SCA of FIG. 19A to the cell array CA One of the current input modes is to turn on transistor F9. By turning on the transistor F9, the line XCL[i] is connected to the cell array C The current through A is calculated by dividing the desired current generated by the circuit XCS by the photodiode PD It can be the difference current between the current generated at m and

[0438] Incidentally, the circuit configuration of the arithmetic circuit MAC4 is as follows: The input terminals and output terminals of the circuit may be interchanged. SPR[i] is the voltage applied from the input terminal of photodiode PDm to the second terminal of transistor F9. The output terminal of the photodiode PDm is electrically connected to the wiring VANL. At this time, the constant voltage given by the wiring VANL is a high level. Therefore, when light is irradiated onto the photodiode PDm, Current flows from the output terminal of the photodiode PDm to the input terminal. When light is irradiated onto Dm, light is transmitted from the wiring VANL through the output terminal of the photodiode PDm. As a result, current flows through the input terminal.

[0439] The current input from the wiring XCL[i] to the cell array CA in the circuit SCA of FIG. 19B One of the modes is, for example, a mode in which the transistor F9 is turned off. By operating in this mode, the transistor F9 in the circuit SCA of FIG. 19A is turned off. Similarly, the current generated in the photodiode PDm does not flow to the wiring XCL[i]. The current flowing from the wiring XCL[i] to the cell array CA is then transferred to the circuit XCS. Therefore, the current can be determined according to the generated reference data or second data.

[0440] Also, for example, from the wiring XCL[i] in the circuit SCA in FIG. 19B to the cell array CA One of the modes of inputting current is, for example, the mode that turns on transistor F9. By operating in this mode, transistor F9 is turned on. The current flowing from the wiring XCL[i] to the cell array CA is generated by the circuit XCS. The desired current generated by the photodiode PDm can be calculated as the sum of the current generated by the photodiode PDm and the current generated by the photodiode PDm. can.

[0441] At this time, the amount of current flowing from the circuit XCS to the wire XCL[i] is set to 0, that is, , by preventing the supply of current from the circuit XCS to the wiring SCL[i], The current flowing from CL[i] to the cell array CA is the current generated in the photodiode PDm. It can be only.

[0442] As described above, by configuring the arithmetic circuit MAC4 of FIG. 18, the wiring XCL[1 ] or wiring XCL[m] to the cell array CA. The current corresponding to the reference data or the second data described in the first embodiment is set depending on the situation. It can be determined.

[0443] For example, the reference data or the second data is input to the cell array CA of the arithmetic circuit MAC4. When the current generated by the sensor SNC is not used, the circuits SPR[1] to SPR[2] are used. The transistor F9 included in each of the circuits SPR[m] is turned off, and the circuit XC S generates a current according to the reference data or the second data, and supplies the current to the wiring XC Just run it through L[1] to wiring XCL[m].

[0444] Also, for example, reference data or second data is input to the cell array CA of the arithmetic circuit MAC4. When using the current generated by the sensor SNC, the circuit SPR[1] The transistor F9 included in each of the circuits SPR[m] is turned on, and the sensor The current generated by the SNC can be passed through the wirings XCL[1] to XCL[m]. In some cases, the current flows from the circuit XCS to the wiring XCL[1] to the wiring XCL[m]. The amount of current that flows may be a desired amount or may be zero.

[0445] In particular, when the operation example of the timing chart of FIG. 6 is performed by the arithmetic circuit MAC4, for example, Between time T13 and time T14, and between time T17 and time T19, the circuit S The transistor F9 included in the circuits PR[1] to SPR[m] is turned off, and the circuit If a current corresponding to the reference data is sent from the circuit XCS to the wiring XCL[1] to the wiring XCL[m], Also, for example, between time T22 and time T23, the line XC The amount of current flowing through the wirings L[1] to XCL[m] is set to 0, and the amount of current flowing through the circuits SPR[1] to SP The transistor F9 included in R[m] is turned on, and the voltage generated by the sensor SNC is The current thus obtained can be passed through the wirings XCL[1] to XCL[m].

[0446] Also, for example, reference data or second data is input to the cell array CA of the arithmetic circuit MAC4. When the input is applied, the current generated by the circuit XCS and the voltage generated by the sensor SNC are The current and the sum of the current (or the difference current) are used as the reference data or second data. The signal may be passed through the wirings L[1] to XCL[m]. 19B, when the photodiode PDm is included, the circuit SCA The current flowing through the wirings XCL[1] to XCL[m] is generated by the photodiode PDm. At this time, correction data for the captured data is The data is generated as a current flowing from the circuit XCS to the wiring XCL[1] to the wiring XCL[m]. As a result, the wirings XCL[1] to XCL[m] are connected to the cell array of the arithmetic circuit MAC4. A current corresponding to the corrected image data can be applied to the CA. For example, color correction that adds intensity to a specific color can be used.

[0447] [Example of circuit LGC configuration] Next, a specific example of the circuit configuration of the circuit LGC will be described. When one of the lines LXS[m] is a bus line that transmits a digital signal, The data DT (reference data and the second data) to be input is input as a digital signal. By treating the data DT as a digital signal, the circuit LGC is a logic circuit. It can be configured as a path.

[0448] When the circuit LGC is configured as a logic circuit, the circuit LGC may be configured as shown in FIG. 20A as an example. The circuit LGC shown in FIG. 20A includes a shift register SR and Latch circuits LTA[1] to LTA[m] and latch circuits LTB[1] to LTB[m] The switch circuit LTB[m] includes switches SW[1] to SW[m].

[0449] The shift register SR includes a line SPL, a line SCL, and lines SEL[1] to SE L[m] and is electrically connected to

[0450] The control terminals (clock The SEL[1] wiring (sometimes called an input terminal, enable signal input terminal, etc.) to wiring SEL[m] are electrically connected, and the latch circuits LTB[1] to LT The wiring LAT is electrically connected to each control terminal of B[m]. The input terminals D of the circuits LTA[1] to LTA[m] are connected to the wiring DAT. The outputs of the latch circuits LTA[1] to LTA[m] are electrically connected to each other. The input terminal Q is electrically connected to each of the wirings DL[1] to DL[m]. The input terminals D of the latch circuits LTB[1] to LTB[m] are connected to the wiring D L[1] to L[m] are electrically connected to the wirings DL[m] to DL[m]. Each output terminal Q of the circuit LTB[m] is connected to a switch SW[1] through a switch SW[m]. The switches SW[1] to SW The second terminals of the wirings LXS[1] to LXS[m] are connected to the wirings LXS[1] to LXS[m], respectively. The control terminals of the switches SW[1] to SW[m] are electrically connected to each other. The wirings SWL[1] to SWL[m] are electrically connected to each of the wirings SWL[1] to SWL[m].

[0451] The switches SW[1] to SW[m] may be, for example, analog switches, An electrical switch such as a transistor can be applied. Also, the switch SW[1] For example, a mechanical switch may be used as the switch SW[m]. When transistors are applied to the switches SW[1] to SW[m], the transistors The transistors can be OS transistors or Si transistors.

[0452] In addition, each of the switches SW[1] to SW[m] shown in FIG. 20A is controlled by When a high-level voltage is input to the terminal, the device is turned on. When a low-level voltage is input to the control terminal, the device is turned on. When input is made, it is in the OFF state.

[0453] The wirings SWL[1] to SWL[m] are, for example, the switches SW[1] to SW[m]. It functions as a wiring for switching the switch SW[m] between a conductive state and a non-conductive state.

[0454] The wiring SPL is, for example, a wiring that transmits a start pulse signal to the shift register SR. It functions as:

[0455] The line SCL is, for example, a line that transmits a clock signal to the shift register SR. It functions as:

[0456] In addition, the wiring DAT functions as a wiring for transmitting data DT to the circuit LGC, for example. do.

[0457] Wiring SEL[1] to wiring SEL[m], wiring DL[1] to wiring DL[m], and wiring Each of the lines DAT can be a wiring for transmitting a digital signal. Lines SEL[1] to SEL[m], lines DL[1] to DL[m], and lines D Each of the ATs can be made into a bus wiring. Also, the wiring SWL can be made into a bus wiring. This can be done.

[0458] The shift register SR, for example, converts potentials input to the wirings SPL and SCL. In accordance with the change, a high-level potential is sequentially output to the wirings SEL[1] to SEL[m]. The shift register SR has the following functions: A high-level potential cannot be output to two or more of the wirings SEL[1] to SEL When any one of the wirings SEL[1] to SE[m] outputs a high-level potential, The remaining wiring of L[m] outputs a low-level potential.

[0459] For example, when a high level potential is input to the wiring SPL as a start pulse signal, The potential rises from a low level to a high level due to the clock signal from the wiring SCL. When the line SEL[1] is turned on, a high-level potential is outputted to the line SEL[1]. When the clock signal from the SCL line is input, the potential again becomes low level. When the potential rises from low to high, the wiring SEL[1] outputs low level potential, and the wiring The line SEL[2] outputs a high level potential. Then, the line SPL outputs a low level potential. When the clock signal from the wiring SCL is input, for example, When a rise occurs, the wiring SEL[1] and wiring SEL[2] output a low level potential. The wiring SEL[3] outputs a high-level potential.

[0460] In this way, every time the potential of the clock signal from the wiring SCL rises, The soft register SR sequentially supplies a high level voltage to one of the lines SEL[1] to SEL[m]. A high level potential can be output to the wiring, and a low level potential can be output to the other wirings.

[0461] Latch circuits LTA[1] to LTA[m] and latch circuits LTB[1] to Each of the latch circuits LTB[m] is turned on when a high-level potential is input to the control terminal. When the data is input to the input terminal D, it is enabled and the data is held. The latch circuit LTA[1] and the latch circuit LTA[2] have the function of outputting the data to the output terminal Q. The latch circuit LTA[m] and the latch circuit LTB[1] to the latch circuit LTB[m] are For example, when a low-level potential is input to the control terminal, the device is disabled. The data input to the input terminal D is not held, and the data is not output to the output terminal Q.

[0462] An example of the operation of the circuit LGC will now be described.

[0463] FIG. 21A is a timing chart showing an example of the operation of the circuit LGC. The chart shows the wiring SPL, wiring SCL, wiring SEL[1], wiring SEL[2], wiring SEL [m-1], wiring SEL[m], wirings SWL[1] to SWL[m], and wiring LA The potential change at T is shown, and the wiring DAT, wiring LXS[1], wiring LXS[2], The data input to the wiring LXS[m-1] and wiring LXS[m] is shown. Oh, wiring SPL, wiring SCL, wiring SEL[1], wiring SEL[2], wiring SEL[m- 1], the high-level potential in the wiring SEL[m], wiring SWL, and wiring LAT A high level potential is described as "High," and a low level potential is described as "Low."

[0464] The timing chart of FIG. 21A shows the period from time T31 to time T40 and the period around that time. At the same time, the circuit LGC supplies the wiring LXS[1] to the wiring LXS[m] with At the same time, the data DT is output. For example, in FIG. It is assumed that this is performed between time T21 and time T23 in the timing chart.

[0465] Furthermore, at a time before time T31, a low level potential is input to the wiring LAT, and A low-level potential is input to each of the lines SWL[1] to SWL[m]. In addition, the shift register SR is configured such that each of the wirings SEL[1] to SEL[m] It is assumed that a low level potential is output to the

[0466] Between time T31 and time T32, a start pulse signal is input to the wiring SPL. A high-level potential is input to the line SCL. A pulse voltage The shift register SR receives the rising edge of the clock signal pulse voltage. By this, a high-level potential, which is the start pulse signal input to the wiring SPL, is obtained. .

[0467] Between time T32 and time T33, data DT[1] is input to the line DAT. In addition, a second pulse voltage is input to the wiring SCL as a clock signal. The shift register SR receives the rising edge of the second pulse voltage of the clock signal. By this, a high-level potential is output to the wiring SEL[1].

[0468] At this time, the latch circuit LTA[1] is enabled, so the signal input to the input terminal D The data DT[1] stored in the register is held and output to the output terminal Q. DT[1] is input to the input terminal D of the latch circuit LTB[1]. Since a low-level potential is input to the control terminal of the latch circuit LTB[1], the latch circuit L TB[1] holds the data DT[1] input to the input terminal D of the latch circuit LTB[1]. The latch circuit LTB[1] outputs the data DT[1] input to its output terminal Q. do not.

[0469] Between time T33 and time T34, data DT[2] is input to the line DAT. Also, a third pulse voltage is input to the wiring SCL as a clock signal. The shift register SR starts when the rising edge of the third pulse voltage of the clock signal is input. By this, a low level potential is output to the wiring SEL[1] and a high level potential is output to the wiring SEL[2]. Output.

[0470] At this time, the latch circuit LTA[1] is disabled, so the latch circuit LTA The data DT[2] input to the input terminal D of the latch circuit [1] is not held. A[1] continues to hold data DT[1] from before time T33, and the output terminal Q Output data DT[1] from

[0471] In addition, the latch circuit LTA[2] is enabled, so the signal input to input terminal D is The data DT[2] is held and output to the output terminal Q. [2] is input to the input terminal D of the latch circuit LTB[2]. Since a low-level potential is input to the control terminal of the circuit LTB[2], the latch circuit LTB [2] holds the data DT[2] input to the input terminal D of the latch circuit LTB[2]. and does not output the data DT[2] input to the output terminal Q of the latch circuit LTB[2]. stomach.

[0472] Between time T34 and time T35, data DT[3] to DT[m -2] are input sequentially, and the shift register SR is used to input the wiring SEL[3] to wiring SEL[4]. A high level potential is sequentially input to SEL[m-2]. This causes the latch LTA[3 ] to latch circuit LTA[m-2], respectively. 2] is held. In addition, each of the latches LTA[3] to LTA[m-2] The data DT[3] to DT[m-2] are output from the output terminal Q.

[0473] Between time T35 and time T36, the data DT[m-1] Also, the mth pulse voltage is input to the wiring SCL as a clock signal. The shift register SR receives the rising edge of the mth pulse voltage of the clock signal. By this, a low level potential is output to the wiring SEL[m-2] and a low level potential is output to the wiring SEL[m-1]. Outputs a high level potential.

[0474] At this time, the latch circuit LTA[m-2] is disabled, so the latch circuit L The data DT[m-1] input to the input terminal D of TA[m-2] is not held. The latch circuit LTA[m-2] continues to hold the data DT[m-2] from before time T35. The output terminal Q outputs data DT[m-2].

[0475] In addition, the latch circuit LTA[m-1] is enabled, so the signal input to the input terminal D The data DT[m-1] stored in the buffer is output to the output terminal Q. The data DT[m-1] is input to the input terminal D of the latch circuit LTB[m-1]. At this time, a low level potential is input to the control terminal of the latch circuit LTB[m-1]. Therefore, the latch circuit LTB[m-1] receives the signal input to the input terminal D of the latch circuit LTB[m-1]. The input data DT[m-1] is not held, and the output terminal of the latch circuit LTB[m-1] The data DT[m-1] input to Q is not output.

[0476] Between time T36 and time T37, data DT[m] is input to the line DAT. Also, the (m+1)th pulse voltage is input to the wiring SCL as a clock signal. The shift register SR is set to the rising edge of the (m+1)th pulse voltage of the clock signal. When this signal is input, a low-level potential is output to the wiring SEL[m-1], and a low-level potential is output to the wiring SEL[m]. Outputs a high level potential.

[0477] At this time, the latch circuit LTA[m-1] is disabled, so the latch circuit L The data DT[m] input to the input terminal D of TA[m-1] is not held. The circuit LTA[m-1] continues to hold the data DT[m-1] from before time 36. and outputs data DT[m-1] from output terminal Q.

[0478] In addition, the latch circuit LTA[m] is enabled, so the signal input to the input terminal D The data DT[m] is held and output to the output terminal Q. [m] is input to the input terminal D of the latch circuit LTB[m]. Since a low-level potential is input to the control terminal of the circuit LTB[m], the latch circuit LTB [m] holds the data DT[m] input to the input terminal D of the latch circuit LTB[m]. and does not output the data DT[m] input to the output terminal Q of the latch circuit LTB[m]. stomach.

[0479] Between time T38 and time T39, a high level potential is input to the wiring LAT. As a result, the control of each of the latch circuits LTB[1] to LTB[m] Since a high-level potential is input to the terminal, the latch circuits LTB[1] to LTB[ m] are enabled. The switching circuit LTB[m] receives the data DT[1] to DT[m] input to each input terminal D. data DT[m], and outputs data DT[1] to data DT[m] from each output terminal Q. Outputs [m].

[0480] Between time T39 and time T40, the wirings SWL[1] to SWL[m] As a result, a high level potential is input to the switches SW[1] to SW[m ] is turned on, and each of the latch circuits LTB[1] to LTB[m] The output terminal Q and the wirings LXS[1] to LXS[m] are in a conductive state. The circuit LGC receives data DT[1 ] to data DT[m] can be output simultaneously.

[0481] The circuit LGC performs the operation of the timing chart shown in FIG. 21A. The data DT[1] to DT[m] input sequentially to the LGC are simultaneously parallelized. The signals can be output to the wirings LXS[1] to LXS[m]. Between time T21 and time T23 in the timing chart of FIG. 6, the arithmetic circuit MA A desired current can be simultaneously supplied to the wirings XCL[1] to XCL[m] of C4. do.

[0482] In the timing chart of FIG. 21A, the circuit LGC is connected to the wiring LXS[1] to the wiring LXS[2]. Although an example of outputting data DT simultaneously to each of the lines LXS[m] has been shown, the circuit LGC outputs data DT sequentially to each of the wirings LXS[1] to LXS[m]. In the timing chart of FIG. 21B, the circuit LGC is connected to the wirings LXS[1] to LXS[2]. This shows an example of the operation of sequentially outputting data DT to each of XS[m]. 21A. The operation before time T39 in the timing chart of FIG. 21B is The operation example from before time T31 to time T39 in the timing chart was performed. It shall be.

[0483] The timing chart of FIG. 21B shows the wiring SWL[1], the wiring SWL[2], and the wiring SWL[3]. WL[m-1] and the potential change in the wiring SWL[m], and the wiring LXS[1 ], wiring LXS[2], wiring LXS[m-1], and wiring LXS[m] The data shown is for wiring SWL[1], wiring SWL[2], wiring SWL[m-1 ] and wiring SWL[m], high level potential is written as High, and low level The potential is described as Low.

[0484] Between time T39 and time T40, a high-level potential is input to the wiring SWL[1]. This turns on the switch SW[1] and the latch circuit LTB[1] Since the output terminal Q and the wiring LXS[1] are in a conductive state, the wiring LXS[1] is The data DT[1] output from the output terminal Q of the switch circuit LTB is transmitted.

[0485] Between time T40 and time T41, a low-level potential is input to the wiring SWL[1]. A high level potential is input to the wiring SWL[2]. Switch SW[1] is turned off, and switch SW[2] is turned on. Latch circuit LTB[1] Since there is no conduction between the output terminal Q and the wiring LXS[1], The data DT[1] output from the output terminal Q of the latch circuit LTB is not transmitted. Since the output terminal Q of the switch circuit LTB[2] and the wiring LXS[2] are in a conductive state, The data DT[2] output from the output terminal Q of the latch circuit LTB is sent to the line LXS[2]. will be done.

[0486] Between time T41 and time T42, the wirings SWL[3] to SWL[m-2] A high-level potential is sequentially input to each of the switches SW[3] to SW [m-2] are sequentially turned on. As a result, the latch circuits LTB[3] to [m-2] are sequentially turned on. The data DT[3] to data DT[m-2] are output to the output terminals Q of the LTB[m-2]. DT[m-2] are output sequentially from the wiring LXS[3] to the wiring LXS[m-2], respectively. can be.

[0487] Between time T42 and time T43, the wiring SWL[m-2] is at a low level potential. is input, and a high-level potential is input to the wiring SWL[m-1]. The latch SW[m-2] is turned off and the switch SW[m-1] is turned on. Since the output terminal Q of the circuit LTB[m-2] and the wiring LXS[m-2] are in a non-conductive state, Therefore, the data DT[ m-2] is not transmitted. Also, the output terminal Q of the latch circuit LTB[m-1] and the wiring LXS Since the line LXS[m-1] is in a conductive state, the output of the latch circuit LTB is connected to the line LXS[m-1]. The data DT[m-1] output from the output terminal Q is transmitted.

[0488] Between time T43 and time T44, the wiring SWL[m-1] is at a low level potential. is input, and a high-level potential is input to the wiring SWL[m]. W[m-1] is turned off and the switch SW[m] is turned on. Since there is no conduction between the output terminal Q of B[m-1] and the wiring LXS[m-1], LXS[m-1] is the data DT[m-1] output from the output terminal Q of the latch circuit LTB is not transmitted. Also, between the output terminal Q of the latch circuit LTB[m] and the wiring LXS[m] Since the signal is in a conductive state, the signal output from the output terminal Q of the latch circuit LTB is sent to the wiring LXS[m]. The resulting data DT[m] is transmitted.

[0489] The circuit LGC operates until time T39 in the timing chart shown in FIG. 21A. After that, the operation of the timing chart shown in FIG. 21B is performed, and the circuit LGC The data DT[1] to DT[m] sequentially input to the wiring LXS[1] to the wiring LXS[m]. The signals can be output sequentially to the line LXS[m].

[0490] In the operation example of the timing chart shown in FIG. 21B, the switches SWL[1] to The switches SWL[m] are sequentially turned on to output data DT[1] to data D An example in which T[m] is output sequentially to the wiring LXS[1] to wiring LXS[m] has been shown. Select the switch to be turned on from switch SWL[1] to switch SWL[m] and wire As an operation of outputting data DT to a wiring selected from LXS[1] to wiring LXS[m] Good too.

[0491] According to the above-described operation example, for example, from time T13 to time T Between time T17 and time T19, the wiring of the arithmetic circuit MAC A desired current can be supplied to any one of the wirings XCL[1] to XCL[m].

[0492] 18 included in the semiconductor device of one embodiment of the present invention, the circuit LGC shown in FIG. The circuit configuration of the circuit LGC in FIG. 20A is changed depending on the situation. For example, the circuit LGC in FIG. 20A may be configured by using the switches SW[1] to SW[3] shown in FIG. Each of the switches SW[m] and each of the wirings LXS[1] to LXS[m] A buffer circuit may be provided between the two. The switches SW[1] to SW[m] and the wirings LXS[1] to LXS Buffer circuits BF[1] to BF[m] are provided between the respective As shown in FIG. 20B, the circuit LGC includes buffer circuits BF[1] to BF[2]. By providing the buffer circuit BF[m], the wiring LXS[1] to the wiring The electrical signal (potential) output to LXS[m] can be stabilized.

[0493] By using the arithmetic circuit MAC4 shown in FIG. 18, the reference data or the second data The current generated by the circuit XCS and / or the current generated by the sensor SNC as a function of A current can be input to the cell array CA.

[0494] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0495] (Fourth embodiment) In this embodiment, a hierarchical neural network will be described. The calculation of the neural network is performed by using the semiconductor device described in the above embodiment. This can be done by:

[0496] <Hierarchical neural network> A hierarchical neural network, for example, has one input layer and one or more intermediate layers. It consists of a total of three or more layers, including a hidden layer and an output layer. The hierarchical neural network 100 shown in Figure 2A is an example of such a network. The network 100 includes layers 1 through R (where R can be an integer greater than or equal to 4). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the remaining layers correspond to the The outer layers correspond to intermediate layers. In FIG. 22A, the (k-1)th layer, the kth layer, and the (where k is an integer between 3 and R-1) is shown, and the other intermediate layers are In some cases, illustration is omitted.

[0497] Each layer of the neural network 100 has one or more neurons. In the first layer, the neuron N1 (1) Neuron N p (1) (where p is 1 or more. The (k-1)th layer has neurons N1 (k-1) Neuron N m (k-1) (where m is an integer greater than or equal to 1), and the kth layer has neurons N1 (k ) Neuron N n (k) (where n is an integer equal to or greater than 1), and the Rth layer is Ron N1 (R) Neuron N q (R) (where q is an integer greater than or equal to 1) do.

[0498] In addition, in Figure 22A, neuron N1 (1) , neuron N p (1) , neuron N1 (k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , neuron N1 (R) , neuron N q (R) In addition, the (k-1)th layer neurons N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j ( k) (where j is an integer between 1 and n) are also shown, and other neurons are omitted from the illustration.

[0499] Next, the transmission of signals from the neurons in the previous layer to the neurons in the next layer, and the In this explanation, we will explain the signals input and output in the k-th layer of the neural network. N j (k) Focus on.

[0500] Figure 22B shows the k-th layer neuron N j (k) and neuron N j (k) is entered into Signal and neuron N j (k) 10 shows the signal output from the

[0501] Specifically, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1 ) The output signal z1 (k-1) ~z m (k-1) But neuron N j ( k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k) is used as the output signal The output is directed to each neuron in the layer (not shown).

[0502] The signals input from the neurons in the previous layer to the neurons in the next layer are transmitted between those neurons. The degree of signal transmission is determined by the strength of the synapse (hereafter referred to as the weighting coefficient) that connects the In the neural network 100, the signal output from the previous layer neuron is The signal is multiplied by the corresponding weighting coefficient and input to the neuron in the next layer. As an integer below, the (k-1)th layer neuron N i (k-1) and the k-th layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the k-th layer Ron N j (k) The signal input to can be expressed by equation (4.1).

[0503]

number

[0504] That is, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) of From each, the k-th layer neuron N j (k) When a signal is transmitted to the (k-1) ~z m (k-1) The weighting coefficients (w1 (k-1 ) j (k) Or even w m (k-1) j (k) ) is multiplied by the k-th layer neuron N j (k) has w1 (k-1) j (k) z1 (k-1) Or even w m (k-1) j (k) · z m (k-1) is input. At this time, the k-th layer neuron N j (k) The signal input to The sum of the numbers j (k) is expressed as equation (4.2).

[0505]

number

[0506] Also, the weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) and neurons signal z1 (k-1) ~z m (k-1) The result of the sum of products of and is biased. When the bias is b, equation (4.2) can be rewritten as .

[0507]

number

[0508] Neuron N j (k) u j (k) Depending on j (k) Generates And neuron N j (k) Output signal z from j (k) is defined as follows:

[0509]

number

[0510] The function f(u j (k) ) is the activation function in a hierarchical neural network , step function, linear ramp function, sigmoid function, etc. The activation function may be the same for all neurons or may be different. Therefore, the activation functions of neurons in each layer may be the same or different.

[0511] By the way, the signal output by the neuron in each layer, the weight coefficient w, or the bias b is The value may be an analog value or a digital value. For example, the digital value may be a binary value. It may be a ternary value, or a value with an even larger number of bits. For analog values, the activation function can be, for example, a linear ramp function, a sigmoid function, etc. In the case of binary digital values, for example, a step function that outputs -1 or 1 can be used. Alternatively, a step function whose output is 0 or 1 can be used. The signals output by neurons in each layer may be three-valued or more. In this case, the activation function is a three-valued For example, a step function with output -1, 0, or 1, or 0, 1, or 2. A step function or the like can be used. For example, an activation function that outputs five values ​​can be A step function of 2, -1, 0, 1, or 2 may be used. For at least one of the output signal, weighting coefficient w, or bias b, By using digital values, it is possible to reduce the circuit size, reduce power consumption, and Or, it can increase the calculation speed. Also, the output of the neurons in each layer For at least one of the signal, weighting coefficient w, or bias b, an analog value By using the above formula, the accuracy of the calculation can be improved.

[0512] The neural network 100 receives an input signal at the first layer (input layer). Therefore, in each layer from the first layer (input layer) to the last layer (output layer), the input from the previous layer is sequentially Based on the input signal, equation (4.1), equation (4.2) (or equation (4.3)), equation (4.4) The output signal is generated using the sigma-based algorithm, and the output signal is output to the next layer. The signal output from the input layer is converted into the result calculated by the neural network 100. Equivalent.

[0513] When the arithmetic circuit MAC1 described in the first embodiment is applied as the hidden layer, the weight Coefficient w s[k-1] (k-1) s[k] (k) (s[k-1] is an integer between 1 and m. , s[k] is an integer between 1 and n) is used as first data, and a current according to the first data is The amount is stored in each cell IM of the same column, and the neuron N in the (k-1)th layer s[k-1] (k-1) Output signal z from s[k-1] (k-1) as the second data, The conversion circuit ITRZ The amount of current I input to S The sum of the products of the first data and the second data can be calculated from Then, by using the sum of products to calculate the value of the activation function, the value of the activation function is made reliable. The number of neurons in the kth layer is N s[k] (k) The output signal z s[k] (k) To be able to can.

[0514] In addition, when the arithmetic circuit MAC1 described in the first embodiment is applied as the output layer described above, , weighting factor ws[R-1] (R-1) s[R] (R) (s[R-1] is an integer greater than or equal to 1. , s[R] is an integer between 1 and q) is used as first data, and a current according to the first data is The amount is stored in each cell IM of the same column, and the neuron N in the (R-1) layer s[R-1] (R-1) Output signal z from s[R-1] (R-1) as the second data, The conversion circuit ITRZ The amount of current I input to S From this, the sum of products of the first data and the second data can be calculated. In addition, the value of the activation function is calculated using the sum of products. The signal is sent to the Rth layer neuron N s[R] (R) The output signal z s[R] (R) To do so can be done.

[0515] The input layer described in this embodiment is a buffer circuit that outputs the input signal to the second layer. It may also function as

[0516] Furthermore, the conversion circuit ITRZD[j] described in the second embodiment is converted into the conversion circuit ITRZD[j] shown in FIG. When the arithmetic circuit MAC2 with the weight coefficient w s[k- 1] (k-1) s[k] (k) is used as the first data, and the current amount according to the first data is calculated in the same column. The cells IM and IMr of each circuit CES are memorized sequentially, and the neurons in the (k-1)th layer are N s[k-1] (k-1) Output signal z from s[k-1] (k-1)as the second data The amount of current corresponding to the second data is passed from the circuit XCS to the wiring XCL of each row. The current I input to the conversion circuit ITRZD4 S , and I Sr From the first data and the second data In other words, the value of the activation function can be calculated based on the sum of the products of the k layers of neurons, N s[k] (k) The output signal z s[k] (k) It can be said that In addition, the conversion circuit ITRZD4 is configured to output a current amount corresponding to the value, For example, a neuron N in the kth layer is input to multiple neurons in the (k+1)th layer. s[k ] (k) The output signal z s[k] (k) can be a current. That is, the (k+1 When the arithmetic circuit MAC2 is applied as a hidden layer of the arithmetic circuit MAC2, the wiring XCL of the arithmetic circuit MAC2 is The k-th layer neuron N s[k] (k) The output signal z s[k] (k) is the circuit X It is not generated by CS, but is output from the conversion circuit ITRZD4 of the calculation circuit MAC2 of the hidden layer of the kth layer. The current can be calculated as:

[0517] Specifically, by using the arithmetic circuit shown in FIG. 23, the above-mentioned hierarchical neural The calculation circuit of FIG. 23 can perform the calculation of the loop network shown in FIG. The arithmetic circuit MAC2-1 has the same configuration as the arithmetic circuit MAC2, and the arithmetic circuit MAC2 in FIG. and an arithmetic circuit MAC2-2 that does not include the circuit XCS. The cell array CA of MAC2-1 has m×n circuits CES arranged in a matrix. The cell array CA of the arithmetic circuit MAC2-2 has n×t (t is an integer of 1 or more) circuits. The wiring OL[1 of the arithmetic circuit MAC2-1 is arranged in a matrix. ] to wiring OL[n] correspond to wirings XCL[1] to XCL[n] of the arithmetic circuit MAC2-2, respectively. It is electrically connected to XCL[n].

[0518] For example, in the arithmetic circuit MAC2-1 in Figure 23, the neurons in the (k-1)th layer and the neurons in the kth layer The weight coefficient between the neurons is used as the first data, and the circuit CES[1,1] of the cell array CA is or circuit CES[m,n], and neuron N in the (k-1)th layer s[k-1] (k- 1) Output signal z from s[k-1] (k-1) is used as the second data, and By supplying the current amount from the circuit XCS to the wiring XCL of each row, the wiring OL[1] to the wiring From each of OL[n], the k-th layer neuron N1 (k) Neuron N n (k) The force signal z1 (k) ~z n (k) The output signal z1 (k) No Toz n (k) The values ​​of the conversion circuits ITRZD4[1] to ITRZD4 It can be expressed as the amount of current output from [n].

[0519] Here, in the arithmetic circuit MAC2-2 in FIG. 23, the neurons in the kth layer and the neurons in the (k+1)th layer are The weight coefficient between the neurons is used as the first data, and the circuit CES[1,1] of the cell array CA is or the amount of current flowing through the wiring XCL of each row, i.e., the kth layer Neuron N1 (k) Neuron N n (k) Output signal z1 (k) ~z n (k) By using this as the second data, the wiring OL[s[k+1]] (where s[k+1] is 1 or more) t) to the (k+1)th layer neuron N s[k+1] (k+1) Output of signal z s[k+1] (k+1) can be output.

[0520] As explained in the second embodiment, the conversion circuit of the arithmetic circuit MAC2-1 in FIG. The conversion circuits ITRZD4[1] to ITRZD4[n] are shown in FIGS. 9, 10A, 11A to 11C. By applying any one of the conversion circuits ITRZD4 shown in FIG. 11D, the conversion circuit ITRZD4 The transform circuits ITRZD4[n] operate as ReLU functions. For example, if the result of the multiplication and accumulation operation in the circuits CES[1,j] to CES[m,j] is “negative”, At a certain time, the amount of current flowing from the conversion circuit ITRZD4 to the wiring OL[j] is ideally 0. However, in reality, a small amount of current flows from the conversion circuit ITRZD4 to the wiring OL[j]. A small current flows, or a small current flows from wiring OL[j] to the conversion circuit ITRZD4. There are cases where this happens.

[0521] Therefore, it is necessary to calculate the next layer of the hierarchical neural network appropriately. An example of the configuration of the circuit MAC2-2 is shown in FIG. 24. The arithmetic circuit MAC2-2 shown in FIG. In the arithmetic circuit MAC2, the circuit CES arranged in the cell array CA is defined as an m×n matrix. The structure is changed from a trix to an n × t matrix, and the circuit XCS is not provided. In addition, the circuit CES of the cell array CA of the arithmetic circuit MAC2-2 is a matrix of n×t. Since the wiring and circuits are arranged in a risk-like manner, The values ​​in brackets such as [ ] have also been changed.

[0522] Furthermore, in the arithmetic circuit MAC2-2 of FIG. 24, as an example, Line TM[1], wiring TM[n], wiring TH[1,h] (h is an integer between 1 and t) , a circuit configuration provided with wiring TH[n,h], wiring THr[1,h], and wiring THr[n,h] In the arithmetic circuit MAC2-2 of FIG. The back gate of the transistor F2m is electrically connected to the wiring TM[1], and the cell IMre The wiring TM[n] is electrically connected to the back gate of the transistor F2m of f[n], The back gate of transistor F2 in cell IM[1,h] is electrically connected to wiring TH[1,h]. The back gate of the transistor F2r of the cell IMr[1,h] is connected to the wiring THr [1,h] is electrically connected to the back gate of transistor F2 of cell IM[n,h] The wiring TH[n,h] is electrically connected to the transistor F2 of the cell IMr[n,h]. The back gate of r is electrically connected to a wiring THr[n,h].

[0523] Wiring TM[1], wiring TM[n], wiring TH[1,h], wiring TH[n,h], wiring T By applying a low level potential to each of the wirings Hr[1,h] and THr[n,h], , the threshold voltage of a transistor having a back gate electrically connected to each wiring. This increases the value voltage of the current that flows through the wiring OL of the arithmetic circuit MAC2-1. A small amount of current flows through the wiring VE via the cell IMref of the arithmetic circuit MAC2-2. That is, the conversion circuits ITRZD4[1] to ITRZD4[2] can be prevented from The output characteristics in [n] can be made closer to the ReLU function. The calculations for the next layer of the neural network can be performed appropriately.

[0524] 23. For example, the configuration of the arithmetic circuit MAC2-2 in FIG. 24 may be changed to that of the arithmetic circuit MAC2- 1. By using such a configuration, the same as the arithmetic circuit MAC2-2 The transistors F2 and F2r included in the arithmetic circuit MAC2-1 are The respective threshold voltages of the transistors F2m and F2m can also be varied.

[0525] In FIG. 24, the wiring TM[1], the wiring TM[n], the wiring TH[1,h], the wiring TH [n,h], wiring THr[1,h], and wiring THr[n,h] are shown, but in FIG. The arithmetic circuit MAC2-2 is, for example, a wiring TM[1], a wiring TH[1,h], and a wiring THr[ 1,h] as one wiring, and wiring TM[n] and wiring TH[n,h] are connected THr[n,h] may be combined into one wiring.

[0526] As mentioned above, the calculation of the hierarchical neural network is performed by constructing the calculation circuit shown in FIG. By creating this, the value of the neuron output signal (amount of current) output by the arithmetic circuit MAC2-1 is ) can be input directly to the arithmetic circuit MAC2-2, so that a hierarchical neural network For example, the calculation of the network can be performed continuously from the first layer. The output signals output from the wirings OL[1] to OL[n] of the circuit MAC2-1 are connected to the external circuit. Since there is no need to temporarily store the data by a route, etc., there is no need to provide a separate storage device for temporary storage. In other words, by configuring the arithmetic circuit of FIG. 23, the circuit area can be reduced. This also reduces the power required for transmitting data for temporary storage.

[0527] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0528] (Embodiment 5) In this embodiment, the configuration example of the semiconductor device described in the above embodiment and the above embodiment will be described. A structural example of a transistor that can be applied to the semiconductor device described in the embodiment will be described.

[0529] <Configuration example of semiconductor device> FIG. 25 shows an example of the arithmetic circuit MAC4 described in the third embodiment, in which the sensor S This shows a configuration in which a photoelectric conversion element is applied as a photodiode to the NC. Specifically, The semiconductor device shown in FIG. 25 includes a transistor 300, a transistor 500, and a capacitor element 6 27A shows the channel of the transistor 500. 27A is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 27B is a cross-sectional view of the transistor 500 in the channel width direction. 27C is a cross-sectional view of the transistor 300 in the channel width direction.

[0530] The transistor 500 is a transistor having a metal oxide in a channel formation region (OS transistor). The transistor 500 has a small off-state current and a low field effect even at high temperatures. The transistor 500 has a characteristic that the resultant mobility does not change. The arithmetic circuit MAC1, arithmetic circuit MAC1A, arithmetic circuit MAC2, and arithmetic circuit MAC1A described in the embodiment By applying this to the transistors included in the circuit MAC3 and the arithmetic circuit MAC4, In particular, it is possible to realize a semiconductor device in which the operating capability does not decrease even at high temperatures. The transistor 500 is applied to the transistors F1 and F1m. This allows the potential written to cells IM and IMref to be maintained for a long time. Cut.

[0531] The transistor 500 is provided, for example, above the transistor 300, and the capacitance element 60 0 is provided above the transistor 300 and the transistor 500, for example. The photoelectric conversion element 700 is provided, for example, above the capacitance element 600. The child 600 includes the arithmetic circuit MAC1, the arithmetic circuit MAC1A, and the arithmetic circuit MAC2A described in the above embodiment. The capacitance may be included in the circuit MAC2, the arithmetic circuit MAC3, etc. Depending on the configuration, the capacitor element 600 shown in FIG. 25 may not necessarily be provided.

[0532] The transistor 300 is disposed on a substrate 311, and includes a conductor 316, an insulator 315, and a substrate a semiconductor region 313 formed of a part of the semiconductor region 311; The transistor 300 has a resistive region 314a and a low resistive region 314b. For example, the arithmetic circuit MAC1, the arithmetic circuit MAC1A, and the arithmetic circuit MA This can be applied to transistors included in the C2, arithmetic circuit MAC3, etc. Specifically, for example, the conversion circuits ITRZ1 to ITRZ3 in FIGS. 4A to 4C have The transistors can be included in the operational amplifier OP1. In this case, the gate of the transistor 300 is connected to the transistor 300 through one of the pair of electrodes of the capacitor 600. 1 shows a configuration in which the transistor 500 is electrically connected to either the source or the drain. However, the arithmetic circuits MAC1, MAC1A, MAC2, MAC3, etc. Depending on the configuration, one of the source and drain of the transistor 300 may be connected to the capacitor 60. 0, one of the source or drain of the transistor 500 is electrically connected to the The source or drain of the transistor 300 may be electrically connected. One of the pair of electrodes of the capacitor 600 is connected to the gate of the transistor 500. The transistor 300 may be electrically connected to the transistor 301. The terminals of the transistor 500 and the capacitor element 600 are not electrically connected to each other. It may also be composed.

[0533] The substrate 311 is a semiconductor substrate (for example, a single crystal substrate or a silicon substrate). It is preferable that

[0534] The transistor 300 is formed by forming a semiconductor region 313 on the upper surface thereof and a channel region thereof as shown in FIG. 27C. The side surfaces in the width direction are covered with the conductor 316 via the insulator 315. By making the resistor 300 a fin type, the effective channel width is increased, and This can improve the on-characteristics of the transistor 300. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300. .

[0535] The transistor 300 may be either a p-channel type or an n-channel type. .

[0536] The region where the channel of the semiconductor region 313 is formed, the region nearby, the source region, or the drain region In the low resistance region 314a and the low resistance region 314b, which are to be the drain region, silicon It is preferable that the material contains a semiconductor such as a silicon-based semiconductor, and it is preferable that the material contains single crystal silicon. are Ge (germanium), SiGe (silicon germanium), and GaAs (gallium arsenide). Nitride), GaAlAs (Gallium Aluminum Arsenide), GaN (Gallium Nitride), etc. The effective mass can be increased by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, a structure using silicon with controlled conductivity may be used. This allows the transistor 300 to be a HEMT (High Electron Mobilit y Transistor).

[0537] The low resistance region 314a and the low resistance region 314b are semiconductor regions applied to the semiconductor region 313. In addition to the material, elements that give n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. It contains an element that provides electrical conductivity.

[0538] The conductor 316, which functions as a gate electrode, is made of arsenic, phosphorus, or the like, which provides n-type conductivity. Semiconductor materials such as silicon that contain elements or elements that give them p-type conductivity, such as boron Conductive materials such as aluminum, metal, alloy, or metal oxide materials can be used.

[0539] Since the work function is determined by the material of the conductor, it is necessary to select the material of the conductor. Specifically, the conductor is made of nitride silicon, and the threshold voltage of the transistor can be adjusted. It is preferable to use materials such as tantalum or tantalum nitride. To achieve this, metal materials such as tungsten and aluminum are used as layers for the conductor. It is preferable to use tungsten, in particular, in terms of heat resistance.

[0540] The transistor 300 shown in FIG. 25 is an example, and the structure is not limited to this. An appropriate transistor may be used depending on the structure, driving method, etc. In the case of a unipolar circuit using only S transistors, as shown in FIG. The structure of the transistor 500 may be the same as that of the transistor 500 including an oxide semiconductor. The transistor 500 will be described in detail later.

[0541] Over the transistor 300 are insulators 320, 322, 324, and The bodies 326 are stacked one on top of the other.

[0542] The insulators 320, 322, 324, and 326 may be, for example, oxide. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxide Aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0543] In this specification, silicon oxynitride refers to a material having a higher content of oxygen than nitrogen in its composition. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen. In this specification, aluminum oxynitride refers to a material with a high content. Aluminum oxide nitride is a material that has a higher oxygen content than nitrogen. It refers to a material that contains more nitrogen than oxygen as a constituent.

[0544] The insulator 322 serves to eliminate a step caused by the transistor 300 and other components disposed below it. For example, the top surface of the insulator 322 may have a function as a planarizing film. To improve flatness, the surface is flattened by a planarization process using chemical mechanical polishing (CMP) or other methods. It may be possible.

[0545] The insulator 324 is also provided with a substrate 311 or a transistor 300, etc. A film having a barrier property to prevent hydrogen, impurities, etc. from diffusing into the area where the heater 500 is provided. It is preferable to use

[0546] An example of a film having a barrier property against hydrogen is silicon nitride formed by CVD. Here, a semiconductor having an oxide semiconductor such as the transistor 500 can be used. The diffusion of hydrogen into semiconductor elements can cause a deterioration in the characteristics of the semiconductor elements. Therefore, a film that suppresses hydrogen diffusion is provided between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film that reduces the amount of hydrogen desorption. The membrane is thin.

[0547] The amount of hydrogen desorption can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorption from the insulator 324 can be determined by TDS analysis as follows: In the range of 50°C to 500°C, the amount of desorption converted to hydrogen atoms is Converted to a hit, it's 10 x 10 15 atoms / cm 2 Less than or equal to 5 x 10 15 a toms / cm2 The following is fine.

[0548] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, The dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the insulator 326 is preferably 0.7 times or less than the relative dielectric constant of the insulator 324, and more preferably 0.6 times or less. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. can be reduced.

[0549] The insulators 320, 322, 324, and 326 are connected to the capacitance element 6. 00, or the conductor 328 and the conductor 330 connected to the transistor 500 are embedded. The conductor 328 and the conductor 330 function as plugs or wiring. In addition, the conductors that function as plugs or wiring are grouped together to form the same structure. In addition, in this specification and the like, a wiring and a plug connected to the wiring may be In other words, when a part of the conductor functions as a wiring, In some cases, a portion of the conductor functions as a plug.

[0550] The materials for each plug and wiring (conductor 328, conductor 330, etc.) include metal materials, alloys, and the like. Conductive materials such as gold, metal nitride, or metal oxide materials are used in a single layer or laminated layers. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, can be used. It is preferable to use a material such as tungsten, or aluminum. It is preferable to form the wiring layer 11 from a low-resistance conductive material such as copper. This can reduce the wiring resistance.

[0551] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring that connects to the transistor 300. The conductor 356 is made of the same material as the conductors 328 and 330. It can be done.

[0552] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 350 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0553] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the overall conductivity. In this case, the tantalum nitride layer having a barrier property against hydrogen is It is preferable that the insulating body 350 has a structure in which the insulating body 350 is in contact with the insulating body 350.

[0554] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. An insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed on the insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0555] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 360 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0556] Moreover, a wiring layer (not shown) may be provided on the insulator 364 and the conductor 366.

[0557] The wiring layer including the conductor 356 and the wiring layer including the conductor 366 have been described above. However, the semiconductor device according to this embodiment is not limited to this. The number of wiring layers similar to the wiring layer including the conductor 356 may be one or less. Alternatively, a wiring layer similar to the wiring layer including the conductor 366 may be provided. Two or more layers may be used.

[0558] On the insulator 364, an insulator 510, an insulator 512, an insulator 514, and an insulator 516 are formed. , are stacked in this order. It is preferable that any of the bodies 516 uses a material that has a barrier property against oxygen, hydrogen, etc. It's nice.

[0559] For example, the insulator 510 and the insulator 514 may include, for example, the substrate 311 or the transistor. The area where the transistor 300 is provided is converted into the area where the transistor 500 is provided by introducing hydrogen, impurities, etc. It is preferable to use a film that has a barrier property that prevents the diffusion of the insulator 3. The same materials as those in 24 can be used.

[0560] As an example of a film with barrier properties against hydrogen, silicon nitride formed by CVD is used. Here, a semiconductor element including an oxide semiconductor, such as the transistor 500, However, the diffusion of hydrogen may deteriorate the characteristics of the semiconductor element. A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen. do.

[0561] In addition, as a film having a barrier property against hydrogen, for example, an insulator 510 and an insulator 5 14 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable.

[0562] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. Therefore, it has a high blocking effect that prevents impurities such as acid and moisture from passing through the membrane. Aluminum oxide is a material that can absorb impurities such as hydrogen and moisture during and after the transistor manufacturing process. This can prevent impurities from being mixed into the transistor 500. Therefore, the release of oxygen from the oxide constituting the transistor 5 can be suppressed. Suitable for use as a protective film against 00.

[0563] For example, the insulators 512 and 516 may be made of the same material as the insulator 320. In addition, by using materials with a relatively low dielectric constant for these insulators, , the parasitic capacitance occurring between the wirings can be reduced. As the film 516, a silicon oxide film, a silicon oxynitride film, or the like can be used.

[0564] In addition, the insulators 510, 512, 514, and 516 are provided with conductors 5 18, and conductors (for example, conductor 503) that constitute the transistor 500 are embedded. Note that the conductor 518 is connected to the capacitor 600 or the transistor 300. The conductor 518 functions as a plug or a wiring. It can be provided using the same material as 30.

[0565] In particular, the insulator 510 and the conductor 518 in the area in contact with the insulator 514 are free of oxygen, hydrogen, It is preferable that the conductive material has a barrier property against water. The transistor 300 and the transistor 500 have barrier properties against oxygen, hydrogen, and water. The layer can be separated, and hydrogen diffusion from transistor 300 to transistor 500 can be suppressed.

[0566] Above the insulator 516 is the transistor 500 .

[0567] As shown in FIGS. 27A and 27B, the transistor 500 includes an insulator 514 and an insulator 516. The conductor 503 is disposed so as to be embedded in the insulator 516, and the insulator 516 and the conductor 50 3, an insulator 520 disposed on the insulator 520, and an insulator 522 disposed on the insulator 520. An insulator 524 is disposed on the insulator 522, and an oxide 53 is disposed on the insulator 524. 530a, oxide 530b disposed on oxide 530a, and oxide 530b disposed on oxide 530b. Conductor 542a and conductor 542b are spaced apart, and conductor 542a and conductor 54 2b, and an opening is formed between the conductors 542a and 542b. The edge 580, the oxide 530c disposed on the bottom and side surfaces of the opening, and the shape of the oxide 530c an insulator 550 disposed on the forming surface; and a conductor 560 disposed on the forming surface of the insulator 550; In this specification and the like, the conductor 542a and the conductor 542b are collectively referred to as the conductor It is written as body 542.

[0568] As shown in FIGS. 27A and 27B, the oxide 530a, the oxide 530b, the conductive The insulator 544 is disposed between the conductor 542a and the insulator 580, and the conductor 542b. As shown in FIGS. 27A and 27B, the conductor 560 is preferably made of an insulator 560. 50, and a conductor 560a provided inside the conductor 560a. 27A and 27B. As shown, an insulator 574 is disposed over an insulator 580, a conductor 560, and an insulator 550. It is preferable that the

[0569] In the following, the oxide 530a, the oxide 530b, and the oxide 530c will be collectively referred to as oxides 530a, 530b, and 530c. It is sometimes called oxide 530.

[0570] In the transistor 500, an oxide is formed in the region where the channel is formed and in the vicinity thereof. 5 shows a structure in which three layers of oxide 530a, oxide 530b, and oxide 530c are stacked. However, one embodiment of the present invention is not limited thereto. a two-layer structure of oxide 530b and oxide 530a; a two-layer structure of oxide 530b and oxide 530c The transistor 500 may have a layer structure or a stacked structure of four or more layers. Although the conductor 560 has a two-layer structure in the example, one embodiment of the present invention is not limited to this. For example, the conductor 560 may have a single layer structure or a laminate of three or more layers. The transistor 50 shown in FIGS. 25, 27A, and 27B may have a layer structure. 0 is an example, and is not limited to this structure. A register can be used.

[0571] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and The conductor 542b functions as a source electrode and a drain electrode, respectively. The conductor 560 is sandwiched between the opening of the insulator 580 and the conductors 542a and 542b. The conductor 560, the conductor 542a, and the conductor 542b are formed so as to be embedded in the region. The placement of 42b is selected to be self-aligned with the opening of the insulator 580. In the transistor 500, the gate electrode is self-aligned between the source electrode and the drain electrode. Therefore, the conductor 560 can be positioned with a margin for alignment. Since the transistor 500 can be formed without any additional wiring, the area occupied by the transistor 500 can be reduced. This allows for miniaturization and high integration of semiconductor devices.

[0572] Furthermore, the conductor 560 is self-aligned in the region between the conductors 542a and 542b. Since the conductor 560 is formed, the conductor 560 has an overlapping region with the conductor 542a or the conductor 542b. As a result, the conductive material 560 is not formed between the conductive material 542a and the conductive material 542b. Therefore, the switching speed of the transistor 500 can be improved. This improves the sound quality and provides high frequency characteristics.

[0573] The conductor 560 may function as a first gate (also called a top gate) electrode. The conductor 503 also functions as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor 503 may be different from the potential applied to the conductor 560. The threshold voltage of the transistor 500 is controlled by changing them independently without linking them together. In particular, applying a negative potential to the conductor 503 can turn on the transistor 5 By increasing the threshold voltage of 00, it is possible to reduce the off-current. Applying a negative potential to the conductor 503 reduces the potential applied to the conductor 560 compared to not applying a negative potential. This can reduce the drain current when the applied potential is 0V.

[0574] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, The electric field and the electric field generated by the conductor 503 are connected, and a channel is formed in the oxide 530. In this specification and the like, the first gate electrode and the second gate electrode can cover the region where the first gate electrode and the second gate electrode are formed. The structure of a transistor in which the electric field of the gate electrode electrically surrounds the channel formation region is called This is called a surrounded channel (S-channel) structure.

[0575] The conductor 503 has the same structure as the conductor 518, and the insulators 514 and 5 Conductor 503a is formed in contact with the inner wall of opening 16, and conductor 503b is formed further inside. In the transistor 500, the conductor 503a and the conductor 503b are stacked. Although a layered structure is shown, one embodiment of the present invention is not limited to this. For example, the conductor 503 may be provided as a single layer or a laminated structure of three or more layers.

[0576] Here, the conductor 503a is a diffusion layer for impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has the function of suppressing the impurities (i.e., the impurities are less likely to permeate). Or, the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) It is preferable to use a conductive material that has the above-mentioned function (which is difficult for oxygen to permeate). In the specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of the impurities or oxygen. The function is to suppress the diffusion of any one or all of the above.

[0577] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503 This can prevent b from being oxidized and the electrical conductivity from decreasing.

[0578] When the conductor 503 also functions as a wiring, the conductor 503b is made of tungsten, copper, or the like. It is preferable to use a conductive material having high conductivity, such as aluminum or aluminum-based material. In addition, if the conductivity of the wiring can be maintained high, the conductor 503a is not necessarily provided. Although the conductor 503b is illustrated as a single layer, it may have a multilayer structure. It may also be a laminate of titanium or titanium nitride and the above conductive material.

[0579] The insulators 520, 522, and 524 function as a second gate insulating film. It has.

[0580] Here, the insulator 524 in contact with the oxide 530 has more oxygen than the stoichiometric composition. It is preferable to use an insulator that contains a large amount of oxygen. That is, the insulator 524 has an excess oxygen region. It is preferable that the insulator containing such excess oxygen is formed in the oxide 530. By providing the oxide 530 in contact with the oxide 530, oxygen vacancies in the oxide 530 are reduced, and the signal quality of the transistor 500 is improved. The reliability can be improved.

[0581] As an insulator having an excess oxygen region, specifically, an oxide in which a part of oxygen is released by heating is used. It is preferable to use oxide materials. Oxides that release oxygen when heated are called TDS (Th Thermal Desorption Spectroscopy (DSS) analysis revealed that the oxygen atoms The converted amount of oxygen desorption is 1.0 x 10 18 atoms / cm 3 Above 1.0, preferably 1.0 x10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / c m 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is 100°C or higher and 700°C or lower. The temperature range is preferably from 0°C to 400°C.

[0582] In addition, the insulator having the excess oxygen region and the oxide 530 are brought into contact with each other and subjected to heat treatment. One or more of microwave treatment and RF treatment may be performed. By performing this, water or hydrogen in the oxide 530 can be removed. At 530, a reaction occurs in which the VoH bond is broken, in other words, "V O H→V O + The reaction "H" occurs, and some of the hydrogen generated at this time is It combines with oxygen to form H2O, which is then removed from the oxide 530 or the insulators adjacent to the oxide 530. In addition, some of the hydrogen may diffuse into the conductor 542a and the conductor 542b. The electrons may be trapped or captured (also called gettered).

[0583] The microwave treatment may be carried out using, for example, an apparatus having a power source that generates high-density plasma. Alternatively, it is preferable to use a device having a power source that applies RF to the substrate side. By using a gas containing oxygen and high density plasma, high density oxygen radicals are generated. By applying RF to the substrate side, the high density plasma generated Oxygen radicals are efficiently introduced into the oxide 530 or into the insulator near the oxide 530. The microwave treatment can be carried out at a pressure of 133 Pa or more, preferably 200 The pressure may be 400 Pa or more, more preferably 400 Pa or more. The gases introduced into the device are, for example, oxygen and argon, with an oxygen flow rate ratio (O / (O2+Ar)) is set to 50% or less, preferably 10% or more and 30% or less.

[0584] In addition, during the m...

Claims

[Claim 1] The arithmetic circuit has a cell array, the cell array includes a first cell and a second cell; the first cell has a function of holding a potential corresponding to a current amount according to first data, The second cell is a semiconductor device having a function of supplying a potential corresponding to second data required for performing a product-sum operation with the potential held in the first cell.

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