Signal receiver, ic, and electrical equipment

Abstract

To confirm that a signal processing function is capable of operating normally.SOLUTION: A signal receiver (100) is configured to have: a processing circuit (10) configured to output a processing signal (SS2) subjected to predetermined processing on received signals (AIN, TEST); a function block (20) configured to receive the processing signal (SS2) and execute processing determined based on the processing signal (SS2); and a self-checking circuit (30) configured to output an inspection signal (TEST) to the processing circuit (10) and perform quality determination based on a signal (SS2) output from the processing circuit (10).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a signal receiving device, and to an IC and an electrical device that include the signal receiving device. [Background technology]

[0002] BACKGROUND ART Conventionally, a signal transmission device that transmits a signal is configured to include a filter for masking noise components contained in the signal (see Patent Document 1, etc.).

[0003] Some devices are also configured to process the received signal and output it to the outside. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2023-52304

[0005] [overview] In the above-mentioned devices, there is an increasing demand to confirm that the signal processing function is in normal operation.

[0006] A signal receiving device according to one aspect of the present disclosure is configured to have a processing circuit configured to output a processed signal that has undergone predetermined processing on a received signal, a functional block configured to receive the processed signal and perform predetermined processing based on the processed signal, and a self-test circuit configured to output a test signal to the processing circuit and determine whether the signal is good or bad based on the test processed signal output from the processing circuit. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing the configuration of a signal receiving device. [Figure 2] FIG. 2 is a diagram showing the state of a signal in a Schmitt trigger circuit. [Figure 3]FIG. 3 is a diagram showing the state of the signal receiving device when the inspection process is performed. [Figure 4] FIG. 4 is a flowchart showing the inspection process. [Figure 5] FIG. 5 is a diagram showing the state of each signal when the filter circuit is in a good state. [Figure 6] FIG. 6 is a diagram showing the state of each signal when the filter circuit is in a faulty state. [Figure 7] FIG. 7 is a diagram showing the state of a signal when it is determined that the signal receiving device is in a malfunctioning state. [Figure 8] FIG. 8 is a diagram showing the state of a signal receiving device according to a modified example. [Figure 9] FIG. 9 is a diagram illustrating an example of a configuration of an electrical device including a signal receiving device.

[0008] [Detailed explanation] An embodiment of the present disclosure will be described below with reference to the drawings.

[0009] <Signal Receiving Device 100> FIG. 1 is a block diagram showing the configuration of a signal receiving device 100. The signal receiving device 100 shown in FIG. 1 is a device that receives an input signal AIN, performs processing in accordance with the input signal AIN, and outputs the processing as an external output signal DOUT. In the signal receiving device 100, for example, the input signal AIN is an analog signal, and the external output signal DOUT is a digital signal. As shown in FIG. 1, the signal receiving device 100 has a processing circuit 10, a functional block 20, and a self-test circuit 30. Note that the signal receiving device 100 may be configured as a single functional integrated circuit (IC), or may be configured as a combination of multiple functional ICs. Furthermore, the signal receiving device 100 may be configured to be incorporated as part of an IC configured to perform multiple functions.

[0010] 1, the processing circuit 10 receives an input signal AIN and generates a processed signal SS2. The processing circuit 10 includes a first diode 11, a second diode 12, a Schmitt trigger circuit 13, a switching circuit 14, and a filter circuit 15.

[0011] The first diode 11 and the second diode 12 are connected in series. More specifically, the anode of the first diode 11 and the cathode of the second diode 12 are connected at a connection point P1. The cathode of the first diode 11 is connected to a power supply terminal to which a power supply voltage VDD is applied. The anode of the second diode 12 is connected to a ground terminal to which a ground voltage VGD is applied.

[0012] An input line L1 is connected to a connection point P1 between the anode of the first diode 11 and the cathode of the second diode 12. An input signal AIN is input to the connection point P1 via the input line L1. The first diode 11 and the second diode 12 form a voltage clamp circuit. If the first diode 11 and the second diode 12 are diodes of the same configuration and have a forward voltage drop of V1, the voltage clamp circuit limits the voltage level of the input signal AIN to be equal to or greater than VGD+V1 and equal to or less than VDD+V1.

[0013] The Schmitt trigger circuit 13 has a first threshold value Th1 and a second threshold value Th2. The Schmitt trigger circuit 13 outputs a conversion signal SCV in accordance with the voltage level of the input signal AIN. The conversion signal SCV is a digital voltage signal that takes either a high level or a low level that is lower than the high level.

[0014] 2 is a diagram showing the state of signals in the Schmitt trigger circuit 13. As shown in Fig. 2, when the voltage level of the input signal AIN in the Schmitt trigger circuit 13 becomes larger than a first threshold value Th1, the conversion signal SCV in the Schmitt trigger circuit 13 switches from low level to high level. Also, when the voltage level of the input signal AIN in the Schmitt trigger circuit 13 becomes smaller than a second threshold value Th2 while the Schmitt trigger circuit 13 is outputting a high-level conversion signal SCV, the conversion signal SCV switches to low level.

[0015] By using the Schmitt trigger circuit 13, once the voltage level of the input signal AIN exceeds the first threshold value Th1, the conversion signal SCV continues to be output at a high level until it falls below the second threshold value Th2. Furthermore, even if the conversion signal SCV exceeds the second threshold value Th2 while outputting a low level, the conversion signal SCV does not switch to a high level until it exceeds the first threshold value Th1. The Schmitt trigger circuit 13 is configured to convert the analog input signal AIN into a digital conversion signal SCV. The Schmitt trigger circuit 13 can output a stable digital conversion signal SCV even if the voltage level of the input signal AIN fluctuates within a certain range.

[0016] In other words, once the Schmitt trigger circuit 13 outputs a high-level conversion signal SCV, it continues to output a high-level conversion signal SCV even if the voltage level of the input signal AIN falls below the first threshold Th1 as long as the voltage level of the input signal AIN is higher than the second threshold Th2. Also, when the Schmitt trigger circuit 13 is outputting a low-level conversion signal SCV, it continues to output a low-level conversion signal SCV even if the voltage level of the input signal AIN rises above the second threshold as long as the voltage level of the input signal AIN is lower than the first threshold Th1. By providing two thresholds, the Schmitt trigger circuit 13 can stably output the conversion signal SCV even if the input signal fluctuates.

[0017] The conversion signal SCV, which is the output of the Schmitt trigger circuit 13, is input to a switching circuit 14. The switching circuit 14 is a circuit that selects and outputs one of the input signals. An example of the switching circuit 14 is a multiplexer circuit.

[0018] The switching circuit 14 has three input terminals 141, 142, and 143 and one output terminal 144. The input terminal 141 is connected to the output of the Schmitt trigger circuit 13, and receives the conversion signal SCV. The input terminal 142 receives a test signal TEST (described later) output from the self-test circuit 30. The input terminal 143 receives a test execution signal BIST_EN (described later) output from the self-test circuit 30. The output terminal 144 outputs an internal signal SS1.

[0019] In the switching circuit 14, a signal input to the input terminal 141 or the input terminal 142 is output as an internal signal SS1 from the output terminal 144 based on a test execution signal BIST_EN input to the input terminal 143. The test execution signal BIST_EN is a signal that takes a high level, i.e., "1," or a low level, i.e., "0." When a low-level test execution signal BIST_EN is input to the input terminal 143, the switching circuit 14 selects the input terminal 141, and outputs the input conversion signal SCV as the internal signal SS1. When a high-level test execution signal BIST_EN is input to the input terminal 143, the switching circuit 14 selects the input terminal 142, and outputs the input test signal TEST as the internal signal SS1.

[0020] As shown in Figure 2, the input signal AIN may contain noise called glitch noise ANZ. Glitch noise ANZ is a pulse-like signal that occurs in a short period of time due to, for example, response delays caused by wiring length or variations in the reaction speed of elements. The glitch noise ANZ may be converted by the Schmitt trigger circuit 13 and output in pulse form. Pulse-like glitch noise GNZ is a signal that is not permitted by design and may cause malfunction of the functional block 20.

[0021] Therefore, the processing circuit 10 has a filter circuit 15 configured to remove the pulse-like glitch noise GNZ. The internal signal SS1 output from the switching circuit 14 is input to the filter circuit 15.

[0022] The pulse-like glitch noise GNZ has a short time t1 from rising to falling (hereinafter referred to as pulse width t1) (see FIG. 5). Therefore, the filter circuit 15 operates to remove pulse signals contained in the internal signal SS1 that have a pulse width of t1 or less as glitch noise GNZ. The pulse width t1 is a value determined based on the wiring pattern, circuit configuration, element configuration, etc. The pulse width t1 may be set in advance or may be configured to be changeable.

[0023] As described above, when the test execution signal BIST_EN is at a high level, the switching circuit 14 outputs the internal signal SS1 having the same wavelength as the test signal TEST from the output terminal 144. The internal signal SS1 output from the output terminal 144 is input to the filter circuit 15.

[0024] <Function Block 20> The functional block 20 is connected to the output terminal of the filter circuit 15 via a wiring Pr1. An internal signal SS1 input from the input terminal of the filter circuit 15 has pulse-like glitch noise GNZ removed by the filter circuit 15, and the signal is input as a processed signal SS2 to the functional block 20 via the wiring Pr1. The functional block 20 outputs an external output signal DOUT corresponding to the processed signal SS2 from the filter circuit 15. An example of the external output signal DOUT is a signal that controls the operation of an external device (not shown).

[0025] <Self-test circuit 30> The self-test circuit 30 is a circuit configured to check the operation of the filter circuit 15. The self-test circuit 30 is connected to the switching circuit 14, the wiring Pr1, and the functional block 20. The self-test circuit 30 supplies a test signal TEST to an input terminal 142 of the switching circuit 14. The self-test circuit 30 also supplies a test execution signal BIST_EN to an input terminal 143 of the switching circuit 14.

[0026] 5, the test signal TEST output from the self-test circuit 30 is a signal similar to the pulse-like glitch noise GNZ generated in the signal receiving device 100. If the glitch noise GNZ is a pulse signal that rises from a low level to a high level, the self-test circuit 30 supplies a pulse signal with a pulse width t1 as the test signal TEST to the input terminal 142 of the switching circuit 14.

[0027] The test execution signal BIST_EN is a signal that takes on two values, high level or low level. The self-test circuit 30 tests the filter circuit 15 at specific timing, which will be described in detail later. When the self-test circuit 30 is not testing the filter circuit 15, for example, in a normal state, the self-test circuit 30 supplies a low-level test execution signal BIST_EN to the input terminal 143 of the switching circuit 14. When the self-test circuit 30 tests the filter circuit 15, the self-test circuit 30 supplies a high-level test execution signal BIST_EN to the input terminal 143 of the switching circuit 14.

[0028] The self-test circuit 30 is connected to the wiring Pr1, and when testing the filter circuit 15, acquires the processed signal SS2, which is the output signal from the filter circuit 15. The self-test circuit 30 may be configured not to accept an input signal when testing the filter circuit 15 is not being performed, or may be configured to prevent a signal from being input using a switch element or the like.

[0029] The self-test circuit 30 determines whether the filter circuit 15 has reliably removed glitch noise in accordance with the input processed signal SS2. Details of the operation of the self-test circuit 30 will be described later. The self-test circuit 30 also outputs a test execution signal DONE, a pass / fail notification signal PASS, and a fail notification signal FAIL to an external device, such as a control circuit (not shown), that operates a system including the signal receiving device 100.

[0030] The inspection execution signal DONE, the pass / fail notification signal PASS, and the fail notification signal FAIL may be input to the functional block 20. The functional block 20 may be configured to receive the processing signal SS2 when the inspection execution signal DONE and the pass / fail notification signal PASS are received.

[0031] The signal receiving device 100 has the above-described configuration. Next, the operation of the signal receiving device 100 will be described with reference to the drawings.

[0032] <Operation of the signal receiving device 100> Fig. 3 is a diagram showing the state of the signal receiving device 100 when the inspection process is performed. Fig. 4 is a flowchart showing the inspection process. Fig. 5 is a diagram showing the state of each signal when the filter circuit 15 is in a good state. Fig. 6 is a diagram showing the state of each signal when the filter circuit 15 is in a bad state.

[0033] In the signal receiving device 100, while the input signal AIN is being input, the glitch noise GNZ, which is obtained by converting the glitch noise ANZ into a pulsed form, is removed by the filter circuit 15, and the processed signal SS2 is supplied to the function block 20. In the signal receiving device 100, it is desirable that the filter circuit 15 accurately remove the glitch noise GNZ while the input signal AIN is being input. Therefore, in the signal receiving device 100, the self-test circuit 30 tests the filter circuit 15, that is, checks its operation.

[0034] 3 and 4, when the signal receiving device 100 is started up from the startup standby state STM (step S101), it transitions to the test mode TSM (step S102). When power supply to the signal receiving device 100 starts, the self-test circuit 30 recognizes that the signal receiving device 100 has been started up.

[0035] When the signal receiving device 100 is started, the self-test circuit 30 outputs a test signal TEST and a test execution signal BIST_EN, which are signals for testing (step S103).

[0036] Furthermore, in the test mode TSM, the self-test circuit 30 supplies a high-level test execution signal BIST_EN to the input terminal 143 of the switching circuit 14. As a result, the input terminal 142 of the switching circuit 14 is selected, and the test signal TEST supplied from the self-test circuit 30 is output from the output terminal 144 as the internal signal SS1. In other words, the internal signal SS1 is input to the filter circuit 15. The filter circuit 15 is configured to remove the glitch noise GNZ when the glitch noise GNZ is included in the internal signal SS1.

[0037] As described above, the test signal TEST is a pulse signal that rises from low to high and has a pulse width t1. The filter circuit 15 is configured to remove glitch noise GNZ. The self-test circuit 30 supplies the test signal TEST, which has a voltage level and pulse width t1 equivalent to those of the expected glitch noise GNZ, to the input terminal 142 of the switching circuit 14.

[0038] Furthermore, in step S103, when the high-level test execution signal BIST_EN is output, the self-test circuit 30 outputs a high-level test execution signal DONE. The test execution signal DONE is supplied to an external device. The test execution signal DONE may be supplied to the functional block 20, and the functional block 20 may not accept the processing signal SS2 while the high-level test execution signal DONE is being input.

[0039] Then, the self-test circuit 30 acquires the processed signal SS2 from the filter circuit 15 and checks whether the filter circuit 15 can remove the glitch noise GNZ. Specifically, the self-test circuit 30 determines whether the acquired processed signal SS2 is at a high level (step S104). The filter circuit 15 has a configuration that can remove pulse signals with a pulse width of t1 or less. In other words, if the processed signal SS2 is at a high level, the self-test circuit 30 determines that the filter circuit 15 has not been able to remove the glitch noise GNZ.

[0040] In the signal receiving device 100, a delay may occur in the output signal relative to the input signal depending on the circuit and element configuration. Therefore, the self-test circuit 30 determines whether the time has reached time T2, which is a certain time t2 after time T1 when the supply of the high-level test execution signal BIST_EN started (step S105).

[0041] 5, the test execution signal BIST_EN switches from high to low at time T2. Similarly, the test execution signal DONE switches from high to low at time T2. That is, the self-test circuit 30 operates to end the test mode TSM at time T2.

[0042] 4, if the self-test circuit 30 determines in step S105 that time T2 has not been reached (NO in step S105), the process returns to step S104, where the self-test circuit 30 determines whether the processing signal SS2 goes high. Also, if the self-test circuit 30 determines in step S105 that time T2 has been reached (YES in step S105), the self-test circuit 30 determines that it has not received a high-level processing signal SS2.

[0043] Then, the self-test circuit 30 determines that the pulse-like portion of the test signal TEST has been removed by the filter circuit 15, and outputs a pass / fail notification signal PASS (step S106, see FIG. 5). The signal receiving device 100 also transitions from the test mode TSM to the normal operation state NMM (step S107, see FIG. 4). Note that the switch from the test mode TSM to the normal operation state NMM can be, for example, the timing when the test execution signal BIST_EN switches from high level to low level, that is, the timing when the pass / fail notification signal PASS is output.

[0044] 6, if the filter circuit 15 is defective, a high-level processing signal SS2 is output in response to the test signal TEST. That is, in the test mode TSM, if the self-test circuit 30 detects a high-level processing signal SS2, it determines that the filter circuit 15 is unable to remove the glitch noise GNZ. That is, if it determines in step S104 that the processing signal SS2 is high (Yes in step S104), the self-test circuit 30 determines that the operation of the filter circuit 15 is defective. Then, upon detecting a high-level processing signal SS2, the self-test circuit 30 outputs a high-level failure notification signal FAIL (step S108, see FIG. 6).

[0045] Then, since the filter circuit 15 cannot reliably remove the glitch noise GNZ, the self-test circuit 30 cannot accurately convert the input signal AIN into the external output signal DOUT. Therefore, the self-test circuit 30 transitions from the test mode TSM to the malfunction state DFM (step S109). The transition from the test mode TSM to the malfunction state DFM may be performed immediately after detecting that the processing signal SS2 is at a high level, or may be performed at the timing when the test execution signal BIST_EN switches from a high level to a low level.

[0046] Here, the malfunction state DFM will be explained. The malfunction state DFM differs depending on the external device to which the external output signal DOUT is output. For example, in the case of a signal input to an element that is switched ON or OFF by the external output signal DOUT and then maintains its initial state until a separate reset signal is received, even if glitch noise GNZ occurs, it does not affect operation. In such a configuration, the malfunction state DFM only outputs a high-level failure notification signal FAIL.

[0047] In such a malfunction state DFM, for example, a control circuit (not shown) including the signal receiving device 100 may notify a user by displaying on a display device (not shown) that the filter circuit 15 of the signal receiving device 100 is not operating normally. The control circuit (not shown) may also store in a storage unit (not shown) the device in which the abnormality occurred (here, the signal receiving device 100) in association with the time, details, etc.

[0048] On the other hand, if the configuration is such that an external device (not shown) malfunctions due to the external output signal DOUT containing glitch noise GNZ, the signal receiving device 100 may stop the operation of the functional block 20 as a malfunction state DFM and stop the output of the external output signal DOUT.

[0049] In this way, the signal receiving device 100 may be configured to execute the test mode TSM at startup to determine whether the filter circuit 15 operates normally and notify the result to the outside.

[0050] 5 and 6, in the signal receiving device 100 according to this embodiment, the test execution signal DONE is configured to be at a high level while the test execution signal BIST_EN is at a high level. However, this is not limited thereto, and it is sufficient to notify an external device that the test mode has been executed, and the test execution signal DONE may be at a high level for a period long enough for the external device to detect it.

[0051] 5 and 6, in this embodiment, the pass / fail notification signal PASS is a pulsed signal, but it may be configured to output a high-level signal for a certain period of time. Also, the pass / fail notification signal PASS is configured to be output when the test execution signal BIST_EN switches from high to low, but this is not limiting. For example, the self-test circuit 30 may determine whether the acquired processing signal SS2 is high within a certain period of time after transitioning to the test mode TSM, regardless of the test execution signal BIST_EN.

[0052] In the signal receiving device 100 configured as above, the filter circuit 15 is inspected immediately after startup, so that the input signal AIN can be accurately converted into the external output signal DOUT and output to the external device.

[0053] Fig. 7 is a diagram showing the state of a signal when it is determined to be in the malfunction state DFM in the signal receiving device 100. Fig. 7 shows the case where the test mode is in operation from time T11 to time T21.

[0054] As described above, during normal operation, the filter circuit 15 is configured to be able to remove pulse signals with a pulse width of up to t1. Assume that there is a malfunction in the filter circuit 15, and that the filter circuit 15 is able to remove pulse signals with a pulse width of t3 or less, which is narrower than the pulse width t1.

[0055] In the test mode TSM, the self-test circuit 30 supplies a test signal TEST with a pulse width t1 to the switching circuit 14. A processed signal SS2 with a pulse width t1 is input to the filter circuit 15. The filter circuit 15 removes the pulse-shaped signal with a pulse width t3. Therefore, as shown in FIG. 7, from the test signal TEST with a pulse width t1, only the component with a pulse width t3 is removed, and the remaining portion is output as the processed signal SS2.

[0056] When the self-test circuit 30 detects at time T12 that the processing signal SS2 is at a high level, it outputs a high-level failure notification signal FAIL.

[0057] In this way, in the signal receiving device 100, even if the filter circuit 15 is configured to be able to remove part of the glitch noise GNZ, if it is configured to be unable to remove the entire signal of the expected pulse width, it can be determined that a defect has occurred in the filter circuit 15.

[0058] The signal receiving device 100 described above can quickly detect the occurrence of a malfunction in the filter circuit 15. Furthermore, it is possible to prevent the external output signal DOUT containing the glitch noise GNZ from being supplied to an external device, thereby preventing the system including the signal receiving device 100 from becoming unstable.

[0059] In the present disclosure, the processing circuit 10 is configured to include a filter circuit 15 that removes glitch noise, but is not limited to this. For example, a wide variety of circuits that perform predetermined processing on input signals, such as a band-pass filter circuit that removes signals of a predetermined frequency, an amplifier circuit, etc., can be used.

[0060] <Modification> Fig. 8 is a diagram showing the state of a modified signal receiving device 100. As shown in Fig. 8, in the signal receiving device 100, when a state in which an input signal AIN is not input has elapsed for a certain period in the normal operation state NMM, the signal receiving device 100 transitions to a low power consumption state SPM in which the power supply is restricted. In the low power consumption state SPM, power is supplied to an extent that the device can be started up when the input signal AIN is input.

[0061] 8, when an input signal AIN is input to the signal receiving device 100 in the low power consumption state SPM, the signal receiving device 100 transitions to the test mode TSM. The operation of the test mode TSM is the same as that described above, and details will be omitted.

[0062] In an electronic circuit such as the signal receiving device 100, a large current is likely to flow immediately after the applied voltage is switched when the device is started up, when returning from the low power consumption state SPM, etc. Therefore, in the signal receiving device 100 of the first modified example, the test mode TSM is executed not only at the time of start-up as described above, but also during the time until the device returns from the low power consumption state SPM to the normal operating state NMM.

[0063] By doing so, the test mode TSM is performed more frequently, and the possibility of detecting a defect in the filter circuit 15 increases.

[0064] In the present disclosure, the self-test circuit 30 is configured to transition to the test mode upon startup or upon recovery from the low power consumption state SPM, but this is not limiting. For example, the self-test circuit 30 may be configured to execute the test mode upon termination of operation or upon transition to the low power consumption state SPM. Alternatively, the self-test circuit 30 may be configured to execute the test mode every time a certain period of time has elapsed.

[0065] <Use> 9 is a diagram showing an example of the configuration of an electric device 200 including the signal receiving device 100. The electric device 200 may be, for example, an industrial robot, a conveying device, or other device that is continuously operated and receives an external signal and transmits it to a control unit.

[0066] As shown in Fig. 9, the electric device 200 includes a signal receiving device 100, a sensor 300, a control device 400, and an actuator 500. In the electric device 200, the sensor 300 may be a detection element that detects the distance to an object within a target area. The sensor 300 measures the distance to the object within the target area. The sensor 300 is connected to an input terminal of the signal receiving device 100, and an input signal AIN is input from the sensor 300 to the signal receiving device 100. Note that the input signal AIN is an analog signal.

[0067] The signal receiving device 100 digitally converts the input signal AIN and supplies the external output signal DOUT, from which glitch noise has been removed by the filter circuit 15, to the control device 400. The control device 400 controls the electrical device 200, and is connected to the signal receiving device 100 and the actuator 500. The control device 400 outputs a drive signal MVS that drives the actuator 500 based on the external output signal DOUT received from the signal receiving device 100. The actuator 500 performs an operation determined by the drive signal MVS.

[0068] As described above, the signal receiving device 100 can suppress the output of glitch noise GNZ, thereby suppressing malfunction of the actuator 500. Note that, in this use example, the electrical device 200 in which the signal receiving device is used has been disclosed as having a configuration in which the actuator 500 is driven in accordance with information detected by the sensor 300, but is not limited to this. For example, the electrical device 200 in which the signal receiving device 100 is used can also be used as a device that transmits an external input signal to another device.

[0069] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is defined by the claims, not by the description of the above-described embodiments. Furthermore, it should be understood that all modifications within the meaning and scope of the claims are included.

[0070] <Additional Notes> The signal receiving device (100) described above includes a processing circuit (10) configured to perform predetermined processing on received signals (AIN, TEST) and output a processed signal (SS2); a functional block (20) configured to receive a processing signal (SS2) and execute a process determined based on the processing signal (SS2); This is a configuration (first configuration) that has a self-test circuit (30) that outputs a test signal (TEST) to the processing circuit (10) and determines whether the circuit is good or bad based on a signal (SS2) output from the processing circuit (10).

[0071] In the signal receiving device (100) of the first configuration, the processing circuit (10) has a configuration (second configuration) including a filter circuit (15) configured to remove noise (GNZ).

[0072] In the signal receiving device (100) of the second configuration, the filter circuit (15) has a configuration for removing glitch noise (GNZ) contained in the received signal, The self-test circuit (30) is configured (third configuration) to output a test signal (TEST) having a pulse width (t1) determined in accordance with the pulse width (t1) of the glitch noise (GNZ) that can be removed by the filter circuit (15).

[0073] In the signal receiving device (100) of any of the first to third configurations, a configuration (fourth configuration) is provided in which the self-test circuit (30) has a test mode (TSM) for performing a self-test by inputting a test signal (TEST) to the processing circuit (10).

[0074] In the signal receiving device (100) of the fourth configuration, the self-test circuit (30) is configured to execute the test mode (TSM) immediately after startup (fifth configuration).

[0075] In the signal receiving device (100) of the fourth or fifth configuration, the self-test circuit (30) is configured to transition to a low power consumption state (SPM) when a state in which no signal is input to the processing circuit (10) continues for a certain period of time; The self-test circuit (30) is configured (sixth configuration) to transition to the test mode (TSM) when returning from the low power consumption state (SPM).

[0076] In the signal receiving device (100) of any of the first to sixth configurations, when the self-test circuit (30) judges the signal receiving device (100) to be good, the device transitions to a normal operating state (NMM) in which a pass notification signal (PASS) is output, and when the self-test circuit (30) judges the signal receiving device to be bad, the device transitions to a faulty operating state (DFM) in which a fail notification signal (FAIL) is output to notify the device of a fault (7th configuration).

[0077] In the signal receiving device (100) of any of the first to seventh configurations, the processing circuit (10) is configured to receive an external signal (SCV) and a test signal (TEST) and to have a switching circuit (14) configured to select either the signal (SCV) or the test signal (TEST) (eighth configuration).

[0078] The IC described above has a configuration (ninth configuration) including a signal receiving device (100) having any one of the first to eighth configurations.

[0079] The electric device (200) described above has a configuration (tenth configuration) that uses the signal receiving device (100) having any of the first to eighth configurations. [Explanation of symbols]

[0080] 10 Processing circuit 11 First diode 12 Second diode 13 Schmitt trigger circuit 14 Switching circuit 15 Filter Circuit 20 Functional Blocks 30 Self-test circuit 100 Signal receiving device 141, 142, 143 Input terminals 144 output terminal 200 Electrical Equipment 300 sensors 400 control device 500 Actuator P1 connection point L1 input line VDD power supply voltage VGD Ground voltage AIN input signal ANZ Glitch Noise DOUT External output signal GNZ Glitch Noise BIST_EN Test execution signal TEST test signal MVS drive signal DONE Inspection execution signal PASS Good notification signal FAIL Failure notification signal Pr1 wiring SCV conversion signal STM startup standby state SPM low power consumption state NMM normal operating state DFM Malfunctioning Condition TSM Check Mode SS1, SS2 internal signals Th1 First threshold Th2 Second threshold t1 pulse width t2 fixed time t3 pulse width

Claims

1. a processing circuit configured to perform predetermined processing on a received signal and output a processed signal; a functional block configured to receive the processing signal and execute a process determined based on the processing signal; a self-test circuit configured to output a test signal to the processing circuit and to determine whether the signal is good or bad in accordance with the signal output from the processing circuit;

2. 2. The signal receiving device according to claim 1, wherein the processing circuitry comprises a filter circuit configured to remove noise.

3. the filter circuit has a configuration for removing glitch noise contained in the received signal; 3. The signal receiving device according to claim 2, wherein the self-test circuit is configured to output the test signal having a pulse width determined in accordance with the pulse width of the glitch noise that can be removed by the filter circuit.

4. 2. The signal receiving device according to claim 1, wherein the self-test circuit has a test mode for performing a self-test by inputting the test signal to the processing circuit.

5. 5. The signal receiving device according to claim 4, wherein the device is configured to transition to a normal operating state in which a good notification signal is output when the self-test circuit judges the signal to be good, and to transition to a faulty operating state in which a fault notification signal is output to notify the user that the signal is bad when the self-test circuit judges the signal to be bad.

6. 5. The signal receiving device according to claim 4, wherein the self-test circuit is configured to execute the test mode immediately after startup.

7. the self-test circuit is configured to transition to a low power consumption state when a state in which no signal is input to the processing circuit continues for a certain period of time; 5. The signal receiving device according to claim 4, wherein the self-test circuit is configured to transition to the test mode when returning from the low power consumption state.

8. 2. The signal receiving device according to claim 1, wherein the processing circuit is configured to receive an external signal and the inspection signal, and to have a switching circuit configured to select either the external signal or the inspection signal.

9. An IC including the signal receiving device according to any one of claims 1 to 8.

10. An electrical device configured using the signal receiving device according to any one of claims 1 to 8.

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