Semiconductor device

Abstract

To provide a miniaturized transistor, alternatively provide a transistor with low parasitic capacitance, alternatively provide a transistor with high frequency characteristics, alternatively provide a transistor with a large on-current, alternatively provide a semiconductor device having the transistor, alternatively provide a highly integrated semiconductor device, and alternatively provide a novel capacitance element.SOLUTION: A capacitive element includes a first conductor, a second conductor, and an insulator, and the first conductor and the second conductor have an overlapping region with the insulator interposed therebetween, the first conductor includes tungsten and silicon, and the insulator includes a silicon oxide film formed by oxidizing the first conductor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to, for example, a transistor and a semiconductor device, and a method for manufacturing the same. Alternatively, the present invention may be applied to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, The present invention relates to a processor, an electronic device, a display device, a liquid crystal display device, a light-emitting device, and a storage device. Also, the present invention relates to a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a manufacturing method thereof, and a semiconductor device. The present invention relates to a device, a storage device, and a method for driving an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. One aspect of the invention is a process, machine, manufacture, or composition of matter. It concerns the matter of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general, including display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices. The vessel may include a semiconductor device. [Background technology]

[0004] In recent years, transistors using oxide semiconductors have been attracting attention. Since it can be deposited using a deposition method, it can be used for the semiconductor manufacturing of transistors that make up large display devices. In addition, a transistor using an oxide semiconductor can be used as a conductor. It is possible to use some of the production equipment for transistors using silicon by modifying it. There is also the benefit of reducing capital investment.

[0005] Furthermore, a transistor including an oxide semiconductor has a very low leakage current in a non-conducting state. For example, the leakage current of a transistor using an oxide semiconductor is known to be small. A low-power CPU that utilizes the small size has been disclosed (see Patent Document 1). .).

[0006] In addition, a transistor using an oxide semiconductor is manufactured by burying a gate electrode in an opening. Methods for doing this have been disclosed (see Patent Documents 2 and 3). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-241407 [Patent Document 3] Japanese Patent Application Laid-Open No. 2014-240833 Summary of the Invention [Problem to be solved by the invention]

[0008] One of the objects is to provide a miniaturized transistor. Another object of the present invention is to provide a transistor with high frequency characteristics. Another object of the present invention is to provide a transistor having favorable electrical characteristics. Another object of the present invention is to provide a transistor with stable electrical characteristics. Another object is to provide a transistor with a large current when on. Another object is to provide a transistor with a small current when off. Another object is to provide a novel transistor. It is an object of the present invention to provide a semiconductor device having a high operating speed. Another object of the present invention is to provide a semiconductor device with high integration. Another object is to provide a novel semiconductor device. Another object of the present invention is to provide a module having the semiconductor device. An object of the present invention is to provide an electronic device having the module.

[0009] The description of these problems does not preclude the existence of other problems. The embodiment does not necessarily solve all of these problems. Problems other than these may be solved by the description. The above facts are self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other issues. [Means for solving the problem]

[0010] (1) One aspect of the present invention is a semiconductor device having a first conductor, a second conductor, and an insulator, The first conductor has an area where it overlaps with the second conductor via an insulator, and the first conductor is The insulator is formed by oxidizing the first conductor. The capacitor element is characterized by having a silicon oxide film.

[0011] (2) One aspect of the present invention is a method for manufacturing a semiconductor device using a first conductor having tungsten and silicon and a second conductor having a thickness of 100 μm. and an insulator in contact with the first conductor, the first conductor being in contact with the second conductor and the insulator. The second conductor and the insulator have an overlapping region with the insulator interposed therebetween, and the second conductor and the insulator have an area where they contact each other. The insulator is a silicon oxide film having a film thickness of 15 nm or less. It is an element.

[0012] (3) One embodiment of the present invention is a semiconductor device including a capacitor and a transistor. has a drain electrode, the capacitor has a first electrode and a second electrode, The first electrode and the drain electrode are electrically connected, and the capacitance element is the capacitor according to (1) or (2). The present invention is a semiconductor device characterized in that the capacitance element is

[0013] (4) In one aspect of the present invention, a module includes the capacitive element according to (1) or (2), and the capacitive element according to (3). The module is characterized by having the above semiconductor device and a printed circuit board.

[0014] (5) One aspect of the present invention is an electronic device comprising: a capacitor element according to (1) or (2); (4) A semiconductor device having a speaker or an operation key. The electronic device is characterized by the above.

[0015] (6) One aspect of the present invention is to form a first conductor, and then subject the first conductor to a plasma treatment including oxygen. By carrying out the above steps, a silicon oxide film is formed on the surface of the first conductor, and the first conductive film is formed on the silicon oxide film. and depositing two conductors, the first conductor comprising tungsten and silicon. This is a method for manufacturing a capacitor element.

[0016] (7) One aspect of the present invention is characterized in that the plasma treatment includes treatment using high-density plasma. The method for manufacturing a capacitor element according to (6) is as follows.

[0017] (8) One embodiment of the present invention is a method for manufacturing a semiconductor device, The transistor has a drain electrode, and the capacitor has a first electrode and a and a second electrode, the first electrode and the drain electrode of the capacitor being electrically connected to each other, The element is manufactured using the method for manufacturing a capacitor element according to either (6) or (7). The present invention relates to a method for manufacturing a semiconductor device, and

[0018] (9) One aspect of the present invention is a method for manufacturing a module, the module being (6) or (7) a capacitor element manufactured by using the manufacturing method of a capacitor element according to any one of (8) to (9), A semiconductor device manufactured by the method for manufacturing a semiconductor device and a printed circuit board are provided. The method for manufacturing a module is characterized by the above.

[0019] (10) One embodiment of the present invention is a method for manufacturing an electronic device, the electronic device comprising: A capacitor manufactured by using the manufacturing method of any one of the capacitors described above, and a semiconductor device according to (8). A semiconductor device manufactured using the semiconductor device manufacturing method, and a module manufacturing method according to (9). The module is characterized by having a speaker or an operation key. This is a method for manufacturing an electronic device.

[0020] (11) In one aspect of the present invention, a second insulator is formed on a first insulator, and a semiconductor is formed on the second insulator. a first conductive material is deposited on the semiconductor, and the first conductive material is deposited by a first lithography; A portion of the first conductor is etched away by the method, and the first conductor, the semiconductor, and the second insulating layer are removed. The first conductor, the semiconductor, and a portion of the second insulator are removed by a second lithography method. By etching, the first conductor is separated into the second conductor and the third conductor, and the second A multilayer film is formed from a conductor, a third conductor, a semiconductor, and a second insulator, and the second conductor The second conductor and the third conductor are subjected to a plasma treatment containing oxygen, The side surface, the top surface of the second conductor, the side surface of the third conductor and the top surface of the third conductor are coated with silicon oxide. A silicon oxide film is formed on the silicon oxide film, on the first insulator, on the side of the second insulator, and on the semiconductor. a third insulator is deposited so as to cover the side surface, and a fourth insulator is deposited on the third insulator; A fourth conductor is formed on the fourth insulator by a third lithography method. Then, a portion of the fourth conductor is etched, and the first conductor is made of tungsten and silicon. The present invention relates to a method for manufacturing a transistor, comprising:

[0021] (12) One aspect of the present invention is characterized in that the plasma treatment includes treatment using high-density plasma. The method for manufacturing a transistor according to (11) above is also provided.

[0022] (13) One embodiment of the present invention is a method for manufacturing a semiconductor device, 12) A transistor manufactured by the method for manufacturing a transistor according to any one of The present invention provides a method for manufacturing a semiconductor device, characterized in that:

[0023] (14) One embodiment of the present invention is a method for manufacturing a module, which comprises either (11) or (12). A transistor manufactured by the manufacturing method of a transistor according to any one of (1) to (13). A semiconductor device manufactured by the method for manufacturing a semiconductor device and a printed circuit board are provided. The method for manufacturing a module is characterized by the above.

[0024] (15) One embodiment of the present invention is a method for manufacturing an electronic device, the electronic device comprising: (11) or (12) a transistor manufactured by the method for manufacturing a transistor according to any one of (1) A semiconductor device manufactured by the method for manufacturing a semiconductor device according to (3), a semiconductor device according to (14), The module is manufactured using the manufacturing method of the module, and the speaker or operation keys are The present invention provides a method for manufacturing an electronic device, comprising:

[0025] Note that in the semiconductor device of one embodiment of the present invention, the oxide semiconductor may be replaced with another semiconductor. It's okay to do that. [Effects of the Invention]

[0026] It is possible to provide a fine transistor or a transistor with small parasitic capacitance. Alternatively, a transistor with high frequency characteristics can be provided. Alternatively, a transistor having good electrical characteristics can be provided. It is possible to provide a stable transistor with a large current when turned on. Alternatively, a transistor with a small current when turned off can be provided. Alternatively, a novel transistor can be provided. A semiconductor device having a resistor can be provided. Alternatively, a highly integrated semiconductor device can be provided. Alternatively, a novel semiconductor device can be provided. Alternatively, an electronic device having the semiconductor device or the module can be provided. Equipment can be provided.

[0027] The description of these effects does not preclude the existence of other effects. It is not necessary to have all of these effects. Effects other than these may be included in the specification, drawings, and claims. This is self-evident from the description of the claims, etc., and is based on the description of the specification, drawings, claims, etc. From this, it is possible to extract other effects. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 1 is a cross-sectional view of a capacitor according to one embodiment of the present invention. [Figure 2] 1A to 1C are cross-sectional views illustrating a method for manufacturing a capacitor according to one embodiment of the present invention. [Figure 3] 1A to 1C are cross-sectional views illustrating a method for manufacturing a capacitor according to one embodiment of the present invention. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 5] 1A and 1B are a top view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 7] 1A and 1B are diagrams illustrating structural analysis of a CAAC-OS and a single-crystal oxide semiconductor by XRD, and a selected-area electron diffraction pattern of a CAAC-OS. [Figure 8] Cross-sectional TEM image of CAAC-OS, as well as planar TEM image and its image analysis. [Figure 9] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Figure 10] Cross-sectional TEM image of a-like OS. [Figure 11] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 12] FIG. 2 is a diagram illustrating the range of the atomic ratio of oxides according to the present invention. [Figure 13] A diagram explaining the InMZnO4 crystal. [Figure 14] Band diagram of an oxide layer structure. [Figure 15] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 16] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 17] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 18] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 19] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 20] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 21] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 22] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 23] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 24] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 25] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 26] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 27] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 28]1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 29] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 30] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 31] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 32] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 33] FIG. 1 is a circuit diagram of a memory device according to one embodiment of the present invention. [Figure 34] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 35] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 36] 1A and 1B are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 37] FIG. 2 is a block diagram illustrating a CPU according to an embodiment of the present invention. [Figure 38] FIG. 10 is a circuit diagram of a memory element according to one embodiment of the present invention. [Figure 39] FIG. [Figure 40] FIG. 2 is a plan view showing pixels of the imaging device. [Figure 41] FIG. [Figure 42] FIG. [Figure 43] FIG. 2 is a diagram illustrating an example of the configuration of an RF tag. [Figure 44] 1A to 1C are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 45] 1A and 1B are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 46] 1A to 1C are a block diagram, a circuit diagram, and waveform diagrams illustrating one embodiment of the present invention. [Figure 47] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 48] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 49] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 50] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 51] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 52] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 53] FIG. 2 is a diagram illustrating a display module. [Figure 54] 1A and 1B are a perspective view showing a cross-sectional structure of a package using a lead frame type interposer and a plan view showing the configuration of a mobile phone module. [Figure 55] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 56] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 57] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 58] 1 shows an example of the use of an RF tag according to one embodiment of the present invention. [Figure 59] Graph of CV measurement in the example. [Figure 60] Cross-sectional STEM image of an example. [Figure 61] Graph of XPS analysis of the example. [Figure 62] Graph of XPS analysis of the example. DETAILED DESCRIPTION OF THE INVENTION

[0029] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description, and various modifications in form and details can be easily made by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same reference numerals are used in different drawings. When referring to similar objects, the hatch pattern is the same, and In some cases, no reference numerals are given. When referring to the description of a component with a different reference numeral, the referenced component The thickness, composition, structure, shape, etc. of the components may be appropriately described. do.

[0030] In the drawings, the size, thickness of the film (layer), or area is exaggerated for clarity. This may be the case.

[0031] In this specification, the terms "film" and "layer" are interchangeable. It is possible to do this.

[0032] In this specification, the shape of an object may be expressed as, for example, a "diameter," a "particle size," a "size," or a "size." When specifying the size or width of an object, the length of one side of the smallest cube that the object can fit into, or Alternatively, it may be read as the equivalent circle diameter in a cross section of an object. refers to the diameter of a perfect circle whose area is equal to one cross-section of an object.

[0033] Also, a voltage is a voltage between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, voltage can be replaced with potential. Generally, potential (voltage) is relative and is determined by the relative magnitude from a reference potential. Therefore, even if it is described as "ground potential," the potential is It is not necessarily 0V. For example, the lowest potential in a circuit may be the "ground potential." Or, the intermediate potential in the circuit may be the "ground potential." , and positive and negative potentials are defined based on this potential.

[0034] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. It does not indicate the layer order. Therefore, for example, "first" should not be changed to "second" or "third." In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers and the ordinal numbers used to identify an aspect of the present invention may not match.

[0035] The impurities in a semiconductor refer to, for example, anything other than the main component that constitutes the semiconductor. Elements present at concentrations of less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of States) in the conductor and the carrier migration The mobility and crystallinity may decrease. In the case of semiconductors, impurities that change the properties of the semiconductor include, for example, Group 1 elements, There are elements of Group 2, Group 14, Group 15, and transition metals other than the main component, especially For example, hydrogen (which is also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, In the case of oxide semiconductors, oxygen vacancies can occur due to the inclusion of impurities such as hydrogen. In addition, when the semiconductor is a silicon film, the properties of the semiconductor may be changed. Examples of impurities include oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, However, in addition to impurities, there are also cases where the main component element is contained in excess. In some cases, it may cause S. In that case, a trace amount (for example, 0.001 atomic % or more but less than 3 atomic % The DOS can be reduced by adding the additives described above. Elements that may be impurities may also be used.

[0036] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source The distance between the drain electrode and the drain region is called the distance between the In the transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the detailed description, the channel length is any one value, the maximum value, in the region where the channel is formed. , the minimum or average value.

[0037] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the gate electrode overlaps with the electrode (the area where current flows) forms a channel. The length of the region where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. In the detailed description, the channel width is any one value, the maximum value in the region where the channel is formed. , the minimum or average value.

[0038] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width shown in the figure becomes larger, and the effect becomes non-negligible. For example, in transistors with a fine, three-dimensional structure, the side surface of the semiconductor In this case, the ratio of the channel region formed in the top view may be increased. The effective channel width of the channel is actually formed rather than the apparent channel width shown. will be larger.

[0039] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width if the channel conditions are not precisely known. .

[0040] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are not mutually connected. The apparent length is the length of the part where the source and drain face each other in the overlapping region. The above channel width is called "Surrounded Channel Width (SCW)". In this specification, it is simply referred to as the channel width. In some cases, it may refer to the enclosed channel width or apparent channel width. In this specification, when simply referring to a channel width, it may refer to an effective channel width. The channel length, channel width, effective channel width, apparent channel width, and The width of the interstitial channel can be determined by acquiring a cross-sectional TEM image and analyzing the image. Thus, the value can be determined.

[0041] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0042] In this specification, when it is stated that A has a shape that protrudes more than B, it means that Or in the cross-sectional view, at least one end of A is outside at least one end of B. Therefore, it is written that A has a shape that protrudes more than B. For example, in the top view, one end of A is located outside one end of B. This can be read as having the following.

[0043] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Almost parallel" means that two straight lines are arranged at an angle of between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0044] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0045] In the specification, when the term "semiconductor" is simply mentioned, it can be replaced with various semiconductors. For example, Group 14 semiconductors such as silicon and germanium, and oxide semiconductors Conductors, silicon carbide, germanium silicide, gallium arsenide, indium phosphide, selenide Can be replaced by compound semiconductors such as zinc and cadmium sulfide, and organic semiconductors .

[0046] Here, when a semiconductor device according to one embodiment of the present invention is manufactured, a lithography method is used. An example of a method for etching a part of a component will be described. First, a photosensitive layer is formed on the component. A layer of organic or inorganic material is formed by spin coating or the like. A photosensitive organic or inorganic layer is irradiated with light using a mask. , KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) In addition, a liquid (e.g., a liquid containing fluorine) can be used between the substrate and the projection lens. A liquid immersion technique may be used, in which the substrate is exposed to light after being filled with a liquid such as water. Alternatively, an electron beam or an ion beam may be used instead of the light irradiated onto the inorganic layer. When using an electron beam or ion beam, a photomask is not required. to remove or leave the exposed areas of the photosensitive organic or inorganic layer. The etching mask having a resist or the like is formed by etching.

[0047] In addition, an anti-reflection layer (BARC: Bottom Anti-Reflection Layer) is provided under the etching mask. If BARC is used, a reflective coating (reflective coating) may be formed. First, the BARC is etched using an etching mask. The BARC is used to etch the components, except that an anti-reflective layer is used instead of the BARC. In some cases, organic or inorganic materials that do not have the above function may be used. A plasma etching device can be used.

[0048] After etching the components, the etching mask used is removed. Plasma treatment and / or wet etching are used to remove the scratches. Plasma ashing is suitable for plasma processing. If this is insufficient, fluoridated water with a concentration of 0.001% to 1% by volume may be used. Even if the remaining etching mask is removed using hydrochloric acid and / or ozone water, good.

[0049] The equipment used for plasma processing and plasma etching has parallel plate electrodes. Capacitively Coupled Plasma (CCP) A capacitively coupled plasma etching device with parallel plate electrodes can be used. The Zuma etching device may be configured to apply a high frequency power supply to one of the parallel plate electrodes. Alternatively, a configuration in which a plurality of different high frequency power sources are applied to one of the parallel plate electrodes may be used. Alternatively, a configuration may be adopted in which high frequency power of the same frequency is applied to each of the parallel plate electrodes. Alternatively, a configuration may be adopted in which high frequency power supplies with different frequencies are applied to the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. As a dry etching apparatus having a plasma source, for example, an inductively coupled plasma (ICP) Inductively Coupled Plasma etching equipment, electron cycle Electron Cyclotron Resonance (ECR) Plasma etching equipment, Helicon Wave Plasma (HWP) lasma etching equipment, surface wave plasma (SWP) Plasma etching equipment or Magnetron Plasma An SMA etching device or the like can be used.

[0050] In this specification, the deposition of conductors, insulators, and semiconductors is carried out by sputtering, Chemical Vapor Deposition (CVD) method, Molecular Beam Epitaxy (MBE) method or Pulsed Laser Deposition (PLD) method, Atomic layer deposition (ALD) method, thermal oxidation method or Alternatively, plasma oxidation or the like can be used.

[0051] The CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD) method, and thermal CVD (TCVD) method. These methods can be further classified into the VD method, which uses light, and the Photo CVD method. Depending on the source gas, metal CVD (MCVD) and metal organic CVD are used. (MOCVD: Metal Organic CVD) method.

[0052] The plasma CVD method can produce high-quality films at relatively low temperatures. This film formation method does not use a plasma, so it is possible to reduce plasma damage to the object being treated. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device ) may become charged up by receiving an electric charge from the plasma. When accumulated electric charges destroy wiring, electrodes, elements, etc. included in a semiconductor device. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage occurs. In addition, the thermal CVD method can increase the yield of semiconductor devices. Since no plasma damage occurs in the film, a film with few defects can be obtained.

[0053] The ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with few defects can be produced. is obtained.

[0054] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is less affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it suitable for forming thin films with high aspect ratios. However, the ALD method is relatively slow in forming films. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a high deposition rate. may be preferable.

[0055] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having the following composition. By changing the flow rate ratio of the source gases while oxidizing, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film using a vacuum chamber, the time required for film formation is shorter due to the time required for transport and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0056] (Embodiment 1) In this embodiment, a structure of a capacitor according to one embodiment of the present invention and a manufacturing method thereof will be described. do.

[0057] FIG. 1 is a cross-sectional view of a capacitor according to one embodiment of the present invention. an insulator 110 on the conductor 105 and having an opening reaching the top surface of the conductor 105; In the opening, a conductor 160 contacts the side surface of the insulator 110 and the conductor 105, and a conductor The insulator 120 on the conductor 160 and the area where the conductor 160 and the insulator 120 overlap each other. The conductor 105 and the conductor 160 are electrically connected to each other. It continues.

[0058] The conductor 105 functions as one electrode of the capacitor, and the conductor 170 functions as the other electrode. The insulator 120 functions as an electrode. The insulator 120 also functions as a dielectric of the capacitor element. do.

[0059] The conductor 105 and the conductor 170 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, or the like. Silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc Lead, gallium, yttrium, zirconium, molybdenum, ruthenium, platinum, silver, Conductors containing one or more of indium, tin, tantalum and tungsten are used in a single layer or For example, an alloy film or a compound film may be used, and a film containing aluminum may be used. Conductors, conductors containing copper and titanium, conductors containing copper and manganese, indium, A conductor containing zinc and oxygen, or a conductor containing titanium and nitrogen, etc. may also be used.

[0060] The conductor 160 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. Aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, Thorium, zirconium, molybdenum, ruthenium, platinum, silver, indium, tin, Conductors containing one or more of tantalum and tungsten may be used in a single layer or a multilayer. For example, the film may be an alloy film or a compound film, and may be a conductor containing aluminum, copper, or titanium. Conductors containing tungsten, conductors containing copper and manganese, conductors containing indium, tin and oxygen Conductor, or conductor containing titanium and nitrogen, conductor containing tungsten and silicon The body may also be used.

[0061] The insulator 120 is an oxide film formed by oxidizing the conductor 160. The oxide film may be formed by thermal oxidation or plasma oxidation. The oxide film formed by the oxidation method or natural oxidation is excluded. The insulator 120 is aluminum oxide, Magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Metal oxides such as ammonium, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide A plurality of insulators are appropriately selected from silicon dioxide, silicon nitride oxide, silicon nitride, etc. Alternatively, a multilayer film may be used.

[0062] The insulator 110 may be aluminum oxide, magnesium oxide, gallium oxide, or germanium oxide. Rumanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, oxide Metal oxides such as hafnium or tantalum oxide, silicon oxide, silicon oxynitride, Silicon oxide or silicon nitride can be used.

[0063] From now on, a manufacturing method of the capacitor in FIG. 1 according to one embodiment of the present invention will be described with reference to FIGS. 2 and 3. This will be used to explain.

[0064] First, a film of the conductor 105 is formed. The film of the conductor 105 is not limited to being formed on a substrate, but may be formed on an insulating layer. The film can be deposited on a semiconductor device.

[0065] Next, an insulator that will become the insulator 110 is formed on the conductor 105. The insulating material is processed by lithography to form an opening that reaches the top surface of the conductor 105. Then, an insulator 110 is formed (see FIG. 2(A)).

[0066] Next, a conductor 115 is formed on the insulator 110 and in the opening. , for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chlorine Iron, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium , molybdenum, ruthenium, platinum, silver, indium, tin, tantalum and tungsten Any conductor containing one or more kinds of tungsten may be used. For example, an alloy film or a compound film may be used. Conductors containing aluminum, conductors containing copper and titanium, conductors containing copper and manganese a conductor containing indium, tin and oxygen, or a conductor containing titanium and nitrogen; Conductors containing tungsten and silicon may also be used (see FIG. 2(B)).

[0067] Next, the conductor 115 is oxidized to form an insulator 125 on the surface of the conductor 115. The oxidation method may be a thermal oxidation method or an oxidation method using a plasma treatment containing oxygen. However, oxidation by high density plasma treatment containing oxygen is more preferable. When the conductor 115 contains tungsten and silicon, the conductor 115 contains oxygen. By performing the plasma treatment, a silicon oxide film can be formed.

[0068] The insulator 125 is formed by oxidizing the surface of the conductor 115. Since the film can be formed with a uniform thickness, the variation in the capacitance value of the capacitor element can be reduced. This is preferable (see FIG. 3(A)).

[0069] The insulator 125 may be formed as a multilayer film of two or more layers by forming an insulator film on the insulator 125. By using a multilayer film, it is possible to reduce the leakage current between the electrodes of the capacitance element. Alternatively, it is possible to improve the withstand voltage between the electrodes of the capacitance element, which is preferable.

[0070] Next, a conductor 165 is formed. The conductor 165 is formed by filling the opening formed in the insulator 110. Therefore, it is preferable to use the CVD method (especially the MCVD method). In addition, in order to improve the adhesion between the conductor and insulator formed by the MCVD method, the ALD method and other methods are used. It is preferable to form a multilayer film of a conductor formed by a method such as SiO2 and a conductor formed by MCVD. For example, titanium nitride or tantalum nitride and tungsten may be deposited in this order. A multilayer film or the like having such a structure may be used (see FIG. 3(B)).

[0071] Next, the conductor 165, the insulator 125, and the conductor 115 are placed on the upper surface of the insulator 110. Chemical Mechanical Polishing (CMP) As a result, the conductor 160 is formed in the opening of the insulator 110, and the insulator 12 0 and conductor 170 are embedded. As a result, one electrode is conductor 105, The other electrode is a conductor 170, and the dielectric is an insulator 120. This is possible (see Figure 1).

[0072] (Embodiment 2) <Transistor structure 1> The structure of a transistor included in a semiconductor device according to one embodiment of the present invention will be described below. do.

[0073] 4A, 4B, and 4C are top views of a semiconductor device according to one embodiment of the present invention. 4(A) is a cross-sectional view. FIG. 4(B) is a top view. FIG. 4(A) is a cross-sectional view. FIG. 4(B) is a cross-sectional view of the device shown in FIG. 4(A). 4(A) is a cross-sectional view corresponding to the dashed line A3-A4 in FIG. 4(A) is a cross-sectional view corresponding to the top view of FIG. 4(A). In order to clarify the drawing, some elements are omitted. The illustration omits elements.

[0074] In FIGS. 4B and 4C, the transistor is formed by an insulator 401 on a substrate 400 and a , and an insulator 301 on an insulator 401. The insulator 301 has an opening. In the opening, a conductor 310a and a conductor 310b are disposed. The conductor is made up of an insulator 301 on an insulator 302 and a conductor 310a and a conductor 310b on an insulator 302. , the insulator 303 on the insulator 302, the insulator 402 on the insulator 303, and the insulator 402 on the insulator 402. The insulator 406a, the semiconductor 406b on the insulator 406a, and the semiconductor 406b are connected to the upper surface of the semiconductor 406b. The conductor 416a1 and the conductor 416a2 have regions corresponding to each other, and the side surface of the conductor 416a1 and an insulator 424a1 covering the top surface of the conductor 416a2. 424a2, on the insulator 402, the side surface of the insulator 406a, the side surface of the semiconductor 406b, the semiconductor The top surface of 406b, the side surface of the insulator 424a1, the top surface of the insulator 424a1, and the insulator 424a2 an insulator 406c having a region in contact with the side surface of the insulator 406a and the top surface of the insulator 424a2; and the semiconductor 406b via the insulator 412 and the insulator 406c. The conductor 404 has an overlapping region, and the insulator 412 and the conductor 404 have an overlapping region. The edge 410, the insulator 408 on the insulator 410, the insulator 408, the insulator 410, the insulator 412, insulator 406c, insulator 402, insulator 303 and conductor passing through insulator 302 310b, and the insulators 408, 410, 412, and 406c, a second opening through the insulator 424a1 to the conductor 416a1, and 08, through insulator 410, insulator 412, insulator 406c and insulator 424a2. a third opening that leads to the conductor 416a2 and a third opening that leads to the conductor 416b through the insulator 408 and the insulator 410; A fourth opening portion is formed in the first opening portion and reaches the fourth opening portion. The second opening is filled with a conductor 431, the third opening is filled with a conductor 429, and the third opening is filled with a conductor 432. A conductive material 437 is embedded in the opening of the insulating material 408. a conductor 434 having a region in contact with the insulator 433; a conductor 434 on the insulator 408; A conductor 432 having a contact area and a region on the insulator 408 that contacts the conductor 429 and a conductor 430 on the insulator 408 having a region in contact with the conductor 437. and a conductive material 438.

[0075] The semiconductor 406b is connected to the upper surface of the semiconductor 406b, the conductor 416a1, and the conductor 416b. 6a2 and has a region 407 in contact with the region 6a2.

[0076] In this transistor, the conductor 404 functions as a first gate electrode. In addition, the conductor 404 may have a laminated structure with a conductor having a function of suppressing oxygen permeation. For example, by forming a conductive material that has the function of suppressing oxygen permeation as a lower layer, The insulator 412 is a gate insulator. The electrical resistance of a conductor is measured using the two-terminal method. It is possible.

[0077] The resistance of the semiconductor 406b can be controlled by applying a potential to the conductor 404. That is, the potential applied to the conductor 404 causes the conductors 416a1 and 416a2 to It is possible to control the conduction / non-conduction between them.

[0078] The conductor 416a1 and the conductor 416a2 are respectively a source electrode and a drain electrode. The side and top surfaces of the conductor 416a1 are covered with an insulator 424a1. The side and top surfaces of the conductor 416a2 are covered with the insulator 424a2. The conductor 416a1 and the conductor 404 are connected to the insulator 412, the insulator 406c, and the insulator 406b. The conductor 416a2 and the conductor 404 overlap with each other through the gap 24a1. The insulator 412, the insulator 406c, and the insulator 424a2 overlap each other. Therefore, the structure of this transistor is such that the parasitic capacitance and the conduction between the conductor 416a1 and the conductor 404 are The parasitic capacitance between the conductor 416a2 and the conductor 404 can be reduced. A transistor is a transistor with high frequency characteristics, in other words, a transistor suitable for high-speed operation. become.

[0079] As shown in FIGS. 4B and 4C, the upper surface of the semiconductor 406b is covered with a conductor 416a1 and a The conductor 416a1 also functions as a first gate electrode. The electric field of the gate electrode 404 can electrically surround the semiconductor 406b. The structure of a transistor that electrically surrounds a semiconductor is called a surrounded This is called a channel (s-channel) structure. In an s-channel structure, the source of the transistor -A large current can flow between the drains, and the current when conducting (on-state current) can be increased. In addition, since the semiconductor 406b is surrounded by the electric field of the conductor 404, Therefore, the current (off current) when the device is not conducting can be reduced.

[0080] The conductor 310a also functions as a second gate electrode. Oa can be laminated with a conductor that has the function of suppressing oxygen permeation. For example, By forming a conductive material having a function of suppressing oxygen permeation as a lower layer, oxidation of the conductive material 310a can be prevented. The insulators 302, 303 and 40 can prevent a decrease in conductivity due to the The conductive layer 2 functions as a gate insulating film. The threshold voltage of the transistor can be controlled. By using the potential, electrons are injected into the insulator 303 to control the threshold voltage of the transistor. Furthermore, by electrically connecting the first gate electrode and the second gate electrode, The current (ON current) can be increased when the first gate electrode is turned on. The functions of the gate electrode 2 may be interchanged.

[0081] FIG. 6(A) shows an example in which the first gate electrode and the second gate electrode are electrically connected. The opening through the edge 408 and the insulator 410 to the conductor 404 contains a conductor 440 The upper surface of the conductor 440 and the conductor 444 formed on the insulator 408 are , are electrically connected. Meanwhile, the insulator 410, the insulator 408, the insulator 412, the insulator 406c, through insulator 402, insulator 303 and insulator 302 to reach conductor 310c. A conductor 442 is embedded in the opening, and the upper surface of the conductor 442 and the conductor 444 That is, the conductor having the function of the first gate electrode is electrically connected to the 404 is connected to the second gate electrode through the conductor 440, the conductor 444 and the conductor 442. The conductive member 310c is electrically connected to the conductive member 310c.

[0082] The transistor is formed by insulating a semiconductor substrate having a function of blocking impurities such as hydrogen and oxygen. By surrounding the transistor with a body, the electrical characteristics of the transistor can be stabilized. The body 408 is an insulator that has the function of blocking impurities such as hydrogen and oxygen. That's fine.

[0083] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include fluorine, Uron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine , argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium Insulators containing titanium, hafnium or tantalum may be used in single or multilayer configurations.

[0084] For example, the insulator 408 may be aluminum oxide, magnesium oxide, or gas oxide. Sodium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, Metal oxides such as neodymium, hafnium oxide or tantalum oxide, silicon oxide nitride or The insulator 408 may be made of silicon nitride or the like. For example, the insulator 408 is preferably formed using a plasma containing oxygen. Oxygen can be added to the insulator 412 that serves as the underlying layer of the body 408. The added oxygen The insulator 408 has aluminum oxide, which results in excess oxygen in the insulator 412. It is possible to prevent impurities such as hydrogen from being mixed into the conductor 406b. The insulator 408 contains aluminum oxide, which prevents the excess aluminum oxide added to the insulator 412. The outward diffusion of oxygen can be reduced.

[0085] The insulator 401 may be aluminum oxide, magnesium oxide, silicon nitride oxide, or nitride. silicon oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, Lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide may be used. Preferably, the insulator 401 comprises aluminum oxide or silicon nitride. For example, the insulator 401 may have aluminum oxide or silicon nitride, and the semiconductor 406 may have a thickness of 100 Å. In addition, for example, the insulator 4 can be prevented from being contaminated with impurities such as hydrogen. O1 has aluminum oxide or silicon nitride, which reduces outward diffusion of oxygen It is possible.

[0086] The insulator 301 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium Insulators containing aluminum, zirconium, lanthanum, neodymium, hafnium or tantalum are used alone. For example, the insulator 301 may be silicon oxide or It is preferable to have silicon oxynitride.

[0087] The insulator 303 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium Insulators containing aluminum, zirconium, lanthanum, neodymium, hafnium or tantalum A metal oxide film may be used as a single layer or a stacked layer. For example, a nitride film may be used as the insulator 303. Preferably, the oxide comprises silicon oxide, hafnium oxide or aluminum oxide.

[0088] The insulators 302 and 402 may include, for example, boron, carbon, nitrogen, oxygen, and fluorine. element, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium nium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum For example, the insulator 402 may be formed of a single layer or a stack of layers. It is preferable to have silicon oxide or silicon oxynitride.

[0089] It is preferable that the insulator 410 has a low dielectric constant. The body 410 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or fluorine. Silicon oxide doped with nitrogen, silicon oxide doped with carbon, and oxide doped with carbon and nitrogen. It is preferable that the material has silicon dioxide, silicon oxide having voids, or resin. The insulator 410 may be silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. , fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide The laminated structure is made of silicon oxide or silicon oxide having pores and resin. Silicon oxide and silicon oxynitride are preferable because they are thermally stable and can be combined with resin. By combining these materials, it is possible to create a laminated structure that is thermally stable and has a low dielectric constant. Examples of such materials include polyester, polyolefin, polyamide (nylon, aramid, etc.) ), polyimide, polycarbonate or acrylic.

[0090] The insulator 412 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium Insulators containing aluminum, zirconium, lanthanum, neodymium, hafnium or tantalum are used alone. For example, the insulator 412 may be a silicon oxide or It is preferable to have silicon oxynitride.

[0091] It is preferable that the insulator 412 has a high relative dielectric constant. The body 412 is an oxide having gallium oxide, hafnium oxide, aluminum, and hafnium. oxides with aluminum and hafnium; oxide nitrides with silicon and hafnium or an oxynitride having silicon and hafnium. Alternatively, the insulator 412 may be made of silicon oxide or silicon oxynitride with a relative dielectric constant It is preferable to have a laminated structure of silicon oxide and silicon oxynitride. Since capacitors are thermally stable, they can be used in combination with insulators with high dielectric constants. For example, aluminum oxide, gas oxide, By having silicon oxide or hafnium oxide on the insulator 406c side, The silicon contained in the silicon nitride can be prevented from being mixed into the semiconductor 406b. Also, for example, silicon oxide or silicon oxynitride can be used on the insulator 406c side. This allows the formation of a mixture of aluminum oxide, gallium oxide, or hafnium oxide with silicon oxide or A trap center may be formed at the interface between the silicon oxynitride and the silicon dioxide. The center captures electrons, shifting the threshold voltage of the transistor in the positive direction. It may be possible to do so.

[0092] The insulator 424a1 and the insulator 424a2 are the conductor 416a1 or the conductor 4 An insulator formed by oxidizing 16a2 may be used. , magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide metal oxides such as tungsten oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide It may also be a multilayer film with silicon oxide, silicon nitride, silicon oxide nitride, silicon nitride, etc. can.

[0093] The conductor 416a1 and the conductor 416a2 may include, for example, boron, nitrogen, oxygen, fluorine, and the like. Fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel , copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, platinum A conductor containing one or more of sodium, silver, indium, tin, tantalum and tungsten is formed in a single layer. For example, an alloy film or a compound film may be used, and an aluminum film may be used. Conductors containing titanium, conductors containing copper and titanium, conductors containing copper and manganese, indium Conductors containing aluminum, tin and oxygen, or titanium and nitrogen, tungsten Conductors containing silicon and silicon may also be used.

[0094] Conductor 310a, conductor 310b, conductor 310c, conductor 404, conductor 429, conductor Conductor 430, Conductor 431, Conductor 432, Conductor 433, Conductor 434, Conductor 437 , conductor 438, conductor 440, conductor 442, and conductor 444 may be, for example: Boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese Cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum Conductors containing one or more of silicon, ruthenium, silver, indium, tin, tantalum and tungsten The dielectric may be a single layer or a multilayer. For example, it may be an alloy film or a compound film. conductors containing aluminum, conductors containing copper and titanium, conductors containing copper and manganese Conductors containing indium, tin and oxygen, or titanium and nitrogen etc. may also be used.

[0095] The semiconductor 406b is preferably an oxide semiconductor. (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide , aluminum gallium arsenide, indium phosphide, gallium nitride, or organic semiconductors. There are cases where it is okay to have them.

[0096] The insulators 406a and 406c are made of a material other than oxygen that constitutes the semiconductor 406b. It is preferable to use an oxide composed of one or more elements, or two or more elements. Silicon (including strained silicon), germanium, silicon germanium, silicon carbide, Lithium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride or organic semiconductor In some cases, it is acceptable to use your body or other objects.

[0097] <Transistor structure 2> Here, a transistor having a different structure from that shown in FIG. 4 will be described with reference to FIG. 5. 1A, 1B, and 1C are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 5(A) is a top view. FIG. 5(B) is a diagram showing the structure of the device along the dashed line A1-A2 in FIG. 5(A). 5(C) is a cross-sectional view corresponding to the dashed line A3-A4 shown in FIG. In the top view of FIG. 5(A), some elements are omitted for clarity. The diagram is as follows:

[0098] 5B and 5C, the transistor is formed by an insulator 401 on a substrate 400 and a , and an insulator 301 on an insulator 401. The insulator 301 has an opening. In the opening, a conductor 310a and a conductor 310b are disposed. The conductor is made up of an insulator 301 on an insulator 302 and a conductor 310a and a conductor 310b on an insulator 302. , the insulator 303 on the insulator 302, the insulator 402 on the insulator 303, and the insulator 402 on the insulator 402. The insulator 406a, the semiconductor 406b on the insulator 406a, and the semiconductor 406b are connected to the upper surface of the semiconductor 406b. The conductor 416a1 and the conductor 416a2 have regions corresponding to each other, and the side surface of the conductor 416a1 The insulator 424a1 and the conductor 416a2 are arranged in a region in contact with the insulator 406c. The insulator 424a2 is disposed on the side surface in a region in contact with the insulator 406c, and the conductor 416a the insulator 410 in contact with the upper surface of the semiconductor 406b and the upper surface of the conductor 416a2; an insulator 406c in contact with the insulator 406c; an insulator 412 on the insulator 406c; A conductor 404 is disposed on the semiconductor 406b via an insulator 406c, and a conductor 404 is disposed on the insulator 410. an insulator 418 on the insulator 404, on the insulator 412, and on the insulator 406c; The insulator 408 on the insulator 408, the insulator 428 on the insulator 408, the insulator 428, the insulator 408, The electrical current is conducted through the insulator 418, the insulator 410, the insulator 402, the insulator 303 and the insulator 302. A first opening reaches the insulator 310b, and the insulators 428, 408, 418, and a second opening through the insulator 410 to the conductor 416a1; an insulator 428; an insulator 408, a third opening through the insulator 418 and the insulator 410 to the conductor 416a2. and a fourth through the insulator 428, the insulator 408, and the insulator 418 to the conductor 404. The first opening is filled with a conductor 433, and the second opening is filled with a conductor The third opening is filled with a conductor 429, and the fourth opening is filled with a conductor 437 is embedded. Also, a region on the insulator 428 that is in contact with the conductor 433 is provided. a conductor 434 that is on the insulator 428 and has a region that contacts the conductor 431; 432, a conductor 430 on the insulator 428 and having an area in contact with the conductor 429; and a conductor 438 located on the insulator 428 and having a region in contact with the conductor 437.

[0099] The semiconductor 406b is connected to the upper surface of the semiconductor 406b, the conductor 416a1, and the conductor 416b. 6a2 and has a region 407 in contact with the region 6a2.

[0100] In this transistor, the conductor 404 functions as a first gate electrode. In addition, the conductor 404 may have a laminated structure with a conductor having a function of suppressing oxygen permeation. For example, by forming a conductive material that has the function of suppressing oxygen permeation as a lower layer, The insulator 412 is a gate insulator. It has the function as.

[0101] The conductor 416a1 and the conductor 416a2 are connected to a source electrode and a drain electrode. The conductor 416a1 and the conductor 416a2 also function as a barrier to oxygen permeation. For example, a conductive material that suppresses oxygen permeation can be used. By forming a conductor having a function of forming a film on the upper layer, the conductor 416a1 and the conductor 416a2 This can prevent an increase in electrical resistance due to oxidation.

[0102] The resistance of the semiconductor 406b can be controlled by applying a potential to the conductor 404. That is, the potential applied to the conductor 404 causes the conductors 416a1 and 416a2 to It is possible to control the conduction / non-conduction between them.

[0103] In this transistor, a region that functions as a gate electrode is formed in an insulator 410 or the like. Since it is formed in a self-aligned manner to fill the opening, TGSA s-channel FET(Trench Gate Self Align s- It can also be called a channel FET.

[0104] In FIG. 5B, the bottom surface of the conductor 404 functioning as the first gate electrode is A region facing parallel to the top surface of the semiconductor 406b through the insulator 412 and the insulator 406c. The length of the insulator 410 etc. is defined as the gate line width. That is, the gate line width can be made smaller than the minimum processing dimension. Specifically, the gate line width can be reduced to 5 nm or more and 60 nm or less, preferably It can be set to 5 nm or more and 30 nm or less.

[0105] If the electric field from the first gate electrode is blocked by another conductor, The switching characteristics may be deteriorated. The thickness of the conductive material 412 separates the conductive material 404, the conductive material 416a1, and the conductive material 416a2. The positional relationship between the source electrode and the drain electrode changes. The thickness of the conductive layer 416a1 and the conductive layer 416a2 and the insulator having a function as a gate insulating film It is clear that the film thickness of 412 affects the electrical characteristics of this transistor.

[0106] In FIG. 5B, the insulator in the region between the conductor 416a1 and the conductor 416a2 The thickness of 412 is set to be equal to or less than the thickness of the conductor 416a1 or the thickness of the conductor 416a2. The electric field from the gate electrode is applied to the entire channel formation region, resulting in good transistor operation. This is preferable. The thickness of 2 is 30 nm or less, preferably 10 nm or less.

[0107] In addition, the structure of this transistor is such that the thickness of the conductor 416a1 or the thickness of the conductor 416a2 The end of the conductor 416a1 is covered with an insulator 406c. The conductive material 412 and the insulator 424a1 face each other. Alternatively, the end of the conductor 416a2 is connected to the insulator 406c, the insulator 412, and the insulator 424a2. The area of ​​the conductive material 404 is smaller than that of the conductive material 404. Furthermore, by providing the insulators 424a1 and 424a2, The insulator thickness in these regions is thicker, so the transistor has a higher parasitic capacitance in these regions. The configuration is kept small.

[0108] In addition, the structure of this transistor is such that the insulator 406 on the side of the conductor 416a1 is An insulator 424a1 is disposed in the region in contact with the conductor 416a2. The insulator 424a2 is disposed in the region in contact with the insulator 406c. A conductor 404 having a function as an electrode and a source electrode or a drain electrode Between the conductor 416a1 or the conductor 416a2, an insulator 412 and an insulator The insulator 424a1 or the insulator 424a2 is added to the edge 406c. A conductor 404 having a function as a first gate electrode and a source electrode or a drain electrode are connected. and the conductor 416a1 or the conductor 416a2 that functions as a pole, and This makes the transistor less susceptible to the short channel effect. can be done.

[0109] The conductor 310a also functions as a second gate electrode. Oa can also be a multilayer film including a conductive film that has the function of suppressing oxygen permeation. By forming a multilayer film including a conductive film having a function of suppressing the permeation of the conductor 310a, the oxidation of the conductor 310a can be prevented. The insulators 302, 303, and 402 can prevent a decrease in conductivity due to the heat treatment. The conductor 310a functions as a gate insulating film. The threshold voltage of the transistor can be controlled. By this, electrons are injected into the insulator 303, and the threshold voltage of the transistor can be controlled. Furthermore, by electrically connecting the first gate electrode and the second gate electrode, The current (ON current) can be increased. The functions of the gate electrodes of may be interchanged.

[0110] FIG. 6(B) shows an example in which the first gate electrode and the second gate electrode are electrically connected. The opening through the edge 428, the insulator 408, and the insulator 418 to the conductor 404 has , a conductor 440 is embedded, and a conductor formed on the upper surface of the conductor 440 and on the insulator 428 The insulator 428 is electrically connected to the insulator 444. 418, the insulator 410, the insulator 402, the insulator 303 and the conductor through the insulator 302 A conductor 442 is embedded in the opening that reaches 310c, and the upper surface of the conductor 442 and It is electrically connected to the conductor 444. That is, it functions as a first gate electrode. The conductor 404 is connected to the second conductor 440, the conductor 444, and the conductor 442. The gate electrode 310c is electrically connected to the conductor 310a.

[0111] The insulators 418 and 428 may include, for example, boron, carbon, nitrogen, oxygen, and fluorine. element, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium nium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum The insulators may be used in a single layer or a multilayer. The body 428 preferably comprises silicon oxide or silicon oxynitride. For other configurations, please refer to the above.

[0112] (Embodiment 3) <Oxide semiconductor structure> The structure of an oxide semiconductor will be described below.

[0113] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned d crystalline oxide semiconductor), polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous- like oxide semiconductor) and amorphous oxide semiconductor be.

[0114] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxides. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC -OS, polycrystalline oxide semiconductor, and nc-OS.

[0115] Amorphous structures are generally isotropic and have no heterogeneous structure, and are characterized by the arrangement of atoms in a metastable state. The position is not fixed, the bond angle is flexible, and there is short-range order but no long-range order. It is said that there is no such thing.

[0116] That is, a stable oxide semiconductor is completely amorphous. s) It cannot be called an oxide semiconductor. Also, it is not isotropic (for example, a periodic structure in a small area) An oxide semiconductor having an amorphous structure cannot be called a completely amorphous oxide semiconductor. ike OS is not isotropic, but has an unstable structure with voids. In terms of instability, a-like OS is similar in physical properties to amorphous oxide semiconductors. stomach.

[0117] <caac-os> First, let me explain about CAAC-OS.

[0118] CAAC-OS is an oxide having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0119] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystal structure was analyzed by the out-of-plane method. As shown in FIG. 7(A), a peak appears at a diffraction angle (2θ) of approximately 31°. The crystal structure is attributed to the (009) plane of the InGaZnO4 crystal. The crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be seen that the crystal is oriented in a direction perpendicular to the surface, or in a direction approximately perpendicular to the surface. In addition to the peaks around 2θ around 36°, a peak may also appear. The peaks around the nucleus are due to the crystal structure classified into the space group Fd-3m. It is preferable that -OS does not exhibit such a peak.

[0120] On the other hand, in-pl, X-rays are incident on the CAAC-OS from a direction parallel to the surface to be formed. When structural analysis is performed using the ane method, a peak appears at 2θ around 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. And, 2θ is fixed at around 56°. The sample is then rotated around the normal vector of the sample surface as the axis (φ axis) for analysis (φ scan). Even if this is done, no clear peak appears, as shown in Figure 7(B). When φ was scanned with 2θ fixed at around 56° for nO4, the results were as shown in Figure 7(C). Six peaks attributable to the crystal plane equivalent to the (110) plane are observed. From the structural analysis using D, it was found that the orientation of the a-axis and b-axis of CAAC-OS is irregular. can be confirmed.

[0121] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the process was performed parallel to the surface on which the CAAC-OS was formed. When an electron beam with a probe diameter of 300 nm is incident, a diffraction pattern (control pattern) like that shown in Figure 7(D) is generated. This diffraction pattern may contain In. This includes spots due to the (009) plane of the GaZnO4 crystal. Even in such cases, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the film is formed. On the other hand, for the same sample, the direction of the sample surface is Figure 7(E) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly. A ring-shaped diffraction pattern is observed in Figure 7(E). The pellets contained in CAAC-OS were also identified by electron diffraction using a 300 nm electron beam. It can be seen that the a-axis and b-axis of the first phosphorus in FIG. The glitches are thought to be due to the (010) and (100) planes of the InGaZnO4 crystal. In addition, the second ring in Figure 7(E) is thought to be due to the (110) plane. do.

[0122] In addition, a transmission electron microscope (TEM) Combined analysis of bright-field images and diffraction patterns of CAAC-OS using a microscope When observing the image (also called a high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain boundaries), are not clearly visible. It may not be possible to clearly identify the boundary. It can be said that C-OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0123] Figure 8(A) shows a high-resolution T image of the cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image shown here is a spherical aberration correction (SAC) image. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. It can be observed that

[0124] From Figure 8(A), we can see the pellet, which is the region where metal atoms are arranged in layers. It has been found that the size of a single pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). Also, CAAC-OS can be used with CANC (C-Axis Aligned Nano The pellets can also be called oxide semiconductors with CAAC -OS surface or upper surface unevenness is reflected, and CAAC-OS surface or upper surface unevenness is reflected. is parallel to the surface.

[0125] In addition, Fig. 8(B) and Fig. 8(C) show the CAAC- Figures 8(D) and 8(E) show Cs-corrected high-resolution TEM images of the OS surface. The images are the processed images of Figures 8(B) and 8(C). The image processing method is explained below. First, let us consider the case where the image in Fig. 8(B) is subjected to a fast Fourier transform (FFT). Then, the FFT image is obtained by performing the r Transform process. 2.8nm based on the origin -1 to 5.0 nm -1 Masking to leave the range between Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT). e Fast Fourier Transform (FT) processing is used to process the image. The image acquired in this way is called an FFT filtered image. FFT filtering The image is an image in which the periodic component is extracted from a Cs-corrected high-resolution TEM image, and shows the lattice arrangement. There are.

[0126] In Figure 8(D), the area where the lattice arrangement is disrupted is indicated by a dashed line. The area surrounded by the dashed line is The area indicated by the broken line is the connection between the pellets. The broken line indicates a hexagonal shape, which indicates that the pellets are hexagonal. The shape of the dot is not limited to a regular hexagon, and is often a non-regular hexagon.

[0127] In FIG. 8(E), a dotted line separates a region with a uniform lattice arrangement from a region with a different uniform lattice arrangement. Even near the dotted line, no clear grain boundaries can be seen. When connecting the surrounding lattice points around a neighboring lattice point, a distorted hexagon, pentagon, or / and heptagon can be formed. In other words, by distorting the lattice arrangement, the formation of grain boundaries can be suppressed. This is because the atomic arrangement of CAAC-OS is dense in the ab-plane direction. The substitution of metal elements changes the bond distance between atoms, This is thought to be because distortion can be tolerated.

[0128] As described above, the CAAC-OS has a c-axis orientation and is Multiple pellets (nanocrystals) are connected to form a distorted crystal structure. AAC-OS, CAA crystal(c-axis-aligned abp It can also be called an oxide semiconductor with lane-anchored crystals. Cut.

[0129] CAAC-OS is an oxide semiconductor with high crystallinity. CAAC-OS is designed to be free from impurities and defects. It can also be said to be an oxide semiconductor with few defects (such as oxygen vacancies).

[0130] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon are more oxidative than metal elements that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0131] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 traps hydrogen and becomes a carrier generation source.

[0132] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. There is. Specifically, 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than, More preferably, 1 × 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than Such an oxide semiconductor can be a high-purity intrinsic or The CAAC-OS is essentially a highly pure intrinsic oxide semiconductor. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0133] <nc-os> Next, we will explain nc-OS.

[0134] We will explain the analysis of nc-OS by XRD. However, when structural analysis was performed using the out-of-plane method, no peaks indicating orientation appeared. That is, the crystals of the nc-OS do not have any orientation.

[0135] For example, an nc-OS having InGaZnO4 crystals was thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed on the region m, the A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. In addition, the diffraction pattern (nano) when an electron beam with a probe diameter of 1 nm is incident on the same sample. The electron diffraction pattern (B) is shown in Figure 9(B). Multiple spots are observed. Therefore, the nc-OS is an electron probe with a diameter of 50 nm. However, when an electron beam with a probe diameter of 1 nm is irradiated, the order is not confirmed. By doing so, order can be confirmed.

[0136] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in Figure 9(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. Therefore, in the range of thickness less than 10 nm, the nc-OS is ordered. It can be seen that the crystals are oriented in various directions. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0137] Figure 9(D) shows the Cs-corrected high-resolution image of the cross section of nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image, with the areas indicated by the auxiliary lines. There are two areas where crystals can be seen, as shown in Fig. 1, and areas where no clear crystals can be seen. The crystal part contained in the nc-OS has a size of 1 nm to 10 nm. In particular, the size is often between 1 nm and 3 nm. An oxide semiconductor having a size of more than 0 nm and not more than 100 nm is called a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor). It is sometimes called a crystalline oxide semiconductor. For example, in the case of nc-OS, the grain boundaries cannot be clearly identified in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, the crystalline part of nc-OS may be referred to as pellets below.

[0138] In this way, nc-OS can be used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. In the case of the SiO2 film, there is no regularity in the crystal orientation between different pellets. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. In some cases, it may be difficult to distinguish them from solid oxide semiconductors.

[0139] In addition, since there is no regularity in the crystal orientation between the pellets (nanocrystals), nc-OS , oxidation with RANC (Random Aligned nanocrystals) semiconductors or NANC (Non-Aligned nanocrystals) The oxide semiconductor may also be called an oxide semiconductor.

[0140] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in the crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0141] <a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a semiconductor.

[0142] Figure 10 shows a high-resolution cross-sectional TEM image of the a-like OS. is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. B) is 4.3 x 10 8 e - / nm 2 electrons (e - ) a-like OS after irradiation These are high-resolution cross-sectional TEM images. Figures 10(A) and 10(B) show that a-like O It can be seen that striped bright regions extending in the vertical direction are observed in S from the start of electron irradiation. It can also be seen that the shape of the bright regions changes after electron irradiation. It is assumed to be a density region.

[0143] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0144] As samples, a-like OS, nc-OS, and CAAC-OS were prepared. Both samples are In-Ga-Zn oxides.

[0145] First, high-resolution cross-sectional TEM images of each sample are acquired. All of the materials have crystalline parts.

[0146] The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn It is known that the structure has a total of nine layers, six of which are -O layers, stacked in layers along the c-axis. The distance between these adjacent layers is determined by the lattice spacing (also called the d value) of the (009) plane. The value is about the same, and is calculated to be 0.29 nm from crystal structure analysis. In the following, the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less is referred to as InGaZ. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0147] Figure 11 shows an example of investigating the average size of the crystal parts (22 to 30 locations) of each sample. The length of the lattice fringes mentioned above is the size of the crystal part. e The crystal part of the OS grows in size according to the cumulative amount of electron irradiation used to obtain the TEM image. From Figure 11, it can be seen that in the early stages of TEM observation, the size of the particles is about 1.2 nm. The part of the crystal that was left behind (also called the initial nucleus) is filled with electrons (e - ) cumulative exposure is 4.2 × 10 8 e - / nm 2 On the other hand, it can be seen that the size of the crystals grows to about 1.9 nm in the case of n For c-OS and CAAC-OS, the cumulative electron irradiation dose was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of 1000 to 10000. Therefore, the size of the crystalline parts of nc-OS and CAAC-OS is constant regardless of the cumulative electron irradiation dose. , and are approximately 1.3 nm and 1.8 nm, respectively. The Hitachi transmission electron microscope H-9000NAR was used for the TEM observations. The conditions were an acceleration voltage of 300 kV and a current density of 6.7 × 10 5 e - / (nm 2 ·s), irradiation area The diameter of the region was set to 230 nm.

[0148] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in nc-OS and CAAC-OS, the growth of the crystals by electron irradiation is almost nonexistent. In other words, a-like OS is not seen in comparison with nc-OS and CAAC-OS. , it is clear that this is an unstable structure.

[0149] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal of the same composition. The density of the nc-OS is 78.6% or more and less than 92.3% of that of the nc-OS. The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0150] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0151] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By combining these, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density corresponding to a single crystal of a desired composition is calculated based on the ratio of the single crystals of different compositions combined. However, the density can be estimated by using as few types of single crystals as possible. It is preferable to estimate them together.

[0152] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the above-mentioned compounds.

[0153] Oxides applicable to the insulator 406a, the semiconductor 406b, the insulator 406c, etc. will be described. Reveal.

[0154] The oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. It is preferable that thorium or tin is contained. Also, boron, silicon, titanium, etc. Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, One selected from the group consisting of chromium, hafnium, tantalum, tungsten, magnesium, etc. It may contain one or more species.

[0155] Here, let us consider a case where the oxide contains indium, element M, and zinc. is aluminum, gallium, yttrium, or tin. Other elements M Applicable elements include boron, silicon, titanium, iron, nickel, germanium, and di Zr, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tantalum However, the element M can be a combination of multiple of the above elements. There are cases where it is acceptable to do so.

[0156] First, the oxidation method according to the present invention will be explained with reference to FIGS. 12(A), 12(B), and 12(C). The preferred range of the atomic ratio of indium, element M, and zinc contained in the product will be explained. In addition, the atomic ratio of oxygen is not shown in FIG. The atomic ratios of elements M and zinc are defined as [In], [M], and [Zn], respectively. do.

[0157] In Figures 12(A), 12(B), and 12(C), the dashed lines indicate the ratio of [In]:[M ]:[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):2, [ The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):3 is n]:[M]:[Zn]=(1+α):(1-α):4, and The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):5 is shown. vinegar.

[0158] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=1:2:β, the line where [In ]:[M]:[Zn]=1:3:β, the atomic ratio is [In]:[M]:[Zn ]=1:4:β, and the atomic ratio of [In]:[M]:[Zn]=2:1:β. The line where the atomic ratio is [In]:[M]:[Zn]=5:1:β Represents in.

[0159] In addition, the atomic ratio of [In]:[M]:[Zn]=0:2:1 shown in FIG. 12 or Oxides with values ​​close to this range tend to have a spinel-type crystal structure.

[0160] 12A and 12B show the indium oxide contained in the oxide of one embodiment of the present invention. 1 shows an example of a preferred range of the atomic ratio of element M and zinc.

[0161] As an example, FIG. 13 shows InMZn where [In]:[M]:[Zn]=1:1:1. Figure 13 shows the crystal structure of InMZ when observed from a direction parallel to the b axis. The metal element in the MZnO2 layer shown in FIG. Or zinc. In this case, the ratio of element M to zinc is equal. Element M and zinc This means that substitutions are possible and the sequence is random.

[0162] InMZnO4 has a layered crystal structure (also called a layered structure), as shown in Figure 13. , the InO2 layer containing indium is 1, and the MZnO2 layer containing elements M and zinc is The result is 2.

[0163] Indium and the element M can be substituted for each other. Therefore, the element M in the (M, Zn) layer M can be replaced with indium and expressed as an (In,M,Zn) layer. In that case, the In layer It has a layered structure with one layer and two (In,M,Zn) layers.

[0164] In the oxide with the atomic ratio of [In]:[M]:[Zn]=1:1:2, the In layer is 1 , (M, Zn) layer has 3 layers. That is, [Z When the oxide crystallizes, the ratio of the (M, Zn) layer to the In layer increases. Increase.

[0165] However, in the oxide, the number of (M, Zn) layers per In layer is not an integer. In this case, there are multiple types of layered structures in which the number of (M, Zn) layers is an integer for one In layer. For example, when [In]:[M]:[Zn]=1:1:1.5, the In layer A layered structure with 1 (M,Zn) layer and 2 (M,Zn) layers, and a layered structure with 3 (M,Zn) layers. In some cases, a layered structure may be formed in which

[0166] For example, when forming an oxide film using a sputtering device, deviation from the atomic ratio of the target occurs. In particular, depending on the substrate temperature during film formation, the [Zn ], the [Zn] of the film may be smaller than that of the film.

[0167] In addition, multiple phases may coexist in an oxide (two-phase coexistence, three-phase coexistence, etc.). For example, At atomic ratios close to [In]:[M]:[Zn]=0:2:1, the spin Two phases, a flanking crystal structure and a layered crystal structure, tend to coexist. At atomic ratios close to the atomic ratio of [Zn]=1:0:0, bixbyite-type Two phases, a crystalline structure and a layered crystalline structure, tend to coexist. When multiple phases coexist in an oxide, In the case where grain boundaries are formed between different crystal structures, There is a match.

[0168] In addition, by increasing the indium content, the carrier mobility (electron mobility) of the oxide This is mainly due to the fact that in oxides containing indium, element M, and zinc, The s orbital of the heavy metal contributes to carrier conduction, and increasing the indium content As a result, the overlapping area of ​​the s orbitals becomes larger, and oxides with a high indium content This is because the carrier mobility is higher compared to oxides with a lower indium content.

[0169] On the other hand, when the content of indium and zinc in the oxide is low, the carrier mobility is low. Therefore, the atomic ratio of [In]:[M]:[Zn]=0:1:0 and its vicinity In the atomic ratio near the value (for example, region C shown in FIG. 12(C)), the insulating property is high.

[0170] Therefore, the oxide of one embodiment of the present invention has a layered structure with high carrier mobility and few grain boundaries. It is preferable that the atomic ratio be that shown in region A in FIG. 12(A), which is likely to form the structure.

[0171] In addition, in the region B shown in FIG. 12(B), [In]:[M]:[Zn]=4:2:3 to 4 .1 and its neighboring values. For example, the atomic ratio [In]:[M ]:[Zn]=5:3:4. Oxides having the atomic ratio shown in region B are particularly In addition, it is an excellent oxide with high crystallinity and high carrier mobility.

[0172] The condition for an oxide to form a layered structure is not uniquely determined by the atomic ratio. The difficulty of forming a layered structure varies depending on the atomic ratio. However, depending on the formation conditions, a layered structure may or may not be formed. The illustrated region is a region showing the atomic ratio in which the oxide has a layered structure, and is represented by Region A to Region B. The bounds of C are not strict.

[0173] Next, the case where the oxide is used in a transistor will be described.

[0174] In addition, by using the above oxide in a transistor, carrier scattering at grain boundaries can be reduced. Therefore, a transistor with high field effect mobility can be realized. Furthermore, a highly reliable transistor can be realized.

[0175] In addition, it is preferable to use an oxide with a low carrier density for the transistor. , the oxide has a carrier density of 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 End This can be done as follows.

[0176] In addition, high-purity intrinsic or substantially high-purity intrinsic oxides have fewer carrier generation sources. Therefore, the carrier density can be reduced. Oxides, which are conductive, have a low density of defect states, and therefore may also have a low density of trap states.

[0177] In addition, the charges trapped in the oxide trap levels take a long time to disappear, Therefore, oxides with high trap level density can behave as if they are fixed charges. A transistor having a channel region formed in a material may have unstable electrical characteristics.

[0178] Therefore, in order to stabilize the electrical characteristics of the transistor, it is necessary to reduce the impurity concentration in the oxide. In order to reduce the impurity concentration in the oxide, it is effective to It is also preferable to reduce the concentration of impurities such as hydrogen, nitrogen, alkali metals, Examples include alkaline earth metals, iron, nickel, and silicon.

[0179] Here, the influence of each impurity in the oxide will be explained.

[0180] When oxides contain silicon or carbon, which are elements of Group 14, Therefore, the concentration of silicon and carbon in the oxide and the The concentration of silicon and carbon near the interface with the silicon substrate was measured by secondary ion mass spectrometry (SIMS). The concentration obtained by ion mass spectrometry (Ion Mass Spectrometry) was calculated by 2× 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following do.

[0181] In addition, if an oxide contains an alkali metal or alkaline earth metal, a defect level is formed. Therefore, alkali metals or alkaline earth metals are Transistors using oxides containing SiO2 tend to be normally-on. It is preferable to reduce the concentration of alkali metals or alkaline earth metals in the oxide. The concentration of alkali metals or alkaline earth metals in the oxide obtained by SIMS is , 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Below Put it down.

[0182] In addition, when nitrogen is contained in an oxide, electrons that act as carriers are generated, and the carrier density As a result, transistors using oxides containing nitrogen as semiconductors Therefore, in the oxide, nitrogen is easily For example, the nitrogen concentration in the oxide is preferably as low as possible by SIMS. , 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Below or less, more preferably 1 x 10 18 atoms / cm 3 Less than 5 × 10, more preferably 1 7 atoms / cm 3 The following applies.

[0183] In addition, the hydrogen contained in the oxide reacts with the oxygen that bonds with the metal atom to form water, so the acid When hydrogen enters the oxygen vacancy, electrons, which act as carriers, are generated. In addition, some of the hydrogen atoms may bond with oxygen atoms that bond with metal atoms, forming carriers. Therefore, transistors using oxides containing hydrogen can generate electrons. Therefore, hydrogen in the oxide should be reduced as much as possible. Specifically, it is preferable that the hydrogen concentration in the oxide is measured by SIMS. Degrees, 1 x 10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 Less than 1×1 0 18 atoms / cm 3 Less than.

[0184] By using an oxide with sufficiently reduced impurities for the channel formation region of a transistor, Stable electrical properties can be imparted.

[0185] Next, we will discuss the case where the oxide is made into a two-layer structure or a three-layer structure. The band diagram of the insulator adjacent to the stacked structure of semiconductor S2 and insulator S3 is shown in Fig. The band diagram of the insulator in contact with the stacked structure of insulator S3 is explained using Figure 14. do.

[0186] FIG. 14(A) shows an insulator I1, an insulator S1, a semiconductor S2, an insulator S3, and an insulator I2 FIG. 14(B) is an example of a band diagram in the film thickness direction of a laminated structure having an insulator I 1. Band diagram in the thickness direction of a stacked structure having semiconductor S2, insulator S3, and insulator I2 This is an example. For ease of understanding, the band diagram is divided into insulator I1, insulator S1, and semiconductor The energy levels (Ec) of the conduction band minimums of S2, insulator S3, and insulator I2 are shown.

[0187] The energy levels of the insulators S1 and S3 at the bottom of the conduction band are closer to the vacuum level than those of the semiconductor S2. The energy level of the semiconductor S2 is close to the bottom of the conduction band, and the energy level of the insulator S1 is close to the bottom of the conduction band. The difference in energy level from the bottom of the conduction band of S3 is 0.15 eV or more, or 0.5 eV or more and preferably 2 eV or less, or 1 eV or less. The electron affinity of the semiconductor S2 is larger than that of the insulator S3, and the insulator S1 and the insulator The difference between the electron affinity of S3 and that of semiconductor S2 is 0.15 eV or more, or 0. It is preferably 5 eV or more and 2 eV or less, or 1 eV or less.

[0188] As shown in FIG. 14(A) and FIG. 14(B), an insulator S1, a semiconductor S2, and an insulator S In 3, the energy level at the bottom of the conduction band changes smoothly. In order to have such a band diagram, Formed at the interface between insulator S1 and semiconductor S2, or between semiconductor S2 and insulator S3 It is preferable to lower the defect level density of the mixed layer.

[0189] Specifically, the insulator S1 and the semiconductor S2, and the semiconductor S2 and the insulator S3 have common properties other than oxygen. By containing the element (as the main component), it is possible to form a mixed layer with a low defect level density. For example, when the semiconductor S2 is an In-Ga-Zn oxide, the insulators S1 and S3 are For this purpose, it is preferable to use In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, or the like.

[0190] At this time, the main path of the carriers is the semiconductor S2. The defect level density at the interface between the semiconductor S2 and the insulator S3 can be reduced. Therefore, the effect of interface scattering on carrier conduction is small, resulting in a high on-current.

[0191] When electrons are captured in the trap level, the captured electrons behave like fixed charges. Therefore, the threshold voltage of the transistor shifts in the positive direction. By providing the body S3, the trap level can be moved away from the semiconductor S2. This structure prevents the threshold voltage of the transistor from shifting in the positive direction. It is possible.

[0192] The insulators S1 and S3 are made of materials with sufficiently low conductivity compared to the semiconductor S2. At this time, the semiconductor S2, the interface between the semiconductor S2 and the insulator S1, and the interface between the semiconductor S2 and the insulator S1 The interface with S3 mainly functions as the channel region. In FIG. 12(C), if an oxide having an atomic ratio shown in region C where the insulating property is high is used, In addition, the region C shown in FIG. 12(C) is [In]:[M]:[Zn]=0:1:0, The atomic ratio is shown as a value close to the atomic ratio.

[0193] In particular, when an oxide having the atomic ratio shown in region A is used for semiconductor S2, the insulator S1 and For the insulator S3, an oxide having [M] / [In] of 1 or more, preferably 2 or more is used. It is also preferable that the insulator S3 has a sufficiently high insulating property [M]. It is preferable to use an oxide in which / ([Zn]+[In]) is 1 or more.

[0194] The substrate 400 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, and stabilized silica substrates. Zirconia substrates (yttria-stabilized zirconia substrates, etc.), resin substrates, etc. The solid substrate may be, for example, a single semiconductor substrate such as silicon or germanium, or silicon carbide. Silicon, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide Furthermore, there are compound semiconductor substrates made of silicon. A semiconductor substrate having a region, such as an SOI (Silicon On Insulator) substrate Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, and the like. Furthermore, a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or a semiconductor is provided on a semiconductor substrate, There are substrates with an insulator provided, and substrates with a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate having elements mounted thereon may be used. The elements include a capacitance element, a resistance element, a switch element, a light-emitting element, a memory element, and the like.

[0195] A flexible substrate may also be used as the substrate 400. As a method for providing a transistor, a transistor is formed on a non-flexible substrate, and then the transistor is There is also a method of peeling off the transistor and transferring it to the substrate 400, which is a flexible substrate. In this case, a peeling layer may be provided between the non-flexible substrate and the transistor. For example, a sheet, film, or foil having woven fibers may be used. The substrate 400 may have elasticity. When the bending or pulling is stopped, the substrate 400 returns to its original shape. The substrate may have the property of returning to its original shape, or may have the property of not returning to its original shape. 400 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less. More preferably, the substrate 400 has a region having a thickness of 15 μm or more and 300 μm or less. By thinning the substrate, the weight of the semiconductor device having the transistor can be reduced. By making 400 thinner, it can be stretched and bent even when using glass. When the force is released, the product may return to its original shape. This can reduce the impact on the semiconductor device on the substrate 400. A suitable semiconductor device can be provided.

[0196] The substrate 400, which is a flexible substrate, may be made of, for example, metal, alloy, resin, or glass. Alternatively, fibers thereof can be used. The substrate 400, which is a flexible substrate, has a linear expansion coefficient of 1.5. The lower the elongation, the more preferable it is because deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1× 10 -5 The resin may be, for example, polyester, Polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate Aramid, in particular, has a low linear expansion coefficient, making it suitable for flexible substrates. It is suitable as the plate 400.

[0197] This embodiment may be used in conjunction with other embodiments and implementations, at least some of which are described herein. It can be implemented in appropriate combination with the examples.

[0198] (Fourth embodiment) <Transistor manufacturing method 1> A method for fabricating the transistor of FIG. 4 according to the present invention will be explained below with reference to FIGS. 15 to 21. Reveal.

[0199] First, a substrate 400 is prepared.

[0200] Next, an insulator 401 is formed, and an insulator that will become the insulator 301 is formed on the insulator 401. Next, a groove is formed in the insulator that will become the insulator 301, reaching the insulator 401. For example, holes and openings are also included. The grooves may be formed by wet etching, but the grooves may be formed by driving Insulator 401 is preferably formed by etching. It acts as an etching stopper film when etching the insulator that will become No. 1 to form a groove. It is preferable to select an insulator. For example, an insulator that will become the insulator 301 that forms the groove is made of an oxide. When a silicon nitride film is used, the insulator 401 is a silicon nitride film, an aluminum oxide film, or Alternatively, a hafnium oxide film may be used.

[0201] After the grooves are formed, a conductor that will become the conductor 310a or the conductor 310b is deposited. The conductor 310a or the conductor 310b has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. Alternatively, tantalum, tungsten, titanium, molybdenum, aluminum, etc. can be used. It can be a laminated film of aluminum, copper, or molybdenum-tungsten alloy.

[0202] Next, CMP is performed to form the conductor 310a or 310b on the insulator 301. As a result, the conductors 310a and 310b are only present in the grooves. By remaining, it is possible to form a wiring layer with a flat upper surface.

[0203] Alternatively, a conductor to be the conductor 310a or the conductor 310b is formed on the insulator 301. Alternatively, the conductors 310a and 310b may be formed using a lithography method or the like. .

[0204] Next, an insulator 302 is formed on the insulator 301, the conductor 310a, and the conductor 310b. An insulator 303 is deposited on the insulator 302. The insulator 303 is preferably a metal such as hydrogen. It is desirable that the silicon nitride film has a function of suppressing the permeation of impurities and oxygen. The insulator 303 may be formed using a silicon film, an aluminum oxide film, or a hafnium oxide film. The deposition method can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. This can be done.

[0205] Next, the insulator 402 is formed on the insulator 303. Next, oxygen is added to the insulator 402. The process of adding oxygen may be, for example, an ion implantation method, a plating method, or the like. Alternatively, heat treatment using an oxidizing gas may be performed. The oxygen added to 402 becomes excess oxygen.

[0206] Next, the insulator 306a is formed on the insulator 402. Next, oxygen is added to the insulator 306a. The process of adding oxygen may be performed by, for example, ion implantation, The oxygen added to the insulator 306a becomes excess oxygen. Next, a semiconductor 306b is formed on the insulator 306a.

[0207] Next, first heat treatment is preferably performed. Preferably, the temperature is 450°C or higher and 600°C or lower, and more preferably, 520°C or higher and 570°C or lower. The first heat treatment may be performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at a concentration of 10 ppm or more. The first heat treatment is carried out in an atmosphere containing 1% or more or 10% or more of the above. Alternatively, the first heat treatment may be performed in an inert gas atmosphere, followed by desorbing the oxygen. To compensate for the oxygen, the gas is heated in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. Heat treatment may be performed. The first heat treatment can improve the crystallinity of the semiconductor and The first heat treatment can remove impurities such as oxygen and water. A plasma treatment containing oxygen may be performed. The plasma treatment containing oxygen may be performed using, for example, microwaves. It is preferable to use an apparatus having a power supply that generates high density plasma using Even if a plasma power source that applies RF (Radio Frequency) to the substrate side is provided, By using high density plasma, high density oxygen radicals can be generated, By applying RF to the plate side, oxygen radicals generated by high density plasma are efficiently Alternatively, this device can be used to introduce a plasma containing an inert gas into the semiconductor 306b. After the plasma treatment, a plasma treatment containing oxygen may be performed to compensate for the oxygen that has been desorbed. .

[0208] Next, a conductor 414 is formed on the semiconductor 306b (FIGS. 15(A), (B), and (C)). )reference.).

[0209] Next, the conductor 414 is processed by lithography or the like to form the conductor 415. (See Figures 16(A), (B) and (C)).

[0210] Next, the insulator 306a, the semiconductor 306b, and the conductor 415 are formed by lithography or the like. Thus, the insulator 406a, the semiconductor 406b, the conductor 416a1, and the conductor 416 When the conductor 414 is formed, a multilayer film having a conductor layer a2 is formed on the upper surface of the semiconductor 306b. By applying a pressure, a region 407 is formed. The region 407 is formed by applying a pressure to the semiconductor 306b. Since the conductive material 415 has a region where the conductive material 415 is in contact with the semiconductor 306b, the contact resistance between the conductive material 415 and the semiconductor 306b is reduced. When forming the multilayer film, the insulator 402 is also etched, and some regions are thinned. That is, the insulator 402 may have a shape having a convex portion in the region in contact with the multilayer film. This may be the case (see Figures 17(A), (B) and (C)).

[0211] Next, a plasma treatment containing oxygen is performed. By performing the plasma treatment containing oxygen, the conductor The side surface of 416a1 and the top surface of conductor 416a1 are oxidized to form insulator 424a1. In addition, the side surface and the top surface of the conductor 416a2 are oxidized to form the insulator 42. For example, tungsten is used as the conductor 416a1 and the conductor 416a2. When using conductors containing iron and silicon, plasma treatment containing oxygen can The insulators 424a1 and 424a2 are silicon oxide.

[0212] The oxygen-containing plasma treatment may use high-density plasma. By performing the masking treatment, the side surface of the conductor 416a1, the upper surface of the conductor 416a1, and the conductor 416 The side surface of conductor 416a2 and the top surface of conductor 416a2 can be efficiently oxidized.

[0213] Furthermore, by performing plasma treatment containing oxygen, oxygen radicals are generated, and the semiconductor 406 b, the region where the side surfaces of the semiconductor 406b and the insulator 406a are exposed, i.e., This allows excess oxygen to be introduced into the region including the channel formation region, and the oxygen in the channel formation region The protein deficiency can be reduced (see Figures 18(A), (B) and (C)).

[0214] Next, the insulator 406c is deposited. Next, the insulator 412 is deposited over the insulator 406c. .

[0215] Next, a conductor that will become the conductor 404 is formed. The conductive material 404 is formed by processing the conductive material using a photolithography method or the like (see FIGS. 19(A), (B) and See (C).

[0216] Although an example in which the insulators 412 and 406c are not processed is shown here, However, the transistor according to one embodiment of the present invention is not limited thereto. During processing, the insulator 412 and the insulator 406c may be processed by etching. The processing of the conductor 404 and the etching of the insulators 412 and 406c are performed in different ways. It may be performed by a lithography process. Processing may make it easier to create independent shapes for each piece.

[0217] Next, the insulator 410 is formed over the insulator 412 and the conductor 404. For example, the insulator 410 may be formed so that its top surface is flat. Alternatively, for example, the insulator 410 may be formed on the rear surface of the substrate after deposition. By removing the insulator from the top surface so that it is parallel to the reference plane, Such a process is called a planarization process. Planarization processes include CMP, However, the top surface of the insulator 410 does not need to be flat. The insulator 410 may have a multi-layer structure. For example, a plasma containing oxygen may be used. An aluminum oxide film or the like can be formed and stacked using plasma containing oxygen. By forming an aluminum oxide film using the above, the oxygen in the plasma is used as excess oxygen, and the insulating film is The side of the insulator 406c, the side of the semiconductor 406b, and the insulator 406a It can be added to the side of the

[0218] Next, the insulator 408 is deposited over the insulator 410. The insulator 408 is a proton-doped silicon dioxide film containing oxygen. By using plasma to form an aluminum oxide film, the oxygen in the plasma is converted into excess oxygen. 20(A), (B), and (C) .).

[0219] The insulator 408 may have a multi-layer structure. For example, the first layer may be formed by sputtering. A first layer of aluminum oxide may be deposited, and a second layer of aluminum oxide may be deposited by ALD. The first layer is made of aluminum oxide by sputtering, which removes excess oxide from the insulator 410. The second layer is made of aluminum oxide by ALD, This can prevent excess oxygen added to the catalyst from diffusing upward.

[0220] At some point after the formation of the insulator 408, a second heat treatment is performed. By performing the second heat treatment, excess oxygen contained in the insulator 410 or the like is converted into an insulating material. The semiconductor 406b passes through the body 412, the insulator 406c, and the insulator 406a. Therefore, defects (oxygen vacancies) in the semiconductor 406b can be reduced.

[0221] The second heat treatment is performed to remove excess oxygen (oxygen) contained in the insulator 410 and the like from the semiconductor 40. For example, the first heat treatment may be carried out at a temperature at which diffusion occurs up to 6b. Alternatively, the second heat treatment is preferably performed at the same temperature or lower than the first heat treatment. The temperature difference between the first and second heat treatments is 0°C or higher and 150°C or lower, preferably 4°C or lower. The temperature is set to 0° C. or higher and 100° C. or lower. This allows excess oxygen (oxygen) to be released from the insulator 402. The second heat treatment can suppress the release of the fluorine. In some cases, this can be achieved by heating during film formation, and therefore this step may not be necessary.

[0222] Next, using a lithography method, an insulator 408, an insulator 410, an insulator 412, an insulator The conductive material 406c passes through the insulator 402, the insulator 303, and the insulator 302 and reaches the conductive material 310b. and an opening for connecting the insulating material 408, the insulating material 410, the insulating material 412, the insulating material 406c, and the insulating material 414. through the insulator 424a1 or the insulator 424a2 to the conductor 416a1 and the conductor 416a2. and an opening through insulator 408 and insulator 410 to conductor 404. , to form.

[0223] As another method for forming the opening, a conductor is formed on the insulator 408, and an insulating layer is formed on the conductor. and processing the conductor and the insulator using a lithography method. forming a hard mask having the conductor and the insulator, and etching the hard mask; The hard mask may be used as an etching mask to form an opening. By doing so, it is possible to prevent the opening from expanding sideways or being deformed. The hard mask can also be a single layer of insulating or conducting material.

[0224] In addition, each opening can be formed simultaneously using a single lithography process. Multiple lithographic processes may be used to form each opening.

[0225] Next, the conductor 433, the conductor 431, the conductor 429, and the conductor 437 are inserted into each opening. Embed (see Figures 21(A), (B) and (C)).

[0226] Next, on the insulator 408, on the conductor 433, on the conductor 431, on the conductor 429 and on the conductor A conductive material is formed on the substrate 437 and processed by lithography or the like. , the conductor 434, the conductor 432, the conductor 430, and the conductor 438 are formed. This allows the fabrication of the transistor shown in FIG. 4 (FIGS. 4(A), (B), and (C)). reference.).

[0227] <Transistor manufacturing method 2> A method for fabricating the transistor of FIG. 5 according to the present invention will be explained below with reference to FIGS. 22 to 32. Note that the steps up to the formation of the conductor 414 are the same as those in the above-described method for manufacturing a transistor. (See Figures 22(A), (B) and (C)).

[0228] Next, the insulator 306a, the semiconductor 306b, and the conductor 414 are formed by a lithography method or the like. The multilayer film having an insulator 406a, a semiconductor 406b, and a conductor 415 is formed by processing the insulating film 406a. Here, when the conductor 414 is formed, the upper surface of the semiconductor 306b is not damaged. The region 407 is formed by the semiconductor 406b. Therefore, the contact resistance between the conductor 415 and the semiconductor 406b is reduced. When forming a multilayer film, the insulator 402 may also be etched, resulting in some areas becoming thinner. That is, the insulator 402 may have a shape with a convex portion in the area in contact with the multilayer film (see FIG. See 23(A), (B) and (C).

[0229] Next, an insulator 446 is formed, and a conductor 426 is formed over the insulator 446. 6 is formed so as to fill the step portion on the upper surface of the insulator 446. It is preferable to use the MCVD method. In order to improve the adhesion between the conductor 426 and the substrate 446, the conductor 426 is formed by the ALD method. In some cases, it may be preferable to form a multilayer film with a conductor formed by MCVD. A layer of titanium may be formed by ALD, and then a layer of tungsten may be formed by MCVD. .

[0230] Next, an insulator 427 is formed on the conductor 426 (FIGS. 24(A), (B), and (C)). reference.).

[0231] Next, the first layer is applied to the insulator 427 and the conductor 426 until the thickness of the conductor 426 is reduced to about half. The CMP process is performed. The slurry (chemical containing abrasive grains) used in the first CMP process is It is desirable to use a slurry suitable for the above (see Figures 25(A), (B) and (C)). .

[0232] Next, the remaining conductor 426 and insulator 446 are exposed and insulated. A second CMP process is performed until the surface of the body 446 is planarized to form the insulator 409. In the second CMP process, the polishing rate of the insulator 446 is higher than the polishing rate of the conductor 426. It is desirable to use a slurry prepared so that the rate of change is as slow as possible. This is preferable because the flatness of the surface of the insulator 446 can be further improved. The CMP processing equipment may then generate an end signal indicating that the insulator 446 has been exposed in the second CMP process. It is more preferable that the second CMP process has a point detection function. This is preferable because it may improve the film thickness controllability of the insulator 446 later (FIGS. 26(A) and 26(B)). ) and (C).

[0233] Alternatively, the insulating layer 446 may be formed without forming a conductor on the insulator 446 and an insulator on the conductor. The insulator 409 may be formed on the body 446 by performing a CMP process or the like so that the top surface is flat. Alternatively, the insulator 446 may have a flat top surface immediately after deposition. The upper surface of the edge 446 does not have to be flat.

[0234] Next, a resist mask 423 is formed on the insulator 409 by lithography or the like. In order to improve the adhesion between the upper surface of the insulator 409 and the resist mask, For example, an organic film may be provided between the insulator 409 and the resist mask 423. A single layer of a conductor or a laminated film of a conductor and an insulator is formed on the insulating film 409, and then the insulating film is formed by lithography. A hard mask may be formed by the CVD method (see FIGS. 27(A), (B) and (C)). ).

[0235] Next, the insulator 409 is processed by dry etching until it reaches the insulator 402. , forming an insulator 410. At this time, etching is performed until the insulator 402 reaches the insulator 303. It may be censored.

[0236] Next, the conductor 415 is processed by dry etching to form a conductor 416a1 and conductor 416a2.

[0237] At this time, the semiconductor 406b has an exposed area. This region 407 may be removed by etching the conductor 415 as described above (FIG. 28). See (A), (B) and (C).

[0238] When the above processing is performed by dry etching, the exposed area of ​​the semiconductor 406b is etched. Impurities such as residual gas components may adhere to the surface. For example, if chlorine is used as an etching gas, If a hydrocarbon gas is used as an etching gas, chlorine may adhere to the surface. When using nitrogen-based gases, carbon and hydrogen may adhere to the surface. If the substrate is exposed to the atmosphere after the process, the exposed area of ​​the semiconductor 406b may corrode. Therefore, if plasma treatment using oxygen gas is performed consecutively after processing by dry etching, Impurities can be removed to prevent corrosion of the exposed areas of the semiconductor 406b. preferable.

[0239] Alternatively, impurities can be removed by, for example, washing with diluted hydrofluoric acid or ozone. A cleaning treatment using a cleaning agent such as a fluorine-containing solvent may be performed. A plurality of cleaning treatments may be combined. As a result, the exposed region of the semiconductor 406b, in other words, the channel forming region, becomes highly resistive. become.

[0240] On the other hand, the conductors 416a1 and 416a2 and the upper surface of the semiconductor 406b are in contact with each other. The region 407 overlapping the conductors 416a1 and 416a2 and the semiconductor The contact resistance between 406b is reduced, and good transistor characteristics can be obtained. I wish.

[0241] Next, a plasma treatment containing oxygen is performed. By performing the plasma treatment containing oxygen, the conductor The side of the conductor 416a1 is oxidized to form an insulator 424a1. The surface is oxidized to form insulator 424a2. For example, conductor 416a1 and conductor 4 When a conductor containing tungsten and silicon is used as 16a2, By performing the plasma treatment, the insulators 424a1 and 424a2 are formed of silicon oxide. This becomes:

[0242] The oxygen-containing plasma treatment may use high-density plasma. By performing the masking process, the side surfaces of the conductor 416a1 and the conductor 416a2 can be efficiently It can be oxidized.

[0243] Furthermore, by performing plasma treatment containing oxygen, oxygen radicals are generated, and the semiconductor 406 b, the region where the side surfaces of the semiconductor 406b and the insulator 406a are exposed, i.e., This allows excess oxygen to be introduced into the region including the channel formation region, and the oxygen in the channel formation region The protein deficiency can be reduced (see Figures 29(A), (B) and (C)).

[0244] Next, an insulator to be the insulator 406c is formed, and an insulator is formed on the insulator to be the insulator 406c. The insulator that will become the insulator 406c and the insulator that will become the insulator 412 are formed. The insulator is formed by the insulator 410, the conductor 416a1, and the conductor 416a2. A film is formed with a uniform thickness on the side and bottom of the opening. Therefore, it is possible to use the ALD method. preferable.

[0245] Next, a film of a conductor that will become the conductor 404 is formed. It can be performed using methods such as sputtering, CVD, MBE, PLD, or ALD. The conductor that becomes the conductor 404 fills the opening formed by the insulator 410 or the like. Therefore, it is preferable to use the CVD method (especially the MCVD method). In addition, in order to improve the adhesion between the conductor 404 and the insulator 410, etc., It is preferable to form a multilayer film of a conductor formed by the D method or the like and a conductor formed by the MCVD method. For example, titanium nitride or tantalum nitride may be deposited by the ALD method. Next, a tungsten film is formed by MCVD.

[0246] Next, from the top surface of the conductor that will become the conductor 404, the conductor that will become the conductor 404, the insulator 412 The insulator to be formed on the insulator 410 and the insulator to be formed on the insulator 406c are formed on the insulator 410 by using CMP or the like. The conductor 404, the insulator 412, and the insulator 406c are polished and planarized until the surface is reached. As a result, the conductor 404 having the function of a gate electrode is formed by lithography. It can be formed in a self-aligned manner without using a gate electrode. The conductor 404 and the conductor 416a1 functioning as a source electrode or a drain electrode are The conductor 416a1 has a function as a gate electrode without considering the alignment accuracy with the conductor 416a2. Since the conductive material 404 can be formed, the area of ​​the semiconductor device can be reduced. Since the roughing process is no longer necessary, productivity is expected to improve due to process simplification (Figure 30(A) ), (B) and (C).

[0247] Next, an insulator 418 is deposited on the insulators 410, 412, and 406c. The insulator 408 is formed on the insulator 418. The insulator 408 is formed by, for example, a method using a silicon dioxide containing oxygen. By forming an aluminum oxide film using a plasma that generates excess oxygen, As an element, it can be added to the top surface of the insulator 418.

[0248] At some time after the deposition of the insulator that will become the insulator 408, a second heating By performing the second heat treatment, excess acid contained in the insulator 418 can be removed. The electrons pass through the insulator 410, the insulator 402, and the insulator 406a to the semiconductor 406b. In addition, excess oxygen contained in the insulator 418 passes through the insulator 412 and flows into the semiconductor 406. b. Also, excess oxygen contained in the insulator 418 passes through the insulator 406c and moves to the semi-conductor layer 406b. In this way, excess oxygen travels to the semiconductor 406b via three routes. Since the oxygen ions move in the semiconductor 406b, defects (oxygen vacancies) in the semiconductor 406b can be reduced.

[0249] Note that the second heat treatment is performed to convert excess oxygen (oxygen) contained in the insulator 418 into the semiconductor 406b. For example, the description of the first heat treatment may be referred to. Alternatively, the second heat treatment is preferably performed at a temperature lower than that of the first heat treatment. The temperature difference between the first heat treatment and the second heat treatment is 20°C or more and 150°C or less, preferably 40°C or more. The temperature is set to 100° C. or less. This causes excess oxygen (oxygen) to be released from the insulator 402. The second heat treatment can be performed by applying the same heat treatment as that performed when forming each layer. In some cases, this step may not be necessary if heating can be used to achieve both.

[0250] Next, an insulator 428 is deposited over the insulator 408. The insulator 428 is deposited by sputtering. This can be done using a method such as a CVD method, an MBE method, a PLD method, or an ALD method (see Figure 1). See 31(A), (B) and (C).

[0251] Next, the insulator 428, the insulator 408, the insulator 418, and the insulator The wire passes through the conductor 410, the insulator 402, the insulator 303, and the insulator 302 to reach the conductor 310b. and an opening through the insulator 428, the insulator 408, the insulator 418, and the insulator 410. The openings reach the conductor 416a1 and the conductor 416a2, and the openings reach the insulator 428, the insulator 408, and the and an opening through the insulator 418 to the conductor 404.

[0252] As another method for forming the opening, a conductor is formed on the insulator 428, and an insulating layer is formed on the conductor. and processing the conductor and the insulator using a lithography method. forming a hard mask having the conductor and the insulator, and etching the hard mask; The hard mask may be used as an etching mask to form an opening. By doing so, it is possible to prevent the opening from expanding sideways or being deformed. The hard mask can also be a single layer of insulating or conducting material.

[0253] In addition, each opening can be formed simultaneously using a single lithography process. Multiple lithographic processes may be used to form each opening.

[0254] Next, the conductor 433, the conductor 431, the conductor 429, and the conductor 437 are inserted into each opening. Embed (see Figures 32(A), (B) and (C)).

[0255] Next, on the insulator 428, on the conductor 433, on the conductor 431, on the conductor 429 and on the conductor A conductive material is formed on the substrate 437 and processed by lithography or the like. , the conductor 434, the conductor 432, the conductor 430, and the conductor 438 are formed. This allows the fabrication of the transistor shown in FIG. 5 (FIGS. 5(A), (B), and (C)). reference.).

[0256] This embodiment may be used in conjunction with other embodiments and implementations, at least some of which are described herein. It can be implemented in appropriate combination with the examples.

[0257] (Embodiment 5) <Storage device 1> A memory device using a transistor according to one embodiment of the present invention and capable of storing stored contents even when power is not supplied An example of a semiconductor device (memory device) that can retain data and has no limit on the number of times it can be written is shown in Figure 3. Shown in 3.

[0258] The semiconductor device shown in FIG. 33A includes a transistor 3200 using a first semiconductor and a second semiconductor. The semiconductor device includes a transistor 3300 and a capacitor 3400. The transistor 3300 can be any of the transistors described above.

[0259] The transistor 3300 is preferably a transistor with low off-state current. For example, a transistor using an oxide semiconductor can be used as the transistor 300. The low off-state current of the STAR 3300 allows for long-term storage of specific nodes in the semiconductor device. It is possible to retain the stored contents, i.e., no refresh operation is required, and This allows for extremely low frequency refresh operations, resulting in low power consumption. It becomes a conductor device.

[0260] In FIG. 33A, a first wiring 3001 is electrically connected to the source of a transistor 3200. The second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300. The fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the source of the transistor 3300 are connected to each other. The other of the drains is electrically connected to one electrode of the capacitor 3400 and is connected to the fifth wiring 3 005 is electrically connected to the other electrode of the capacitor 3400 .

[0261] The semiconductor device shown in FIG. 33A can hold the potential of the gate of the transistor 3200. This property makes it possible to write, store, and read information, as shown below. be.

[0262] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to The transistor 3300 is set to a potential at which it becomes conductive, thereby making the transistor 3300 conductive. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 3200 and The voltage is applied to a node FG electrically connected to one electrode of the capacitor 3400. A predetermined charge is applied to the gate of the transistor 3200 (write). The charges that give two potential levels (hereinafter referred to as low-level charge and high-level charge) ) is applied. Then, the potential of the fourth wiring 3004 is applied to the transistor 330 0 is set to a potential at which the transistor 3300 is in a non-conducting state, thereby making the transistor 3300 in a non-conducting state. , the charge is retained at node FG (retention).

[0263] Since the off-state current of the transistor 3300 is small, the charge of the node FG is maintained for a long period of time. Retained.

[0264] Next, reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the second wiring The line 3002 takes on a potential corresponding to the amount of charge held in the node FG. If the transistor 3200 is an n-channel type, a high level voltage is applied to the gate of the transistor 3200. The apparent threshold voltage V under load th_H is a transistor 3200 The apparent threshold voltage V when a low-level charge is applied to the gate of th_L Here, the apparent threshold voltage is the voltage at which the transistor 3200 The potential of the fifth wiring 3005 required to make the fifth wiring 3005 in a "conducting state" is therefore The potential of the wiring 3005 is V th_H and V th_L By setting the potential between For example, in a write operation, a high charge is applied to node FG. When the h level charge is applied, the potential of the fifth wiring 3005 becomes V0 (>V th_ H ), the transistor 3200 is in a "conducting state." On the other hand, if the node FG is low, When a level charge is applied, the potential of the fifth wiring 3005 becomes V0 ( <V th_L ), transistor 3200 remains in a "non-conducting state." The potential of the wiring 3002 is determined to read data stored in the node FG. can be done.

[0265] When memory cells are arranged in an array, the information of a desired memory cell is read out. For example, in a memory cell that does not read information, A potential at which the transistor 3200 is in a "non-conducting state" regardless of the potential applied to the node FG. In other words, V th_H By applying a lower potential to the fifth wiring 3005, a desired memory cell Alternatively, in the case of a memory cell from which information is not read, In this case, the transistor 3200 is in a "conducting state" regardless of the potential applied to the node FG. The potential at the th_L By applying a higher potential to the fifth wiring 3005, a desired It is only necessary to have a configuration in which only the information in the memory cells can be read out.

[0266] <Semiconductor device structure 1> 34 is a cross-sectional view of the semiconductor device corresponding to FIG. 33(A). The device includes a transistor 3200, a transistor 3300, and a capacitor 3400. The transistor 3300 and the capacitor 3400 are connected to the upper side of the transistor 3200. The transistor 3300 is the transistor shown in FIG. 1 is used as the capacitor element 3400. The semiconductor device according to one embodiment of the present invention is not limited to this. Please refer to the description of the capacitor and the capacitance element.

[0267] The semiconductor device shown in FIG. 34 is a case where a transistor 3200 is a Fin type. By making the transistor 3200 a fin type, the effective channel width is increased. By doing so, the on-state characteristics of the transistor 3200 can be improved. Since the contribution of the electric field of the gate electrode can be increased, the off-characteristics of the transistor 3200 can be improved. The transistor 3200 is a transistor using a semiconductor substrate 450. The transistor 3200 is formed by a region 474a in the semiconductor substrate 450 and a region 474b in the semiconductor substrate 450. 450, an insulator 462, and a conductor 454.

[0268] In transistor 3200, regions 474a and 474b are source and drain regions. The insulator 462 also functions as a gate insulator. The conductor 454 also functions as a gate electrode. The resistance of the channel forming region can be controlled by the potential applied to the electrode 454 . That is, the potential applied to the conductor 454 causes conduction between the region 474a and the region 474b. Non-conduction can be controlled.

[0269] The semiconductor substrate 450 may be, for example, a single semiconductor substrate such as silicon or germanium. or silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide A compound semiconductor substrate made of lead or gallium oxide may be used. A single crystal silicon substrate is used as the plate 450 .

[0270] The semiconductor substrate 450 is a semiconductor substrate containing impurities that impart n-type conductivity. However, a semiconductor substrate having impurities that impart p-type conductivity is used as the semiconductor substrate 450. In this case, the region that will become the transistor 3200 is given n-type conductivity. Alternatively, if the semiconductor substrate 450 is an i-type, It's okay.

[0271] The upper surface of the semiconductor substrate 450 preferably has a (110) surface. The on-state characteristics of the transistor 3200 can be improved.

[0272] Regions 474a and 474b are regions containing impurities that impart p-type conductivity. In this way, the transistor 3200 constitutes a p-channel transistor.

[0273] Although the transistor 3200 is a p-channel transistor, The transistor 3200 may be an n-channel transistor.

[0274] Note that the transistor 3200 is separated from adjacent transistors by a region 460 or the like. The region 460 is an insulating region.

[0275] The semiconductor device shown in FIG. 34 includes an insulator 464, an insulator 466, an insulator 468, and an insulator Insulator 470, insulator 472, insulator 475, insulator 402, insulator 410, and insulator Insulator 408, insulator 428, insulator 465, insulator 467, insulator 469, and insulator Conductor 498, conductor 480a, conductor 480b, conductor 480c, and conductor 478a , conductor 478b, conductor 478c, conductor 476a, conductor 476b, and conductor Conductor 476c, conductor 479a, conductor 479b, conductor 479c, and conductor 477 a, conductor 477b, conductor 477c, conductor 484a, conductor 484b, and conductor Conductor 484c, conductor 484d, conductor 483a, conductor 483b, and conductor 48 3c, a conductor 483d, a conductor 483e, a conductor 483f, and a conductor 485a, Conductor 485b, conductor 485c, conductor 485d, conductor 487a, and conductor 4 87b, conductor 487c, conductor 488a, conductor 488b, and conductor 488c. , conductor 490a, conductor 490b, conductor 489a, conductor 489b, and conductor 491a, conductor 491b, conductor 491c, conductor 492a, and conductor 492b , conductor 492c, conductor 494, conductor 496, insulator 406a, semiconductor 40 6b and an insulator 406c.

[0276] The insulator 464 is disposed on the transistor 3200. The insulator 466 is disposed on the insulator 464. Insulator 468 is disposed on insulator 466. Insulator The insulator 470 is disposed on the insulator 468. The insulator 472 is disposed on the insulator 470. The insulator 475 is disposed over the insulator 472. The transistor 3300 is , and is disposed on the insulator 475. Also, the insulator 408 is disposed on the transistor 3300. The insulator 428 is disposed on the insulator 408. The insulator 465 is disposed on the insulator 408. 428. The capacitor element 3400 is disposed on the insulator 465. , an insulator 469 is disposed on the capacitive element 3400 .

[0277] The insulator 464 has an opening that reaches the region 474a, an opening that reaches the region 474b, and a conductive The openings also include openings that reach the conductors 480a and 454. The conductor 480b or the conductor 480c is embedded.

[0278] Insulator 466 also has an opening that reaches conductor 480a and an opening that reaches conductor 480b. The openings each have a mouth and an opening that reaches the conductor 480c. The conductive body 478a, the conductive body 478b, or the conductive body 478c is embedded therein.

[0279] Insulator 468 also has an opening that reaches conductor 478a and an opening that reaches conductor 478b. The openings each have a mouth and an opening that reaches the conductor 478c. The conductive body 476a, the conductive body 476b, or the conductive body 476c is embedded therein.

[0280] In addition, a conductor 479a in contact with the conductor 476a and a conductor 476b are provided over the insulator 468. and a conductor 479c in contact with the conductor 476c. , insulator 472 has an opening through insulator 470 to conductor 479a, and insulator 47 479b through insulator 470 and to conductor 479c. The openings each have a conductor 477a, 477b, or 477c. 77c is embedded.

[0281] The insulator 475 has an opening overlapping the channel formation region of the transistor 3300 and An opening reaching the conductor 477a, an opening reaching the conductor 477b, and an opening reaching the conductor 477c. The openings are provided with conductors 484d and 484e, respectively. a, the conductor 484b or the conductor 484c is embedded.

[0282] The conductor 484d also functions as the bottom gate electrode of the transistor 3300. Alternatively, for example, a constant potential may be applied to the conductor 484d. The electrical characteristics of the transistor 3300, such as the threshold voltage, may be controlled. The conductor 484d may be electrically connected to the top gate electrode of the transistor 3300. This allows the on-state current of the transistor 3300 to be increased. In addition, the punch-through phenomenon can be suppressed, so that the saturation region of the transistor 3300 The electrical characteristics can be stabilized.

[0283] In addition, the insulator 402 has an opening that reaches the conductor 484a and an opening that reaches the conductor 484c. It has a mouth and an opening that reaches the conductor 484b.

[0284] Also, insulator 428 provides electrical conduction through insulators 408, 410, and 402. Three openings leading to the conductor 484a, the conductor 484b and the conductor 484c, and the insulator 40 8 through insulator 410 and insulator 402 to the source electrode or drain of transistor 3300. Two openings leading to one conductor of the rain electrode and through the insulators 408 and 410. and an opening that reaches the conductor of the gate electrode of the transistor 3300. The mouths are provided with conductors 483a, 483b, 483c, and 483e. , a conductor 483f or a conductor 483d is embedded.

[0285] In addition, a conductor 485a in contact with the conductors 483a and 483e is provided over the insulator 428. The conductor 485b contacts the conductor 483b, and the conductors 483c and 483f contact each other. The insulating layer 485 includes a conductor 485c that is in contact with the conductor 483d and a conductor 485d that is in contact with the conductor 483d. Body 465 has an opening that reaches conductor 485a, an opening that reaches conductor 485b, and a conductive The openings have openings that reach the conductors 487a and 485c. The conductor 487b or the conductor 487c is embedded.

[0286] In addition, a conductor 488a in contact with the conductor 487a, a conductor 487b, and a The conductor 488b is in contact with the conductor 487c, and the conductor 488c is in contact with the conductor 487c. The insulator 467 has an opening that reaches the conductor 488a, an opening that reaches the conductor 488b, and In addition, a conductor 490a or a conductor 490b is embedded in the opening. The conductor 488c is in contact with the conductor 494 of one electrode of the capacitor 3400. are.

[0287] In addition, a conductor 489a in contact with the conductor 490a and a conductor 490b are provided on the insulator 467. The insulator 469 has a conductor 489b that is in contact with the conductor 489a. An opening, an opening that reaches the conductor 489b, and a conductor that is the other electrode of the capacitor 3400 The openings are provided with conductors 491a and 496, respectively. The conductor 491b or the conductor 491c is embedded therein.

[0288] In addition, a conductor 492a in contact with the conductor 491a and a conductor 491b are formed on the insulator 469. The conductor 492b is in contact with the conductor 491b, and the conductor 492c is in contact with the conductor 491c.

[0289] Insulator 464, Insulator 466, Insulator 468, Insulator 470, Insulator 472, Insulator 4 75, insulator 402, insulator 410, insulator 408, insulator 428, insulator 465, insulation The insulator 467, the insulator 469, and the insulator 498 may be, for example, boron, carbon, nitrogen, or oxide. silicon, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium , germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or The insulator containing tantalum may be used as a single layer or a multilayer. For example, an insulator formed by oxidizing the conductor 494 may be used. Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttria oxide ammonium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tungsten oxide a multi-layer structure with metal oxides such as aluminum, silicon oxide, silicon nitride oxide, or silicon nitride, etc. It can also be a layered film.

[0290] Insulator 464, Insulator 466, Insulator 468, Insulator 470, Insulator 472, Insulator 4 75, insulator 402, insulator 410, insulator 408, insulator 428, insulator 465, insulation One or more of the insulator 467, the insulator 469, or the insulator 498 may be configured to trap impurities such as hydrogen and oxygen. It is preferable to have an insulator with a blocking function. By placing an insulator that has the function of blocking impurities such as hydrogen and oxygen, This allows the electrical characteristics of the transistor 3300 to be stable.

[0291] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include fluorine, Uron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine , argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium Insulators containing titanium, hafnium or tantalum may be used in single or multilayer configurations.

[0292] Conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478 b, conductor 478c, conductor 476a, conductor 476b, conductor 476c, conductor 479 a, conductor 479b, conductor 479c, conductor 477a, conductor 477b, conductor 477 c, conductor 484a, conductor 484b, conductor 484c, conductor 484d, conductor 483 a, conductor 483b, conductor 483c, conductor 483d, conductor 483e, conductor 48 3f, conductor 485a, conductor 485b, conductor 485c, conductor 485d, conductor 48 7a, conductor 487b, conductor 487c, conductor 488a, conductor 488b, conductor 48 8c, conductor 490a, conductor 490b, conductor 489a, conductor 489b, and conductor 491a, conductor 491b, conductor 491c, conductor 492a, conductor 492b, conductor The conductors 492c, 494, and 496 may include, for example, boron, nitrogen, oxygen, fluorine, and the like. Fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel , copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, Conductors containing one or more of indium, tin, tantalum and tungsten, in a single layer or For example, an alloy or a compound may be used, and a conductor containing aluminum may be used. , conductors containing copper and titanium, conductors containing copper and manganese, conductors containing indium, tin and and oxygen-containing conductors, titanium and nitrogen-containing conductors, tungsten and silicon-containing conductors A conductor containing fluorine may also be used.

[0293] The semiconductor 406b is preferably an oxide semiconductor. (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide , aluminum gallium arsenide, indium phosphide, gallium nitride, or organic semiconductors. There are cases where it is okay to have them.

[0294] The insulators 406a and 406c are made of a material other than oxygen that constitutes the semiconductor 406b. It is preferable to use an oxide composed of one or more elements, or two or more elements. Silicon (including strained silicon), germanium, silicon germanium, silicon carbide, Lithium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride or organic semiconductor In some cases, it is acceptable to use your body or other objects.

[0295] The source or drain of transistor 3200 is connected to conductor 480a and conductor 478a. , conductor 476a, conductor 479a, conductor 477a, conductor 484a, and conductor of the transistor 3300 via the conductor 483a, the conductor 485a, and the conductor 483e. It is electrically connected to a conductor that is either a source electrode or a drain electrode. Conductor 454, which is the gate electrode of gate electrode 3200, is connected to conductors 480c and 478c. , conductor 476c, conductor 479c, conductor 477c, conductor 484c, and conductor 483c, conductor 485c, and conductor 483f. The source electrode and the drain electrode are electrically connected to the conductor.

[0296] The capacitor 3400 is connected to one of the source electrode and the drain electrode of the transistor 3300. an electrode, a conductor 483f, a conductor 485c, a conductor 487c, and a conductor 488c; The conductor 494, which is one electrode of the capacitor 3400, is electrically connected to the insulating layer 492 through an insulating layer. The capacitor 3400 has a conductor 498 and a conductor 496 which is the other electrode of the capacitor 3400. The capacitor 3400 can be formed above or below the transistor 3300 to form a semiconductor device. This is advantageous because it allows the size of the device to be reduced.

[0297] In this embodiment, a transistor 3300 is provided over a transistor 3200. Although an example of a semiconductor device having a capacitor element 3400 on a transistor 3300 has been shown, 3200 has one or more transistors having the same semiconductor as the transistor 3300 Alternatively, a capacitor 3400 may be provided over the transistor 3200, The transistor 3300 may be provided over the capacitor 3400. This allows the integration density of the semiconductor device to be further increased (see FIG. 35).

[0298] For other structures, please refer to the descriptions in Figure 4 etc. as appropriate.

[0299] <Storage device 2> The semiconductor device shown in FIG. 33B is different from the semiconductor device shown in FIG. 33A in that it does not include the transistor 3200. This is different from the semiconductor device shown in FIG. This allows information to be written and retained.

[0300] How to read data from the semiconductor device shown in FIG. When the capacitor 3300 is brought into a conductive state, the third wiring 3003 and the capacitor element 340, which are in a floating state, 0 is electrically connected, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is The potential of one electrode of the capacitor 3400 (or the charge stored in the capacitor 3400) and take different values.

[0301] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the The capacitance component of the third wiring 3003 is CB, and the capacitance of the third wiring 3003 before the charge is redistributed is If the potential of the third wiring 3003 after the charge is redistributed is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB ×VB0+C×V) / (CB+C). Therefore, the state of the memory cell is The potential of one electrode of the element 3400 takes two states: V1 and V0 (V1>V0). and the potential of the third wiring 3003 when the potential V1 is maintained (=(CB×VB0+C× V1) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is maintained. =(CB×VB0+C×V0) / (CB+C)).

[0302] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. This can be done.

[0303] In this case, the first semiconductor is applied to a driving circuit for driving the memory cell. A transistor in which a second semiconductor is applied as the transistor 3300. may be stacked on the drive circuit.

[0304] The semiconductor device described above includes a transistor using an oxide semiconductor and having low off-state current. By using this function, it is possible to retain the memory contents for a long period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, a semiconductor device with low power consumption can be realized. Even if the potential is fixed, it is possible to store it for a long period of time. The content can be preserved.

[0305] Furthermore, since the semiconductor device does not require a high voltage to write information, deterioration of the elements does not occur. For example, unlike conventional non-volatile memory, the flow of electrons to the floating gate Since there is no injection or extraction of electrons from the floating gate, there is no degradation of the insulator. That is, the semiconductor device according to one embodiment of the present invention does not have the same problem as the conventional nonvolatile memory. There is no limit to the number of times that data can be rewritten, which is a problem in the past, and reliability has improved dramatically. Furthermore, information is written depending on whether the transistor is conductive or non-conductive. This embodiment is at least partially based on the principles of the present invention. The present invention can be implemented in appropriate combination with other embodiments and examples described herein.

[0306] (Sixth embodiment) <Semiconductor device structure 2> In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in FIG. This will be explained with reference to the following. <Cross-sectional structure> 36(A) and 36(B) are cross-sectional views of a semiconductor device according to one embodiment of the present invention. ), the X1-X2 direction is the channel length direction, and in FIG. 36(B), the Y1-Y2 direction The semiconductor device shown in FIGS. 36(A) and 36(B) has a first A transistor 2200 made of a semiconductor material is provided on top of a transistor made of a second semiconductor material. 36(A) and (B), a second semiconductor material is used. 4 is used as the transistor 2100. do.

[0307] The first and second semiconductor materials preferably have different band gaps. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon (strained silicon) (including), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum arsenide (e.g., aluminum gallium phosphide, indium phosphide, gallium nitride, organic semiconductors, etc.), and the second semiconductor The conductive material can be an oxide semiconductor. On the other hand, transistors using oxide semiconductors can be easily operated at high speed. The transistor can have excellent characteristics by applying the transistor exemplified in the above embodiment. It is possible to obtain low threshold characteristics and make a fine transistor. The high switching speed allows for high-speed operation, and the low off-state current reduces leakage current.

[0308] The transistor 2200 may be an n-channel transistor or a p-channel transistor. Either transistor or transistors may be used, and an appropriate transistor may be used depending on the circuit. In addition to using a transistor of one embodiment of the present invention using an oxide semiconductor, the materials and structure used are For example, the specific configuration of the semiconductor device does not need to be limited to that shown here.

[0309] In the configuration shown in FIGS. 36(A) and 36(B), an insulator 2200 is provided on the top of the transistor 2200. 201, a transistor 2100 is provided via an insulator 2207 and an insulator 2208. In addition, a plurality of wirings 22 are provided between the transistor 2200 and the transistor 2100. 02 is provided. In addition, a plurality of plugs 2203 embedded in various insulators are provided. The wiring and electrodes provided on the upper and lower layers are electrically connected. An insulator 2204 is provided to cover the sintered body 2100, and a wiring 2205 is provided on the insulator 2204. are.

[0310] In this way, stacking two types of transistors reduces the area occupied by the circuit. , multiple circuits can be arranged at higher density.

[0311] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, The hydrogen in the insulator provided near the semiconductor film of the transistor 2200 is converted into silicon dioxide. This has the effect of terminating green bonds and improving the reliability of the transistor 2200. When an oxide semiconductor is used for the transistor 2100 provided in the upper layer, Hydrogen in the insulator provided near the semiconductor film 100 generates carriers in the oxide semiconductor. This may be one of the factors that cause the transistor 2100 to become less reliable. Therefore, an oxide film is formed on the upper layer of the transistor 2200 using a silicon-based semiconductor material. When the transistor 2100 using a nitride semiconductor is stacked, hydrogen diffusion occurs between the transistors. It is particularly effective to provide an insulator 2207 having the function of preventing diffusion. 07, the reliability of the transistor 2200 is improved by confining hydrogen in the lower layer. In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, so that the transistor 2100 At the same time, the reliability of the system can be improved.

[0312] The insulator 2207 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0313] In addition, a transistor 2100 including an oxide semiconductor film is formed on the transistor 2100 so as to cover the transistor 2100. It is preferable to form a blocking film on the resistor 2100, which has the function of preventing hydrogen diffusion. The blocking film can be made of the same material as the insulator 2207, and in particular It is preferable to use aluminum oxide, which is a film that is formed by depositing the underlying insulating layer. Excess oxygen can be added to the body, and the thermal process will cause the excess oxygen to The oxide semiconductor layer is then migrated to the oxide semiconductor layer, and defects in the oxide semiconductor layer are repaired. The aluminum membrane is impermeable to both impurities such as hydrogen and moisture, and oxygen. Therefore, the blocking effect is high. By using an aluminum oxide film as the insulating film, the oxide film included in the transistor 2100 Preventing oxygen from being released from the semiconductor film and preventing water and hydrogen from being mixed into the oxide semiconductor film The blocking film can be prevented by laminating the insulator 2204. It may be used or provided underneath the insulator 2204.

[0314] The transistor 2200 is not limited to a planar transistor, but may be of various types. For example, FIN type, TRI-GATE type The transistors can be of a tri-gate type. An example of a cross section of such a transistor is shown below. 36(E) and (F). An insulator 2212 is provided on a semiconductor substrate 2211. The semiconductor substrate 2211 has a protrusion with a thin tip (also called a fin). An insulator may be provided on the protrusion. The insulator is formed when the protrusion is formed. This acts as a mask to prevent the semiconductor substrate 2211 from being etched. The tip of the protrusion does not have to be thin. For example, the protrusion may be a substantially rectangular parallelepiped protrusion. The gate insulator 2214 may be thick on the protrusion of the semiconductor substrate 2211. On the semiconductor substrate 2211, a gate electrode 2213 is provided. In this case, a source region and a drain region 2215 are formed. Although an example in which the substrate 2211 has a protrusion is shown, a semiconductor device according to one embodiment of the present invention may have a protrusion. For example, a semiconductor region having a protrusion may be formed by processing an SOI substrate. It's okay.

[0315] This embodiment may be used in conjunction with other embodiments and implementations, at least some of which are described herein. It can be implemented in appropriate combination with the examples.

[0316] (Embodiment 7) [CMOS Circuit] The circuit diagram shown in FIG. 36C is a circuit diagram of a p-channel transistor 2200 and an n-channel transistor The transistors 2100 are connected in series and the gates of the transistors are connected together. The configuration of the OS circuit is shown.

[0317] [Analog Switch] The circuit diagram shown in FIG. 36(D) shows the transistors 2100 and 2200. The figure shows a configuration in which the source and drain of each are connected. This embodiment can function as a so-called analog switch. Some of these may be implemented in appropriate combination with other embodiments and examples described in this specification. It is possible.

[0318] (Embodiment 8) <cpu> Hereinafter, a CPU including semiconductor devices such as the above-mentioned transistors and the above-mentioned memory devices will be described. We will explain about this.

[0319] FIG. 37 is a block diagram showing the configuration of an example of a CPU that uses the above-described transistor in part. is.

[0320] The CPU shown in FIG. 37 includes an ALU 1191 (Arithmetic and logic unit) on a board 1190. tic logic unit, arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. 1199 and the ROM interface 1189 may be provided on separate chips. The CPU shown in FIG. 37 is merely an example of a simplified configuration, and an actual CPU may differ from the For example, the CPU or the arithmetic circuit shown in Figure 37 A configuration including a path is considered to be one core, and multiple such cores are included, and each core operates in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit and data bus can be For example, it can be 8-bit, 16-bit, 32-bit, 64-bit, etc.

[0321] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, Interrupt controller 1194, register controller 1197, timing controller It is entered into La1195.

[0322] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to trigger the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it accordingly. Generates an address and reads or writes register 1196 depending on the CPU state. .

[0323] In the CPU shown in FIG. 37, a memory cell is provided in the register 1196. The above-mentioned transistors and memory devices can be used as memory cells of the memory cell 1196. Cut.

[0324] In the CPU shown in FIG. 37, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 6, data is held by a flip-flop or a capacitance element. If data is held by a flip-flop, the data is held by the flip-flop. If selected, the power supply voltage is supplied to the memory cells in the register 1196 . If data retention in the capacitor is selected, data rewriting to the capacitor is This allows the supply of power supply voltage to the memory cells in register 1196 to be stopped.

[0325] FIG. 38 is a circuit diagram of an example of a storage element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 in which memory data is not volatile, a switch 1203, a switch 1204, and a logic The circuit includes an element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory element 1200 may include a diode, a resistor, an inductor, etc., as needed. It may further include other elements such as a converter.

[0326] Here, the above-described memory device can be used for the circuit 1202. When the supply of power supply voltage to GND is stopped, the gate of transistor 1209 in circuit 1202 is GND (0V) or a potential that turns off the transistor 1209 is continuously input. For example, if the gate of the transistor 1209 is grounded via a load such as a resistor, do.

[0327] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first transistor 1214 of the switch 1203 is used. The terminal corresponds to one of the source and drain of the transistor 1213, and the first terminal of the switch 1203. The terminal 2 corresponds to the other of the source and drain of the transistor 1213, and the terminal 3 corresponds to the other of the source and drain of the switch 1203. The first terminal and the second terminal are connected by a control signal RD input to the gate of the transistor 1213. Conduction or non-conduction between the terminals of (i.e., the conductive or non-conductive state of transistor 1213) The first terminal of the switch 1204 is connected to the source of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the transistor 1214. The switch 1204 connects the input to the gate of the transistor 1214. The control signal RD determines whether the first terminal and the second terminal are electrically connected or disconnected (i.e., , the conductive or non-conductive state of transistor 1214) is selected.

[0328] One of the source and drain of the transistor 1209 is connected to one of the pair of electrodes of the capacitor 1208. The gate of the transistor 1210 is electrically connected to one of the gates of the transistor 1210. The part is designated as node N2. One of the source and drain of the transistor 1210 is connected to the low power supply voltage. The other is electrically connected to a wiring (for example, a GND line) that can supply a voltage. The first terminal of the transistor 1203 (one of the source and drain of the transistor 1213) is electrically connected to the The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the other terminal of the switch 1204 (the source and drain of the transistor 1214) The second terminal of the switch 1204 (one of the terminals of the transistor 1214) is electrically connected to the The other of the source and drain) is electrically connected to the wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (as well as the source and drain of the transistor 1213) the first terminal of the switch 1204 (one of the source and drain of the transistor 1214) the input terminal of the logic element 1206 and one of the pair of electrodes of the capacitor 1207. , are electrically connected. Here, the connection point is referred to as node N1. The other electrode of the pair may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a The pair of electrodes of the capacitor 1208 are electrically connected to a wiring (for example, a GND line). The other terminal may be configured to receive a constant potential. For example, a low power supply potential (GND The capacitor element 12 may be configured to receive a high power supply potential (VDD, etc.) or a high power supply potential (VDD, etc.). The other of the pair of electrodes 08 is connected to a wiring (e.g., GN D line).

[0329] The capacitors 1207 and 1208 are formed by using parasitic capacitances of transistors and wirings. It is also possible to omit this by actively using

[0330] A control signal WE is input to the first gate (first gate electrode) of the transistor 1209. The switches 1203 and 1204 are connected to a control signal R, which is different from the control signal WE. D selects the conductive state or non-conductive state between the first terminal and the second terminal, and one When the first terminal and the second terminal of the switch are in a conductive state, the first terminal of the other switch and The second terminals are in a non-conductive state.

[0331] The other of the source and drain of the transistor 1209 is connected to a data terminal of the circuit 1201. In FIG. 38, the signal output from the circuit 1201 is The example shown is input to the other of the source and drain of the transistor 1209. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and the inverted signal is output via the circuit 1220. and input to the circuit 1201.

[0332] In FIG. 38, the second terminal of the switch 1203 (the source of the transistor 1213) The signal output from the other drain is passed through the logic element 1206 and the circuit 1220. Although an example of inputting the signal to the circuit 1201 is shown, this is not limiting. The signal output from the other of the source and drain of the transistor 1213 is It may be input to the circuit 1201 without being inverted. For example, If there is a node that holds a signal whose logical value is the inverse of the signal input from the input terminal, In this case, the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) can be input to the node.

[0333] In addition, in FIG. 38, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are made of a film or a substrate 11 made of a semiconductor other than an oxide semiconductor. For example, a transistor having a channel formed in a silicon film or The memory element may be a transistor in which a channel is formed in a silicon substrate. All the transistors used in the element 1200 are transistors whose channels are formed of oxide semiconductors. Alternatively, the memory element 1200 may be implemented by any other element than the transistor 1209. The other transistors may include a transistor in which the channel is formed of an oxide semiconductor. The transistor has a channel formed in a film or substrate 1190 made of a semiconductor other than an oxide semiconductor. The transistor may also be a transistor that is

[0334] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0335] In the semiconductor device according to one embodiment of the present invention, while power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0336] Further, a transistor whose channel is formed in an oxide semiconductor has an extremely small off-state current. For example, the off-state current of a transistor whose channel is formed in an oxide semiconductor is The off-state current is significantly lower than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, the memory element 12 Even when power supply voltage is not supplied to 00, the signal held in the capacitor 1208 is retained for a long period of time. In this way, the memory element 1200 can maintain its stored contents (data) even when the supply of power supply voltage is stopped. It is possible to hold the data.

[0337] In addition, by providing the switches 1203 and 1204, the precharge Since the memory element is characterized by performing the following operation, after the power supply voltage is supplied again, the circuit 1201 This can shorten the time it takes to restore the original data.

[0338] In the circuit 1202, the signal held by the capacitor 1208 is transferred to the transistor. Therefore, the supply of the power supply voltage to the memory element 1200 is restarted. After the capacitor 1208 is opened, the transistor 1210 The state (conducting or non-conducting) is determined and can be read out from the circuit 1202 Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original It is possible to accurately read out the signal.

[0339] Such a storage element 1200 may be a register or cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one of the components of the processor, In addition, power can be stopped for a short period of time in multiple logic circuits, reducing power consumption. can be suppressed.

[0340] Although the memory element 1200 has been described as being used in a CPU, the memory element 1200 may also be used in a DSP. (Digital Signal Processor), Custom LSI, PLD(P LSI such as rogrammable Logic Device), RF-Tag (Ra It can also be applied to radio frequency tags (RF tags).

[0341] This embodiment may be used in conjunction with other embodiments and implementations, at least some of which are described herein. It can be implemented in appropriate combination with the examples.

[0342] (Embodiment 9) <Imaging device> 39A is a top view illustrating an example of an imaging device 200 according to one embodiment of the present invention. The device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and a peripheral The pixel section 210 has a pixel circuit 270, a peripheral circuit 280, and a peripheral circuit 290. It has a plurality of pixels 211 arranged in a matrix of columns (p and q are integers of 2 or more). The peripheral circuits 260, 270, 280, and 290 are respectively The pixel 211 is connected to the plurality of pixels 211 and has a function of supplying signals for driving the plurality of pixels 211. In this specification and the like, the peripheral circuits 260, 270, 280, and The peripheral circuit 290 and the like may be referred to as the "peripheral circuit" or the "drive circuit." For example, peripheral circuit 260 can be considered a part of the peripheral circuit.

[0343] The imaging device 200 preferably includes a light source 291. The light source 291 emits detection light. It can emit P1.

[0344] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be fabricated on the same substrate on which the pixel section 210 is formed. Also, semiconductor devices such as IC chips may be used for part or all of the peripheral circuits. The peripheral circuits are peripheral circuits 260, 270, 280, and 29. One or more of the 0s may be omitted.

[0345] Also, as shown in FIG. 39(B), in the pixel section 210 of the imaging device 200, The pixels 211 may be arranged at an angle. By arranging the pixels 211 at an angle, the pixel This allows the pixel interval (pitch) in the column direction to be shortened. This can further improve the quality of imaging in the imaging device.

[0346] <Pixel configuration example 1> One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and each The sub-pixel 212 is combined with a filter (color filter) that transmits light of a specific wavelength band. By doing so, it is possible to obtain information for realizing a color image display.

[0347] FIG. 40(A) is a top view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in FIG. 40(A) has a color filter that transmits light in the red (R) wavelength band. The sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") has a wavelength band of green (G). A sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") provided with a light-transmitting color filter and blue (B) wavelength band light. 2 (hereinafter also referred to as "subpixel 212B"). This can be used to make it function.

[0348] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 2 31, and are electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The subpixels 212R, 212G, and 212B are each connected to an independent wiring 2 53. In this specification, for example, the pixel connected to the n-th row pixel 211 is The wiring 248, the wiring 249, and the wiring 250 are respectively referred to as wiring 248[n] and wiring 249[n] and wiring 250[n]. The connected wiring 253 is referred to as wiring 253[m]. The wiring 253 connected to the sub-pixel 212R of the pixel 211 in the m-th column is designated as wiring 253[m]R. The wiring 253 connected to the subpixel 212G is a wiring 253[m]G, and the wiring 253 connected to the subpixel 212B is a wiring 253[m]G. The connecting wiring 253 is described as wiring 253[m]B. The semiconductor memory device is electrically connected to the peripheral circuits via the semiconductor memory device.

[0349] In addition, the imaging device 200 detects color components of adjacent pixels 211 that transmit light in the same wavelength band. The sub-pixels 212 provided with the filters are electrically connected to each other via switches. In Figure 40(B), there are n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q). and a sub-pixel 212 of a pixel 211 arranged in the (n+1)th row and the (m)th column adjacent to the pixel 211. 40B shows an example of connection of the sub-pixels 212 included in the pixel 211 arranged in the The sub-pixel 212R arranged in the nth row and the mth column and the sub-pixel 212R arranged in the n+1th row and the mth column are The sub-pixels 212G are connected via a switch 201. The sub-pixels 212G are arranged in n rows and m columns. The sub-pixels 212G arranged in the n+1th row and the mth column are connected via the switches 202. In addition, the sub-pixel 212B arranged in the nth row and the mth column and the sub-pixel 212B arranged in the n+1th row and the mth column are connected via a switch 203.

[0350] The color filters used for the subpixel 212 are limited to red (R), green (G), and blue (B). color filters that transmit cyan (C), yellow (Y) and magenta (M) light, respectively. A sub-pixel for detecting light of three different wavelength bands may be used in one pixel 211. By providing the element 212, a full color image can be obtained.

[0351] Alternatively, color filters that transmit red (R), green (G), and blue (B) light are used. In addition to the sub-pixel 212, a color filter that transmits yellow (Y) light is provided. Alternatively, a pixel 211 having sub-pixels 212 may be used. The sub-pixel 212 is provided with a color filter that transmits light of blue (Y) and magenta (M). In addition, a pixel 212 having a sub-pixel 212 provided with a color filter that transmits blue (B) light is 11 may be used. One pixel 211 may have four sub-pixels that detect light in different wavelength bands. By providing 212, the color reproducibility of the acquired image can be further improved.

[0352] Also, for example, in FIG. 40(A), the sub-pixel 212 that detects light in the red wavelength band, a sub-pixel 212 that detects light in the blue wavelength band, and a sub-pixel 21 The pixel ratio (or light receiving area ratio) of 2 does not have to be 1:1:1. For example, A Bayer array with a ratio (light receiving area ratio) of red:green:blue=1:2:1 may also be used. Alternatively, the pixel number ratio (light receiving area ratio) may be set to red:green:blue=1:6:1.

[0353] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that the number is two or more. For example, by providing two or more sub-pixels 212 that detect light in the same wavelength band, redundancy can be increased. The reliability of the imaging device 200 can be improved.

[0354] In addition, IR (Infrared) filters absorb or reflect visible light and transmit infrared light. ) filter, an imaging device 200 that detects infrared light can be realized.

[0355] In addition, ND (Neutral Density) filters (light-reducing filters) are used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, The dynamic range of the device can be increased.

[0356] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described using the cross-sectional view of the pixel 211. By providing the lens 255, the photoelectric conversion element provided in the sub-pixel 212 can efficiently convert incident light. Specifically, as shown in FIG. 41(A), The lens 255, the filter 254 (filter 254R, filter 254G and filter 254B), and the light 256 is incident on the photoelectric conversion element 220 through the pixel circuit 230, etc. The structure can be such that:

[0357] However, as shown in the area surrounded by the dashed line, part of the light 256 indicated by the arrow is connected to the wiring 257. Therefore, as shown in Figure 41(B), the light is blocked by a part of the A lens 255 and a filter 254 are arranged on the photoelectric conversion element 220 side. A structure in which the light 256 is efficiently received by the photoelectric conversion element 220 is preferable. By making the light incident on the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity can be provided. This can be done.

[0358] As the photoelectric conversion element 220 shown in FIG. 41, a pn-type junction or a pin-type junction is formed. Alternatively, a photoelectric conversion element may be used.

[0359] The photoelectric conversion element 220 is made of a material having a function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating charges may be: Selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy There is money etc.

[0360] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element with optical absorption coefficient over a wide wavelength range, including X-rays and gamma rays 220 can be achieved.

[0361] Here, one pixel 211 included in the imaging device 200 is added to a sub-pixel 212 shown in FIG. In addition, there may be a subpixel 212 having a first filter.

[0362] <Pixel configuration example 2> Hereinafter, a transistor using silicon and a transistor using an oxide semiconductor according to one embodiment of the present invention will be described. An example of a pixel formed using the transistor will be described.

[0363] 42(A) and (B) are cross-sectional views of elements that constitute the imaging device.

[0364] The imaging device shown in FIG. 42(A) is a silicon substrate 300 having a channel. The oxide semiconductor layer formed on the transistor 351 used as the formation region is used as a channel. The transistor 353 and the transistor 354 used as the transistor forming region, and the silicon A photodiode having an anode 361 and a cathode 362 is provided on a photodiode substrate 300. Each transistor and photodiode 360 ​​is connected to a different plug 370. and is electrically connected to the wiring 371. 61 has an electrical connection with plug 370 through low resistance region 363 .

[0365] The imaging device also includes a transistor 351 and a photodiode 352 provided on a silicon substrate 300. A layer 305 having a diode 360 ​​and a layer 371 provided in contact with the layer 305. 320, and a transistor 353 and a transistor 354 are provided in contact with the layer 320. a layer 331 having a wiring 372 and a wiring 373 provided in contact with the layer 331; It is equipped with 340.

[0366] In the example of the cross-sectional view of FIG. 42(A), a transistor is formed on a silicon substrate 300. The light receiving surface of the photodiode 360 ​​is located on the opposite side to the surface on which the photodiode 351 is formed. This configuration ensures an optical path without being affected by various transistors and wiring. Therefore, it is possible to form pixels with a high aperture ratio. The light-receiving surface of the board 360 may be the same as the surface on which the transistor 351 is formed.

[0367] Note that a pixel is formed using a transistor that uses silicon as a channel formation region. In this case, the layer 305 may be a layer having a transistor. Alternatively, a pixel may be formed using only a transistor in which an oxide semiconductor is used for a channel formation region. stomach.

[0368] In the cross-sectional view of FIG. 42(A), a photodiode 360 ​​is provided in the layer 305. The transistor can be formed so as to overlap with the transistor provided in the layer 331. This allows for an increase in the degree of integration of elements, which in turn allows for an increase in the resolution of the imaging device.

[0369] In addition, in FIG. 42(B), the imaging device has a photodiode 365 on the layer 340 side. In FIG. 42(B), for example, the layer 305 has a structure in which a , a transistor 351 and a transistor 35 2, the layer 320 includes a wiring 371, and the layer 331 includes an oxide semiconductor as a channel formation region. The layer 340 has a transistor 353 and a transistor 354 used as a photodiode. The photodiode 365 has a semiconductor layer 366 and a semiconductor layer 367, a semiconductor layer 368, and a wiring 373 and a wiring 370 through a plug 370. 74 and electrically connected to each other.

[0370] By using the element configuration shown in FIG. 42(B), the aperture ratio can be increased.

[0371] In addition, the photodiode 365 uses an amorphous silicon film or a microcrystalline silicon film. Alternatively, a pin-type diode element may be used. A structure in which an i-type semiconductor layer 368, an i-type semiconductor layer 367, and a p-type semiconductor layer 366 are stacked in this order. It is preferable to use amorphous silicon for the i-type semiconductor layer 367. The p-type semiconductor layer 366 and the n-type semiconductor layer 368 are given respective conductivity types. Amorphous silicon or microcrystalline silicon containing a dopant can be used. The photodiode 365, which uses porous silicon as a photoelectric conversion layer, has a sensitivity in the visible light wavelength range. It has high sensitivity and is easy to detect weak visible light.

[0372] Here, a layer 305 having a transistor 351 and a photodiode 360, An insulator 380 is provided between the layer 331 having the transistor 353 and the transistor 354. However, the location of the insulator 380 is not limited.

[0373] The hydrogen in the insulator provided near the channel formation region of the transistor 351 is This has the effect of terminating dangling bonds and improving the reliability of the transistor 351. On the other hand, the water in the insulator provided near the transistor 353 and the transistor 354 is The element is one of the factors that generate carriers in the oxide semiconductor. This may cause a decrease in reliability of the transistor 353 and the transistor 354. Therefore, a transistor using an oxide semiconductor is placed on top of a transistor using a silicon semiconductor. When stacking the sintered bodies, an insulator 380 having a function of blocking hydrogen is provided between the sintered bodies. By confining hydrogen below the insulator 380, the transistor The reliability of the capacitor 351 can be improved. Since hydrogen can be prevented from diffusing into layers above the body 380, the transistor 353 and the transistor The reliability of the transistor 354 can be improved. By providing the insulator 381 over the transistor 354, oxygen in the oxide semiconductor This is preferable because it can prevent diffusion.

[0374] This embodiment may be used in conjunction with other embodiments and implementations, at least some of which are described herein. It can be implemented in appropriate combination with the examples.

[0375] (Embodiment 10) <RFタグ> In this embodiment, the R The F tag will be described with reference to FIG.

[0376] The RF tag in this embodiment has a memory circuit inside, and stores necessary information in the memory circuit. It stores information and transmits and receives information to and from the outside using non-contact means, such as wireless communication. Due to these characteristics, RF tags can identify items by reading their individual information. It can be used for individual authentication systems, etc. Extremely high reliability is required.

[0377] The structure of an RF tag will be explained with reference to Fig. 43. Fig. 43 shows an example of the structure of an RF tag. FIG.

[0378] As shown in FIG. 43, an RF tag 800 includes a communicator 801 (such as an interrogator, reader / writer, etc.). 803 is transmitted from an antenna 802 connected to The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 804, and a 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, the reverse current of the transistor having the rectifying action included in the demodulation circuit 807 is sufficiently suppressed. A material capable of controlling the temperature, such as an oxide semiconductor, may be used. This suppresses the degradation of rectification caused by reverse current and prevents the output of the demodulation circuit from saturating. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit can be made closer to linearity. The data transmission format is a pair of coils arranged facing each other and communicating by mutual induction. electromagnetic coupling method, which communicates by induced electromagnetic fields; electromagnetic induction method, which communicates by using radio waves; The RF tag 800 shown in this embodiment is compatible with any of these methods. It can also be used in formulas.

[0379] Next, the configuration of each circuit will be explained. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 805 adjusts the input AC signal generated by receiving a radio signal with the antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is averaged by a capacitive element provided in the subsequent stage. The rectifier circuit 805 is a circuit for generating an input potential by smoothing the input voltage. A limiter circuit may be provided on the output side. When the internally generated voltage is large, power above a certain level is not input to the subsequent circuit. This is a circuit for controlling the

[0380] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to reset the logic circuit 8. This is a circuit for generating the reset signal for 09.

[0381] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation in response to the

[0382] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. , a circuit that holds input information, such as a row decoder, a column decoder, a memory area, etc. The ROM 811 stores a unique number (ID) and outputs it according to the processing. This is a circuit for doing this.

[0383] The above-mentioned circuits can be selected or removed as needed.

[0384] Here, the memory circuit described in the above embodiment can be used as the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when power is cut off. Furthermore, the memory circuit of one embodiment of the present invention can be suitably used for an RF tag. The power (voltage) required for writing is significantly lower than that of conventional non-volatile memory, It is also possible to eliminate the difference in maximum communication distance between when reading and writing data. and suppressing malfunctions or erroneous writing caused by a power shortage when writing data. This can be done.

[0385] The memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the manufacturer must A separate command is provided to write data, preventing users from freely rewriting it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to every RF tag produced, we only assign a unique number to good products to be shipped. Only the manufacturer can assign a unique number, and the unique numbers of products will not be consecutive after shipping. This makes it easier to manage customers' accounts after products are shipped.

[0386] Note that this embodiment mode may be combined as appropriate with other embodiment modes and examples shown in this specification. It is possible.

[0387] (Embodiment 11) <Display device> A display device according to one embodiment of the present invention will be described below with reference to FIGS. 44 and 45. do.

[0388] Display elements used in display devices include liquid crystal elements (also called liquid crystal display elements), light-emitting elements, The light-emitting element can be a light-emitting element that emits current or voltage. This category includes elements whose brightness is controlled by the These include fluoroluminescence, organic electroluminescence (EL), etc. The display devices using EL elements (EL display devices) and the display devices using liquid crystal elements (LCD devices) are This section explains the display device.

[0389] The display device described below is a panel in which a display element is sealed, and a display device in which a display element is sealed. This includes modules that have ICs, including controllers, mounted on them.

[0390] Moreover, the display device described below refers to an image display device or a light source (including a lighting device). Also, connectors, such as FPC (Flexible Printed Circuit s), TCP (Tape Carrier Package) mounted module module with a printed wiring board at the end of TCP or a COG (Chip On Glass) All modules with ICs (integrated circuits) directly mounted on glass are also displayed. The display device is included.

[0391] 44A and 44B are examples of EL display devices according to one embodiment of the present invention. 44(B) is a top view showing the entire EL display device. FIG. 44(C) is a cross section of the MN corresponding to a part of the dashed line MN in FIG. 44(B). do.

[0392] FIG. 44(A) is an example of a circuit diagram of a pixel used in an EL display device.

[0393] In this specification, the terms "active elements (transistors, diodes, etc.)" and "passive elements" are used interchangeably. For all terminals of elements (capacitance elements, resistance elements, etc.), the connection destination must be specified. Even if the invention is not so simple, a person skilled in the art may be able to construct one aspect of the invention. Even if the connection destination is not specified, one aspect of the invention can be said to be clear. When the content of the above is described in this specification, etc., one aspect of the invention that does not specify a connection destination is the present invention. In some cases, it may be possible to determine that the information is written in the detailed instructions, etc. In particular, If multiple locations are expected, there is no need to limit the connection destination of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements) By specifying the connection destinations for only some of the terminals of a device (such as a semiconductor device), This may constitute an aspect of the invention.

[0394] In this specification, if at least the connection destination of a certain circuit is specified, the circuit is considered to be a A person skilled in the art may be able to identify the invention. A person skilled in the art may be able to identify an invention by simply specifying its functions. In other words, if the function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in this specification, etc. Therefore, even if the function of a circuit is not specified, if the connection destination is specified, it can be considered as an invention. The invention is disclosed as an embodiment and can be implemented as an embodiment of the invention. Regarding a certain circuit, even if the connection destination is not specified, specifying the function is considered as one aspect of the invention. and can constitute one aspect of the invention.

[0395] The EL display device shown in FIG. 44(A) includes a switch element 743, a transistor 741, and The pixel includes a capacitor 742 and a light-emitting element 719 .

[0396] Note that FIG. 44(A) is an example of a circuit configuration, so if a transistor is added, Conversely, at each node in FIG. 44(A), it is possible to It is also possible to avoid adding switches, passive elements, etc.

[0397] The gate of the transistor 741 is connected to one end of the switch element 743 and one end of the capacitance element 742. The source of the transistor 741 is electrically connected to the other electrode of the capacitor 742. The transistor 719 is electrically connected to one electrode of the light emitting element 719. The drain of the switch element 741 is supplied with a power supply potential VDD. The other electrode of the light-emitting element 719 is electrically connected to the line 744. A constant potential is applied to the other electrode of the light-emitting element 719. The constant potential is the ground potential GND or a potential lower than that.

[0398] It is preferable to use a transistor as the switch element 743. This allows the pixel area to be reduced, resulting in an EL display device with high resolution. In addition, the switching element 743 is a transistor manufactured through the same process as the transistor 741. The use of transistors can improve the productivity of EL display devices. As the transistor 41 and / or the switch element 743, for example, the transistor shown in FIG. It can be used.

[0399] 44B is a top view of the EL display device. The EL display device includes a substrate 700 and a substrate 750, a sealing material 734, a driving circuit 735, a driving circuit 736, a pixel 737, and F The sealing material 734 covers the pixels 737, the driving circuit 735, and the driving circuit 736. The driving circuit 73 is disposed between the substrate 700 and the substrate 750 so as to surround the path 736. 5 and / or the driving circuit 736 may be disposed outside the sealing material 734 .

[0400] FIG. 44(C) is a cross section of an EL display device corresponding to a part of the dashed line MN in FIG. 44(B). Figure.

[0401] In FIG. 44C, a transistor 741 is shown, which is made of an insulator 712a on a substrate 700 and a conductor and a conductive body 704a, which is on the insulator 712a and the conductive body 704a. an insulator 706a having a region overlapping with the semiconductor 706b; and a semiconductor 706b on the insulator 706a. The conductors 716a1 and 716a2 in contact with the top surface of the semiconductor 706b, and the conductors 71 The insulator 724a1 covers the top and side surfaces of the conductor 716a1, and the top and side surfaces of the conductor 716a2. and an insulator 724a2 covering the insulator 712a, the upper surface of the insulator 724a1, and the insulator 7 an insulator 706c having a region in contact with the upper surface of the insulator 71; 8b, the insulator 710 on the insulator 718b, and the insulator 718b and the insulator 706c. The figure shows a structure having a conductor 714a disposed on the semiconductor 706b. The structure of the resistor 741 is an example, and it may be different from the structure shown in FIG. 44(C). do not have.

[0402] In the transistor 741 shown in FIG. 44C, the conductor 704a serves as a gate electrode. The insulator 712a functions as a gate insulator, and the conductor 716a1 the conductor 716a1 functions as a drain electrode, the conductor 716a2 functions as a source electrode, The insulator 718b functions as a gate insulator, and the conductor 714a functions as a gate electrode. The insulator 706a, the semiconductor 706b, and the insulator 706c have the following functions: The electrical characteristics may change when the conductor 704a and the conductor 71 It is preferable that at least one of the conductors 6a1, 716a2, and 714a has a light-shielding property. I wish.

[0403] In FIG. 44C, the capacitor 742 is formed by using an insulator 712a on a substrate 700 and an insulator Insulator 706c on 712a, insulator 718 on insulator 706c, and The conductive material 722 and the insulator 723 are arranged so as to cover the surface of the conductive material 722. and a conductor 714b having an overlapping region with an insulator 723 interposed therebetween. The structure is shown below.

[0404] In the capacitor 742, the conductor 722 functions as one electrode, and the conductor 714b functions as It functions as the other electrode.

[0405] The capacitor 742 can be formed using the same film as that of the transistor 741 . It is preferable that the conductors 714a and 714b are made of the same type of conductor. The conductive body 714a and the conductive body 714b can be formed through the same process.

[0406] The capacitor 742 shown in FIG. 44C has a large capacitance per occupied area. Therefore, the EL display device shown in FIG. 44(C) has high display quality. The structure of the child 742 is an example, and it may be different from the structure shown in FIG. 44(C). For example, the structure shown in Embodiment Mode 1 can be used.

[0407] An insulator 728 is disposed over the transistor 741 and the capacitor 742. An insulator 720 is disposed on the insulating layer 28. Here, the insulating layer 728 and the insulating layer 720 are The conductor 716a2 serves as the source electrode of the transistor 741. A conductor 781 is disposed on the insulator 720. The conductor 781 is 8 and may be electrically connected to the transistor 741 through an opening in the insulator 720. The conductor 781 is connected to the capacitor 74 through the openings of the insulator 728 and the insulator 720. The electrode may be electrically connected to one of the electrodes.

[0408] A partition 784 having an opening that reaches the conductor 781 is arranged over the conductor 781 . A light-emitting layer 782 is disposed over the partition wall 784 and is in contact with the conductor 781 through the opening of the partition wall 784. A conductor 783 is disposed over the light-emitting layer 782. The overlapping region of the FPC and the conductor 783 is the light-emitting element 719. 732 is connected to a wiring 733a via a terminal 731. The same type of conductor or semiconductor as that constituting the transistor 741 It may be used.

[0409] Up to this point, an example of an EL display device has been explained. Next, an example of a liquid crystal display device will be explained. Reveal.

[0410] FIG. 45(A) is a circuit diagram showing an example of the configuration of a pixel of a liquid crystal display device. The pixel includes a transistor 751, a capacitor 752, and a pair of electrodes filled with liquid crystal. The liquid crystal display device 750 includes an element (liquid crystal element) 753.

[0411] In the transistor 751, one of the source and the drain is electrically connected to a signal line 755. , the gate is electrically connected to the scan line 754 .

[0412] One electrode of the capacitor 752 is connected to the other of the source and drain of the transistor 751. The other electrode is electrically connected to a wiring that supplies a common potential.

[0413] In the liquid crystal element 753, one electrode is connected to the other of the source and drain of the transistor 751. The other electrode is electrically connected to a wiring that supplies a common potential. The common potential applied to the wiring to which the other electrode of the capacitor 752 is electrically connected is The potential applied to the other electrode of the liquid crystal element 753 may be different from the common potential applied to the other electrode of the liquid crystal element 753 .

[0414] The liquid crystal display device will be described assuming that the top view is the same as that of the EL display device. A cross-sectional view of the liquid crystal display device corresponding to the dashed line MN is shown in FIG. In this case, the FPC 732 is connected to the wiring 733a via the terminal 731. 33a is a conductor of the same type as the conductor or semiconductor that constitutes the transistor 751. Alternatively, a semiconductor may be used.

[0415] For the transistor 751, refer to the description of the transistor 741. For the capacitor 752, refer to the description of the capacitor 742. 4(C) shows the structure of the capacitor element 752 corresponding to the capacitor element 742, but is not limited to this. do not have.

[0416] Note that when an oxide semiconductor is used as the semiconductor of the transistor 751, the off-state current is extremely small. Therefore, the charge held in the capacitor 752 can be It is difficult to leak and can maintain the voltage applied to the liquid crystal element 753 for a long period of time. Therefore, when displaying a moving image or a still image with little movement, the transistor 751 is turned off. By doing so, power for operating the transistor 751 is not required, and power consumption is low. In addition, the area occupied by the capacitor 752 can be reduced. Therefore, it is possible to provide a liquid crystal display device with a high aperture ratio or a high-definition liquid crystal display device. .

[0417] The insulators 721 and 728 are provided over the transistor 751 and the capacitor 752. Here, the insulator 721 and the insulator 728 reach the transistor 751. The insulator 721 has an opening. A conductor 791 is disposed on the insulator 721. The transistor 751 is electrically connected to the insulator 721 through the openings in the insulator 728. The conductor 791 is connected to the capacitor 7 through the openings of the insulators 721 and 728. 52 is electrically connected to one of the electrodes.

[0418] An insulator 792 functioning as an alignment film is disposed over the conductor 791. A liquid crystal layer 793 is disposed thereon. An insulating layer functioning as an alignment film is disposed on the liquid crystal layer 793. 794 is disposed on the insulating material 794. A spacer 795 is disposed on the insulating material 794. A conductor 796 is disposed on the substrate 75 and the insulator 794. 97 will be placed.

[0419] By using the above-described structure, a display device having a capacitor element with a small occupation area can be provided. Alternatively, a display device with high display quality can be provided. It is possible to provide a thin display device.

[0420] For example, in this specification, a display element, a display device which is a device having a display element, a light-emitting device, The light-emitting device, which is a device having an element and a light-emitting element, can be used in various forms, or A display element, a display device, a light-emitting element, or a light-emitting device can have various elements. For example, EL elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LED (white LED, red LED, green LED, blue LED, etc.), transistor (current transistors that emit light in response to light), electron-emitting devices, liquid crystal devices, electronic ink, electrophoretic devices , Grating Light Valve (GLV), Plasma Display Panel (PDP), M Display elements using EMS (microelectromechanical systems), digital monitors Micromirror Device (DMD), DMS (Digital Micro Shutter), IMO D (Interferometric Modulation) element, shutter type MEMS surface display element, optical interference type MEMS display element, electrowetting element, piezoelectric ceramic a display element using carbon nanotubes, or In addition to these, contrast, brightness, reflectivity, etc. can be improved by electrical or magnetic effects. It may also have a display medium whose transmittance or the like changes.

[0421] An example of a display device using an EL element is an EL display. An example of a display device using electrons is a field emission display (FED). or SED type flat panel display (SED: Surface-conduction LCDs are liquid crystal displays. An example of a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display). Spray, reflective LCD, direct-view LCD, projection LCD An example of a display device using electronic ink or electrophoretic elements is an electronic pen. In addition, there are also other LCDs that can be used to realize semi-transmissive LCDs and reflective LCDs. In this case, a part or all of the pixel electrodes should function as a reflective electrode. For example, a part or all of the pixel electrodes may be made of aluminum, silver, etc. Furthermore, in this case, a memory circuit such as an SRAM can be provided under the reflective electrode. This makes it possible to further reduce power consumption.

[0422] When using an LED, graphene or graphene is placed under the LED electrode or nitride semiconductor. Graphene and graphite can be arranged in layers to form a multilayer film. In this way, by providing graphene or graphite, it is possible to form nitride on it. This makes it easy to form films of semiconductors, such as crystalline n-type GaN semiconductors. Furthermore, a p-type GaN semiconductor with crystals is placed on top of it to form an LED. It is possible to form a crystalline n-type GaN semiconductor with graphene or graphite. An AlN layer may be provided. The GaN semiconductor in the LED is formed by MOCVD. However, by providing graphene, the GaN semiconductor of the LED can be It is also possible to form the film by sputtering.

[0423] Note that this embodiment mode may be combined as appropriate with other embodiment modes and examples shown in this specification. It is possible.

[0424] (Embodiment 12) <Single power supply circuit> In this embodiment, the transistor ( An example of a semiconductor device having a plurality of circuits each having an OS transistor is shown in FIGS. 54 will be used to explain.

[0425] FIG. 46A is a block diagram of a semiconductor device 900. The semiconductor device 900 is A circuit 901, a circuit 902, a voltage generating circuit 903, a circuit 904, a voltage generating circuit 905, and a circuit It has a path 906.

[0426] The power supply circuit 901 supplies a reference voltage V ORG This is a circuit that generates a voltage V ORG teeth, Instead of a single voltage, multiple voltages may be used. Voltage V ORG is external to the semiconductor device 900. The semiconductor device 900 can generate the voltage V based on the voltage V0 given from the external The voltage V ORG Therefore, the semiconductor device 900 can generate It can operate without applying multiple power supply voltages from the outside.

[0427] The circuits 902, 904, and 906 are circuits that operate on different power supply voltages. The power supply voltage of the circuit 902 is V ORG and voltage V SS (V ORG >V SS ) and applied based on For example, the power supply voltage of the circuit 904 is a voltage V POG and voltage V SS (V POG >V ORG ) is a voltage applied based on the power supply voltage of the circuit 906. is the voltage V ORG and voltage V SS and voltage V NEG (V ORG >V SS >V NEG ) and based on is the applied voltage. SS is equivalent to the ground potential (GND), Therefore, the number of types of voltages generated by the power supply circuit 901 can be reduced.

[0428] The voltage generating circuit 903 generates a voltage V POG The voltage generating circuit 903 is a circuit that generates The voltage V given by the power supply circuit 901 ORG Based on the voltage V POG can be generated. The semiconductor device 900 having the circuit 904 operates based on a single power supply voltage applied from the outside. It can be made.

[0429] The voltage generating circuit 905 generates a voltage V NEG The voltage generating circuit 905 is a circuit that generates The voltage V given by the power supply circuit 901 ORG Based on the voltage V NEG can be generated. The semiconductor device 900 having the circuit 906 operates based on a single power supply voltage applied from the outside. It can be made.

[0430] Figure 46(B) shows the voltage V POG FIG. 46(C) shows an example of a circuit 904 that operates in the 10 is an example of a waveform of a signal for operating the

[0431] FIG. 46B shows a transistor 911. The applied signal is, for example, a voltage V POG and voltage V SS The signal is generated based on the When transistor 911 is in the conducting state, the voltage V POG , the voltage when operating in a non-conducting state V SS Voltage V POG As shown in Figure 46(C), the voltage V ORG Bigger Therefore, the transistor 911 has a more reliable connection between the source (S) and the drain (D). As a result, the circuit 904 can be a circuit with reduced malfunction. Cut.

[0432] Figure 46(D) shows the voltage V NEG FIG. 46(E) shows an example of a circuit 906 that operates in the 10 is an example of a waveform of a signal for operating the

[0433] FIG. 46D shows a transistor 912 having a back gate. The signal applied to the gate of the gate electrode 912 is, for example, a voltage V ORG and voltage V SS Generated based on This signal is applied to the voltage V ORG , non-guided When the voltage V SS Also, the back of the transistor 912 The signal applied to the gate is voltage V NEG It is generated based on the voltage V NEG Figure 46(E) As shown in the figure, the voltage V SS (GND). Therefore, the The threshold voltage can be controlled to be positively shifted. 12 can be more reliably made non-conductive, and the As a result, the circuit 906 has reduced malfunctions and low power consumption. This can result in a circuit with improved power.

[0434] Furthermore, the voltage V NEG may be directly applied to the back gate of the transistor 912. Alternatively, the voltage V ORG and voltage V NEG Based on this, a voltage is applied to the gate of the transistor 912. and supplying the signal to the back gate of the transistor 912. stomach.

[0435] Also, FIGS. 47(A) and (B) show modified examples of FIGS. 46(D) and (E).

[0436] In the circuit diagram shown in FIG. 47(A), a control circuit is provided between the voltage generating circuit 905 and the circuit 906. The transistor 922 has a conduction state that can be controlled by a path 921. is an n-channel OS transistor. BG is a signal that controls the conduction state of the transistor 922. Transistors 912A and 912B are OS transistors like transistor 922.

[0437] In the timing chart of FIG. 47(B), the control signal S BG The change in the potential of the transformer The state of the potential of the back gates of the resistors 912A and 912B is connected to the node N BG The change in potential is shown by Control signal S BG When is at a high level, the transistor 922 is in a conductive state, and the node N BG is the voltage V NEG Then, the control signal S BG When is low, node N B G The transistor 922 is an OS transistor. Therefore, the off-state current is small. BG Even if is electrically floating, Once the voltage V is applied NEG can be held.

[0438] FIG. 48A shows an example of a circuit configuration applicable to the voltage generating circuit 903 described above. The voltage generating circuit 903 shown in FIG. 48(A) includes diodes D1 to D5 and a capacitor C The charge pump is a five-stage circuit having C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 to C5 directly or via an inverter INV. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS The voltage applied based on voltage, by applying a clock signal CLK, the voltage V ORG to a positive voltage five times greater than The boosted voltage V POG It should be noted that the forward currents of the diodes D1 to D5 are The voltage is set to 0 V. By changing the number of stages in the charge pump, the desired voltage V PO G can be obtained.

[0439] FIG. 48B shows an example of a circuit configuration applicable to the voltage generating circuit 905 described above. The voltage generating circuit 905 shown in FIG. 48(B) includes diodes D1 to D5 and a capacitor C The charge pump is a four-stage circuit having C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 to C5 directly or via an inverter INV. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS The voltage applied based on voltage, the clock signal CLK is applied to the ground, i.e., the voltage V S S to voltage V ORG The voltage V is stepped down to a negative voltage four times that of NEG It is possible to obtain The forward voltage of the diodes D1 to D5 is set to 0 V. By changing NEG can be obtained.

[0440] The circuit configuration of the voltage generating circuit 903 described above is not limited to the configuration of the circuit diagram shown in FIG. Modifications of the voltage generating circuit 903 are shown in FIGS. 49(A) to 49(C), 50(A) and 50(B). Shown below.

[0441] The voltage generating circuit 903A shown in FIG. 49A includes transistors M1 to M10, a capacitor The clock signal CLK is supplied to the inverters C11 to C14 and the inverter INV1. The voltage Vcc is applied directly to the gates of the transistors M1 to M10 or via an inverter INV1. By applying a clock signal CLK, the voltage V ORG is boosted to a positive voltage four times higher than the The voltage V POG By changing the number of stages, the desired voltage V POG The voltage generating circuit 903A shown in FIG. By using OS transistors for M11 to M10, the off-state current can be reduced. This can suppress leakage of the charge stored in C14. Therefore, the voltage V ORG to voltage V POG It is possible to boost the voltage to

[0442] The voltage generating circuit 903B shown in FIG. 49B includes transistors M11 to M14, The clock signal CLK is generated by: The voltage is applied to the gates of the transistors M11 to M14 directly or via an inverter INV2. By applying a clock signal CLK, the voltage V ORG rises to twice the positive voltage The applied voltage V POG The voltage generating circuit 903B shown in FIG. By using OS transistors as the transistors M11 to M14, the off-state current can be reduced. Therefore, leakage of the electric charge held in the capacitors C15 and C16 can be suppressed. Pressure V ORG to voltage V POG It is possible to boost the voltage to

[0443] The voltage generating circuit 903C shown in FIG. 49(C) includes an inductor In1 and a transistor M 15, diode D6, and capacitor C17. Transistor M15 is controlled The conduction state is controlled by the signal EN. ORG is boosted The applied voltage V POG The voltage generating circuit 903C shown in FIG. Since the inductor In1 is used to boost the voltage, the voltage can be boosted with high conversion efficiency. can be done.

[0444] 48(A)。 The voltage generating circuit 903D shown in FIG. 50(A) is the same as the voltage generating circuit 903D shown in FIG. The diodes D1 to D5 of the O3 are placed in diode-connected transistors M16 to M20. The voltage generating circuit 903D shown in FIG. By using OS transistors M16 to M20, the off-state current can be reduced. Therefore, the leakage of the charge held in C5 can be suppressed. ORG Voltage from V POG It is possible to boost the voltage to

[0445] 50(B) is the same as the voltage generating circuit 903E shown in FIG. The transistors M16 to M20 of the first embodiment are replaced with transistors M21 to M20 having back gates. The voltage generating circuit 903E shown in FIG. Since the same voltage can be applied to the gate as to the clock gate, the amount of current flowing through the transistor Therefore, the voltage V ORG to voltage V POG Figure 1 shows the boost to It is possible.

[0446] The modified example of the voltage generating circuit 903 is also applicable to the voltage generating circuit 905 shown in FIG. 48(B). The circuit configuration in this case is shown in FIGS. 51(A) to 51(C), 52(A), and 52(B). The voltage generating circuit 905A shown in FIG. 51A supplies a clock signal CLK. and the voltage V SS to voltage V ORG The voltage V is stepped down to a negative voltage three times that of NEG Get Furthermore, the voltage generating circuit 905B shown in FIG. By applying SS to voltage V ORG The voltage V is stepped down to a negative voltage twice that of NEG can be obtained.

[0447] The voltage generating circuits 905A to 905C shown in FIGS. 5E, the voltage generating circuit 903A shown in FIGS. 49(A) to 49(C) and 50(A) and 50(B) In the above-mentioned steps 903A to 903E, the voltage applied to each wiring is changed or the arrangement of the elements is changed. The voltage generating circuits shown in FIGS. 51(A) to 51(C) and 52(A) and 52(B) correspond to the above configuration. The circuits 905A to 905E, like the voltage generating circuits 903A to 903E, efficiently generate voltages. V SS to voltage V NEG It is possible to reduce the pressure to

[0448] As described above, in the configuration of this embodiment, the voltage required for the circuit of the semiconductor device is Therefore, the semiconductor device can generate the power supply voltage from the outside. It can be reduced.

[0449] Note that this embodiment mode may be combined as appropriate with other embodiment modes and examples shown in this specification. It is possible.

[0450] (Embodiment 13) In this embodiment, a display module to which the semiconductor device of one embodiment of the present invention is applied will be described. The explanation will be given using Figure 53.

[0451] <Display module> The display module 6000 shown in FIG. 53 includes an upper cover 6001 and a lower cover 6002. Between them, touch panel 6004 connected to FPC6003 and A display panel 6006, a backlight unit 6007, a frame 6009, a printed circuit board The backlight unit 6007, the battery 6011, and the The television 6011, touch panel 6004, etc. may not be provided.

[0452] The semiconductor device of one embodiment of the present invention is implemented on, for example, the display panel 6006 or a printed circuit board. It can be used in an integrated circuit equipped with a semiconductor device.

[0453] The upper cover 6001 and the lower cover 6002 are connected to the touch panel 6004 and the display panel. The shape and dimensions can be changed as appropriate to fit the size of the panel 6006.

[0454] The touch panel 6004 is a resistive or capacitive touch panel. The display panel 6006 can be used by overlapping it with the opposing substrate (sealing substrate) of the display panel 6006. It is also possible to provide a touch panel function to the display panel. It is also possible to add an optical sensor to each pixel of the 6006 to add an optical touch panel function. Alternatively, a touch sensor electrode is provided in each pixel of the display panel 6006, and a capacitance It is also possible to add a touch panel function to the system.

[0455] The backlight unit 6007 includes a light source 6008. It may be provided at the end of the light source unit 6007 and configured to use a light diffusion plate.

[0456] The frame 6009 not only protects the display panel 6006 but also protects the printed circuit board 6010 from It also functions as an electromagnetic shield to block the electromagnetic waves generated. 09 may also function as a heat sink.

[0457] The printed circuit board 6010 includes a power supply circuit, a video signal circuit, and a clock signal circuit. The power supply circuit is supplied with power from an external commercial power source. Alternatively, a separately provided battery 6011 may be used. In this case, the battery 6011 can be omitted.

[0458] The display module 6000 also includes components such as a polarizing plate, a retardation plate, and a prism sheet. Additional ones may be provided.

[0459] Note that this embodiment mode may be combined as appropriate with other embodiment modes and examples shown in this specification. It is possible.

[0460] (Embodiment 14) <Package using lead frame type interposer> Figure 54(A) shows the cross-sectional structure of a package using a lead frame type interposer. 54A is a perspective view showing a package of a semiconductor device according to one embodiment of the present invention. A chip 551 corresponding to the The terminal 552 is connected to the chip 551 of the interposer 550. The chip 551 is placed on a surface that is bonded to the chip 551 by a molding resin 553. However, it is preferable that the terminals 552 are sealed in a state where a part of each terminal 552 is exposed. .

[0461] The module configuration of an electronic device (mobile phone) in which a package is mounted on a circuit board is The mobile phone module shown in FIG. 54(B) includes a printed wiring board 6 601, a package 602 and a battery 604 are mounted. A printed wiring board 601 is mounted on the provided panel 600 by an FPC 603. There are.

[0462] Note that this embodiment mode may be combined as appropriate with other embodiment modes and examples shown in this specification. It is possible.

[0463] (Embodiment 15) In this embodiment, an electronic device and a lighting device according to one embodiment of the present invention will be described with reference to drawings. Reveal.

[0464] <Electronic equipment> Electronic devices and lighting devices can be manufactured using the semiconductor device of one embodiment of the present invention. By using the semiconductor device of one embodiment, highly reliable electronic devices and lighting devices can be manufactured. The semiconductor device of one embodiment of the present invention is used in an electronic device or a lighting device in which the detection sensitivity of a touch sensor is improved. It is possible to create a lighting device.

[0465] Examples of electronic devices include television sets (televisions or television receivers) (also known as computer monitors, digital cameras, digital video cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable game consoles , portable information terminals, audio playback devices, large game machines such as pachinko machines, etc.

[0466] Furthermore, when the electronic device or lighting device of one embodiment of the present invention is flexible, it can be installed in a house or a building. It can also be installed along the curved surfaces of interior or exterior walls, or the interior or exterior of a vehicle. It is Noh.

[0467] Furthermore, the electronic device of one embodiment of the present invention may include a secondary battery and may perform contactless power transmission. It is preferable that the secondary battery can be charged using the power supply.

[0468] As the secondary battery, for example, a lithium polymer battery (lithium ion battery) using a gel electrolyte is used. Lithium-ion secondary batteries such as lithium-ion polymer batteries, nickel-metal hydride batteries, nickel-cadmium batteries, organic Examples include radical batteries, lead-acid batteries, secondary air batteries, nickel-zinc batteries, and silver-zinc batteries. do.

[0469] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images, information, etc. on the display unit. , the antenna may be used for contactless power transfer.

[0470] FIG. 55A shows a portable game machine, which includes a housing 7101, a housing 7102, and a display portion 7103. , a display unit 7104, a microphone 7105, a speaker 7106, operation keys 7107, a stylus The semiconductor device according to one embodiment of the present invention is built in the housing 7101. The display portion 7103 or the display portion 7104 can be used for an integrated circuit, a CPU, etc. By using the light-emitting device according to one embodiment of the present invention, the user experience is excellent and the quality is not deteriorated. It is possible to provide a portable game machine that is less likely to cause such a problem. The handheld game machine has two display units 7103 and 7104. The number of display units that the computer has is not limited to this.

[0471] FIG. 55(B) shows a smart watch, which includes a housing 7302, display units 7304 and 7305. and 7306, operation buttons 7311 and 7312, connection terminal 7313, The semiconductor device according to one embodiment of the present invention has a housing 7 It can be used for the memory, CPU, etc. built into 302.

[0472] FIG. 55C shows a portable information terminal having a display portion 7502 incorporated in a housing 7501. Others include operation buttons 7503, external connection port 7504, speaker 7505, microphone 750 6 and the like. The semiconductor device according to one embodiment of the present invention is built in a housing 7501. The display portion 7502 can be used for a mobile memory, a CPU, etc. It can be made to be extremely high definition, so it can be used in small to medium-sized devices with full high definition, 4K, or It can display a variety of images, including 8k, and produces extremely clear images.

[0473] FIG. 55D shows a video camera, which includes a first housing 7701, a second housing 7702, a display unit 7 703, operation keys 7704, a lens 7705, a connection part 7706, etc. The display unit 7704 and the lens 7705 are provided in the first housing 7701, and the display unit 7703 is provided in the second housing 7702. The first housing 7701 and the second housing 7702 are connected to each other. The first housing 7701 and the second housing 7702 are connected by a connector 7706, and the angle between them is The image on the display unit 7703 can be changed by the connection unit 7706. 06 according to the angle between the first housing 7701 and the second housing 7702. The imaging device of one embodiment of the present invention may be provided at the focal position of the lens 7705. The semiconductor device according to one embodiment of the present invention is built in the first housing 7701. It can be used in integrated circuits, CPUs, etc.

[0474] FIG. 55(E) shows a digital signage system, which is a display unit 792 installed on a utility pole 7921. 2. A display device according to one embodiment of the present invention includes a control circuit for the display portion 7922. It is possible.

[0475] FIG. 56(A) shows a notebook personal computer, which includes a housing 8121 and a display unit 812. 2, a keyboard 8123, a pointing device 8124, etc. The semiconductor device according to the present invention can be applied to a CPU and a memory built in the housing 8121. The display portion 8122 can be made to have extremely high resolution, so it can be used in small and medium-sized It is possible to display 8K images while using a HDMI cable, resulting in extremely clear images.

[0476] Figure 56(B) shows the exterior of the car 9700. Figure 56(C) shows the driver's seat of the car 9700. The automobile 9700 includes a body 9701, wheels 9702, a dashboard 9703, a The semiconductor device of one embodiment of the present invention includes a display portion of the automobile 9700 and For example, the display unit 971 shown in FIG. The semiconductor device of one embodiment of the present invention can be provided in the display portion 9710 to the display portion 9715.

[0477] The display portion 9710 and the display portion 9711 are display devices provided on a windshield of an automobile. The display device or the input / output device according to one embodiment of the present invention is a display device, Alternatively, electrodes of the input / output device may be formed using a light-transmitting conductive material. It can be used as a so-called see-through display device or input / output device, allowing you to see through to the other side. If it is a see-through display device or an input / output device, it is possible to Therefore, the display device or input device according to one embodiment of the present invention does not obstruct the view even when driving. The output device can be installed on the windshield of the automobile 9700. Or, in the input / output device, a display device or a transistor for driving the input / output device, etc. When provided, an organic transistor using an organic semiconductor material or a transistor using an oxide semiconductor is used. A light-transmitting transistor such as a transistor is preferably used.

[0478] The display unit 9712 is a display device provided in a pillar portion. By displaying the image from the imaging means on the display unit 9712, the view blocked by the pillars can be cleared. The display unit 9713 is a display device provided in the dashboard. For example, an image captured by an imaging means provided on the vehicle body is displayed on the display unit 9713. This allows the driver to supplement the view obstructed by the dashboard. By projecting images from the imaging means installed in the In addition, by projecting images that complement the invisible parts, it is possible to create a more natural and natural appearance. Safety can be checked without any sense of discomfort.

[0479] Also, Figure 56(D) shows the interior of a car with bench seats for the driver and passenger seats. The display unit 9721 is a display device or an input / output device provided in the door. For example, by displaying an image from an imaging means provided on the vehicle body on the display unit 9721, It can complement the view blocked by the door. The display unit 9723 is a display device provided in the center of the seat surface of the bench seat. The display device is installed on the seat or backrest, and the display device is The heat generated by the display device can also be used as a seat heater.

[0480] The display unit 9714, the display unit 9715, or the display unit 9722 displays navigation information, speech such as the odometer, tachometer, mileage, fuel level, gear status, and air conditioning settings. It is also possible to provide various other information. The above information can be changed as needed to suit the user's preferences. The images can also be displayed on the display units 9710 to 9713, the display unit 9721, and the display unit 9723. In addition, the display units 9710 to 9715 and the display units 9721 to 9723 are illuminated. The display units 9710 to 9715 can also be used as a lighting device. The portion 9721 to the display portion 9723 can also be used as a heating device.

[0481] 57(A) shows the appearance of the camera 8000. The camera 8000 is housed in a housing 800 1, display unit 8002, operation buttons 8003, shutter button 8004, connection unit 8005 The camera 8000 can also be fitted with a lens 8006.

[0482] The coupling portion 8005 has electrodes and is connected to the finder 8100 (to be described later) as well as the strobe device. etc. can be connected.

[0483] Here, the camera 8000 is assumed to have a lens 8006 that is detached from the housing 8001 and replaced. However, the lens 8006 and the housing may be integrated.

[0484] An image can be taken by pressing the shutter button 8004. 8002 has a function as a touch panel, and an image is taken by touching the display unit 8002. It is also possible to do this.

[0485] The display device or the input / output device of one embodiment of the present invention can be applied to the display portion 8002. Cut.

[0486] FIG. 57(B) shows an example in which a finder 8100 is attached to a camera 8000. is doing.

[0487] The finder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc. .

[0488] The housing 8101 has a coupling portion that engages with the coupling portion 8005 of the camera 8000. A viewfinder 8100 can be attached to the camera 8000. The device has electrodes, and displays images received from a camera 8000 via the electrodes on a display unit 8102. It can be shown.

[0489] The button 8103 functions as a power button. The 8102 display can be switched on and off.

[0490] The semiconductor device of one embodiment of the present invention is mounted in an integrated circuit or an image sensor in a housing 8101. can be applied.

[0491] In addition, in Figures 57(A) and (B), the camera 8000 and the finder 8100 are separate electronic devices. The camera 8000 is configured to have a detachable structure. The display device may have a built-in finder equipped with one of the display devices or the input / output device.

[0492] FIG. 57(C) shows the appearance of the head mounted display 8200.

[0493] The head-mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0494] A cable 8205 supplies power from a battery 8206 to the main body 8203. 203 is equipped with a wireless receiver and the like, and displays video information such as received image data on a display unit 8204 In addition, a camera installed in the main body 8203 can capture the image of the user's eyeballs and eyelids. By capturing the user's movements and calculating the coordinates of the user's viewpoint based on that information, can be used as input means.

[0495] Also, a plurality of electrodes may be provided at positions on the mounting part 8201 that touch the user. . By detecting the current flowing through the electrodes as the main body 8203 moves along with the movement of the user's eyeball, it may have a function of recognizing the user's viewing point. Also, by detecting the current flowing through the electrodes, it may have a function of monitoring the user's pulse. Also, the mounting part 820 1 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display part 8204. Also, it may detect movements of the user's head and change the video displayed on the display part 8204 in accordance with the movements.

[0496] The semiconductor device according to one aspect of the present invention can be applied to the integrated circuit inside the main body 8203.

[0497] This embodiment can be implemented in appropriate combination with other embodiments and examples described in this specification, at least in part.

[0498] (Embodiment 16) In this embodiment, a usage example of an RF tag using the semiconductor device according to one aspect of the present invention will be described with reference to FIG. 58.

[0499] <Usage Example of RF Tag> The uses of RF tags are extensive. For example, banknotes, coins, securities, bearer bonds, certificates (such as driver's licenses and resident cards, see FIG. 58(A)), vehicles (such as bicycles, see FIG. 58(B )), packaging containers (such as wrapping paper and bottles, see FIG. 58(C)), recording media (DVDs and Video tapes, etc. (See Figure 58(D)), personal belongings (bags, glasses, etc.), food, plants, animals objects, the human body, clothing, daily necessities, medical supplies including medicines and pharmaceuticals, or electronic devices (including liquid crystal displays) (electroluminescence display devices, television devices, or mobile phones) or attached to each item It can be attached to a tag (see Figure 58(E) and Figure 58(F)) and used.

[0500] The RF tag 4000 according to one embodiment of the present invention can be attached to or embedded in a surface. It is fixed to the object. For example, if it is a book, it is embedded in the paper and the packaging is made of organic resin. If so, the RF tag according to one aspect of the present invention is embedded in the organic resin and fixed to each article. The GU4000 is small, thin, and lightweight, so even after it is fixed to an object, it does not lose its shape. It does not impair the design of banknotes, coins, securities, bearer bonds, or certificates. By providing an RF tag 4000 according to one embodiment of the present invention to a document or the like, an authentication function is provided. By utilizing this authentication function, it is possible to prevent counterfeiting. The present invention can be applied to vessels, recording media, personal belongings, food, clothing, household goods, electronic devices, etc. By attaching an RF tag according to one aspect, the efficiency of a system such as an inspection system can be improved. Furthermore, even in the case of vehicles, the RF tag according to one aspect of the present invention can be attached. This can improve security against theft and the like.

[0501] As described above, an RF tag using a semiconductor device according to one embodiment of the present invention is By using it for each of the applications listed above, it is possible to reduce the operating power consumption, including the writing and reading of information. This allows for a longer maximum communication distance. Since it can retain information for an extremely long period of time, it is suitable for applications where writing and reading are performed infrequently. can also be suitably used.

[0502] Note that this embodiment mode may be combined as appropriate with other embodiment modes and examples shown in this specification. It is possible. [Example]

[0503] In this example, a sample having a capacitance element according to the present invention is fabricated, and the capacitance of the capacitance element is measured. did.

[0504] The sample was prepared by first depositing a first silicon oxide layer on a single crystal silicon wafer using thermal oxidation. Next, a silicon dioxide film was formed on the first silicon dioxide film by sputtering. A tungsten silicon alloy film was formed to a thickness of 50 nm using the method described above. A resist mask was formed on the silicon alloy film by lithography.

[0505] Next, using the resist mask as an etching mask, the tongue is removed by dry etching. The tungsten silicon alloy film is processed to form a first electrode having a tungsten silicon alloy film. Successful.

[0506] Next, a plasma treatment containing oxygen gas is performed to form a film having a tungsten silicon alloy film. The surface of the first electrode is oxidized, and a tungsten silicon alloy film is formed on the surface of the first electrode. The oxidation film of the tungsten silicon alloy film was formed. A device with a high density plasma source (High Density Plasma device) is used. A mixture of Ar gas (flow rate 900 sccm) and oxygen gas (flow rate 40 sccm) was used. A microwave power of 4000 W was applied at a pressure of 666.65 Pa and a temperature of 4 The treatment was carried out at 00°C for 3600 seconds.

[0507] Next, a tantalum nitride film is formed on the oxide film of the tungsten silicon alloy film by using a sputtering method. A 30 nm thick film was formed on the silicon substrate, followed by a 170 nm thick tungsten film. Then, a resist mask was formed on the tungsten film by lithography.

[0508] Next, using the resist mask as an etching mask, the tongue is removed by dry etching. The tungsten film and the tantalum nitride film are processed to form a film having a tungsten film and a tantalum nitride film. A second electrode was formed.

[0509] Next, a second silicon oxide film was formed to a thickness of 300 nm by CVD. , a second silicon oxide film and a tungsten silicon alloy film are formed by lithography. A contact hole that passes through the oxide film and reaches the top surface of the first electrode and a second silicon oxide film A contact hole was formed through the second electrode to reach the top surface of the second electrode.

[0510] Next, a titanium film was formed to a thickness of 50 nm and an aluminum film to a thickness of 200 nm by sputtering. A titanium film was successively formed to a thickness of 50 nm.

[0511] Next, the titanium film, the aluminum film, and the titanium film are processed using a lithography method, Titanium film, aluminum film, and titanium film wiring and measurement electrodes are formed. The capacitor element was fabricated in this manner.

[0512] Next, the capacitance-voltage measurement (CV measurement) of the fabricated capacitor element was carried out. The measurement voltage range was , -3V to +3V, and the measurement frequencies were 1kHz, 10kHz, and 100kHz. The capacitance element designed to measure 380 μm × 110 μm was measured. The results of the CV measurement are shown in Figure 59. As a result of the CV measurement, the capacitance of the capacitor element was measured to be 1.01 × 10 -10 [F] there were.

[0513] In addition, to measure the thickness of the oxide film on the tungsten silicon alloy film, the same The cross section of the sample prepared under oxidizing conditions was observed using STEM (Scanning Transmission Electron Microscopy). The results were obtained using STEM (Scanning Electron Microscopy). The cross-sectional image is shown in Figure 60. From Figure 60, the thickness of the oxide film on the tungsten silicon alloy film is approximately 14 nm. It turned out to be the case.

[0514] Next, the oxide film of the tungsten silicon alloy film is assumed to be a silicon oxide film. The capacitance of the oxide film, C ox , the dielectric constant in vacuum is ε0, the relative dielectric constant of the oxide film is ε, and the oxide The thickness of the oxide film is t ox Then, C ox =(ε×ε0) / t ox The silicon oxide film Relative permittivity ε = 3.8, ε0 = 8.854 × 10 -12 , t ox =14×10 -9 Calculated as When you put it out, C ox =2.4×10 -3 [F / m 2 ].

[0515] Therefore, the capacitance C of the capacitor element designed to be 380 μm × 110 μm is C = 2.4 × 10 -3 x380x10 -6 x110x10 -6 =1.00×10 -10 [F] and the above C -V measurement value is 1.01 x 10 -10 The result was almost the same as [F]. Therefore, the oxide film of the tungsten silicon alloy film has almost the same relative dielectric constant as the silicon oxide film. The results were estimated as follows. [Example]

[0516] In this example, XPS (X-ray Photoelectron Spectroscopy) of the oxide film of the tungsten silicon alloy film was performed. The sample was first prepared as a single crystal. A silicon oxide film was formed on the silicon wafer using a thermal oxidation method to a thickness of 50 nm. A tungsten silicon alloy film was deposited on the silicon oxide film by sputtering. Next, a heat treatment was carried out at 400°C in air for 1 hour. A tungsten silicon alloy oxide film was formed on the tungsten silicon alloy film to prepare the sample. For comparison, a sample without heat treatment was also prepared.

[0517] The samples prepared as described above were subjected to XPS analysis. The results of the test are shown in Figures 61(A) and (B). Figure 61(A) shows the results of the test without heat treatment. Fig. 61(B) shows the depth profile of the heat-treated sample. The epth profile of the tungsten silicon alloy film is shown in Fig. 1. An oxide film of tungsten silicon alloy film is formed on the top, and the tungsten concentration is It can be seen that the silicon concentration is higher.

[0518] For the heat-treated sample, the Si2p spectrum is shown in Figure 62(A). Figure 62(B) shows a montage plot of the O1s spectrum. Montage plot is a plot of the results of each depth (each region) using Binding Energy This is a graph plotted overlaid with y (binding energy). In the graph, the horizontal axis is the binding energy. The vertical axis is the sputtering time of the sample, which is the depth. The bottom of the vertical axis is the sample surface, and From these results, it is clear that the oxidation of the tungsten silicon alloy film Since a SiO2 peak is observed in the oxide film region, it is possible to determine the oxidation state of the tungsten silicon alloy film. The tungsten silicon alloy film was confirmed to be mainly composed of SiO2 before heat treatment. Silicon is deposited on the surface of the substrate, and when heat treated, it is oxidized and a silicon oxide film is formed. This is thought to be what inhibits the oxidation of tungsten. Therefore, in XPS analysis, the oxide film of the tungsten silicon alloy film is also found to be silicon oxide. The results suggest that silicon is the main component. I realized that this was the case. [Explanation of symbols]

[0519] 105 Conductors 110 Insulator 115 Conductors 120 Insulator 125 Insulator 160 Conductors 165 Conductors 170 Conductors 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel section 211 pixels 212 subpixels 212B subpixel 212G subpixel 212R subpixel 220 Photoelectric conversion element 230 pixel circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 filters 254B filter 254G filter 254R filter 255 Lens 256 light 257 Wiring 260 Peripheral Circuits 270 Peripheral Circuits 280 Peripheral Circuits 290 Peripheral Circuits 291 Light source 300 silicon substrate 301 Insulators 302 Insulators 303 Insulators 305 layers 306a Insulator 306b Semiconductors 310a Conductor 310b conductor 310c conductor 320 layers 330 Transistor 331 layers 340 layers 351 Transistor 352 transistors 353 Transistor 354 Transistor 360 photodiode 361 Anode 362 cathode 363 Low resistance region 365 Photodiode 366 Semiconductor Layer 367 Semiconductor Layer 368 Semiconductor Layer 370 Plug 371 Wiring 372 Wiring 373 Wiring 374 Wiring 380 Insulator 381 Insulators 400 boards 401 Insulator 402 Insulator 404 Conductors 406 Insulator 406a Insulator 406b Semiconductors 406c insulator 407 area 408 Insulator 409 Insulator 410 Insulator 412 Insulator 414 Conductors 415 Conductors 416a1 Conductors 416a2 Conductor 418 Insulator 423 Resist Mask 424a1 Insulator 424a2 Insulator 426 Conductors 427 Insulator 428 Insulator 429 Conductors 430 Conductors 431 Conductors 432 Conductors 433 Conductors 434 Conductors 437 Conductors 438 Conductors 440 Conductors 442 Conductors 444 Conductors 446 Insulator 450 Semiconductor Substrate 454 Conductors 460 areas 462 Insulator 464 Insulator 465 Insulator 466 Insulator 467 Insulator 468 Insulator 469 Insulator 470 Insulator 472 Insulator 474a area 474b area 475 Insulator 476a Conductors 476b Conductor 476c Conductor 477a Conductor 477b Conductor 477c Conductor 478a Conductor 478b Conductor 478c Conductor 479a Conductors 479b Conductors 479c Conductor 480a Conductor 480b Conductor 480c conductor 483a Conductor 483b Conductor 483c Conductor 483d Conductor 483e Conductor 483f Conductor 484a Conductor 484b Conductor 484c Conductor 484d Conductor 485a Conductor 485b Conductor 485c Conductor 485d Conductor 487a Electric conductor 487b Conductor 487c Conductor 488a Conductor 488b Conductor 488c Conductor 489a Conductors 489b Conductors 490a Conductors 490b Conductor 491a Conductors 491b Conductors 491c Conductor 492a Conductors 492b Conductor 492c Conductor 494 Conductors 496 Conductors 498 Insulator 550 Interposer 551 chips 552 terminals 553 Molding resin 600 panels 601 Printed wiring board 602 packages 603 FPC 604 Battery 700 boards 704a Conductor 706a Insulator 706b Semiconductors 706c insulator 710 Insulator 712 Insulator 712a Insulator 714a Conductor 714b Conductor 716a1 Conductors 716a2 Conductor 718 Insulator 718b Insulator 719 Light-emitting element 720 Insulator 721 Insulator 722 Conductors 723 Insulator 724a1 Insulator 724a2 Insulator 728 Insulator 731 terminal 732 FPC 733a wiring 734 Sealing material 735 Drive Circuit 736 Drive Circuit 737 pixels 741 Transistor 742 Capacitor 743 Switching Elements 744 signal line 750 board 751 Transistor 752 Capacitor 753 Liquid crystal elements 754 scan lines 755 signal line 781 Conductors 782 luminescent layer 783 Conductors 784 Bulkhead 791 Conductors 792 Insulators 793 Liquid Crystal Layer 794 Insulators 795 Spacer 796 Conductors 797 Circuit Board 800 RF tags 801 Communication Device 802 antenna 803 wireless signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 900 Semiconductor device 901 Power supply circuit 902 circuits 903 Voltage Generation Circuit 903A Voltage Generation Circuit 903B Voltage Generator Circuit 903C Voltage Generation Circuit 903D Voltage Generation Circuit 903E Voltage Generation Circuit 904 circuits 905 Voltage Generation Circuit 905A Voltage Generation Circuit 905E Voltage Generation Circuit 906 Circuit 911 Transistor 912 Transistor 912A Transistor 912B transistor 921 Control circuit 922 Transistor 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Elements 1207 Capacitor element 1208 Capacitor 1209 Transistor 1210 transistor 1213 Transistor 1214 transistor 1220 circuits 2100 transistors 2200 transistors 2201 Insulator 2202 Wiring 2203 Plug 2204 Insulator 2205 Wiring 2207 Insulators 2208 Insulator 2211 Semiconductor substrate 2212 Insulator 2213 Gate electrode 2214 Gate insulator 2215 Source and Drain Regions 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitor 3600sec processing time 4000 RF tags 6000 Display Module 6001 Top cover 6002 Lower cover 6003 FPC 6004 Touch Panel 6005 FPC 6006 Display Panel 6007 Backlight Unit 6008 Light source 6009 Frame 6010 printed circuit board 6011 Battery 7101 Housing 7102 Housing 7103 Display section 7104 Display section 7105 Microphone 7106 Speaker 7107 Operation key 7108 Stylus 7302 Housing 7304 Display section 7305 Display section 7311 Operation button 7312 Operation button 7313 Connection terminal 7321 Band 7322 Clasp 7501 Case 7502 Display section 7503 Operation button 7504 External connection port 7505 Speaker 7506 Microphone 7701 Housing 7702 Case 7703 Display section 7704 Operation key 7705 Lens 7706 Connection 7902 Display section 7921 Electric pole 7922 Display section 8000 Camera 8001 Case 8002 Display section 8003 Operation button 8004 Shutter button 8005 Joint 8006 Lens 8100 Finder 8101 Housing 8102 Display section 8103 Button 8121 Housing 8122 Display section 8123 keyboard 8124 pointing device 8200 Head Mounted Display 8201 Mounting part 8202 Lens 8203 Main unit 8204 Display section 8205 Cable 8206 Battery 9700 Automobiles 9701 Body 9702 wheels 9703 Dashboard 9704 Light 9710 Display section 9711 Display section 9712 Display section 9713 Display section 9714 Display section 9715 Display section 9721 Display section 9722 Display section 9723 Display section< / cpu>

Claims

1. a first transistor having silicon in a channel formation region, a second transistor having an oxide semiconductor in a channel formation region, and a capacitor; a gate of the first transistor, one of a source and a drain of the second transistor, and one electrode of the capacitor element are electrically connected to each other; a first insulating layer having a region located above a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as one electrode of the capacitor; a second insulating layer having a region located above the first conductive layer; a second conductive layer having a region located above the second insulating layer and functioning as the other electrode of the capacitor; a third insulating layer having a region located above the second conductive layer; an oxide semiconductor layer having a region located above the third insulating layer and including a channel formation region of the second transistor; a fourth insulating layer having a region located above the oxide semiconductor layer; a third conductive layer having a region located above the fourth insulating layer and functioning as a gate electrode of the second transistor; a fourth conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; In a cross-sectional view of the second transistor in a channel length direction, the fourth insulating layer has a first opening that overlaps with the oxide semiconductor layer and a second opening that does not overlap with the oxide semiconductor layer; the fourth conductive layer is electrically connected to the first conductive layer through the first opening and the second opening; the first conductive layer has a region overlapping with a channel formation region of the first transistor, the second conductive layer has a region overlapping with a channel formation region of the first transistor.

2. a first transistor having silicon in a channel formation region, a second transistor having an oxide semiconductor in a channel formation region, and a capacitor; a gate of the first transistor, one of a source and a drain of the second transistor, and one electrode of the capacitance element are electrically connected to each other; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the first transistor, a first insulating layer having a region located above a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as one electrode of the capacitor; a second insulating layer having a region located above the first conductive layer; a second conductive layer having a region located above the second insulating layer and functioning as the other electrode of the capacitor; a third insulating layer having a region located above the second conductive layer; an oxide semiconductor layer having a region located above the third insulating layer and including a channel formation region of the second transistor; a fourth insulating layer having a region located above the oxide semiconductor layer; a third conductive layer having a region located above the fourth insulating layer and functioning as a gate electrode of the second transistor; a fourth conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; In a cross-sectional view of the second transistor in a channel length direction, the fourth insulating layer has a first opening that overlaps with the oxide semiconductor layer and a second opening that does not overlap with the oxide semiconductor layer; the fourth conductive layer is electrically connected to the first conductive layer through the first opening and the second opening; the first conductive layer has a region overlapping with a channel formation region of the first transistor, the second conductive layer has a region overlapping with a channel formation region of the first transistor.

3. a first transistor having silicon in a channel formation region, a second transistor having an oxide semiconductor in a channel formation region, and a capacitor; a gate of the first transistor, one of a source and a drain of the second transistor, and one electrode of the capacitance element are electrically connected to each other; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the first transistor, a first insulating layer having a region located above a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as one electrode of the capacitor; a second insulating layer having a region located above the first conductive layer; a second conductive layer having a region located above the second insulating layer and functioning as the other electrode of the capacitor; a third insulating layer having a region located above the second conductive layer; an oxide semiconductor layer having a region located above the third insulating layer and including a channel formation region of the second transistor; a fourth insulating layer having a region located above the oxide semiconductor layer; a third conductive layer having a region located above the fourth insulating layer and functioning as a gate electrode of the second transistor; a fourth conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a fifth conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; In a cross-sectional view of the second transistor in a channel length direction, the fourth insulating layer has: a first opening that overlaps with the oxide semiconductor layer and also overlaps with the fourth conductive layer; a second opening and a third opening that do not overlap with the oxide semiconductor layer; and a fourth opening that overlaps with the oxide semiconductor layer and also overlaps with the fifth conductive layer; the fourth conductive layer is electrically connected to the first conductive layer through the first opening and the second opening; the fifth conductive layer is electrically connected to the other of the source and the drain of the first transistor through the fourth opening and the third opening; the first conductive layer has a region overlapping with a channel formation region of the first transistor, the second conductive layer has a region overlapping with a channel formation region of the first transistor.

Images