Manufacturing method of semiconductor device

Abstract

To realize a method of manufacturing a semiconductor device in which peeling of an insulating film in an end part region and generation of a foreign matter caused by the peeling are suppressed while suppressing creeping discharge in an end part.SOLUTION: A method of manufacturing a semiconductor device includes steps of preparing a semiconductor wafer W, forming a plurality of active regions 110 serving as a main current path in the semiconductor wafer, and forming a lattice-shaped dicing region D that partitions the plurality of active regions 110. This includes a step of forming a vertical crack C in the dicing region D using a blade, pressing the semiconductor wafer W from a surface of the semiconductor wafer W opposite to the surface on which a vertical crack C is formed, cleaving and dividing the semiconductor wafer W from the vertical crack C as a starting point, and singulating the semiconductor wafer W. In the formation of the dicing region D, the dicing region D has a configuration in which a stress relaxation film 20, an insulating film 19, and the semiconductor wafer W are stacked in this order from the outermost surface. In the formation of the vertical crack C, the vertical crack C is formed in a surface layer of the semiconductor wafer W from the side of the stress relaxation film 20.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] In recent years, development of power semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) using silicon carbide (SiC) as a semiconductor material has been progressing. While SiC has lower on-resistance and higher breakdown voltage compared to silicon, it is harder than silicon. Therefore, when a semiconductor wafer made of SiC is cut into individual pieces with a blade, the blade may tilt, which can cause distortion in the individual semiconductor substrates.

[0003] An example of a semiconductor device configuration that uses SiC as a semiconductor material and can suppress defects during dicing is that described in Patent Document 1. The semiconductor device described in Patent Document 1 has a configuration in which the dicing region, which is the region that comes into contact with a blade when a semiconductor wafer made of SiC is diced, is free of a film. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-47673 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the semiconductor device described in Patent Document 1 has a configuration in which there is no film in the dicing region, i.e., there is no insulating film at the edge of the semiconductor substrate, which may result in the risk of creeping discharge. Furthermore, if an insulating film is not provided, a self-alignment process cannot be used in the manufacture of the semiconductor device, which increases the number of processes using masks, which may result in an increase in manufacturing costs.

[0006] A known semiconductor wafer dicing method involves a scribing process, which forms cracks or grooves in the dicing region of the semiconductor wafer as starting points for dicing, followed by a breaking process, which applies pressure to the starting points to cleave the semiconductor wafer and separate it into individual pieces. Hereinafter, for ease of explanation, the dicing process consisting of the scribing process and the subsequent breaking process will be referred to as the "scribe-break process." Compared to the blade-based cutting method described above, the scribe-break process reduces the processing width in the dicing region and the load on the blade, and therefore its application to semiconductor devices made of hard semiconductor materials such as SiC in addition to silicon is also being considered.

[0007] In order to suppress creeping discharge in semiconductor devices that are separated into individual pieces by the scribe-and-break process, the inventors conducted extensive research into a configuration that has an insulating film in the dicing area, and as a result, it was found that peeling of the insulating film in the dicing area and the resulting generation of foreign matter occur during the scribing process.

[0008] In view of the above, an object of the present invention is to provide a method for manufacturing a semiconductor device that is configured to suppress creeping discharge at the edge of a semiconductor substrate while suppressing peeling of an insulating film in a dicing region during a scribing process and the resulting generation of foreign matter. [Means for solving the problem]

[0009] In order to achieve the above object, the method for manufacturing a semiconductor device according to claim 1 includes the steps of preparing a semiconductor wafer (W), forming a plurality of active regions (110) in the semiconductor wafer that serve as paths for main currents, forming a lattice-shaped dicing region (D) that partitions the plurality of active regions, forming vertical cracks (C) in the dicing region using a blade, and after the vertical cracks are formed, pressing the semiconductor wafer from the side of the semiconductor wafer opposite to the side on which the vertical cracks are formed, and dividing and singulating the semiconductor wafer using the vertical cracks as starting points, wherein in forming the dicing region, the dicing region is configured such that a stress relaxation film (20), an insulating film (19), and the semiconductor wafer are laminated in this order from the outermost surface, and in forming the vertical cracks, vertical cracks are formed in the surface layer of the semiconductor wafer from the side of the stress relaxation film, and in singulating the semiconductor wafer, the semiconductor wafer is cleaved using the vertical cracks as starting points.

[0010] This semiconductor device manufacturing method includes a step of stacking a dicing region of a semiconductor wafer in the following order from the top surface: a stress relaxation film, an insulating film, and a semiconductor wafer; or a stress relaxation film made of an insulating material, and a semiconductor wafer from the top surface. Then, a scribing step is performed from the stress relaxation film side to form vertical cracks in the surface layers of the insulating film and the semiconductor wafer, and a breaking step is performed to separate the semiconductor wafer from the vertical cracks, thereby manufacturing a semiconductor device. This allows a blade to press the semiconductor wafer through the insulating film or the stress relaxation film that also serves as an insulating film, thereby suppressing peeling of the insulating film or the stress relaxation film that also serves as an insulating film and the resulting generation of foreign matter during the scribing step. This makes it possible to manufacture a semiconductor device that is configured to suppress peeling of the insulating film or the stress relaxation film that also serves as an insulating film and the generation of foreign matter while suppressing creeping discharge at the edge of the semiconductor substrate.

[0011] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is an enlarged cross-sectional view showing a cross section of an end region. [Figure 3A] 3A to 3C are cross-sectional views showing a step of forming an epitaxial layer on a semiconductor substrate in the manufacturing process of the semiconductor device according to the embodiment. [Figure 3B] FIG. 3B is a cross-sectional view showing a step subsequent to FIG. 3A. [Figure 3C] FIG. 3C is a cross-sectional view showing a step subsequent to FIG. 3B. [Figure 3D] FIG. 3D is a cross-sectional view showing a step subsequent to FIG. 3C. [Figure 3E] FIG. 3B is a cross-sectional view showing a step subsequent to FIG. 3D. [Figure 3F] FIG. 3B is a cross-sectional view showing a step subsequent to FIG. 3E. [Figure 3G] FIG. 3C is a cross-sectional view showing a step subsequent to FIG. 3F. [Figure 3H] FIG. 3C is a cross-sectional view showing a step subsequent to FIG. 3G. [Figure 3I] FIG. 3C is a diagram showing a top view of the semiconductor wafer in the step of FIG. 3H. [Figure 3J] FIG. 3C is a cross-sectional view showing a step subsequent to FIG. 3H. [Figure 3K] FIG. 3C is a cross-sectional view showing a step subsequent to FIG. 3J. [Figure 4] 10A and 10B are diagrams showing the results of performing a scribing step and a breaking step on a sample of a comparative example having an insulating film. [Figure 5] 10A and 10B are diagrams showing the results of performing a scribing step and a breaking step on a sample of an example having an insulating film and a stress relaxation film. [Figure 6] FIG. 10 is a cross-sectional view showing another example of the configuration of the end region in the semiconductor device according to the modified example. [Figure 7] FIG. 10 is a cross-sectional view showing another example of the configuration of the end region in the semiconductor device according to the modified example. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.

[0014] (Embodiment) A semiconductor device 100 according to an embodiment will be described with reference to the drawings. The semiconductor device 100 is suitable for use in power semiconductor devices such as IGBTs and MOSFETs based on a SiC semiconductor substrate, but can also be used for other purposes. In this specification, the semiconductor device 100 will be described as a typical example in which it is configured as a vertical MOSFET, but is not limited to this configuration.

[0015] In the drawings, "n" or "p" attached to a component of the semiconductor device 100 indicates that electrons or holes are the majority carriers, respectively. Furthermore, a "+" attached to an n or p indicates a region with a relatively higher impurity concentration than the n or p layer without the "+" attached. A "++" attached to a p indicates a region with an even higher impurity concentration than the p layer with the "+" attached. For ease of explanation, as indicated by arrows in FIG. 1 , the direction along the substrate thickness direction of the semiconductor device 100 on the plane of the paper in FIG. 1 is referred to as the "z direction," the direction perpendicular to the z direction on the same plane is referred to as the "x direction," and the direction perpendicular to the xz plane is referred to as the "y direction." The x, y, and z directions in FIG. 1 and subsequent figures correspond to the x, y, and z directions in FIG. 1 .

[0016] [Basic configuration] 1, the semiconductor device 100 of this embodiment includes an active region 110 that serves as a path for the main current, a termination region 120 that surrounds the outer periphery of the active region 110, and an edge region 130 that surrounds the active region 110 and the termination region 120. The semiconductor device 100 is located in the edge region 130, and an end face 100a of the base that includes the semiconductor substrate 1 serves as a cleavage plane formed by a breaking process described below.

[0017] The active region 110 has a device structure such as a MOSFET, and serves as a path for a main current along the thickness direction of the substrate when the active region 110 is in an on-state. The active region 110 has, for example, a configuration in which trench MOS structures (described later) are repeatedly arranged along the planar direction of the substrate, and the number and arrangement of the trench MOS structures can be changed as appropriate.

[0018] It should be noted that the device configuration in the active region 110 described in this specification is merely an example, and may be another known MOSFET configuration, or another device configuration such as an IGBT. Details of the device configuration example of the active region 110 will be described later.

[0019] The termination region 120 is, for example, in the form of a frame surrounding the active region 110 when the substrate is viewed from above, and is a region provided to improve the breakdown voltage of the entire semiconductor device 100. The termination region 120 includes, for example, a JTE (Junction Termination Extension) structure 17 as a termination structure that relieves or disperses the electric field at the outer edge of the active region 110, and an n + and a n-type semiconductor region 18. + The n-type semiconductor region 18 functions as a channel stopper. The termination region 120 is, for example, a region including the JTE structure 17 and the n-type semiconductor region 18. + The type semiconductor region 18 is covered with an insulating film 19. The termination region 120 may have any configuration that can improve the breakdown voltage of the semiconductor device 100, and may have a configuration that has another breakdown voltage structure such as a guard ring structure instead of the JTE structure 17, and may be modified as appropriate.

[0020] The edge region 130 includes a portion that comes into contact with a blade during a scribing process in the manufacturing process of the semiconductor device 100, which will be described later. The edge region 130 is a region that becomes the edge of the semiconductor substrate 1 when the semiconductor wafer is divided into individual pieces, and may also be referred to as a dicing region. The edge region 130 is a frame-shaped region that surrounds the active region 110 and the termination region 120, and has a width that is wider than the width of the blade. As shown in FIG. 2 , the edge region 130 has a configuration in which a semiconductor base portion including the semiconductor substrate 1, an insulating film 19 that directly covers the semiconductor base portion, and a stress relief film 20 that covers the insulating film 19 are stacked in this order. In other words, the edge region 130 has an upper layer / lower layer / semiconductor base configuration, with the layer that contacts the semiconductor base portion being the lower layer and the layer that covers the lower layer being the upper layer, with the insulating film 19 being the lower layer and the stress relief film 20 being the upper layer. The term "semiconductor base" as used herein refers to a portion that is primarily composed of a semiconductor material such as SiC, and that is made up of a semiconductor substrate 1 and an n-type epitaxial layer 2 and a p-type epitaxial layer 3 that are stacked on the semiconductor substrate 1 by, for example, epitaxial growth.

[0021] The insulating film 19 is made of an insulating material such as SiO2 and is formed by CVD (Chemical Vapor Deposition). The insulating film 19 is covered with a stress relaxation film 20 to prevent peeling from the semiconductor base during the scribing process and to suppress the generation of foreign matter resulting from this.

[0022] The stress relaxation film 20 is made of, for example, an aluminum alloy material or a resin material such as polyimide, which has a Vickers hardness of less than 100 HV and is softer than the insulating film 19 (e.g., SiO2 has a Vickers hardness of approximately 1000 HV). The stress relaxation film 20 may have a thickness of, for example, 1 μm, but is preferably thicker than the insulating film 19. Examples of aluminum alloy materials include, but are not limited to, AlSi, AlSiCu, and AlCu. The resin material constituting the stress relaxation film 20 is not limited to polyimide, and may be other resin materials having a Vickers hardness of less than 100 HV. The Vickers hardnesses of AlSi and polyimide are 19 HV and 26 HV, respectively, which are less than 100 HV. The stress relaxation film 20 is made of, for example, the same material as an electrode or protective film formed on the semiconductor base, and is formed simultaneously during the formation process of the electrode or protective film. The stress relaxation film 20 is disposed on the outermost surface of the edge region 130, and serves to prevent the insulating film 19 from peeling off from the semiconductor base when cracks are formed in the surface layer of the insulating film 19 and the semiconductor base by a blade in the scribing step described below. This will be described in detail later.

[0023] Next, an example of a device structure in the active region 110 formed on the semiconductor substrate 1 will be described.

[0024] The semiconductor substrate 1 is an n-type semiconductor substrate made of a single crystal of a semiconductor material such as Si (silicon) doped with P (phosphorus) or SiC doped with N (nitrogen). + The semiconductor substrate 1 is, for example, an n-type semiconductor substrate. + The substrate is an n-type SiC substrate, and an n-type epitaxial layer 2 is laminated on the (0001) plane, that is, the Si plane.

[0025] The n-type epitaxial layer 2 is, for example, an n-type drift layer doped with nitrogen and having a lower impurity concentration than the semiconductor substrate 1. The n-type epitaxial layer 2 is, for example, an n-type SiC epitaxial layer and is formed by epitaxial growth. The surface layer of the n-type epitaxial layer 2 on the side opposite to the semiconductor substrate 1 is, for example, an n-type high-concentration region 4. The n-type high-concentration region 4 is, for example, a high-concentration n-type drift layer doped with nitrogen at a higher impurity concentration than the n-type epitaxial layer 2.

[0026] The surface layer of the n-type epitaxial layer 2 on the side opposite to the semiconductor substrate 1 includes an n-type high concentration region 4 and a first p + The second p region is located directly below the trench 9 and has a width wider than the trench 9. + The first p + The mold base region 5 and the second p + The first p-type base region 6 is doped with an impurity such as Al (aluminum). + The mold base region 5 is partially extended toward the trench 9 side, and the second p + The n-type heavily doped region 4 may be connected to the first p-type base region 6. + The mold base region 5 and the second p + The layout of the mold base region 6 is not limited to the example shown in FIG. 1, and may be changed as appropriate.

[0027] The p-type epitaxial layer 3 is provided on the surface layer of the n-type epitaxial layer 2 and is deposited by epitaxial growth. The surface layer of the p-type epitaxial layer 3 on the opposite side to the n-type epitaxial layer 2 is, for example, + type source region 7 and p ++ and a contact region 8. + The source region 7 is p ++ The contact region 8 and the trench 9 are in contact with each other. ++ The contact region 8 is, for example, between the two trenches 9 and is located on the first p + It is disposed in a region located above the mold base region 5 .

[0028] The trench 9 is a groove extending in the z direction from the surface of the p-type epitaxial layer 3, and is located at the second p-type epitaxial layer 2. + The trenches 9 have a depth that reaches the p-type base region 6. A plurality of trenches 9 are formed at intervals, and their inner walls and bottom surfaces are covered with a gate insulating film 10 made of an insulating material such as SiO2. The inside of the gate insulating film 10 of the trench 9 is filled with a gate electrode 11 made of a material such as polysilicon, and the trench 9 is electrically insulated from the gate electrode 11 by the gate insulating film 10. The gate insulating film 10 covers not only the inside of the trench 9 but also part of the surface layer of the p-type epitaxial layer 3 and the outer peripheral region of the trench 9, and is covered together with the gate electrode 11 by an interlayer insulating film 12.

[0029] The interlayer insulating film 12 is provided, for example, on the main surface of the semiconductor base on the p-type epitaxial layer 3 side (hereinafter simply referred to as the "main surface"), and covers the gate insulating film 10 and the gate electrode 11. + A part of the type source region 7 and p ++ A contact hole is provided exposing the mold contact region 8 .

[0030] The source electrode 13 is made of, for example, a metal material such as Al or an alloy material thereof, and covers the active region 110 including the interlayer insulating film 12 on the main surface of the semiconductor base. The source electrode 13 is connected to the n-type semiconductor substrate 11 through a contact hole in the interlayer insulating film 12. + Type source region 7 and p ++ While it is in contact with the die contact region 8, it is electrically insulated from the gate electrode 11 by an interlayer insulating film 12. A plating film 14 made of a metal material or its alloy material is laminated on the source electrode 13, for example, to improve contact with solder or the like. A protective film 15 made of a resin material such as polyimide is laminated on the plating film 14 in areas other than the areas where solder or the like is to be provided. A back surface electrode 16 that functions as a drain electrode is formed on the back surface of the semiconductor base opposite the main surface.

[0031] The above is the basic configuration of the semiconductor device 100 according to the embodiment. The semiconductor device 100 has an edge region 130 in which the insulating film 19 and the stress relaxation film 20 are stacked in this order on the semiconductor base, and in the scribing step of the manufacturing process described next, a blade presses the insulating film 19 via the stress relaxation film 20. This prevents the insulating film 19 from peeling off from the semiconductor base in the scribe-and-break step.

[0032] [Manufacturing method] Next, a method for manufacturing semiconductor device 100 will be described with reference to Figures 3A to 3K. Figures 3A to 3H, 3J, and 3K are cross-sectional views including a cross section corresponding to Figure 1, and show a part of a semiconductor wafer in the middle of manufacturing.

[0033] First, for example, n + A semiconductor substrate 1 made of an n-type SiC substrate is prepared. Next, as shown in Fig. 3A, a first n-type epitaxial layer 2a made of SiC is epitaxially grown on the main surface of the semiconductor substrate 1 while doping it with n-type impurities such as nitrogen atoms. At this time, the first n-type epitaxial layer 2a is epitaxially grown to a thickness of, for example, several tens of micrometers.

[0034] Next, a pattern mask for ion implantation (not shown) is formed of an oxide film or the like by photolithography on the surface of the first n-type epitaxial layer 2a on the side opposite to the semiconductor substrate 1. Then, p-type impurities such as Al atoms are doped into the openings of the pattern mask for ion implantation (not shown) on the surface of the first n-type epitaxial layer 2a, forming first p-type impurities spaced apart from each other, as shown in FIG. 3B, for example. + Mold area 5a and 2nd p + The first p + Mold area 5a, 2nd p + The mold regions 5b are respectively + A part of the mold base region 5, the second p + This is the portion that will become the mold base region 6 .

[0035] Subsequently, a part of the ion implantation pattern mask (not shown) is removed, and n-type impurities such as nitrogen atoms are ion-implanted to form the first p-type epitaxial layer 2a in the surface layer thereof. + Mold area 5a and 2nd p + A lower n-type heavily doped region 4a is provided between the n-type region 5b and the lower n-type heavily doped region 4a.

[0036] 3C, a second n-type epitaxial layer 2b is epitaxially grown on the first n-type epitaxial layer 2a, thereby forming an n-type epitaxial layer 2.

[0037] Thereafter, a pattern mask for ion implantation (not shown) is formed on the surface of the second n-type epitaxial layer 2b using, for example, an oxide film by the same method as described above. P-type impurities such as Al atoms are implanted into the openings of this mask (not shown), and the first p-type impurities are implanted into the openings of the mask (not shown). + p on mold area 5a + A mold region is formed. + The mold base region 5 and the second p + A mold base region 6 is formed.

[0038] Next, a portion of the ion implantation pattern mask (not shown) is removed, and n-type impurities such as nitrogen atoms are implanted into the openings of the mask to form an upper n-type heavily doped region 4b in a portion of the surface layer of the second n-type epitaxial layer 2b, thereby forming an n-type heavily doped region 4.

[0039] Subsequently, a p-type epitaxial layer 3 made of SiC is epitaxially grown on the n-type epitaxial layer 2 to a thickness of, for example, 1 to several μm while doping it with p-type impurities such as Al atoms.

[0040] Then, for example, an ion implantation pattern mask (not shown) is formed on the surface of the p-type epitaxial layer 3 using an oxide film in the same manner as described above, and n-type impurities such as phosphorus (P) are implanted into the openings of the mask to form n + Then, the n-type source region 7 is formed. +The mask (not shown) used to form the n-type source region 7 is removed, and a new pattern mask (not shown) for ion implantation is formed on the n-type epitaxial layer 2 in the same manner as described above. P-type impurities such as Al atoms are implanted into the openings of this mask (not shown), and n + p-type source region 7 ++ A type contact region 8 is formed. Next, an oxide film is laminated on a mask (not shown), and a new pattern mask (not shown) for ion implantation having openings at different positions is formed by photolithography. P-type impurities such as Al atoms are implanted into the openings of this new mask (not shown), forming the JTE structure 17. After that, the outside (n + n-type impurities are implanted into the region located opposite the n-type source region 7, + 3D.

[0041] Thereafter, a trench forming pattern mask (not shown) is formed on the surface of the p-type epitaxial layer 3 using an oxide film, for example, by the same method as described above. Next, as shown in FIG. 3E, for example, a second p + A trench 9 is formed so as to reach the mold base region 6. After the trench 9 is formed, the trench forming pattern mask (not shown) is removed.

[0042] Next, an insulating film made of SiO2 or the like is formed by, for example, CVD on the surface of the p-type epitaxial layer 3 as well as on the inner wall and bottom surface of the trench 9. A portion of the insulating film covering the surface of the p-type epitaxial layer 3 is removed. This forms the gate insulating film 10 and the insulating film 19. Next, a polysilicon layer doped with, for example, P atoms is formed inside the gate insulating film 10, and unnecessary portions are removed to form the gate electrode 11. This results in the semiconductor wafer having the configuration shown in FIG. 3F.

[0043] Next, an insulating material such as phosphorus glass is deposited on the surface of the p-type epitaxial layer 3 to a thickness of about 1 μm to form an insulating film, and then the portion of the insulating film that is not part of the trench gate structure is removed by photolithography etching. + Type source region 7 and p ++ The interlayer insulating film 12 is formed in a pattern shape having contact holes that expose the mold contact regions 8. Thereafter, the surface of the interlayer insulating film 12 is planarized by, for example, a reflow process using heat.

[0044] Then, a front surface electrode made of a conductive material such as Ni (nickel) is formed by sputtering or the like to cover the interlayer insulating film 12 and the inside of the contact hole. After that, a back surface electrode 16 made of a conductive material such as Ni is formed by sputtering or the like on the surface of the semiconductor substrate 1 opposite to the n-type epitaxial layer 2. Next, the semiconductor wafer on which the front surface electrode and back surface electrode 16 have been formed is subjected to a heat treatment at about 1000°C in an inert gas atmosphere such as nitrogen. As a result, the front surface electrode is turned into an n-type electrode. + Type source region 7 and p ++ The contact region 8 and the back electrode 16 each form an ohmic junction with the semiconductor substrate 1. Next, the front electrode side is washed with sulfuric acid / hydrogen peroxide (SPM) to remove unreacted Ni (nickel) other than in the contact holes (self-aligned silicide). After that, a film of a conductive material such as Al is laminated, and then patterned by photolithography etching to form the source electrode 13 with a predetermined pattern shape.

[0045] Thereafter, a seed layer (not shown) is formed on the source electrode 13 by sputtering or the like, and then a plating film 14 is formed by electroplating. Next, a film made of an insulating material such as polyimide is formed by spin coating or the like on the surface of the semiconductor wafer facing the plating film 14, and a portion covering the plating film 14 is removed by photolithography etching to form a protective film 15. This results in the semiconductor wafer W in the state shown in FIG. 3H. At this point, as shown in FIG. 3I, the semiconductor wafer W is in a state in which multiple active regions 110 having MOSFET structures and a frame-like termination region 120 (not shown) surrounding each active region 110 are partitioned by a grid-like dicing region D. This dicing region D corresponds to the edge region 130 that will come into contact with the blade in the subsequent dicing process.

[0046] Next, as shown in Figure 3J, for example, a blade B is run along the edge region 130 of the semiconductor wafer, i.e., the dicing region D, to press against the insulating film 19 and the semiconductor base via the stress relaxation film 20. At this time, the surface of the semiconductor wafer W on the back electrode 16 side is temporarily fixed with an adhesive or the like to a support substrate (not shown) made of glass or the like. This scribing process generates vertical cracks C in the insulating film 19 and part of the surface layer of the semiconductor base of the semiconductor wafer W, along the thickness direction of the substrate.

[0047] Next, for example, a protective film F is attached to the surface of the semiconductor wafer W on which the vertical crack C is formed. After the semiconductor wafer W is removed from the support substrate (not shown), a fixing tape T is attached to the surface of the semiconductor wafer W facing the back electrode 16. Then, as shown in FIG. 3K, the semiconductor wafer W is placed on a pedestal P. At this time, the pedestal P supports, for example, the edge of the semiconductor wafer W, leaving the portion of the semiconductor wafer W where the vertical crack C is formed hollow. A breaking plate BP is then pressed against the surface of the semiconductor wafer W opposite the surface where the vertical crack C is formed, at a position directly above the portion where the vertical crack C is formed. At this time, for example, an alignment mark (not shown) may be formed in advance on the semiconductor wafer W, and the breaking plate BP is aligned using an imaging device such as a camera. The semiconductor wafer W is then pressed against the breaking plate BP, and the semiconductor wafer W is cleaved using the pedestal P in a three-point bending manner, starting from the vertical crack C. As a result, the semiconductor wafer W is divided and separated into individual pieces by cleavage, so that the end faces 100a become cleavage surfaces, and the stress relaxation film 20 can be used to manufacture a semiconductor device 100 having a structure in which peeling of the insulating film 19 and the resulting generation of foreign matter are suppressed.

[0048] The above is the basic manufacturing method of semiconductor device 100. Note that the steps of forming active region 110 and termination region 120 may be modified as appropriate depending on the device configuration in active region 110 and the structure of termination region 120. Also, although the above describes an example in which stress relaxation film 20 is formed simultaneously with the step of forming protective film 15, this is not limiting, and stress relaxation film 20 may also be formed simultaneously with source electrode 13. In this case, by forming a conductive film that constitutes source electrode 13 and patterning the conductive film so that a portion that covers insulating film 19 remains, source electrode 13 and stress relaxation film 20 can be formed in a single step.

[0049] [Effect of stress relaxation film] Next, the prevention of peeling of the insulating film 19 by the stress relaxation film 20 in the scribe and break process will be described with reference to FIGS.

[0050] In the evaluation results shown in Figure 4, "x" means that peeling of the insulating film or the insulating film and the film covering it was observed in at least one of the scribing and breaking processes. In the evaluation results shown in Figure 5, "o" means that peeling of the insulating film or the insulating film and the film covering it was not observed in the scribing and breaking processes.

[0051] First, we will explain the cases where the scribing and breaking processes were performed on samples of Comparative Examples 1 to 4, which have a configuration in which the insulating film covering the semiconductor base is exposed to the outside and a configuration in which the insulating film is covered with a hard film. As shown in Figure 4, samples of Comparative Examples 1 to 4 were prepared, and the scribing and breaking processes were performed on each, and the state of the insulating film in each process was confirmed. All of the samples of Comparative Examples 1 to 4 have a configuration in which the semiconductor base is made of SiC, and the surface of the SiC is covered with an insulating film made of SiO2 with a thickness of 1 μm.

[0052] In the sample of Comparative Example 1, no other film was formed on the insulating film (SiO2), leaving the SiO2 exposed. In the sample of Comparative Example 1, as shown in Figure 4, for example, immediately after the scribing process, peeling of the insulating film with a width of 11 to 12 μm occurred along the scribe line surrounded by the dashed line, and the peeling of the insulating film remained even after the breaking process.

[0053] In the sample of Comparative Example 2, a 0.6 μm thick film made of polysilicon is laminated on an insulating film (SiO2), and the SiO2 is covered with the polysilicon film. In the sample of Comparative Example 2, just after the scribing process, peeling of about 20 μm in width occurred in the polysilicon film and insulating film over a wide area along the scribe line, similar to Comparative Example 1, and this peeling remained even after the breaking process.

[0054] In the sample of Comparative Example 3, a 0.05 μm thick film made of Ti (titanium) was laminated on an insulating film (SiO2), and the SiO2 was covered with the Ti film. In the sample of Comparative Example 3, immediately after the scribing process, although the frequency was lower than in Comparative Examples 1 and 2, many peelings with widths of about 13 to 17 μm occurred in the Ti film and insulating film, and these peelings remained even after the breaking process.

[0055] In the sample of Comparative Example 4, a film composed of a 0.21 μm thick TiN (titanium nitride) / Ti laminated film was formed on an insulating film (SiO2), and the SiO2 was covered with a TiN / Ti film. In the sample of Comparative Example 4, similar to Comparative Example 3, many peels about 20 μm wide occurred in the TiN / Ti film and insulating film immediately after the scribing process, and these peels remained even after the breaking process.

[0056] Furthermore, all of the samples of Comparative Examples 1 to 4 had numerous foreign particles near the scribe lines that appeared to be caused by peeling of the insulating film or the insulating film and the film covering it. These results indicate that in semiconductor wafers in which the semiconductor base made of SiC is covered with an SiO2 film or a hard film / SiO2 film with a Vickers hardness of 100 HV or more, peeling of the insulating film and resulting foreign particles occur during the scribing process. Although not shown in Figure 4, the samples of Comparative Examples 1 to 4 also showed similar results when the scribe-break process was performed in a direction perpendicular to the scribe lines in Figure 4.

[0057] In contrast, as shown in Fig. 5, the samples of Examples 1 and 2 were evaluated in the same manner as the samples of Comparative Examples 1 to 4. In both the samples of Examples 1 and 2, a semiconductor base made of SiC is covered with an insulating film 19 made of SiO2. The sample of Example 1 has a structure in which the insulating film 19 is covered with a stress relaxation film 20 made of AlSi and having a thickness of 5 µm. The sample of Example 2 has a structure in which the insulating film 19 is covered with a stress relaxation film 20 made of polyimide and having a thickness of 10 µm.

[0058] In the samples of Examples 1 and 2, no peeling of the insulating film or generation of foreign matter was observed immediately after the scribing process or after the breaking process. These results indicate that in semiconductor wafers in which a semiconductor base made of SiC is covered with a soft film / SiO2 film having a Vickers hardness of less than 100 HV, peeling of the insulating film and the resulting generation of foreign matter can be suppressed during the scribe-and-break process. In other words, by covering the insulating film 19 with a stress relaxation film 20 and performing the scribing process through the stress relaxation film 20, peeling of the insulating film 19 and the generation of foreign matter can be suppressed. Note that, although not shown in FIG. 5, the samples of Examples 1 and 2 also showed similar results when the scribe-and-break process was performed along a direction perpendicular to the scribe line in FIG. 5.

[0059] In the semiconductor device 100 of the embodiment, the edge region 130, which was the dicing region D, is covered with the insulating film 19 and the stress relaxation film 20, and the insulating film 19 suppresses creeping discharge. Furthermore, since the insulating film 19 is covered with the stress relaxation film 20 in the edge region 130, peeling of the insulating film 19 from the semiconductor base during the scribe-and-break process and the resulting generation of foreign matter can be suppressed. Therefore, the semiconductor device 100 has a structure that suppresses creeping discharge, peeling of the insulating film 19, and generation of foreign matter in the edge region 130. While the above description has been given as a representative example in which the semiconductor base constituting the semiconductor device 100 is made of SiC, the present invention is not limited to this example. The semiconductor device 100 can achieve the same effect even if, for example, the semiconductor base is made primarily of silicon.

[0060] (Variation) The semiconductor device 100 may have a laminated structure in which the stress relaxation film 20 is made of a first layer 201 and a second layer 202, as shown in Fig. 6, for example. Alternatively, the semiconductor device 100 may have a structure in which the semiconductor base is directly covered with the stress relaxation film 20, which is made of an insulating material such as polyimide and also serves as the insulating film 19, as shown in Fig. 7, for example. In this case, the stress relaxation film 20 may be a single film, or may be a laminated film in which multiple layers are laminated. These variations also result in the semiconductor device 100 having the same effects as those described above.

[0061] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one, or less than one, are also within the scope and spirit of the present disclosure.

[0062] In the above embodiment, the insulating film 19 is made of SiO2 and is formed by CVD, but the present invention is not limited to this. For example, if the semiconductor substrate 1 is made of silicon, the insulating film 19 may be made of SiO2 formed by thermal oxidation.

[0063] It goes without saying that in each of the above embodiments, the elements constituting the embodiments are not necessarily essential unless they are specifically stated as essential or are clearly considered essential in principle. Furthermore, in each of the above embodiments, when numerical values ​​such as the number, values, amounts, and ranges of the components of the embodiments are mentioned, they are not limited to the specific numbers unless they are specifically stated as essential or are clearly limited to a specific number in principle. Furthermore, in each of the above embodiments, when the shapes, positional relationships, etc. of the components are mentioned, they are not limited to the shapes, positional relationships, etc., unless they are specifically stated or are clearly limited to a specific shape, positional relationship, etc. in principle. [Explanation of symbols]

[0064] 1. Semiconductor substrate 100a end face 110 Active area 130 End area 19 Insulating film 20 Stress relaxation film C Vertical crack D Dicing area W semiconductor wafer

Claims

1. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor wafer (W); forming a plurality of active regions (110) in the semiconductor wafer, the active regions serving as paths for main currents; forming a lattice-shaped dicing region (D) that partitions the plurality of active regions; forming a vertical crack (C) in the dicing area using a blade; After forming the vertical crack, pressing the semiconductor wafer from a surface of the semiconductor wafer opposite to the surface on which the vertical crack is formed, and dividing the semiconductor wafer into individual pieces using the vertical crack as a starting point, In forming the dicing region, the dicing region is configured by laminating a stress relaxation film (20), an insulating film (19), and the semiconductor wafer in this order from the outermost surface, In forming the vertical crack, the vertical crack is formed in the surface layer of the semiconductor wafer from the stress relaxation film side; In the step of dividing the semiconductor wafer into individual pieces, the semiconductor wafer is cleaved starting from the vertical crack.

2. In forming the dicing region, the insulating film is made of SiO ２ 2. The method for manufacturing a semiconductor device according to claim 1, comprising:

3. 3. The method for manufacturing a semiconductor device according to claim 1, wherein, in forming the dicing region, the stress relaxation film is configured to be thicker than the insulating film.

4. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the step of preparing the semiconductor wafer comprises preparing the semiconductor wafer made of SiC.

5. 5. The method for manufacturing a semiconductor device according to claim 4, wherein in forming the dicing region, the stress relaxation film is made of an aluminum alloy material or polyimide having a Vickers hardness of less than 100 HV.

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