Sequence generating apparatus and processing method

Abstract

To provide a small sequence generating apparatus capable of performing operations.SOLUTION: A sequence generating apparatus comprises a plurality of random number generation units connected in series, each random number generation unit outputting 0 from one of two outputs and 1 from the other output with a probability of one half when 1 is input, an OR circuit, and a plurality of input units each connected to a corresponding one of the plurality of random number generation units, each input unit receiving an output of the connected random number generation unit and a binary number sequence to be converted as inputs, and outputting, to the OR circuit, a value corresponding to a result of a logical AND operation between the inputs.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a number sequence generating device and processing method. [Background technology]

[0002] Techniques such as machine learning and image processing are used in a variety of fields. In recent years, it has become clear that operations using stochastic numbers are effective in the fields of machine learning and image processing. Non-Patent Document 1 discloses a related technique for realizing multiplication using stochastic numbers. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Akihiro Watanabe, Shigeru Yamashita, "Reducing SNG by Allowing Correlation in Stochastic Computing," IPSJ SIG Technical Report, Information Processing Society of Japan, March 9, 2017, Vol. 2017-ARC-225 No. 19, Vol. 2017-SLDM-179 No. 19, Vol. 2017-EMB-44 No. 19, pp. 1-6. Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, in the calculations using stochastic numbers related to Non-Patent Document 1, there is a demand for a compact number sequence generating device capable of performing the calculations.

[0005] An object of each aspect of the present disclosure is to provide a number sequence generating device and a processing method that can solve the above-mentioned problems. [Means for solving the problem]

[0006] According to one aspect of the present disclosure, a number sequence generation device includes a plurality of random number generation units connected in series, each of which outputs 0 from one of two outputs and 1 from the other with a 50% probability when a 1 is input; an OR circuit; and a plurality of input units, one connected to each of the plurality of random number generation units, which receive as input the outputs of the connected random number generation units and the binary number sequence to be converted, and output a value corresponding to the result of a logical AND operation between the inputs to the OR circuit.

[0007] According to another aspect of the present disclosure, a processing method is a processing method executed by a number sequence generation device having a plurality of random number generation units connected in series, an OR circuit, and a plurality of input units each connected to each of the plurality of random number generation units, wherein when a 1 is input to the random number generation unit, with a 50% probability the random number generation unit outputs a 0 from one of two outputs and a 1 from the other, and each of the plurality of input units is connected to each of the plurality of random number generation units, and receives as input the output of the random number generation unit to which it is connected and the binary number sequence to be converted, and outputs a value corresponding to the result of calculating the logical product of the inputs to the OR circuit.

[0008] According to each aspect of the present disclosure, it is possible to provide a compact number sequence generating device capable of performing calculations using stochastic numbers. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 10 is a diagram illustrating an example of multiplication of stochastic numbers using an AND gate. [Figure 2] FIG. 1 illustrates an example of a configuration of a stochastic number generator according to an embodiment of the present disclosure. [Figure 3] FIG. 1 is a diagram illustrating an example of the configuration of a complementary output random number generator according to an embodiment of the present disclosure. [Figure 4] FIG. 2 is a diagram illustrating an example of a configuration of a random number generator according to an embodiment of the present disclosure. [Figure 5]10 is a diagram illustrating an example of a relationship between a current flowing through a random number generator and a probability that the random number generator outputs 1 according to an embodiment of the present disclosure. FIG. [Figure 6] FIG. 2 is a diagram illustrating an example of input signals and output signals of a complementary output random number generator according to an embodiment of the present disclosure. [Figure 7] FIG. 10 is a diagram illustrating an example of the configuration of a random number generation unit according to an embodiment of the present disclosure when N is 3. [Figure 8] FIG. 10 is a diagram illustrating an example of the probability of each signal output by a random number generation unit according to an embodiment of the present disclosure. [Figure 9] FIG. 10 is a diagram illustrating an example of the configuration of a stochastic number generator according to an embodiment of the present disclosure when N is 3. [Figure 10] FIG. 10 is a diagram illustrating a first example of a state of an input unit according to an embodiment of the present disclosure when N is 3. [Figure 11] 11 is a diagram for explaining the probability P that the OR circuit shown in FIG. 10 outputs 1. FIG. [Figure 12] FIG. 10 is a diagram illustrating a second example of a state of the input unit according to an embodiment of the present disclosure when N is 3. [Figure 13] FIG. 13 is a diagram for explaining the probability P that the OR circuit shown in FIG. 12 outputs 1. [Figure 14] FIG. 10 is a diagram illustrating a third example of a state of the input unit according to an embodiment of the present disclosure when N is 3. [Figure 15] FIG. 15 is a diagram for explaining the probability P that the OR circuit shown in FIG. 14 outputs 1. [Figure 16] FIG. 2 is a diagram illustrating an example of a configuration of a circuit to be compared; [Figure 17] 17 is a diagram showing the configuration of a calculation unit included in the circuit shown in FIG. 16. FIG. [Figure 18] FIG. 2 is a diagram illustrating an example of a configuration of a circuit to be compared; [Figure 19] FIG. 1 is a first diagram for explaining the operation of a circuit to be compared. [Figure 20] FIG. 10 is a second diagram for explaining the operation of the comparison circuit. [Figure 21]FIG. 10 is a third diagram for explaining the operation of the comparison circuit. [Figure 22] FIG. 2 is a diagram illustrating a first example of the configuration of a comparator included in the circuit. [Figure 23] FIG. 10 is a diagram illustrating a second example of the configuration of a comparator included in the circuit. [Figure 24] FIG. 10 is a diagram illustrating a third example of the configuration of a comparator included in the circuit. [Figure 25] FIG. 2 is a diagram illustrating an example of the number of elements in a circuit and the number of elements in a stochastic number generator 1 according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, the embodiments will be described in detail with reference to the drawings. <Embodiment> A stochastic number generator 1 according to an embodiment of the present disclosure will be described with reference to the drawings. The stochastic number generator 1 is a system that generates a corresponding stochastic number for an N-bit binary number.

[0011] (About stochastic numbers) First, a stochastic number according to an embodiment of the present disclosure will be described. A stochastic number is a bit string consisting of 0 and 1, and represents information by the probability of 1 existing in the bit string.

[0012] For example, the 10-bit number "1100101001" has five 1's, so (5 / 10) = 0.5. Also, the 10-bit number "0100000010" has two 1's, so (2 / 10) = 0.2.

[0013] Similarly, the 2-bit binary number 11 (decimal 3) becomes, for example, the 8-bit stochastic number 11011101. The 2-bit binary number 10 (decimal 2) becomes, for example, the 8-bit stochastic number 11010001. The 2-bit binary number 01 (decimal 1) becomes, for example, the 8-bit stochastic number 00100010. The 2-bit binary number 00 (decimal 0) becomes, for example, the 8-bit stochastic number 00000000. Note that the above-mentioned stochastic numbers are monopolar representations. Stochastic numbers also have bipolar representations that can represent negative values.

[0014] Furthermore, when stochastic numbers are used, complex calculations can be realized with a simple circuit configuration. For example, multiplication of stochastic numbers can be realized with a single AND gate. Figure 1 shows an example of multiplication of stochastic numbers using an AND gate. As shown in Figure 1, the operation of 1100101001 (= 0.5) and 0100000010 (= 0.2) using an AND gate results in 0100000000 (= 0.1), which is a multiplication of 0.5 and 0.2. In addition, addition of stochastic numbers can be realized with a single multiplexer.

[0015] (Structure of a stochastic number generator) 2 is a diagram illustrating an example of the configuration of a stochastic number generator 1 according to an embodiment of the present disclosure. As shown in FIG. 2, the stochastic number generator 1 includes a random number generation unit 10, an input unit 20, and an OR circuit 30.

[0016] The random number generation unit 10 includes complementary output random number generators 101a1, 101a2, ..., 101aN, as shown in Fig. 2. Each of the complementary output random number generators 101a1, 101a2, ..., 101aN is connected in series in order, as shown in Fig. 2. Hereinafter, the complementary output random number generators 101a1, 101a2, ..., 101aN may be collectively referred to as complementary output random number generator 101a.

[0017] Each of the complementary output random number generators 101a has an input terminal IN (INput), an output terminal O (Output), and an output terminal CO. The input terminal IN receives a clock signal CLK. When the input terminal receives a 1 as the clock signal CLK, the output terminal O outputs either 0 or 1 with a 50% probability. The output terminal CO (Complementary Output) is the complementary output of the output terminal O. In other words, when the input terminal receives a 1 as the clock signal CLK, if the output terminal O outputs a 0, the output terminal CO outputs a 1, and if the output terminal O outputs a 1, the output terminal CO outputs a 0. Note that the same signal (0 or 1) is never output from the output terminal O and the output terminal CO at the same time.

[0018] 3 is a diagram illustrating an example of the configuration of a complementary output random number generator 101a according to an embodiment of the present disclosure. As shown in FIG. 3, the complementary output random number generator 101a includes a random number generator 1011 (denoted as RNG (Random Number Generator) in FIG. 3), a D-FF (D Flip-Flop) 1012, and a NOT circuit 1013.

[0019] The random number generator 1011 generates 0 or 1 with a 50% probability. Then, the random number generator 1011 outputs the generated signal (i.e., 0 or 1). FIG. 4 is a diagram showing an example of the configuration of the random number generator 1011 according to an embodiment of the present disclosure. For example, as shown in FIG. 4, the random number generator 1011 includes Josephson junctions 1011a and 1011b.

[0020] As shown in FIG. 4, one end of the Josephson junction 1011a is connected to one end of the Josephson junction 1011b. The other end of the Josephson junction 1011b is connected to ground GND. FIG. 5 is a diagram illustrating an example of the relationship between the current Ictl flowing through the random number generator 1011 and the probability that the random number generator 1011 outputs 1 according to an embodiment of the present disclosure. The relationship illustrated in FIG. 5 indicates the probability that the random number generator 1011 outputs 1 with respect to the current Ictl when the other end of the Josephson junction 1011a receives 1 as the clock signal CLK. In the example of the relationship illustrated in FIG. 5, the probability that the random number generator 1011 outputs 1 when the current Ictl is equal to the threshold Ith is 0.5. The probability that the random number generator 1011 outputs 1 when the current Ictl is greater than the threshold Ith is equal to the probability that the random number generator 1011 outputs 0 when the current Ictl is smaller than the threshold Ith, and each of these is 1 / 2.

[0021] The D-FF 1012 holds the signal output by the random number generator 1011 in response to the clock signal CLK. The D-FF 1012 also outputs the held signal from the output terminal O in response to the clock signal CLK.

[0022] The NOT circuit 1013 receives the signal output by the random number generator 1011. Then, the NOT circuit 1013 inverts the received signal and outputs the inverted signal from the output terminal CO.

[0023] 6 is a diagram showing an example of input signals and output signals of a complementary output random number generator 101a according to an embodiment of the present disclosure. When the input terminal of the complementary output random number generator 101a receives a 1 as a clock CLK signal, with a 50% probability, it outputs a 0 from the output terminal O and a 1 from the output terminal CO. Furthermore, when the input terminal of the complementary output random number generator 101a receives a 1 as a clock CLK signal, with a 50% probability, it outputs a 1 from the output terminal O and a 0 from the output terminal CO. Details of the operation of the random number generation unit 10 will be described later.

[0024] As shown in Fig. 2, the input unit 20 includes switches 201a1, 201a2, ..., 201aN. As shown in Fig. 2, the switches 201a1, 201a2, ..., 201aN are each connected to the output terminal O of the corresponding complementary output random number generator 101a and the corresponding input terminal of the OR circuit 30. Hereinafter, the switches 201a1, 201a2, ..., 201aN may be collectively referred to as switch 201a.

[0025] Each switch 201a receives a corresponding bit of the N-bit binary number to be converted. Each switch 201a is turned on when the received bit is 1. In this case, each switch 201a outputs a signal of 0 or 1 received from the output terminal O of the corresponding complementary output random number generator 101a to the input terminal of the OR circuit 30 to which it is connected.

[0026] Furthermore, each of the switches 201a is turned off when the received 1 bit is 0. In this case, each of the switches 201a outputs 0 to the input terminal of the OR circuit 30 to which it is connected.

[0027] That is, when the corresponding bit of the N-bit binary number to be converted is 1 and when each switch 201a receives a 1 from the output terminal O of the corresponding complementary output random number generator 101a, it outputs a 1 to the input terminal of the connected OR circuit 30. In other cases, each switch 201a outputs a 0 to the input terminal of the connected OR circuit 30. That is, each switch 201a performs an AND operation.

[0028] The input unit 20 may include N processing units capable of performing an AND operation instead of the switches 201a1, 201a2, ..., 201aN. For example, the input unit 20 may include an AND gate. However, the input unit 20 is not limited to an AND gate, as long as it includes N processing units capable of performing an AND operation on a signal output from the output terminal O of the complementary output random number generator 101a corresponding to a corresponding bit of the N-bit binary number to be converted. The operation of the input unit 20 will be described in detail later.

[0029] The OR circuit 30 performs an OR operation on N inputs of signals received from each of the switches 201a. That is, the OR circuit 30 outputs 1 from the output terminal when all of the signals received from each of the switches 201a are 0. In other cases, the OR circuit 30 outputs 0 from the output terminal. Details of the operation of the OR circuit 30 will be described later.

[0030] The above-described process performed by the stochastic number generator 1 according to the embodiment of the present disclosure is merely an example, and the stochastic number generator 1 is not limited to the above-described process. For example, the stochastic number generator 1 may perform the process described below.

[0031] (How the stochastic number generator works) Next, the operation of the stochastic number generator 1 will be described.

[0032] (Operation of the random number generator) First, a detailed description will be given of the operation of the random number generation unit 10 included in the stochastic number generation unit 1. Fig. 7 is a diagram showing an example of the configuration of the random number generation unit 10 according to an embodiment of the present disclosure when N is 3. Here, as shown in Fig. 7, the signal output from output terminal O of complementary output random number generator 101a1 is denoted as R2, the signal output from output terminal O of complementary output random number generator 101a2 is denoted as R1, and the signal output from output terminal O of complementary output random number generator 101a3 is denoted as R0.

[0033] When complementary output random number generator 101a1 receives 1 as clock CLK, it outputs 1 from output terminal O of complementary output random number generator 101a1 with a 1 / 2 probability. Also, complementary output random number generator 101a1 outputs 0 from output terminal CO. When complementary output random number generator 101a1 outputs 0 from output terminal CO, complementary output random number generator 101a2 receives 0 as clock CLK and outputs 0 from each of output terminals O and CO. When complementary output random number generator 101a2 outputs 0 from output terminal CO, complementary output random number generator 101a3 receives 0 as clock CLK and outputs 0 from each of output terminals O and CO. Therefore, in this case, if signals R2, R1, and R0 are represented as (R2 R1 R0), random number generation unit 10 will output a signal of (R2 R1 R0)=(1 0 0) with a 1 / 2 probability.

[0034] Furthermore, when complementary output random number generator 101a1 receives a 1 as clock CLK, it outputs a 0 from output terminal O of complementary output random number generator 101a1 with a 1 / 2 probability. Furthermore, complementary output random number generator 101a1 outputs a 1 from output terminal CO. When complementary output random number generator 101a1 outputs a 1 from output terminal CO, complementary output random number generator 101a2 receives a 1 as clock CLK. When complementary output random number generator 101a2 receives a 1 as clock CLK, it outputs a 1 from output terminal O of complementary output random number generator 101a2 with a 1 / 2 probability. Furthermore, complementary output random number generator 101a2 outputs a 0 from output terminal CO. When complementary output random number generator 101a2 outputs a 0 from output terminal CO, complementary output random number generator 101a3 receives a 0 as clock CLK and outputs a 0 from each of its output terminals O and CO. The probability that the complementary output random number generator 101a2 receives 1 as the clock CLK is 1 / 2. Therefore, in this case, the random number generation unit 10 outputs a signal of (R2 R1 R0)=(0 1 0) with a probability of 1 / 4.

[0035] Furthermore, when complementary output random number generator 101a1 receives 1 as clock CLK, it outputs 0 from output terminal O of complementary output random number generator 101a1 with a 1 in 5 probability. Furthermore, complementary output random number generator 101a1 outputs 1 from output terminal CO. When complementary output random number generator 101a1 outputs 1 from output terminal CO, complementary output random number generator 101a2 receives 1 as clock CLK. When complementary output random number generator 101a2 receives 1 as clock CLK, it outputs 0 from output terminal O of complementary output random number generator 101a2 with a 1 in 5 probability. Furthermore, complementary output random number generator 101a2 outputs 1 from output terminal CO. When complementary output random number generator 101a3 receives 1 as clock CLK, it outputs 1 from output terminal O of complementary output random number generator 101a3 with a 1 in 5 probability. Furthermore, complementary output random number generator 101a3 outputs 0 from output terminal CO. Note that there is a 1 in 4 probability that complementary output random number generator 101a3 receives 1 as the clock CLK. Therefore, in this case, there is a 1 in 8 probability that random number generation unit 10 will output a signal of (R2 R1 R0)=(0 0 1).

[0036] FIG. 8 is a diagram illustrating an example of the probability of each signal output by the random number generation unit 10 according to an embodiment of the present disclosure. The probabilities of the signals output by the random number generation unit 10 illustrated in FIG. 8 are the probabilities of each signal output by the random number generation unit 10 when N is 3 illustrated in FIG. 7. As illustrated in FIG. 8, the random number generation unit 10 outputs a signal (R2 R1 R0)=(1 0 0) with a probability of 1 / 2. The random number generation unit 10 also outputs a signal (R2 R1 R0)=(0 1 0) with a probability of 1 / 4. The random number generation unit 10 also outputs a signal (R2 R1 R0)=(0 0 1) with a probability of 1 / 8. The random number generation unit 10 also outputs a signal (R2 R1 R0)=(0 0 0) with a probability of 1 / 8.

[0037] In addition, the probability that a random number generation unit 10, which includes N complementary output random number generators 101a1 to 101aN arranged in series, outputs 1 from the output terminal O of the nth complementary output random number generator 101a, can be generalized as (1 / 2)^n, where "^" is the symbol representing exponentiation.

[0038] (Operation of input section, operation of OR circuit) Next, the details of the operation of the input unit 20 and the operation of the OR circuit 30 will be described. FIG. 9 is a diagram illustrating an example of the configuration of the stochastic number generator 1 according to an embodiment of the present disclosure when N is 3. Note that FIG. 9 also illustrates the input unit 20 and OR circuit 30 when N is 3, as well as the random number generation unit 10 shown in FIG. 7 when N is 3. Here, as shown in FIG. 9, the signal output by the switch 201a1 to the OR circuit 30 is R2a, the signal output by the switch 201a2 to the OR circuit 30 is R1a, and the signal output by the switch 201a3 to the OR circuit 30 is R0a.

[0039] If the 3-bit binary number to be converted is represented as (b2 b1 b0), switch 201a1 receives a signal representing b2. Switch 201a1 then turns on or off depending on the received signal. Switch 201a2 also receives a signal representing b1. Switch 201a2 then turns on or off depending on the received signal. Switch 201a3 also receives a signal representing b0. Switch 201a3 then turns on or off depending on the received signal.

[0040] Furthermore, when each switch 201a is in the on state, it outputs 0 or 1, which is output from the output terminal O of the connected complementary output random number generator 101a, to the OR circuit 30. When each switch 201a is in the off state, it outputs 0 to the OR circuit 30.

[0041] As a first specific example, the operation of the input unit 20 and the OR circuit 30 when the 3-bit binary number (b2 b1 b0) to be converted is (1 0 0) will be described. FIG. 10 is a diagram illustrating a first example of the state of the input unit 20 according to an embodiment of the present disclosure when N is 3. FIG. 11 is a diagram for explaining the probability P that the OR circuit 30 shown in FIG. 10 will output 1. Suppose the 3-bit binary number (b2 b1 b0) to be converted is (1 0 0), the switch 201a1 is in the ON state, and the switches 201a2 and 201a3 are in the OFF state. In this case, the OR circuit 30 outputs 1 only when it receives a 1 from the switch 201a1.

[0042] As explained above regarding the operation of the random number generation unit 10, the switch 201a1 outputs 1 as b2 to the OR circuit 30 when the signal (R2 R1 R0)=(1 0 0) shown in FIG. 11 is satisfied. Therefore, as can be seen from FIG. 11, the probability P that the OR circuit 30 outputs 1 is 1 / 2. Therefore, the OR circuit 30 outputs a stochastic number SN such as 1100101000101101, for example.

[0043] As a second specific example, the operation of the input unit 20 and the OR circuit 30 when the 3-bit binary number (b2 b1 b0) to be converted is (1 1 1) will be described. FIG. 12 is a diagram illustrating a second example of the state of the input unit 20 according to an embodiment of the present disclosure when N is 3. FIG. 13 is a diagram for explaining the probability P that the OR circuit 30 shown in FIG. 12 outputs 1. Suppose the 3-bit binary number (b2 b1 b0) to be converted is (1 1 1) and the switches 201a1, 201a2, and 201a3 are in the on state. In this case, the OR circuit 30 outputs 1 when it receives a 1 from the switch 201a1, when it receives a 1 from the switch 201a2, and when it receives a 1 from the switch 201a3.

[0044] As explained above regarding the operation of the random number generation unit 10, the switch 201a1 outputs 1 as b2 to the OR circuit 30 when the signal (R2 R1 R0)=(1 0 0) shown in FIG. 13 is satisfied. The switch 201a2 outputs 1 as b1 to the OR circuit 30 when the signal (R2 R1 R0)=(0 1 0) shown in FIG. 13 is satisfied. The switch 201a3 outputs 1 as b0 to the OR circuit 30 when the signal (R2 R1 R0)=(0 0 1) shown in FIG. 13 is satisfied. Therefore, as can be seen from FIG. 13, the probability P that the OR circuit 30 outputs 1 is 7 / 8, calculated by (1 / 2) + (1 / 4) + (1 / 8). Therefore, the OR circuit 30 outputs a stochastic number SN, such as 1111101110111111, for example.

[0045] As a third specific example, the operation of the input unit 20 and the OR circuit 30 when the 3-bit binary number (b2 b1 b0) to be converted is (1 0 1) will be described. FIG. 14 is a diagram illustrating a third example of the state of the input unit 20 according to an embodiment of the present disclosure when N is 3. FIG. 15 is a diagram for explaining the probability P that the OR circuit 30 shown in FIG. 14 outputs 1. Suppose the 3-bit binary number (b2 b1 b0) to be converted is (1 0 1), the switches 201a1 and 201a3 are in the on state, and the switch 201a3 is in the off state. In this case, the OR circuit 30 outputs 1 when it receives a 1 from the switch 201a1 and when it receives a 1 from the switch 201a3.

[0046] As explained above regarding the operation of the random number generation unit 10, switch 201a1 outputs 1 as b2 to OR circuit 30 when the signal (R2 R1 R0)=(1 0 0) shown in FIG. 15 is satisfied. Switch 201a3 outputs 1 as b0 to OR circuit 30 when the signal (R2 R1 R0)=(0 0 1) shown in FIG. 15 is satisfied. Therefore, as can be seen from FIG. 15, the probability P that OR circuit 30 outputs 1 is 5 / 8, calculated by (1 / 2)+(1 / 8). Therefore, OR circuit 30 outputs a stochastic number SN such as 1101101100111101, for example.

[0047] In the above specific example, we have described the probability P that the OR circuit 30 outputs 1 when N is 3. However, the probability P that the OR circuit 30 outputs 1 can be generalized by expanding 3 to N and expressing it as in equation (1).

[0048]

number

[0049] Note that bi is the i-th bit in an N-bit binary number.

[0050] (advantage) The above has described the stochastic number generator 1 according to an embodiment of the present disclosure. The stochastic number generator 1 (an example of a number sequence generating device) includes a plurality of complementary output random number generators 101a (an example of a random number generating unit) connected in series, each of which outputs 0 from one of two outputs and 1 from the other with a 50% probability when a 1 is input, an OR circuit 30, and a plurality of switches 201a (an example of an input arithmetic unit) connected one to each of the plurality of complementary output random number generators 101a, each of which receives as input the output of the connected complementary output random number generator 101a and a binary number sequence to be converted, and outputs a value corresponding to the result of arithmetic operation of the logical product of the inputs to the OR circuit 30.

[0051] Here, in order to clarify the advantages of the stochastic number generator 1 according to an embodiment of the present disclosure, the stochastic number generator 1 when generating a stochastic number SN from an N-bit binary number will be compared with circuits 100a and 100b that perform the multiplication to be compared. Hereinafter, the circuits 100a and 100b may be collectively referred to as the circuit 100.

[0052] First, a comparative circuit 100a will be described. FIG. 16 illustrates an example of the configuration of the comparative circuit 100a. The circuit 100a is a multiplication circuit described in https: / / ifdl.jp / akita / class_old / old / 04 / lsi / 8.html that performs 4-bit multiplication. As shown in FIG. 16, the circuit 100a includes 16 arithmetic units BC that perform binary arithmetic and four full adders FA. FIG. 17 illustrates the configuration of the arithmetic units BC included in the circuit 100a shown in FIG. 16. As shown in FIG. 17, the arithmetic units BC include AND gates and full adders FA. To perform N-bit multiplication using a multiplication circuit configured in this manner, N×N arithmetic units BC and N full adders FA are required. As such, the circuit configuration of the circuit 100a is more complex than that of the stochastic number generator 1 shown in FIG. 1, and the number of elements included in the circuit 100a is greater.

[0053] FIG. 18 is a diagram showing an example of the configuration of a circuit 100b to be compared. The circuit 100b is the multiplication circuit described in Non-Patent Document 1 above. As shown in FIG. 18, the circuit 100b includes a random number generator (referred to as an LFSR in FIG. 18) and a comparator. The random number generator generates an n-bit random number (for example, when n is 2, one of 00, 01, 10, or 11). The random number generator is, for example, an LFSR (Linear Feedback Shift Register). When the comparator receives the output x of the random number generator and an n-bit binary value y, the comparator outputs 1 if y is greater than x and outputs 0 if y is equal to or less than x. A specific example when n is 2 will be described below.

[0054] Here, the operation of the circuit 100b will be described. FIG. 19 is a first diagram illustrating the operation of the comparison circuit 100b. FIG. 20 is a second diagram illustrating the operation of the comparison circuit 100b. FIG. 21 is a third diagram illustrating the operation of the comparison circuit 100b. FIGS. 19 to 21 show whether the comparator outputs 0 or 1 for input y (and consequently, whether the circuit 100b outputs 0 or 1). For example, when the circuit 100b receives 00 as input y, it outputs 0 regardless of the input x (i.e., the random number generated by the random number generator), as shown in FIG. 19. As a result, the circuit 100b outputs 00000000. For example, when the circuit 100b receives 11 as input y, it outputs 0 when the input x is 11, as shown in FIG. 20, and outputs 1 when the input x is other than 11. Therefore, the circuit 100b outputs, for example, 11011101, which has a three-quarters probability of outputting 1. 21, when circuit 100b receives 10 as input y, it outputs 0 when input x is 10 and 10, and outputs 1 when input x is 01 and 00. Therefore, circuit 100b outputs, for example, 10010110, which outputs 1 with a probability of 2 in 4 (i.e., 1 in 2).

[0055] As can be seen from the above description, even a circuit such as circuit 100b that includes a random number generator and a comparator can perform multiplication using stochastic numbers. FIG. 22 illustrates a first example of the configuration of the comparator included in circuit 100b. FIG. 23 illustrates a second example of the configuration of the comparator included in circuit 100b. FIG. 24 illustrates a third example of the configuration of the comparator included in circuit 100b. The comparator shown in FIG. 22 is a 1-bit comparator described in the non-patent document "Demonstration of photonic micro-ring resonator based digital bit magnitude comparator" (researchgate.net). The comparator shown in FIG. 23 is a 2-bit comparator described in the non-patent document "Intrinsic Evolution of Digital Circuits Based on a Reconfigurable Hyper-Structure" (researchgate.net). The comparator shown in FIG. 24 is a 4-bit comparator described in the non-patent document "An Absolute-value Detector with Threshold Comparing for Spike Detection in Brain-machine Interface" (researchgate.net). 22 to 24, the number of elements constituting the comparator increases rapidly as the number of bits to be calculated increases. Fig. 25 is a diagram showing an example of the number of elements in a circuit 100b and the number of elements in a stochastic number generator 1 according to an embodiment of the present disclosure. The number of elements in the circuit 100b is approximately 7N, while the number of elements in the stochastic number generator 1 is approximately 4N.

[0056] As described above, the stochastic number generator 1 can reduce the circuit scale and the mounting area compared to the circuit 100. In other words, it is possible to provide a small-sized number sequence generating device capable of performing calculations.

[0057] Although several embodiments of the present disclosure have been described, these embodiments are merely examples and do not limit the scope of the disclosure. Various additions, omissions, substitutions, and modifications may be made to these embodiments without departing from the spirit of the disclosure.

[0058] Note that part or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0059] (Appendix 1) a plurality of random number generators connected in series, each of which outputs a 0 from one of two outputs and a 1 from the other with a 50% probability when a 1 is input; An OR circuit, a plurality of input units, each connected to each of the plurality of random number generation units, each input unit receiving the output of the random number generation unit connected thereto and a binary sequence to be converted, and outputting a value corresponding to the result of a logical AND operation between the inputs to the OR circuit; A sequence generating device comprising:

[0060] (Appendix 2) The output of the random number generator and the sequence of binary numbers to be converted are stochastic numbers. 2. The sequence generating device according to claim 1.

[0061] (Appendix 3) The random number generation unit a random number generator that generates random binary numbers; a D flip-flop connected to the output of the random number generator; a NOT circuit connected to the output of the random number generator; 3. The sequence generating device according to claim 1, comprising:

[0062] (Appendix 4) The random number generator Two Josephson junctions, Equipped with 4. The sequence generating device according to claim 3.

[0063] (Appendix 5) A processing method executed by a number sequence generation device including a plurality of serially connected random number generation units, an OR circuit, and a plurality of input units, each connected to one of the plurality of random number generation units, the method comprising: The random number generation unit When a 1 is input, there is a 50 / 50 chance that one of the two outputs will be a 0 and the other will be a 1. Each of the plurality of input units a plurality of input units, each connected to each of the plurality of random number generation units, each receiving an output from the connected random number generation unit and a binary sequence to be converted, and outputting a value corresponding to the result of a logical AND operation between the inputs to the OR circuit; Processing method. [Explanation of symbols]

[0064] 1···Stochastic number generator 10. Random number generator 20 Input section 30... OR circuit 100... circuits 101a Complementary Output Random Number Generator 201a···Switch

Claims

1. a plurality of random number generation units connected in series, each of which outputs 0 from one of two outputs and 1 from the other with a probability of 50 / 50 when a value of 1 is input; an OR circuit; a plurality of input units, each connected to each of the plurality of random number generation units, each input unit receiving an output from the connected random number generation unit and a binary sequence to be converted, and outputting a value corresponding to a result of a logical product operation between the inputs to the OR circuit; A sequence generating device comprising:

2. the output of the random number generator and the sequence of binary numbers to be converted are stochastic numbers; The sequence generating device according to claim 1 .

3. The random number generation unit a random number generator that generates random binary numbers; A D Flip-Flop connected to the output of the random number generator; a NOT circuit connected to the output of the random number generator; 3. The sequence generating device according to claim 1, further comprising:

4. The random number generator Two Josephson junctions, Equipped with 4. The sequence generating device according to claim 3.

5. A processing method executed by a number sequence generation device including a plurality of serially connected random number generation units, an OR circuit, and a plurality of input units, each connected to one of the plurality of random number generation units, the method comprising: The random number generation unit When a 1 is input, there is a 50 / 50 probability that one of the two outputs will be a 0 and the other will be a 1. Each of the plurality of input units a plurality of input units, each connected to each of the plurality of random number generation units, each receiving an output from the connected random number generation unit and a binary sequence to be converted, and outputting a value corresponding to a result of a logical product operation between the inputs to the OR circuit; Processing method.

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